Semiconductor equipment

Abstract

To improve the reliability of semiconductor devices. [Solution] The semiconductor device of the embodiment comprises a first electrode, a second electrode in contact with the upper surface of the first electrode, a third electrode provided above the second electrode, an oxide semiconductor in contact with the upper surface of the second electrode and extending in a first direction toward the third electrode, a first insulating film provided on the side surface of the oxide semiconductor, and a first conductor that, when viewed from above, surrounds at least a part of the first insulating film, wherein the first insulating film includes a first region and a second region that, together with the oxide semiconductor, sandwiches the first region in a second direction intersecting the first direction, and the first concentration of nitrogen contained in the first insulating film in the first region is higher than the second concentration of nitrogen contained in the first insulating film in the second region.

Description

[Technical Field]

[0001] The embodiments relate to semiconductor devices. [Background technology]

[0002] Semiconductor devices using capacitors and transistors are known. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2022 / 0254931 [Patent Document 2] U.S. Patent Application Publication No. 2022 / 0254897 Specification [Patent Document 3] U.S. Patent Application Publication No. 2012 / 0248432 [Overview of the project] [Problems that the invention aims to solve]

[0004] To improve the reliability of semiconductor devices. [Means for solving the problem]

[0005] The semiconductor device of the embodiment comprises a first electrode, a second electrode in contact with the upper surface of the first electrode, a third electrode provided above the second electrode, an oxide semiconductor in contact with the upper surface of the second electrode and extending in a first direction toward the third electrode, a first insulating film provided on the side surface of the oxide semiconductor, and a first conductor that, when viewed from above, surrounds at least a part of the first insulating film, wherein the first insulating film includes a first region and a second region that, together with the oxide semiconductor, sandwiches the first region in a second direction intersecting the first direction, and the first concentration of nitrogen contained in the first insulating film in the first region is higher than the second concentration of nitrogen contained in the first insulating film in the second region. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of a memory system including a semiconductor device according to the embodiment. [Figure 2] A circuit diagram showing an example of the circuit configuration of a memory cell array in a semiconductor device according to the embodiment. [Figure 3] A plan view showing an example of a planar layout of a memory cell array in a semiconductor device according to this embodiment. [Figure 4] A cross-sectional view along line IV-IV in Figure 3, showing an example of the cross-sectional structure of a memory cell array in a semiconductor device according to the embodiment. [Figure 5] A cross-sectional view along the VV line in Figure 3, showing an example of the cross-sectional structure of a memory cell array provided in the semiconductor device according to the embodiment. [Figure 6] A cross-sectional view illustrating an example of the structure of the gate insulating film of a transistor in a semiconductor device according to this embodiment. [Figure 7] A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 8] A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 9] A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 10] A cross-sectional view illustrating an example of the structure of the gate insulating film of a transistor in a semiconductor device according to the first modified example. [Figure 11] A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first modified example. [Figure 12] A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first modified example. [Figure 13] A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a second modified example. [Figure 14] A cross-sectional view illustrating an example of the structure of the gate insulating film of a transistor in a semiconductor device relating to another example of the second modification. [Figure 15] A cross-sectional diagram illustrating an example of the structure of the gate insulating film of a transistor in a semiconductor device relating to other examples. [Figure 16] Cross-sectional view showing an example of a method for manufacturing a semiconductor device according to another example.

Embodiments for Carrying Out the Invention

[0007] Embodiments will be described below with reference to the drawings. Note that the dimensions and ratios in the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. Also, when particularly distinguishing between elements having similar configurations, different characters or numbers may be added to the end of the same reference numeral.

[0008] Also, in the following description, the connection of two different configurations means being electrically connected. Also, the connection of the two configurations includes that the two configurations are electrically connected via a configuration different from the two configurations. Also, being electrically connected may be via an insulator as long as it can operate in the same manner as that which is electrically connected.

[0009] 1 Embodiment The semiconductor device according to the embodiment will be described below.

[0010] 1.1 Configuration The configuration of the semiconductor device according to the embodiment will be described.

[0011] 1.1.1 Memory System The configuration of the memory system including the semiconductor device according to the embodiment will be described with reference to FIG. 1. FIG. 1 is a block diagram showing an example of the configuration of the memory system including the semiconductor device according to the embodiment.

[0012] The memory system 100 executes operations such as data writing and reading in response to commands from a host device external to the memory system 100 (not shown).

[0013] The memory system 100 includes a semiconductor device 1 and a memory controller 2.

[0014] The semiconductor device 1 is a memory device that uses transistors to select memory elements. The semiconductor device 1 stores data using, for example, capacitors. The semiconductor device 1 is, for example, a DRAM (Dynamic Random Access Memory). The memory controller 2 controls the semiconductor device 1.

[0015] The semiconductor device 1 includes a memory cell array 11, an input / output circuit 12, a control circuit 13, a voltage generation circuit 14, a write circuit 15, a read circuit 16, a row selection circuit 17, a column selection circuit 18, and a sense amplifier 19.

[0016] The memory cell array 11 includes multiple memory cells MC, multiple word lines WL, multiple bit lines BL, and a plate line PL. Figure 1 illustrates one memory cell MC, one word line WL, and one bit line BL. Each memory cell MC stores one bit of data. Each memory cell MC is connected between one of the multiple bit lines BL and the plate line PL. Each memory cell MC is also connected to one of the multiple word lines WL. Word lines WL are associated with rows. Bit lines BL are associated with columns. In the memory cell array 11, one memory cell MC is identified by selecting one row and one column.

[0017] The input / output circuit 12 receives the control signal CNT, command CMD, address signal ADD, and data DAT from the memory controller 2. The input / output circuit 12 also transmits data DAT to the memory controller 2. When writing data to the semiconductor device 1, data DAT is the data to be written. When reading data from the semiconductor device 1, data DAT is the data to be read.

[0018] The control circuit 13 receives a control signal CNT and a command CMD from the input / output circuit 12. Based on the control signal CNT and the command CMD, the control circuit 13 instructs the writing circuit 15 to write data to the semiconductor device 1. Based on the control signal CNT and the command CMD, the control circuit 13 instructs the reading circuit 16 to read data from the semiconductor device 1. The control circuit 13 also instructs the voltage generation circuit 14 to generate a voltage based on the control signal CNT and the command CMD.

[0019] The voltage generation circuit 14 generates various voltages based on instructions from the control circuit 13. The voltage generation circuit 14 supplies the generated voltages to the memory cell array 11, the write circuit 15, the read circuit 16, the row selection circuit 17, the column selection circuit 18, and the sense amplifier 19.

[0020] The writing circuit 15 performs processing and control for writing data to the memory cell MC. The writing circuit 15 receives the write data Dw from the input / output circuit 12. The write data Dw is the data to be written to the memory cell MC that is the target of the data writing. The writing circuit 15 receives one or more voltages used in the data writing operation from the voltage generation circuit 14. Based on the control of the control circuit 13 and the write data Dw, the writing circuit 15 supplies one or more voltages used in the data writing operation to the column selection circuit 18.

[0021] The read circuit 16 performs processing and control for reading data from the memory cell MC. The read circuit 16 receives one or more voltages from the voltage generation circuit 14 that are used in the data reading operation. Based on the control of the control circuit 13, the read circuit 16 uses the voltages used in the data reading operation to determine the data stored in the memory cell MC. The determined data is supplied to the input / output circuit 12 as read data Dr.

[0022] The row selection circuit 17 receives the address signal ADD from the input / output circuit 12. The row selection circuit 17 supplies the voltage received from the voltage generation circuit 14 to the memory cell array 11. As a result, the row selection circuit 17 selects one word line WL associated with the row identified by the received address signal ADD.

[0023] The column selection circuit 18 receives the address signal ADD from the input / output circuit 12. The column selection circuit 18 supplies the voltage received from the voltage generation circuit 14 to the memory cell array 11. As a result, the column selection circuit 18 selects the bit line BL associated with the column identified by the received address signal ADD.

[0024] The sense amplifier 19 uses the voltage received from the voltage generation circuit 14 to amplify the voltage of the bit line BL during data read operation in order to determine the data stored in the memory cell MC to be read.

[0025] 1.1.2 Circuit configuration of memory cell array The circuit configuration of the memory cell array in the semiconductor device according to the embodiment will be explained with reference to Figure 2. Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array in the semiconductor device according to the embodiment.

[0026] The memory cell array MCA includes M word lines WL (WL1 to WLM), N bit lines BL (BL1 to BLN), and a plate line PL. M and N are positive integers.

[0027] Each of the multiple bit lines BL is connected, for example, to M memory cells MC from among the multiple memory cells MC that correspond to that bit line BL. Each of the M memory cells MC corresponding to the bit line BL corresponds, for example, to M word lines WL.

[0028] Each memory cell MC includes a cell capacitor CC and a cell transistor CT.

[0029] A cell transistor (CT) is, for example, an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In the following, one of the source and drain ends of a cell transistor (CT) will be simply referred to as one end of the cell transistor (CT), and the other end will be simply referred to as the other end of the cell transistor (CT). One end of each cell transistor (CT) is connected to a bit line BL corresponding to that cell transistor (CT). The gate of each cell transistor (CT) is connected to a word line WL corresponding to that cell transistor (CT).

[0030] The semiconductor constituting a part of a cell transistor (CT) includes a region where a channel is formed (channel region). The material of this semiconductor includes an oxide semiconductor. Furthermore, the semiconductor material is composed of, for example, an oxide semiconductor. Note that when the material is composed of configuration A, the material may contain unintended impurities different from those in configuration A.

[0031] A cell capacitor CC is a capacitive element. One electrode at one end of each cell capacitor CC is connected to the other end of the cell transistor CT corresponding to that cell capacitor CC. The other electrode at the other end of each cell capacitor CC is connected to a plate wire PL. The cell capacitor CC stores data based on the charge accumulated at the node connected to the cell transistor CT. Hereafter, this node will also be referred to as a storage node SN.

[0032] The amount of charge accumulated in the storage node SN determines whether the memory cell MC is storing "1" data or "0" data. In the following, as an example, a state in which the potential of the storage node SN is charged to a potential relatively higher than the potential of the plate wire PL is considered to be a state in which the memory cell MC is storing "1" data. Conversely, a state in which the potential of the storage node SN is charged to a potential relatively lower than the potential of the plate wire PL is considered to be a state in which the memory cell MC is storing "0" data.

[0033] With the above configuration, in each memory cell MC, the cell capacitor CC and cell transistor CT are connected in series between the bit line BL corresponding to the memory cell MC and the plate line PL.

[0034] 1.1.3 Planar layout of memory cell array The planar layout of the memory cell array 11 provided in the semiconductor device 1 according to the embodiment will be described with reference to Figure 3. Figure 3 is a plan view showing an example of the planar layout of the memory cell array provided in the semiconductor device according to the embodiment. In Figure 3, four word lines WL1 to WL4 and four bit lines BL1 to BL4 are shown as an example.

[0035] In the following explanation, the X direction is approximately parallel to the substrate of the semiconductor device 1. The X direction corresponds to the extension direction of the word line WL. The Y direction is approximately parallel to the substrate of the semiconductor device 1 and perpendicular to the X direction. The Y direction corresponds to the extension direction of the bit line BL. The Z direction is approximately perpendicular to the substrate. In the Z direction, the side facing the memory cell array 11 from the substrate is called the upper side. In the Z direction, the side facing the substrate from the memory cell array 11 is called the lower side. Of the two surfaces of a certain component that are perpendicular to the Z direction, the upper surface is called the top surface, and the lower surface is called the bottom surface.

[0036] The memory cell array 11 includes a plurality of pillars PI and a plurality of upper electrodes TE associated with a plurality of bit lines BL and a plurality of word lines WL. Each pillar PI functions, for example, as a vertical transistor. Each pillar PI also corresponds to a cell transistor CT. In the embodiment, each of the plurality of gate electrodes GE functions as a word line WL.

[0037] Figure 3 shows a set of four pillar PIs. Each set of four pillar PIs corresponds to a word line WL1 to WL4. In each row, four pillar PIs are arranged along the X direction. The arrangement of the four pillar PIs in each of two adjacent sets of pillar PIs is, for example, similar. Furthermore, the positions of the four pillar PIs in one row are different from those of the four pillar PIs in the other row in the X direction. With this arrangement, in two adjacent sets of pillar PIs, the four pillar PIs in one row are offset from those in the other row in the X direction. Note that Figure 3 shows the case where each of the four sets of pillar PIs contains four pillar PIs, but the number of pillar PI rows and the number of pillar PIs in each row are not limited to this. The number of pillar PI rows and the number of pillar PIs in each row can be changed as appropriate.

[0038] Each pillar PI is connected to the corresponding bit line BL via an upper electrode TE. Each of the multiple bit lines BL extends along the Y direction. The multiple bit lines BL are aligned along the X direction. In the following, of bit lines BL1 and BL4, the side of bit line BL1 is referred to as one end in the X direction, and the side of bit line BL4 is referred to as the other end in the X direction. Each bit line BL is positioned so as to overlap with at least a portion of one of the pillar PIs in each row when viewed in the Z direction. Each bit line BL overlaps, for example, with respect to the X direction, with respect to one end of a pillar PI included in the row corresponding to word line WL1 or WL3 (included in odd-numbered rows). Also, with respect to the X direction, the bit line BL overlaps, for example, with respect to the other end of a pillar PI included in the row corresponding to word line WL2 or WL4 (included in even-numbered rows).

[0039] Each bit line BL is electrically connected to each pillar PI that overlaps with that bit line BL. The number of pillar PIs that overlap each bit line BL can be designed to be any number depending on the number of word lines WL.

[0040] Each gate electrode GE (word line WL) extends in the X direction, as described above. Multiple gate electrode GEs are aligned in the Y direction. Each gate electrode GE is positioned so as to surround each pillar PI corresponding to that gate electrode GE when viewed in the Z direction.

[0041] 1.1.4 Cross-sectional structure of memory cell array The cross-sectional structure of the memory cell array 11 provided in the semiconductor device 1 according to the embodiment will be described with reference to Figures 4 and 5. Figure 4 is a cross-sectional view along line IV-IV in Figure 3, showing an example of the cross-sectional structure of the memory cell array provided in the semiconductor device according to the embodiment. Figure 5 is a cross-sectional view along line VV in Figure 3, showing an example of the cross-sectional structure of the memory cell array provided in the semiconductor device according to the embodiment.

[0042] The memory cell array 11 includes a plurality of conductors 21-29, insulators 31-36, a plurality of oxide semiconductors 40, a plurality of gate insulating films 41 and 42, and a component SLT.

[0043] An insulator 31 is provided above the substrate S.

[0044] The insulator 31 and its layer contain electrodes at one end of each of the multiple cell capacitors CC. Hereinafter, the electrodes at one end of the cell capacitor CC will also be simply referred to as the cell capacitor CC. The multiple cell capacitors CC contain a conductive material. This material includes, for example, silicon (Si). This material is, for example, silicon germanium. The multiple cell capacitors CC have, for example, a columnar shape extending along the Z direction. The shape of the columnar shape in the XY cross-section may be, for example, circular or rectangular, and is not particularly limited.

[0045] In the same layer as the insulator 31, above the plurality of cell capacitors CC, a plurality of conductors 21 are provided, corresponding to the plurality of cell capacitors CC. The plurality of conductors 21 include, for example, conductive oxides. The plurality of conductors 21 include, for example, at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo), and oxygen (O). The plurality of conductors 21 include, for example, indium (In), tin (Sn), and oxygen (O). The plurality of conductors 21 include, for example, ITO (Indium Tin Oxide). On the lower surface and side surface of each conductor 21, a conductor 22 corresponding to the conductor 21 is provided. The upper surfaces of the multiple conductors 21 and 22 are arranged to be flush with the upper surface of the insulator 31. The lower surface of each conductor 22 is in contact with the upper surface of the cell capacitor CC corresponding to that conductor 22. The pairs of conductors 21 and 22 that correspond to each other function as the lower electrode BE.

[0046] Insulators 32, 33, and 34 are provided in this order, facing upward, on the upper surface of the insulator 31 and on the upper surfaces of the multiple conductors 21 and 22.

[0047] Multiple oxide semiconductors 40 are provided corresponding to multiple conductors 21 and 22. Each oxide semiconductor 40 is provided on the upper surface of the conductor 21 corresponding to the oxide semiconductor 40. Each oxide semiconductor 40 is provided such that its lower surface is in contact with the upper surface of the conductor 21. Multiple oxide semiconductors 40 penetrate the insulators 32 to 34. Multiple oxide semiconductors 40 are, for example, oxide semiconductors. Multiple oxide semiconductors 40 include, for example, at least one element from indium (In), gallium (Ga), zinc (Zn), aluminum (Al), and tin (Sn). Multiple oxide semiconductors 40 include, for example, at least one element from indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), as well as zinc (Zn). Oxide semiconductors 40 include, for example, indium-gallium-zinc oxide.

[0048] With the above configuration, a conductor 21 corresponding to the oxide semiconductor 40 is provided between the oxide semiconductor 40 and the conductor 22 corresponding to the oxide semiconductor 40. In this configuration, the conductor 21 is provided in such a way as to reduce the contact resistance between the conductor 22 and the oxide semiconductor 40.

[0049] Gate insulating films 41 and 42 are provided on the sides of each oxide semiconductor 40.

[0050] The gate insulating film 41 is provided on at least a portion of the side surface of the oxide semiconductor 40. The gate insulating film 41 includes an insulator. The gate insulating film 41 includes, for example, silicon oxide, silicon oxynitride, or metal oxide, or metal oxynitride. The metal contained in the metal oxide or metal oxynitride is, for example, at least one element from aluminum (Al), hafnium (Hf), and zirconium (Zr). A more detailed configuration of the gate insulating film 41 will be described later.

[0051] Each gate insulating film 42 is provided so as to cover the side surface of the gate insulating film 41. The gate insulating film 42 includes an insulator. The gate insulating film 42 includes, for example, silicon nitride, metal oxide, metal nitride, or metal oxynitride. The metal element contained in the metal oxide, metal nitride, or metal oxynitride is, for example, at least one element from among aluminum (Al), hafnium (Hf), and zirconium (Zr). The gate insulating film 42 is a monolayer film including one layer containing silicon nitride, metal oxide, metal nitride, or metal oxynitride, or a laminated film including multiple layers, each containing silicon nitride, metal oxide, metal nitride, or metal oxynitride. In the embodiment, the case in which the gate insulating film 42 is provided is described, but the gate insulating film 42 may not be provided.

[0052] The thickness of the gate insulating films 41 and 42 along the X or Y direction is, for example, 7 nanometers (nm) or less.

[0053] Each pair of corresponding oxide semiconductors 40 and gate insulating films 41 and 42 functions as a pillar PI. Each oxide semiconductor 40 corresponds to a semiconductor that constitutes part of a cell transistor CT. The upper surfaces of the multiple oxide semiconductors 40, as well as the upper surfaces of the multiple gate insulating films 41 and 42, are arranged to be flush with the upper surface of the insulator 34.

[0054] Furthermore, the pillar PI may have a tapered shape. Also, the pillar PI may have a Boeing shape in which the central part along the Z direction bulges out.

[0055] Multiple conductors 23 are provided in the same layer as the insulator 33. Each conductor 23 functions as a gate electrode GE (word line WL). Each of the multiple conductors 23 extends in the X direction corresponding to the gate electrode GE. As a result, in the XZ cross-section shown in Figure 4, the conductors 23 are in contact with the sides of multiple pillars PI aligned in the X direction. Furthermore, the multiple conductors 23 are aligned in the Y direction corresponding to multiple gate electrode GEs. As a result, in the YZ cross-section shown in Figure 5, each conductor 23 is in contact with the side of one pillar PI corresponding to that conductor 23.

[0056] An insulator 35 is provided on the upper surface of the insulator 34, the upper surfaces of the multiple oxide semiconductors 40, and the upper surfaces of the gate insulating films 41 and 42.

[0057] Multiple conductors 24 are provided in the same layer as the insulator 35, corresponding to multiple pillars PI. Each conductor 24 is provided on the upper surface of the oxide semiconductor 40 of the pillar PI corresponding to the conductor 24. Each conductor 24 is provided so as to cover the upper surface of the oxide semiconductor 40 corresponding to the conductor 24. The multiple conductors 24 include, for example, conductive oxides. The multiple conductors 24 include, for example, at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo), and oxygen (O). The multiple conductors 24 include, for example, an oxide of at least one element from indium (In) and tin (Sn). The conductive oxide includes, for example, at least one compound from indium tin oxide and tin oxide.

[0058] Multiple conductors 25 are provided on the upper surfaces of multiple conductors 24, corresponding to the multiple conductors 24. The multiple conductors 25 include, for example, at least one element from among titanium (Ti), tin (Sn), zinc (Zn), ruthenium (Ru), and niobium (Nb). Furthermore, the multiple conductors 25 include, for example, a nitride of at least one of these elements. The multiple conductors 25 include, for example, titanium nitride (TiN).

[0059] Multiple conductors 26 are provided on the upper surfaces of multiple conductors 25, corresponding to the multiple conductors 25. The multiple conductors 26 include, for example, tungsten (W). The upper surfaces of the multiple conductors 26 are provided so as to be flush with the upper surface of the insulator 35. In the Z direction, the thickness of the multiple conductors 26 is, for example, greater than the thickness of each of the multiple conductors 24 and 25.

[0060] In the configuration described above, the pairs of conductors 24-26 that correspond to each other function as upper electrodes TE. Furthermore, each conductor 25 is provided in such a way that it prevents the metallic elements contained in the conductor 26 corresponding to it from entering the conductor 24 by diffusion. For this reason, the multiple conductors 25 can be said to function as, for example, barrier metals.

[0061] Multiple conductors 27 are provided on the upper surface of the insulator 35 and on the upper surfaces of the multiple conductors 26, corresponding to multiple upper electrodes TE. Each conductor 27 is provided so as to be in contact with the conductor 26 of the multiple upper electrodes TE corresponding to that conductor 27. Each conductor 27 extends along the Y direction, corresponding to the bit line BL. The multiple upper electrodes TE corresponding to each conductor 27 correspond to multiple different word lines WL. The multiple conductors 27 are aligned in the X direction, corresponding to the multiple bit lines BL. The multiple conductors 27 include, for example, titanium nitride (TiN).

[0062] A conductor 28 corresponding to each conductor 27 is provided on the upper surface of each conductor 27. The multiple conductors 28 include, for example, tungsten (W).

[0063] A conductor 29 corresponding to the conductor 27 is provided on the upper surface of each conductor 28. The multiple conductors 29 include, for example, titanium nitride (TiN).

[0064] In the configuration described above, the corresponding conductors 27, 28, and 29 function as bit lines BL. Furthermore, the multiple conductors 27 and 29 are arranged to prevent the metallic elements contained in the multiple conductors 28 from diffusing into the layers below the multiple conductors 27 and the layers above the multiple conductors 29. For this reason, the multiple conductors 27 and 29 can be said to function as, for example, barrier metals. Note that the multiple conductors 27 and 29 may be omitted.

[0065] An insulator 36 is provided on the upper surface of the multiple conductors 29.

[0066] Multiple member SLTs are provided above the insulator 34. Each member SLT extends along the Y direction. The multiple member SLTs are arranged along the X direction. Each member SLT is provided so as to penetrate the conductors 27-29. The upper surface of each member SLT is provided so as to be flush with, for example, the upper surface of the insulator 36. The lower surface of each member SLT is in contact with, for example, the conductor 26. The lower surface of each member SLT only needs to reach the height of the upper surface of the insulator 35. The multiple member SLTs are, for example, insulators such as silicon oxide. With the above configuration, two adjacent bit lines BL in the X direction are separated from each other by the member SLTs corresponding to the two bit lines BL. Furthermore, the two bit lines BL are insulated from each other by the member SLTs.

[0067] In the XZ section including word line WL1 or WL3, each member SLT is provided so as to overlap, for example, one end of each upper electrode TE in the X direction. In the XZ section including word line WL2 or WL4, each member SLT is provided so as to overlap, for example, the other end of each upper electrode TE in the X direction. Figure 4 shows an example in which each member SLT is provided so as to overlap the other end of the upper electrode TE corresponding to that member SLT.

[0068] 1.1.5 Structure of the gate insulating film Next, the structure of the gate insulating film 41 will be described using Figure 6. Figure 6 is a cross-sectional view illustrating an example of the structure of the gate insulating film of a transistor provided in the semiconductor device according to this embodiment.

[0069] The gate insulating film 41 is provided above the conductor 21. This causes the gate insulating film 41 to be separated from the conductor 21, for example. The gate insulating film 41 covers the sides of the oxide semiconductor 40, for example, in a range from a height above the top surface of the conductor 21 to a height above the top surface of the oxide semiconductor 40. The gate insulating film 42 covers the sides and bottom surfaces of the gate insulating film 41, for example.

[0070] The gate insulating film 41 includes regions 41A and 41B. In Figure 6, region 41A is indicated by the region enclosed by the dotted line.

[0071] Region 41A is, for example, a region provided so as to be in contact with the side surface of the oxide semiconductor 40. Region 41A covers the side surface of the oxide semiconductor 40, for example, in the range from a height above the lower surface of the gate insulating film 41 to the height of the upper surface of the oxide semiconductor 40. Region 41A may also be provided covering the entire area from the height of the upper surface to the height of the lower surface of the gate insulating film 41.

[0072] Region 41B is, for example, the region of the gate insulating film 41 excluding region 41A. Region 41A is sandwiched between region 41B and the oxide semiconductor 40 in the X and Y directions. Region 41B is provided so as to be in contact with the side surface portion of the oxide semiconductor 40 that is located below region 41A and where region 41A is not provided. For example, the conductor 21 is in contact with the oxide semiconductor 40, but the conductor 21 is not in contact with the gate insulating film 41.

[0073] Region 41A is formed, for example, by a nitriding treatment described later. The gate insulating film 41 has a higher concentration of nitrogen (N) atoms in region 41A than in region 41B. The concentration of nitrogen (N) atoms in region 41A is, for example, 1 × 10⁻⁶ 15 atoms / cm 3 That is all, and 1 × 10 18 atoms / cm 3 The following applies. Furthermore, the gate insulating film 41 may be configured to have a concentration gradient such that, in an XY cross-section including regions 41A and 41B, the concentration of nitrogen (N) atoms gradually decreases from region 41A towards region 41B (from the oxide semiconductor 40 towards the conductor 23). Also, for example, as described above, if region 41B has a portion that is located below region 41A, the gate insulating film 41 includes region 41B with a lower nitrogen (N) concentration than region 41A between region 41A and the gate insulating film 42 and the conductor 21 along the Z direction.

[0074] If the gate insulating film 41 contains silicon oxide or silicon oxynitride, in region 41A, the gate insulating film 41 contains, for example, silicon oxynitride. Also in this case, in region 41B, the gate insulating film 41 contains, for example, silicon oxide or silicon oxynitride. If the gate insulating film 41 contains metal oxide or metal oxynitride, in region 41A, the gate insulating film 41 contains, for example, metal oxynitride. Also in this case, in region 41B, the gate insulating film 41 contains, for example, metal oxide or metal oxynitride.

[0075] Furthermore, for example, the concentration of nitrogen (N) atoms in the gate insulating film 42 is higher than the concentration of nitrogen (N) atoms in region 41A. In this case, oxidation of the conductor 23 can be suppressed. Note that, depending on the material of the conductor 23, the concentration of nitrogen (N) atoms in the gate insulating film 42 may be lower than the concentration of nitrogen (N) atoms in region 41A.

[0076] 1.2 Manufacturing method Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described using Figures 7, 8, and 9. Figures 7, 8, and 9 are cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the embodiment. The cross-sections shown in Figures 7 to 9 correspond to the cross-sectional view shown in Figure 6.

[0077] First, an insulator 31, multiple cell capacitors CC, and multiple lower electrodes BE are provided above the substrate S.

[0078] Next, insulators 32, 33, and 34, and a plurality of conductors 23 are formed. In addition, a plurality of holes H corresponding to a plurality of pillars PI are formed. The plurality of holes H are formed, for example, by photolithography and anisotropic etching, so as to extend from the upper surface of insulator 34 to the upper surfaces of conductors 21 and 22. The anisotropic etching is, for example, RIE (Reactive Ion Etching).

[0079] Then, as shown in Figure 7, insulators 420 and 410 are formed continuously, for example, in this order, so as to cover the side and bottom surfaces of hole H. Insulators 410 and 420 correspond to gate insulating films 41 and 42, respectively. The material of insulator 410 is, for example, equivalent to the composition of gate insulating film 41 in region 41B. The material of insulator 420 is, for example, equivalent to the composition of gate insulating film 42.

[0080] Next, a surface nitriding treatment is performed within the hole H where the insulator 410 is formed. This surface nitriding treatment is, for example, plasma isotropic nitriding. Through this process, as shown in Figure 8, the insulator 410 is divided into a nitrided region 410A and an unnitrided region 410B. For example, the region of the insulator 410 exposed within the hole H in Figure 7 is designated as region 410A. Region 410A is formed separately from the insulator 420 and the conductor 21. The material of the insulator 410 in region 410A is made equivalent to the composition of the gate insulating film 41 in region 41A by the surface nitriding treatment. Also, for example, the region of the insulator 410 excluding the region designated as region 410A is designated as region 410B. The material of the insulator 410 in region 410B is maintained to be equivalent to the composition of the gate insulating film 41 in region 41B. Region 410B is located between the insulator 420 and region 410A.

[0081] Furthermore, as shown in Figure 9, the removal of the bottom of hole H forms a gate insulating film 41 including regions 41A and 41B, and a gate insulating film 42. More specifically, for example, the portions of insulator 410 and insulator 420 that constitute the bottom of hole H in Figure 8 are removed by anisodirectional etching using a mask. This anisodirectional etching is, for example, RIE. This process is carried out until the upper surface of the conductor 21 is exposed. After the portions of insulator 410 and insulator 420 are removed by this process, the region that was included in region 410A becomes region 41A of the gate insulating film 41. The region that was included in region 410B becomes region 41B of the gate insulating film 41. Also, insulator 420 becomes the gate insulating film 42.

[0082] Then, multiple oxide semiconductors 40 are embedded in each of the multiple holes H. In addition, multiple conductors 24-29, insulators 35-36, and a component SLT are formed.

[0083] The semiconductor device 1 is manufactured through the above process.

[0084] 1.3 Effects According to the embodiment, the reliability of the semiconductor device can be improved. The effects of the embodiment are described below.

[0085] According to this embodiment, the semiconductor device 1 comprises a cell capacitor CC, a lower electrode BE and an upper electrode TE, a pillar PI, and a word line WL. The lower electrode BE is in contact with the upper surface of the cell capacitor CC. The upper electrode TE is provided above the lower electrode BE. The pillar PI includes an oxide semiconductor 40 extending in the Z direction and a gate insulating film 41 provided on the side surface of the oxide semiconductor 40. The oxide semiconductor 40 is in contact with the upper surface of the lower electrode BE. The word line WL surrounds at least a portion of the gate insulating film 41. The gate insulating film 41 includes region 41A and region 41B. Region 41B is provided together with the oxide semiconductor 40 so as to sandwich region 41A. The concentration of nitrogen (N) atoms contained in the gate insulating film 41 in region 41A is higher than the concentration of nitrogen (N) contained in the gate insulating film 41 in region 41B. With this configuration, according to this embodiment, by providing region 41A, the diffusion of metal elements contained in the oxide semiconductor 40 into the gate insulating film 41 can be suppressed. Furthermore, dielectric breakdown in the gate insulating film 41 can be suppressed. Therefore, the reliability of the semiconductor device 1 can be improved.

[0086] To elaborate, if there is no region in the oxide semiconductor of a cell transistor that suppresses the diffusion and intrusion of metal elements into the gate insulating film, metal elements such as indium (In), gallium (Ga), zinc (Zn), aluminum (Al), and tin (Sn) may penetrate into the gate insulating film. In such cases, these metal elements that have penetrated into the gate insulating film, along with electrical stress, can cause defects (trap sites) to randomly occur in the gate insulating film. Furthermore, if such defects increase due to prolonged voltage application, a problem can arise where defects form in a chain-like fashion between the oxide semiconductor and the gate electrode, leading to dielectric breakdown. This type of dielectric breakdown is also called TDDB (Time-Dependent Dielectric Breakdown).

[0087] According to the embodiment, in the gate insulating film 41, region 41A is provided between region 41B and the side surface of the oxide semiconductor 40. Furthermore, the gate insulating film 41 has a higher concentration of nitrogen (N) atoms in region 41A than in region 41B. As a result, the portion of the gate insulating film 41 included in region 41A can prevent metallic elements such as indium (In), gallium (Ga), zinc (Zn), aluminum (Al), and tin (Sn) contained in the oxide semiconductor 40 from diffusing into region 41B of the gate insulating film 41. In other words, region 41A functions as a barrier region to prevent the penetration of the metallic elements from the oxide semiconductor 40 into region 41B. Therefore, dielectric breakdown due to the diffusion of the metallic elements in the gate insulating film 41 is suppressed.

[0088] Furthermore, in this embodiment, the gate insulating film 41 includes a portion of region 41B located below region 41A. The gate insulating film also includes region 41B located below region 41A and the gate insulating film 42. This configuration makes it possible to suppress the reduction of the on-current Ion of the cell transistor CT. In addition, by having this configuration, the semiconductor device 1 suppresses electron trapping by silicon oxynitride and metal oxynitride directly above the conductor 21. As a result, a fringe field is more easily applied at the interface between the oxide semiconductor 40 and the conductor 21. Therefore, according to this embodiment, the characteristics of the on-current Ion of the cell transistor CT are improved.

[0089] 2. First variation In the above-described embodiment, a region having a high concentration of nitrogen (N) atoms in the gate insulating film is provided away from the conductor of the lower electrode, but the invention is not limited to this. In a semiconductor device, a region having a high concentration of nitrogen (N) atoms in the gate insulating film may be provided in contact with the conductor of the lower electrode. Furthermore, the conductor of the lower electrode in contact with the oxide semiconductor may also have a region having a high concentration of nitrogen (N) atoms. Below, the configuration and manufacturing method of the semiconductor device 1 according to the first modification will be mainly described in terms of the differences from the configuration and manufacturing method of the semiconductor device according to the embodiment.

[0090] The configuration of the semiconductor device 1 according to the first modified example will be explained with reference to Figure 10. Figure 10 is a cross-sectional view illustrating an example of the structure of the gate insulating film of the transistor in the semiconductor device according to the first modified example. Figure 10 corresponds to the cross-section shown in Figure 6 of the embodiment.

[0091] In the first modified example, region 41A of the gate insulating film 41 is provided so as to completely cover the side surface of the oxide semiconductor 40 that is included in the height from the upper surface to the lower surface of the gate insulating film 41. Region 41B is provided so as to completely cover the side surface of region 41A.

[0092] In the first modified example, the gate insulating film 42 includes regions 42A and 42B. Region 42A is a region below the gate insulating film 41 that is in contact with the side surface of the oxide semiconductor 40. Region 42A, together with region 41A, completely covers the side surface of the oxide semiconductor 40. Region 42B is the region of the gate insulating film 42 excluding region 42A. In Figure 10, region 42A is shown by the region enclosed by the dotted line.

[0093] Region 42A is formed, for example, together with region 41A by surface nitriding treatment, as will be described later. The gate insulating film 42 has, for example, a higher concentration of nitrogen (N) atoms in region 42A than in region 42B. The concentration of nitrogen (N) atoms in region 42A is, for example, 1 × 10⁻⁶ 15 atoms / cm 3 That is all, and 1 × 10 18 atoms / cm3 It is as follows. Further, the gate insulating film 42 may be configured to have a concentration gradient such that the concentration of nitrogen (N) atoms gradually decreases from the region 42A side to the region 42B side (from the oxide semiconductor 40 toward the conductor 23) in the XY cross section including the regions 42A and 42B.

[0094] In the first modification, the lower electrode BE of the semiconductor device 1 includes conductors 121 and 22. That is, the lower electrode BE includes the conductor 121 instead of the conductor 21 in the embodiment. The conductor 121 includes regions 121A and 121B. In FIG. 10, the region 121A is shown by the region surrounded by the dotted line in the conductor ①21.

[0095] The region 121A is provided at the upper end portion of the conductor 121. The region 121A is in contact with the gate insulating film 42 and the lower surface of the oxide semiconductor 40. Thereby, the region 121A, the region 41A of the gate insulating film 41, and the region 42A of the gate insulating film 42 cover the side surface and the lower surface of the oxide semiconductor 40. The region 121B is the region of the conductor 121 excluding the region 121A. The region 121B sandwiches the region 121A in the Z direction together with the lower surface of the oxide semiconductor 40 and the portion included in the region 42A of the gate insulating film 42. Although not shown, the region 121A may be provided inside the gate insulating film 42 corresponding to the region 121A when viewed from above. In this case, the region 121A does not contact the region 42A.

[0096] The region 121A is formed by surface nitridation treatment together with the regions 41A and 42A, for example, as will be described later. The conductor 121 has a higher concentration of nitrogen (N) atoms in the region 121A than in the region 121B. The concentration of nitrogen (N) atoms in the region 121A is, for example, 1×10 15 atoms / cm 3 or more and 1×10 18 atoms / cm 3 or less. Note that the concentration of nitrogen (N) atoms on the surface of the conductor 22 may be higher than the concentration of nitrogen (N) atoms at a position away from the gate insulating films 41 and 42 of the conductor 22.

[0097] The conductor 121 contains a conductive oxide equivalent to that of the conductor 21 in the embodiment. In region 121A, the conductor 121 contains a nitride of the conductive oxide (for example, a conductive oxynitride). In region 121B, the conductor 121 contains a material equivalent to the conductive oxide.

[0098] Next, a method for manufacturing the semiconductor device 1 according to the first modified example will be described using Figures 11 and 12. Figures 11 and 12 are cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first modified example. Figures 11 and 12 correspond to the cross-section shown in Figure 10.

[0099] In the first modified example, insulators 410 and 420 are formed by the same process as shown with reference to Figure 7 in the embodiment. In the first modified example, a conductor 1210 is formed instead of the conductor 21 in the embodiment. The material of the conductor 1210 is equivalent to the material of the conductor 21 in the embodiment.

[0100] Furthermore, the bottom of the hole H is removed by a process similar to the one described with reference to Figure 9 in the embodiment, as shown in Figure 11. As a result, for example, the upper surface of the conductor 1210 is exposed inside the hole H.

[0101] Then, surface nitriding treatment is performed on the hole H where the upper surface of the conductor 1210 is exposed, by the same process as described with reference to Figure 8 in the embodiment. As a result of this process, as shown in Figure 12, the insulator 410 becomes a gate insulating film 41 including regions 41A and 41B. The insulator 420 becomes a gate insulating film 42 including regions 42A and 42B. The conductor 1210 becomes a conductor 121 including regions 121A and 121B. More specifically, for example, the region of the insulator 410 exposed in the hole H in Figure 11 is region 41A. Also, for example, the region of the insulator 410 excluding the region designated as region 41A is designated as region 41B. Also, for example, the region of the insulator 420 exposed in the hole H in Figure 11 is region 42A. Also, for example, the region of the insulator 420 excluding the region designated as region 42A is designated as region 42B. Furthermore, for example, in Figure 11, the region of the conductor 1210 exposed within hole H is designated as region 121A of the conductor 121. Also, for example, the region of the conductor 1210 excluding the region designated as region 121A is designated as region 121B of the conductor 121.

[0102] Then, a plurality of conductors 24-29, insulators 35-36, a plurality of oxide semiconductors 40, and a component SLT are formed by the same process as in the embodiment.

[0103] By the above process, the semiconductor device 1 according to the first modified example is manufactured.

[0104] The reliability of the semiconductor device 1 can also be improved by the first modification, similar to the embodiment.

[0105] Furthermore, according to the first modification, the contact resistance between the oxide semiconductor 40 and the conductor 121 can be reduced. As described above, the conductor 121 of the semiconductor device 1 according to the first modification includes a region 121A that is in contact with the oxide semiconductor 40 and has a high concentration of nitrogen (N) atoms. As a result, when the oxide semiconductor 40 contains indium (In), the conductor 121 contains more nitrogen (N) atoms with a greater number of valence electrons than indium (In) in region 121A than in region 121B. Therefore, according to the first modification, the interfacial resistance between the oxide semiconductor 40 and the conductor 121 can be reduced.

[0106] 3. Second variation In the embodiments described above and the first modification, it was shown that the gate insulating film, or the gate insulating film and the lower electrode, include regions with a high concentration of nitrogen atoms as a result of nitriding treatment of the inner surface of the holes during the manufacturing process, but the invention is not limited thereto. Regions with a high concentration of nitrogen atoms in the gate insulating film, or the gate insulating film and the lower electrode, may be formed by a film deposition process.

[0107] The configuration of the semiconductor device 1 according to the second modified example is the same as that of the semiconductor device according to the embodiment, except that the portion of the gate insulating film 41 included in region 41A is formed by a film deposition process that includes nitrogen (N) atoms. Below, the differences between the manufacturing method of the semiconductor device 1 according to the second modified example and the manufacturing method of the semiconductor device according to the embodiment will be explained.

[0108] A method for manufacturing the semiconductor device 1 according to the second modified example will be explained with reference to Figure 13. Figure 13 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device according to the second modified example.

[0109] In the second modified example, insulators 410 and 420 are formed by the same process as in Figure 7 of the embodiment, as shown in Figure 13. Note that the insulator 410 formed in this process corresponds to the portion included in region 410B in the embodiment.

[0110] Furthermore, a material containing silicon oxynitride or metal oxynitride is formed on the surface of the insulator 410 within hole H. The formed portion has a similar structure to, for example, the portion included in region 410A in the embodiment. This process forms a structure similar to the structure shown in Figure 8 of the embodiment.

[0111] Then, following the same process as in the embodiment, a plurality of conductors 24-29, insulators 35-36, a plurality of oxide semiconductors 40, gate insulating films 41 and 42, and a member SLT are formed.

[0112] The second modification also suppresses the decrease in reliability of the semiconductor device 1, similar to the embodiment.

[0113] Furthermore, in the second modification, as in the embodiment, region 41A does not come into contact with the conductor 21. Also, between region 41A and the conductor 21, there is a region 41B with a lower nitrogen concentration than region 41A. As a result of the above, as in the embodiment, the reduction of the on-current Ion of the cell transistor CT can be suppressed.

[0114] In the above example, as in the embodiment, the gate insulating film 41 is shown to include two regions 41A and 41B, but it is not limited to this. The semiconductor device may be composed of a material in which the entire gate insulating film 41 is silicon oxynitride or metal oxynitride, as shown in Figure 14. That is, the gate insulating film 41 may include only one region. Figure 14 is a cross-sectional view illustrating an example of the structure of the gate insulating film of a transistor in a semiconductor device according to another example of the second modification.

[0115] In this case, the gate insulating film 41 corresponds to a region with a high concentration of nitrogen atoms. Furthermore, the material of the gate insulating film 41 in another example of the second modification is equivalent to, for example, the material of region 41A in the embodiment. Also, in another example of the second modification, the concentration of nitrogen (N) atoms in the gate insulating film 42 is lower than the concentration of nitrogen (N) atoms in the gate insulating film 41. Thus, the gate insulating film 42 corresponds to a region with a low concentration of nitrogen atoms.

[0116] In the manufacturing method of the semiconductor device 1 according to another example of the second modification, in Figure 13, instead of forming an insulator 410 corresponding to region 410B, an insulator 410 corresponding to the gate insulating film 41 with a high concentration of nitrogen atoms is formed. The material of the insulator 410 is, for example, equivalent to the material of the gate insulating film 41 in another example of the second modification. After the insulator 410 is formed, the bottom of the hole H is removed to form the gate insulating films 41 and 42. Also, similar to the embodiment, a plurality of conductors 24-29, insulators 35-36, a plurality of oxide semiconductors 40, and a component SLT are formed.

[0117] This configuration, like the embodiment, can suppress a decrease in the reliability of the semiconductor device 1.

[0118] Furthermore, in another example of the second modification, the gate insulating film 41 with a high concentration of nitrogen atoms does not come into contact with the conductor 21. Also, a gate insulating film 42 with a lower nitrogen concentration than the gate insulating film 41 is included between the gate insulating film 41 and the conductor 21. From the above, in another example of the second modification, as in the embodiment, the reduction of the on-current Ion of the cell transistor CT can be suppressed.

[0119] 4. Others The embodiments, first modification, and second modification described above show, but are not limited to, a case in which the removal of the bottom of the hole is performed after two insulators corresponding to the gate insulating film are formed in succession during the manufacturing process. The second insulator may be formed after the removal of the bottom of the hole in the first insulator is performed.

[0120] In the following section, Figure 15 will be used to explain the differences between the configuration of the semiconductor device 1 according to other examples and the configuration of the semiconductor device according to the embodiment. Figure 15 is a cross-sectional view illustrating an example of the structure of the gate insulating film of a transistor in the semiconductor device according to other examples.

[0121] In other examples, the gate insulating film 41 is in contact with the lower electrode BE. In this configuration, the gate insulating film 42 covers the side surface of the gate insulating film 41 but does not cover the lower surface of the gate insulating film 41. In the example of Figure 15, region 41A of the gate insulating film 41 is provided from a height above the lower surface of the gate insulating film 41 to the height of the upper surface of the oxide semiconductor 40, similar to the embodiment. As a result, region 41A is separated from the lower electrode BE. However, it is not limited to this. Region 41A may be provided from the height of the lower surface of the gate insulating film 41 to the height of the upper surface of the oxide semiconductor 40. In this case, region 41A covers the entire side surface of the oxide semiconductor 40.

[0122] Next, using Figure 16, the differences between the manufacturing method of the semiconductor device 1 according to the embodiment and other examples will be explained. Figure 16 is a cross-sectional view showing an example of a manufacturing method of a semiconductor device according to other examples.

[0123] In other examples, in the process corresponding to Figure 7 of the embodiment, after the gate insulating film 42 is formed on the side surface of the hole H, an insulator 410 is formed to cover the side surface of the gate insulating film 42 and the bottom surface of the hole H, as shown in Figure 16. That is, the insulator 410 is formed after the bottom of the insulator 420 formed in the hole H is removed. Other steps can be the same as those for the manufacturing method of the semiconductor device according to the embodiment.

[0124] Other examples also produce the same effects as the embodiments.

[0125] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0126] 1… Semiconductor equipment, 2…Memory controller, 11…Memory cell array, 12…Input / Output Circuits, 13…Control circuits, 14…Voltage generation circuit, 15... Programming circuit, 16...Read circuit, 17... Row selection circuit, 18…Column selection circuit, 19...Sense Amp, 21-29... Conductors, 31-36...Insulator, 40…Oxide semiconductors, 41, 42... gate insulating film, 100...Memory system, MC…Memory cell CC... Cell Capacitor, CT... Cell Transistor BL... bit line, WL... Word line, PL...plate wire, TE… Upper electrode, BE...Lower electrode, PI... Pillar.

Claims

1. First electrode and A second electrode in contact with the upper surface of the first electrode, A third electrode is provided above the second electrode, An oxide semiconductor in contact with the upper surface of the second electrode and extending in a first direction from the second electrode toward the third electrode, A first insulating film provided on the side surface of the oxide semiconductor, Viewed from above, the first conductor surrounds at least a portion of the first insulating film, Equipped with, The first insulating film is The first area and, In a second direction intersecting the first direction, a second region sandwiching the first region together with the oxide semiconductor, Includes, In the first region, the first concentration of nitrogen contained in the first insulating film is higher than the second concentration of nitrogen contained in the first insulating film in the second region. Semiconductor equipment.

2. The first region is provided above the second electrode and at a distance from the second electrode. The semiconductor device according to claim 1.

3. The first region is provided on the entire side surface of the oxide semiconductor, The semiconductor device according to claim 1.

4. The second electrode includes a second conductor that is in contact with the lower surface of the oxide semiconductor. The second conductor is A third region in contact with the lower surface of the oxide semiconductor, A fourth region sandwiching the third region in the first direction together with the oxide semiconductor, It has, In the third region, the third concentration of nitrogen contained in the second conductor is higher than the fourth concentration of nitrogen contained in the second conductor in the fourth region. The semiconductor device according to claim 1.

5. The first insulating film further includes a fifth region in the second direction that sandwiches the second region together with the first region and is in contact with the first conductor, In the fifth region, the fifth concentration of nitrogen contained in the first insulating film is higher than the first concentration. The semiconductor device according to claim 1.

6. The first concentration is 1 × 10 １５ atoms / cm ３ That is all, and 1 × 10 １８ atoms / cm ３ The following is: The semiconductor device according to claim 1.

7. The first insulating film is provided such that the nitrogen concentration gradually decreases from the first region side toward the second region side. The semiconductor device according to claim 1.

8. The first insulating film is an insulator containing silicon oxide, silicon oxynitride, metal oxide, or metal oxynitride. The semiconductor device according to claim 1.

9. The second insulating film is provided so as to be in contact with the side surface of the first insulating film and is in contact with the first conductor, The semiconductor device according to claim 1.

10. The thickness of the first insulating film and the second insulating film along the second direction is 7 nanometers or less. The semiconductor device according to claim 9.

11. The second insulating film is an insulator containing silicon nitride, a metal oxide, a metal nitride, or a metal oxynitride. The semiconductor device according to claim 9.

12. The second insulating film is A monolayer film comprising one layer containing silicon nitride, metal oxide, metal nitride, or metal oxynitride, A multilayer film comprising multiple layers, each containing silicon nitride, metal oxide, metal nitride, or metal oxynitride. That is, The semiconductor device according to claim 11.

13. The first insulating film is in contact with the first conductor. The semiconductor device according to claim 1.

14. The oxide semiconductor comprises at least one element from among indium, gallium, zinc, aluminum, and tin. The semiconductor device according to claim 1.

15. The said oxide semiconductor includes indium gallium zinc oxide, The semiconductor device according to claim 14.

16. The first insulating film is in contact with the side surface of the oxide semiconductor in the first region. The semiconductor device according to claim 1.

17. The oxide semiconductor and the first insulating film constitute a vertical transistor. The semiconductor device according to claim 1.

18. The first electrode acts as an electrode for a capacitor. The semiconductor device according to claim 1.

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