Semiconductor equipment

Abstract

Improve lithography margins. [Solution] One embodiment of a semiconductor device comprises a control circuit provided on a substrate and a plurality of conductors provided on a layer located away from the substrate in a first direction. The plurality of conductors include a first conductor, a second conductor, a third conductor, and a fourth conductor arranged in this order in a second direction. When a first voltage is applied to the first conductor, the control circuit is configured to apply a second voltage different from the first voltage to the third and fourth conductors so as to insulate them from the second conductor. The third and fourth conductors are arranged in a second direction with a first pitch. The first, second, and third conductors are arranged in a second direction with a second pitch of less than or equal to the first pitch.

Description

Technical Field

[0001] The embodiments relate to semiconductor devices.

Background Art

[0002] As a semiconductor device capable of storing data non-volatiley, a NAND flash memory is known. In a semiconductor device such as a NAND flash memory, a plurality of wirings are arranged in the same layer for high integration and large capacity.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the lithography margin.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment comprises a control circuit provided on a substrate and a plurality of conductors provided on a layer located away from the substrate in a first direction. The plurality of conductors include a first conductor, a second conductor, a third conductor, and a fourth conductor arranged in this order in a second direction. When a first voltage is applied to the first conductor, the control circuit is configured to apply a second voltage different from the first voltage to the third and fourth conductors so as to insulate them from the second conductor. The third and fourth conductors are arranged in the second direction at a first pitch. The first conductor, the second conductor, and the third conductor are arranged in the second direction at a second pitch less than or equal to the first pitch. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of a memory system including a memory device according to the first embodiment. [Figure 2] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a memory device according to the first embodiment. [Figure 3] A circuit diagram showing an example of the connections between the memory cell array, the row decoder module, and the driver module of a memory device according to the first embodiment. [Figure 4] A plan view showing an example of a planar layout of a memory cell array included in a memory device according to the first embodiment. [Figure 5] A plan view showing an example of region V in Figure 4, which is part of the planar layout of the memory cell array in the memory device according to the first embodiment. [Figure 6] A cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory cell array provided in a memory device according to the first embodiment. [Figure 7] A cross-sectional view along line VII-VII in Figure 6, showing an example of the cross-sectional structure of a memory pillar in a memory cell array according to the first embodiment. [Figure 8] A perspective view showing an overview of the bonding structure of a memory device according to the first embodiment. [Figure 9]A cross-sectional view showing an example of the cross-sectional structure of a memory device according to the first embodiment. [Figure 10] A plan view showing an example of a planar layout of wiring near the low decoder module of a memory device according to the first embodiment. [Figure 11] A plan view showing an example of a planar layout of wiring near the low decoder module of a memory device according to a modified example of the first embodiment. [Figure 12] A plan view showing an example of a planar layout of wiring near the low decoder module of a memory device according to the second embodiment. [Figure 13] A plan view showing an example of a planar layout of wiring near the low decoder module of a memory device according to a first modified example of the second embodiment. [Figure 14] A plan view showing an example of a planar layout of wiring near the low decoder module of a memory device according to a second modified example of the second embodiment. [Figure 15] A plan view showing an example of a planar layout of wiring near the low decoder module of a memory device according to a third modified example of the second embodiment. [Figure 16] A plan view showing an example of a planar layout of wiring near the low decoder module of a memory device according to the third embodiment. [Figure 17] A plan view showing an example of a planar layout of wiring near the low decoder module of a memory device according to the fourth embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. The dimensions and proportions in the drawings are not necessarily the same as those in reality.

[0008] In the following explanation, components having substantially the same function and structure will be assigned the same reference numeral. When elements with similar structures need to be specifically distinguished, different letters or numbers may be added to the end of the same reference numeral.

[0009] 1. First Embodiment 1.1 Functional Configuration 1.1.1 Memory System FIG. 1 is a block diagram showing an example of the configuration of a memory system including a memory device according to the first embodiment. The memory system 1 is a storage device configured to be connected to an external host (not shown). The memory system 1 is, for example, a memory card such as an SD TM card, a UFS (universal flash storage), or an SSD (solid state drive). The memory system 1 includes a memory controller 2 and a memory device 3.

[0010] The memory controller 2 is composed of an integrated circuit such as a SoC (system-on-a-chip), for example. The memory controller 2 controls the memory device 3 based on requests from the host. Specifically, for example, the memory controller 2 writes data requested to be written from the host to the memory device 3. Also, the memory controller 2 reads data requested to be read from the host from the memory device 3 and transmits it to the host.

[0011] The memory device 3 is a semiconductor device having a function of storing data non-volatilely. The memory device 3 is, for example, a NAND flash memory.

[0012] The communication between the memory controller 2 and the memory device 3 complies with, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0013] 1.1.2 Memory Device Continuing, referring to the block diagram shown in FIG. 1, the configuration of the memory device according to the first embodiment will be described.

[0014] <Overall Configuration> The memory device 3 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0015] The memory cell array 10 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). The number of blocks BLK included in the memory cell array 10 may be one or less. A block BLK is a collection of multiple memory cells. A block BLK is used, for example, as a data erasure unit. The memory cell array 10 is also provided with multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0016] The command register 11 stores the command CMD received by the memory device 3 from the memory controller 2. The command CMD includes instructions that cause the sequencer 13 to perform read operations, write operations, erase operations, etc.

[0017] The address register 12 stores the address information ADD received by the memory device 3 from the memory controller 2. The address information ADD includes, for example, the block address BAd, the page address PAAd, and the column address CAD. For example, the block address BAd, the page address PAAd, and the column address CAD are used for selecting the block BLK, word line, and bit line, respectively.

[0018] The sequencer 13 controls the operation of the entire memory device 3. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16, etc., based on the command CMD stored in the command register 11, to perform read operations, write operations, erase operations, etc.

[0019] The driver module 14 generates voltages used in read, write, and erase operations. Then, based on the page address PAd stored in the address register 12, for example, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line.

[0020] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address Bad stored in the address register 12. Then, the row decoder module 15 transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0021] During a write operation, the sense amplifier module 16 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 2. During a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line and transfers the determination result to the memory controller 2 as read data DAT.

[0022] <Memory cell array> Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array provided in the memory device according to the first embodiment. In Figure 2, one of the multiple block BLKs included in the memory cell array 10 is shown. As shown in Figure 2, the block BLK includes, for example, four string units SU0 to SU3.

[0023] Each string unit SU includes multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). The number of bit lines BL may be one or less. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, and stores data nonvolatilically. Each of the selection transistors ST1 and ST2 is used to select the string unit SU during various operations.

[0024] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. The drain of selection transistor ST1 is connected to the associated bit line BL. The source of selection transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. The drain of selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of selection transistor ST2 is connected to the source line SL.

[0025] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of selection transistors ST1 in string units SU0 to SU3 are connected to selection gate lines SGD0 to SGD3, respectively. The gates of multiple selection transistors ST2 are connected to the selection gate line SGS.

[0026] Bit lines BL0 to BLm are each assigned a different column address. Each bit line BL is shared among multiple block BLKs by a NAND string NS that is assigned the same column address. Word lines WL0 to WL7 are provided for each block BLK. Source lines SL are shared, for example, among multiple block BLKs.

[0027] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0028] The circuit configuration of the memory cell array 10 provided in the memory device 3 according to the first embodiment is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to any number.

[0029] <Raw Decoder Module> Figure 3 is a circuit diagram showing an example of the connection between the memory cell array, the row decoder module, and the driver module according to the first embodiment. As shown in Figure 3, the row decoder module 15 includes a plurality of row decoders RD (RD0, RD1, ...). The number of row decoders RD corresponds to the number of blocks BLK. Each of the plurality of row decoders RD has an equivalent configuration. In the example in Figure 3, the configuration of row decoder RD0 corresponding to block BLK0 is shown. Row decoder RD0 includes a block decoder BD and transistors TR0 to TR17.

[0030] Each of the transistors TR0 to TR12 is, for example, an N-type transistor. The first terminal of each of the transistors TR0 to TR7 is connected to block BLK0 via word lines WL0 to WL7, respectively. The second terminal of each of the transistors TR0 to TR7 is connected to driver module 14 via wirings CG0 to CG7, respectively. The gate of each of the transistors TR0 to TR7 is connected to block decoder BD via wiring BLKSEL.

[0031] For example, during a write operation, transistors TR0 to TR7 can each transfer the write voltage to the word lines WL0 to WL7. The write voltage is a high voltage that can raise the threshold voltage of the memory cell transistor MT. Therefore, transistors TR0 to TR7 have a high withstand voltage capable of transferring the write voltage. Hereinafter, transistors with a high withstand voltage capable of transferring the write voltage will also be called "high-voltage transistors" or "HV transistors". HV transistors have a gate oxide film thickness of at least 10 nm or more, and for transistors that can operate up to 30 V, it is designed to be, for example, around 40 nm. Transistors with a lower withstand voltage than HV transistors are also called "low-voltage transistors" or "LV transistors". LV transistors are designed, for example, to have a gate oxide film thickness of 5 nm or more and 7 nm or less. Transistors with an even lower withstand voltage than LV transistors are also called "ultra-low voltage transistors" or "VLV transistors". VLV transistors are designed, for example, so that the gate oxide film thickness is between 2.5 nm and 3.5 nm.

[0032] Transistor TR8 is, for example, an N-type HV transistor. The first end of transistor TR8 is connected to block BLK0 via the selection gate line SGS. The second end of transistor TR8 is connected to driver module 14 via wiring SGSD. The gate of transistor TR8 is connected to block decoder BD via wiring BLKSEL.

[0033] Each of the transistors TR9 to TR12 is, for example, an N-type HV transistor. The first terminal of each of the transistors TR9 to TR12 is connected to block BLK0 via the selection gate lines SGD0 to SGD3, respectively. The second terminal of each of the transistors TR9 to TR12 is connected to driver module 14 via the wirings SGDD0 to SGDD3, respectively. The gate of each of the transistors TR9 to TR12 is connected to block decoder BD via the wiring BLKSEL.

[0034] Transistor TR13 is, for example, an N-type HV transistor. The first end of transistor TR13 is connected to block BLK0 via the selection gate line SGS. The second end of transistor TR13 is connected to driver module 14 via wiring USGS. The gate of transistor TR13 is connected to block decoder BD via wiring BLKSELn.

[0035] Each of the transistors TR14 to TR17 is, for example, an N-type HV transistor. The first terminal of each of the transistors TR14 to TR17 is connected to block BLK0 via the selection gate lines SGD0 to SGD3, respectively. The second terminal of each of the transistors TR14 to TR17 is connected to driver module 14 via wiring USGD. The gate of each of the transistors TR14 to TR17 is connected to block decoder BD via wiring BLKSELn.

[0036] The block decoder BD supplies voltages of different logic levels to the wiring BLKSEL and BLKSELn. When block BLK0 is selected, the block decoder BD supplies a "H" level voltage to wiring BLKSEL and a "L" level voltage to wiring BLKSELn. When block BLK0 is not selected, the block decoder BD supplies a "L" level voltage to wiring BLKSEL and a "H" level voltage to wiring BLKSELn.

[0037] 1.2 Structure Next, the structure of the memory device according to the first embodiment will be described.

[0038] 1.2.1 Memory cell array First, we will describe the detailed structure of the memory cell array 10.

[0039] <Floor layout> Figure 4 is a plan view showing an example of a planar layout of a memory cell array in a memory device according to the first embodiment. In Figure 4, four blocks BLK0 to BLK3 are shown as examples of the multiple blocks BLK in the memory cell array 10.

[0040] The memory cell array 10 includes a stacked wiring structure. The stacked wiring structure is a structure in which wiring layers (word lines WL0 to WL7, and selected gate lines SGD and SGS) are stacked.

[0041] In the following, the plane approximately parallel to the stacking plane of the wiring layers will be referred to as the XY plane. The directions that are orthogonal to each other in the XY plane will be the X direction and the Y direction. The direction approximately perpendicular to the XY plane and moving from the selected gate line SGS to the selected gate line SGD will be referred to as the Z1 direction. The direction approximately perpendicular to the XY plane and moving from the selected gate line SGD to the selected gate line SGS will be referred to as the Z direction. If neither the Z1 direction nor the Z2 direction is specified, it will be referred to as the Z direction.

[0042] As shown in Figure 4, the stacked wiring structure has memory regions MRa and MRb aligned in the X direction, and a lead region HR. Memory regions MRa and MRb are regions where memory cell transistors MT are provided. The lead region HR is a region where contacts are provided to electrically connect each wiring layer and the low decoder module 15. The lead region HR is located, for example, between memory region MRa and memory region MRb.

[0043] Each of the multiple block BLKs includes a portion of the stacked wiring structure that extends in the X direction across the memory area MRa, the lead area HR, and the memory area MRb. The multiple block BLKs are aligned in the Y direction. The memory cell array 10 includes, for example, multiple members SLT and multiple members SHE.

[0044] Each SLT extends in the X direction so as to traverse the memory area MRa, the extraction area HR, and the memory area MRb. Multiple SLTs are aligned in the Y direction. Each SLT has a structure, for example, with an embedded insulator. Each SLT separates adjacent wiring layers through it. In the memory cell array 10, each region separated by an SLT corresponds to one block BLK.

[0045] Multiple member SHEs include multiple member SHEs aligned in the Y direction in memory area MRa and multiple member SHEs aligned in the Y direction in memory area MRb. Each member SHE located in memory area MRa extends in the X direction so as to traverse memory area MRa. Each member SHE located in memory area MRb extends in the X direction so as to traverse memory area MRb. In the example in Figure 4, in each of memory areas MRa and MRb, three member SHEs are arranged between two adjacent member SLTs in the Y direction. Each member SHE has, for example, a structure in which an insulator is embedded. Each member SHE separates the selected gate line SGD of the adjacent wiring layer through the member SHE. In the memory cell array 10, each region demarcated by a pair of adjacent member SLTs and SHEs, or a pair of two adjacent member SHEs, corresponds to one string unit SU.

[0046] The planar layout of the memory cell array 10 may be any other layout. For example, the number of member SHEs placed between two adjacent member SLTs can be designed to be any number. The number of string units SUs provided in each block BLK can be changed based on the number of member SHEs placed between two adjacent member SLTs.

[0047] Figure 5 is a plan view showing an example of region V in Figure 4, which is part of the planar layout of the memory cell array in the memory device according to the first embodiment. In Figure 5, the extraction region HR of block BLK0, and the boundary portion between the extraction region HR and the memory regions MRa and MRb are shown.

[0048] First, we will describe the planar layout of the memory cell array 10 in memory regions MRa and MRb.

[0049] As shown in Figure 5, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL in each of the memory regions MRa and MRb.

[0050] Each memory pillar MP functions as a single NAND string NS. Multiple memory pillar MPs are arranged in a staggered pattern, for example, 19 rows, in the region between two adjacent members SLT. For example, counting from the top of the paper, one member SHE is placed overlapping the 5th, 10th, and 15th memory pillar MPs.

[0051] Multiple bit lines BL are aligned in the X direction. Each bit line BL is positioned to overlap with at least one memory pillar MP for each string unit SU. In the example in Figure 5, two bit lines BL overlap one memory pillar MP. The memory pillar MP is electrically connected to one of the multiple overlapping bit lines BL via contact CV. On the other hand, contact CV between a memory pillar MP and a bit line BL that is in contact with two different selection gate lines SGD (i.e., overlapping with member SHE) may be omitted.

[0052] Furthermore, the planar layout in the memory area MR may be any other layout. For example, the number and arrangement of memory pillars MP and members SHE placed between two adjacent members SLT can be changed as appropriate. The number of bit lines BL overlapping each memory pillar MP can be designed to be any number.

[0053] Next, the planar layout of the memory cell array 10 in the extraction area HR will be described.

[0054] The memory cell array 10 includes a plurality of contacts CC in the lead-out region HR. The stacked wiring structure also has a terrace portion and a highway portion HW in the lead-out region HR. The terrace portion is the part in which the wiring layers constituting the stacked wiring structure do not overlap with the upper wiring layers in the Z1 direction. The highway portion HW is the part aligned with the terrace portion in the Y direction.

[0055] The stacked wiring structure forms a staircase structure in the terrace section. In the example in Figure 5, steps are formed between the selection gate line SGS and word line WL0, between word line WL0 and word line WL1, ..., between word line WL6 and word line WL7, and between word line WL7 and selection gate line SGD. Note that not all steps are necessarily aligned in one direction. For example, the selection gate line SGS and a portion of the word lines WL0 to WL7 (in the example in Figure 5, the selection gate line SGS and word lines WL0 to WL2) may form steps in descending order in the X direction, while the remaining portion (in the example in Figure 5, word lines WL3 to WL7) may form steps in ascending order in the X direction. Alternatively, for example, the selection gate line SGS and a portion of the word lines WL0 to WL7 may form steps in the Y direction.

[0056] The wiring layers of memory area MRa and memory area MRb are provided continuously via a highway section HW, except for the selection gate line SGD. In other words, the highway section HW is the part that electrically connects the wiring layers, excluding the selection gate line SGD, between memory area MRa and memory area MRb. The selection gate line SGD is divided into a portion for memory area MRa and a portion for memory area MRb by the lead-out section HR.

[0057] Contact CC is a conductor used to connect the row decoder module 15 to each wiring layer. Multiple contact CCs associated with block BLK are connected to the selection gate lines SGS and SGD provided in the lead-out area HR, and to the respective terrace portions of the word lines WL0 to WL7. Separate contact CCs are provided for the selection gate line SGD on the memory area MRa side and the selection gate line SGD on the memory area MRb side. The selection gate line SGD on the memory area MRa side and the selection gate line SGD on the memory area MRb side, which are associated with the same string unit SU, are electrically connected, for example, via their respective contact CCs and upper wiring layers (not shown).

[0058] <Cross-sectional structure> Figure 6 is a cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory cell array provided in the memory device according to the first embodiment. In Figure 6, the cross-sectional structure of a portion of the memory region MRb and the extraction region HR is shown.

[0059] As shown in Figure 6, the memory cell array 10 includes, for example, a semiconductor layer 21, wiring layers 22, 23, 24, a conductive layer 25 (25a and 25b), and insulating layers 31, 32, 33, 34, and 35. The insulating layers 31-35 include, for example, silicon oxide. In Figure 6, the Z1 direction corresponds to the top of the paper.

[0060] A semiconductor layer 21 is provided on the insulating layer 31. The semiconductor layer 21 is formed, for example, in the shape of a plate extending along the XY plane. The semiconductor layer 21 contains, for example, silicon and is used as a source wire SL.

[0061] An insulating layer 32 is provided on the semiconductor layer 21. A wiring layer 22 is provided on the insulating layer 32. The wiring layer 22 is formed, for example, in the shape of a plate extending along the XY plane. The wiring layer 22 contains, for example, tungsten and is used as a selectable gate wire (SGS).

[0062] Multiple insulating layers 33 and wiring layers 23 are alternately arranged on the wiring layer 22. The multiple wiring layers 23 are formed, for example, in a plate shape extending along the XY plane. The multiple wiring layers 23 contain, for example, tungsten and are used as word lines WL0 to WL7 in order from the semiconductor layer 21 side.

[0063] An insulating layer 34 is provided on the uppermost wiring layer 23. Another wiring layer 24 is provided on the insulating layer 34. The wiring layer 24 is formed, for example, in a plate shape extending along the XY plane. The wiring layer 24 contains, for example, tungsten and is used as a selected gate wire SGD.

[0064] In memory region MRb, each of the multiple memory pillars MP extends in the Z direction and penetrates the wiring layers 22-24 and the insulating layers 32-34. Although not shown in Figure 6, multiple memory pillars MP are similarly provided in memory region MRa.

[0065] Each of the multiple memory pillars MP includes, for example, a core film 41, a semiconductor film 42, and a multilayer film 43. The core film 41 is an insulator extending in the Z direction. The semiconductor film 42 covers the core film 41. The lower part of the semiconductor film 42 is in contact with the semiconductor layer 21. The multilayer film 43 covers the sides of the semiconductor film 42.

[0066] Figure 7 is a cross-sectional view along line VII-VII in Figure 6, showing an example of the cross-sectional structure of a memory pillar in a memory device according to the first embodiment. In Figure 7, a cross-section is shown that includes the memory pillar MP and the wiring layer 23 and is parallel to the XY plane. As shown in Figure 7, the laminated film 43 includes, for example, a tunnel insulating film 44, a charge storage film 45, and a block insulating film 46.

[0067] The core film 41 is provided, for example, in the central portion of the memory pillar MP. The semiconductor film 42 surrounds the sides of the core film 41. The tunnel insulating film 44 surrounds the sides of the semiconductor film 42. The charge storage film 45 surrounds the sides of the tunnel insulating film 44. The block insulating film 46 surrounds the sides of the charge storage film 45. The wiring layer 23 surrounds the sides of the block insulating film 46. The semiconductor film 42 is used as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The tunnel insulating film 44 and the block insulating film 46 each contain, for example, silicon oxide. The charge storage film 45 contains, for example, silicon nitride.

[0068] With the above configuration, each memory pillar MP functions as a single NAND string NS. That is, the portion where the memory pillar MP intersects with the wiring layer 22 functions as a selection transistor ST2. The portion where the memory pillar MP intersects with the wiring layer 23 functions as a memory cell transistor MT. The portion where the memory pillar MP intersects with the wiring layer 24 functions as a selection transistor ST1.

[0069] A contact CV is provided on the upper surface of the semiconductor film 42 in the Z1 direction of the memory pillar MP. A conductive layer 25a is provided on the upper surface of the contact CV in the Z1 direction. The conductive layer 25a is formed, for example, in the shape of a line extending in the Y direction. The conductive layer 25a contains, for example, copper and is used as a bit line BL.

[0070] In the lead-out region HR, each of the multiple contacts CC extends in the Z direction. Each of the multiple contacts CC is in contact with the terrace portion of the corresponding wiring layers 22-24, and is provided at a distance from the non-corresponding wiring layers 22-24.

[0071] A conductive layer 25b is provided on the upper surface of the contact CC in the Z1 direction. The conductive layer 25b contains, for example, copper and is provided in the same layer as the conductive layer 25a. Hereinafter, the layer on which the conductive layers 25a and 25b are provided will be referred to as layer M0.

[0072] An insulating layer 35 is provided so as to cover the stacked wiring structure, contacts CC and CV, and conductive layers 25a and 25b as described above.

[0073] 1.2.2 Memory Devices Next, we will describe the overall structure of memory device 3.

[0074] <Lamination structure> Figure 8 is a perspective view showing an overview of the bonded structure of a memory device according to the first embodiment. As shown in Figure 8, the memory device 3 comprises a memory chip 100 and a circuit chip 200. The memory chip 100 includes a structure corresponding to a memory cell array 10. The circuit chip 200 includes structures corresponding to, for example, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0075] Furthermore, each of the memory chip 100 and the circuit chip 200 includes a plurality of bonding pads BP. The memory device 3 is formed by bonding the memory chip 100 and the circuit chip 200 together via a plurality of bonding pads BP. That is, the Z2 direction side of the circuit chip 200 is bonded to the Z1 direction side of the memory chip 100.

[0076] <Cross-sectional structure> Figure 9 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to the first embodiment. In Figure 9, the Z2 direction corresponds to the top of the paper.

[0077] As shown in Figure 9, the memory device 3 further includes conductive layers 26 and 27, a protective layer 30, and contacts V0 and V1 in the memory chip 100. The memory device 3 also includes, in the circuit chip 200, a substrate 50, an insulating layer 51, conductive layers 52, 53, 54, and 55, an insulating member STI, a transistor TR0, and contacts CS, C0, C1, C2, and C3.

[0078] First, let me explain the memory chip 100.

[0079] The protective layer 30 is provided on the upper surface of the insulating layer 31 in the Z2 direction. The protective layer 30 is a layer corresponding to the surface of the memory device 3 and includes, for example, a resin material such as polyimide. In areas not shown, a portion of the protective layer 30 is removed. A power pad, which is responsible for electrical connection to the outside, is provided in the portion where the protective layer 30 has been removed.

[0080] A contact V0 is provided on the upper surface of each of the conductive layers 25a and 25b in the Z1 direction. A conductive layer 26 is provided on the upper surface of the contact V0 in the Z1 direction.

[0081] A contact V1 is provided on the upper surface of the conductive layer 26 in the Z1 direction. A conductive layer 27 is provided on the upper surface of contact V1 in the Z1 direction. The conductive layer 27 functions as a bonding pad BP on the bonding surface of the memory chip 100 with the circuit chip 200. The conductive layers 26 and 27, and contacts V0 and V1 are covered by an insulating layer 35. Hereinafter, the layers on which the conductive layers 26 and 27 are provided will be referred to as layer M1 and bonding layer B1, respectively.

[0082] Next, we will explain the circuit chip 200.

[0083] The substrate 50 is a silicon substrate. An insulating layer 51 is provided on the upper surface of the substrate 50 in the Z2 direction. Multiple transistors TR are provided on the substrate 50 and the insulating layer 51. Multiple transistors TR constitute various circuits provided on the circuit chip 200. In Figure 9, as an example, transistor TR0, which constitutes the low decoder module 15, is shown among the multiple transistors TR.

[0084] A contact C0 is provided on the upper surface of the gate electrode of transistor TR0 in the Z2 direction. A contact CS is provided on the upper surface of the region of the substrate 50 that functions as the source or drain of transistor TR0 in the Z2 direction. A conductive layer 52 is provided on the upper surface of each of the contacts C0 and CS in the Z2 direction.

[0085] A contact C1 is provided on the upper surface of the conductive layer 52 in the Z2 direction. A conductive layer 53 is provided on the upper surface of contact C1 in the Z2 direction. A contact C2 is provided on the upper surface of conductive layer 53 in the Z2 direction. A conductive layer 54 is provided on the upper surface of contact C2 in the Z2 direction. A contact C3 is provided on the upper surface of conductive layer 54 in the Z2 direction. A conductive layer 55 is provided on the upper surface of contact C3 in the Z2 direction. Conductive layer 55 is in contact with the corresponding conductive layer 27 and functions as an adhesive pad BP on the bonding surface of the circuit chip 200 with the memory chip 100. Conductive layers 52, 53, 54, and 55, as well as contacts CS, C0, C1, C2, and C3, are covered by an insulating layer 51. Hereinafter, the layers on which the conductive layers 52, 53, 54, and 55 are provided will be referred to as layers D0, D1, D2, and the bonding layer B2, respectively.

[0086] 1.2.3 Raw Decoder Module Next, we will describe the wiring layout near the low decoder module 15.

[0087] Figure 10 is a plan view showing an example of a planar layout of wiring near the low decoder module of a memory device according to the first embodiment. Figure 10 shows an example of a planar layout of a plurality of conductive layers 52 provided in layer D0.

[0088] Note that while Figure 10 shows a planar layout in layer D0 as an example, the vicinity of the raw decoder module 15 is not limited to layer D0. For example, layers D1 and D2 are also in the vicinity of the raw decoder module 15 and may have characteristics equivalent to the planar layout in layer D0, as shown below.

[0089] As shown in Figure 10, in layer D0, the multiple conductive layers 52 form a periodic line-and-space pattern. The multiple conductive layers 52 include multiple conductive layers 52A, 52B, and 52C.

[0090] The multiple conductive layers 52A are a group of wirings that do not generate a relatively large potential difference between them during write and read operations. Each of the multiple conductive layers 52A extends in the X direction. The multiple conductive layers 52A are arranged at equal intervals in the Y direction with a pitch P1. Each of the multiple conductive layers 52A has a line width W1. That is, the space between two adjacent conductive layers 52A is (P1-W1). The pitch P1 and line width W1 are, for example, 120 nanometers (nm) or less and 60 nm or less, respectively.

[0091] The multiple conductive layers 52B are a group of wires that do not generate a relatively large potential difference from each other during write and read operations. Each of the multiple conductive layers 52B extends in the X direction. The multiple conductive layers 52B are arranged at equal intervals in the Y direction with a pitch P1. Each of the multiple conductive layers 52B has a line width W1. That is, the space between two adjacent conductive layers 52B is (P1-W1).

[0092] In a given operation, the potential difference between the voltage applied to multiple conductive layers 52B and the voltage applied to multiple conductive layers 52A can be relatively large. For example, when a high voltage is applied to multiple conductive layers 52A, a low voltage may be applied to multiple conductive layers 52B. When a low voltage is applied to multiple conductive layers 52A, a high voltage may be applied to multiple conductive layers 52B. In the following, it will be assumed that the potential difference between the voltage applied to multiple conductive layers 52B and the voltage applied to multiple conductive layers 52A in a given operation is, for example, 15V or more. Furthermore, it will be assumed that the potential difference between the voltages applied to multiple conductive layers 52A and the potential difference between the voltages applied to multiple conductive layers 52B in a given operation is, for example, less than 15V.

[0093] The conductive layer 52C is a wiring that is not subjected to a predetermined voltage (floating state) during writing and reading operations. In other words, the conductive layer 52C is electrically insulated from various circuits formed on the substrate 50, such as the low decoder module 15. The conductive layer 52C extends in the X direction. The conductive layer 52C is provided between a plurality of conductive layers 52A and a plurality of conductive layers 52B. The conductive layer 52C and the conductive layer 52A adjacent to the conductive layer 52C are aligned in the Y direction with a pitch P1. The conductive layer 52C and the conductive layer 52B adjacent to the conductive layer 52C are aligned in the Y direction with a pitch P1. The conductive layer 52C has a line width W1. In other words, the space between adjacent conductive layers 52A and conductive layer 52C, and the space between adjacent conductive layers 52B and conductive layer 52C are both (P1-W1).

[0094] Thus, in layer D0, multiple conductive layers 52A, 52B, and 52C are arranged at equal intervals in the Y direction with a pitch P1. In this case, the space between adjacent conductive layers 52A and 52B (excluding the line width of conductive layer 52C) via conductive layer 52C is (P1-W1)×2. This space (P1-W1)×2 between conductive layers 52A and 52B is designed so that the dielectric strength of the insulator provided in this space exceeds the potential difference that may occur between conductive layers 52A and 52B. In other words, the space (P1-W1)×2 between conductive layers 52A and 52B is designed to be greater than or equal to a threshold based on the potential difference between conductive layers 52A and 52B.

[0095] As mentioned above, no potential difference of the magnitude that can occur between conductive layer 52A and conductive layer 52B occurs between multiple conductive layers 52A. Similarly, no potential difference of the magnitude that can occur between conductive layer 52A and conductive layer 52B occurs between multiple conductive layers 52B. For this reason, the space (P1-W1) between two adjacent conductive layers 52A, and the space (P1-W1) between two adjacent conductive layers 52B, may be designed such that the dielectric strength of the insulator provided in the space is below the potential difference that can occur between conductive layer 52A and conductive layer 52B. In this case, the conductive layers 52A and 52C adjacent to each other in the space (P1-W1), and conductive layers 52B and 52C, may also be designed so that their dielectric strength is below a threshold based on the potential difference between conductive layer 52A and conductive layer 52B.

[0096] 1.3 Effects of the First Embodiment According to the first embodiment, a conductive layer 52C is placed between conductive layer 52A and conductive layer 52B. The space (P1-W1) × 2 between conductive layer 52A and conductive layer 52B is greater than or equal to a threshold based on the potential difference between conductive layer 52A and conductive layer 52B. The space (P1-W1) between conductive layer 52A and conductive layer 52C, and the space (P1-W1) between conductive layer 52B and conductive layer 52C are less than a threshold based on the potential difference between conductive layer 52A and conductive layer 52B. This makes it possible to improve the lithography margin (process tolerance) while ensuring the dielectric strength of the insulator provided in the space between conductive layer 52A and conductive layer 52B.

[0097] To elaborate, as the number of stacked word lines WL increases, the number of wires connecting the low decoder module 15 and the word lines WL also increases. With this increase in the number of wires, miniaturization (narrowing of the pitch) is required for the conductive layer 52 located in layer D0. On the other hand, under lighting conditions necessary to achieve fine pattern formation, the lithography margin for intermediate pitches around twice the minimum pitch may decrease. Therefore, when applying a narrow pitch such that the minimum pitch is 120 nm or less, it is necessary to form the pattern without using intermediate pitches.

[0098] According to the first embodiment, a conductive layer 52C is placed between conductive layer 52A and conductive layer 52B, while conductive layers 52A, 52B, and 52C are arranged at equal intervals with a pitch P1. This makes it possible to make the space between conductive layer 52A and conductive layer 52B (P1-W1) × 2 twice the space between adjacent conductive layers 52 (P1-W1). Therefore, it is possible to ensure the dielectric strength of the insulator provided between conductive layer 52A and conductive layer 52B.

[0099] Furthermore, by placing conductive layer 52C between conductive layers 52A and 52B, it is possible to suppress the pitch between adjacent conductive layers 52A and 52B from becoming an intermediate pitch of about twice the pitch P1. Therefore, it is possible to avoid applying a pitch that locally reduces the lithography margin under lighting conditions required to achieve fine pattern formation.

[0100] In addition, by arranging the conductive layers 52A, 52B, and 52C at equal intervals with a pitch P1, the lithography margin can be improved compared to arrangements where the pitch varies.

[0101] 1.4 Modifications of the First Embodiment The first embodiment can be modified in various ways. The following mainly describes configurations that differ from the first embodiment. Configurations equivalent to the first embodiment will be omitted from the description as appropriate.

[0102] In the first embodiment described above, a case was described in which a plurality of conductive layers 52A, 52B, and 52C aligned in the Y direction are arranged at an equal pitch P1, but the invention is not limited to this. For example, the pitch between adjacent conductive layers 52A and 52C, and the pitch between adjacent conductive layers 52B and 52C, may be shorter than the pitch P1.

[0103] Figure 11 is a plan view showing an example of a planar layout of wiring near the low decoder module of a Mori Device according to a modified example of the first embodiment. Figure 11 corresponds to Figure 10 in the first embodiment.

[0104] As shown in Figure 11, in layer D0, the multiple conductive layers 52 may include multiple conductive layers 52A, 52B, and 52Cn.

[0105] The conductive layer 52Cn is a wiring that is not subjected to a predetermined voltage during write and read operations (i.e., is in a floating state). The conductive layer 52Cn extends in the X direction. The conductive layer 52Cn is provided between a plurality of conductive layers 52A and a plurality of conductive layers 52B. The conductive layer 52Cn and the conductive layer 52A adjacent to the conductive layer 52Cn are aligned in the Y direction with a pitch P2 shorter than the pitch P1. The conductive layer 52Cn and the conductive layer 52B adjacent to the conductive layer 52Cn are aligned in the Y direction with a pitch P2. The conductive layer 52Cn has a line width W2 shorter than the line width W1. That is, the space between adjacent conductive layers 52A and conductive layer 52Cn, and the space between adjacent conductive layers 52B and conductive layer 52Cn are both (P2 - W1 / 2 - W2 / 2). The pitch P2 and line width W2 are, for example, 110 nanometers (nm) or less and 55 nm or less, respectively. As described above, the conductive layer 52Cn is a floating wiring and, unlike conductive layers 52A and 52B, is not subject to constraints regarding wiring resistance. Therefore, the pitch P2 and line width W2 of the conductive layer 52Cn can be shorter than the pitch P1 and line width W1 of conductive layers 52A and 52B, which are subject to constraints regarding wiring resistance.

[0106] The space between adjacent conductive layers 52A and 52B separated by conductive layer 52Cn (excluding the line width of conductive layer 52Cn) is (P2 - W1 / 2 - W2 / 2) × 2. This space between conductive layer 52A and conductive layer 52B (P2 - W1 / 2 - W2 / 2) × 2 is designed such that the dielectric strength of the insulator provided in this space exceeds the potential difference that may occur between conductive layer 52A and conductive layer 52B.

[0107] As described above, by making the pitch P2 shorter than the pitch P1 between conductive layer 52A and conductive layer 52Cn, and between conductive layer 52B and conductive layer 52Cn, the layout size of the conductive layer 52 in layer D0 can be reduced within the range that satisfies the dielectric strength constraints.

[0108] 2. Second Embodiment Next, a memory device according to the second embodiment will be described. In the second embodiment, a planar layout around the wiring that functions as a pad is shown. The following description will mainly focus on configurations that differ from the first embodiment. Configurations equivalent to those in the first embodiment will be omitted as appropriate.

[0109] 2.1 Configuration Figure 12 is a plan view showing an example of a planar layout of wiring near the raw decoder module of a memory device according to the second embodiment. Figure 12 corresponds to Figure 10 in the first embodiment.

[0110] As shown in Figure 12, in layer D0, the multiple conductive layers 52 include multiple conductive layers 52Ap, 52B, and 52C.

[0111] The conductive layer 52Ap is a wiring having a pad portion connected to contact C1, for example. The pad portion of the conductive layer 52Ap has a line width W3. The line width W3 is designed to be an odd multiple of the line width W1. In the example in Figure 12, the case where the line width W3 is three times the line width W1 is shown.

[0112] Furthermore, the conductive layer 52Ap may have a wiring portion connected to the pad portion and extending in the X direction. The wiring portion of the conductive layer 52Ap has a line width W1. By making the pad portion of the conductive layer 52Ap an odd multiple of the line width W1, the wiring portion of the conductive layer 52Ap can be provided in the Y direction at a pitch P1.

[0113] The multiple conductive layers 52B are a group of wires that do not generate a relatively large potential difference between them during write and read operations. The multiple conductive layers 52B are arranged in the Y direction, flanking the conductive layer 52Ap. Adjacent conductive layers 52B are arranged at equal intervals in the Y direction with a pitch P1. Each of the multiple conductive layers 52B has a line width W1. That is, the space between two adjacent conductive layers 52B is (P1-W1).

[0114] In a given operation, the potential difference between the voltage applied to multiple conductive layers 52B and the voltage applied to conductive layer 52Ap can be relatively large. For example, when a high voltage is applied to conductive layer 52Ap, a low voltage may be applied to multiple conductive layers 52B. When a low voltage is applied to conductive layer 52Ap, a high voltage may be applied to multiple conductive layers 52B.

[0115] A conductive layer 52C is provided between conductive layer 52Ap and a plurality of conductive layers 52B arranged at a pitch P1. Conductive layer 52C is a wiring that is not subjected to a predetermined voltage during write and read operations (i.e., is in a floating state). Conductive layer 52C and conductive layer 52B adjacent to conductive layer 52C are arranged at a pitch P1 in the Y direction. Conductive layer 52C and the wiring portion of conductive layer 52Ap are arranged at a pitch P1 in the Y direction. Conductive layer 52C has a line width W1. That is, the space between adjacent conductive layers 52Ap and conductive layer 52C, and the space between adjacent conductive layers 52B and conductive layer 52C are both (P1-W1).

[0116] Thus, in layer D0, the wiring sections 52B and 52C of the multiple conductive layers 52Ap are arranged at equal intervals in the Y direction with a pitch P1. In this case, the space between adjacent conductive layers 52Ap and 52B (excluding the line width of conductive layer 52C) via conductive layer 52C is (P1-W1)×2. This space (P1-W1)×2 between conductive layer 52Ap and conductive layer 52B is designed such that the dielectric strength of the insulator provided in this space exceeds the potential difference that may occur between conductive layer 52Ap and conductive layer 52B.

[0117] As mentioned above, no potential difference of the magnitude that could occur between conductive layer 52Ap and conductive layer 52B occurs between multiple conductive layers 52B. For this reason, the space (P1-W1) between two adjacent conductive layers 52B may be designed such that the dielectric strength of the insulator provided in that space is lower than the potential difference that could occur between conductive layer 52Ap and conductive layer 52B.

[0118] 2.2 Effects according to the second embodiment According to the second embodiment, a conductive layer 52C is placed between conductive layer 52Ap and conductive layer 52B. The space (P1-W1) × 2 between the wiring portion of conductive layer 52Ap and conductive layer 52B is greater than or equal to a threshold based on the potential difference between conductive layer 52Ap and conductive layer 52B. The space (P1-W1) between the wiring portion of conductive layer 52Ap and conductive layer 52C, and the space (P1-W1) between conductive layer 52B and conductive layer 52C are less than a threshold based on the potential difference between conductive layer 52Ap and conductive layer 52B. As a result, similar to the first embodiment, the lithography margin can be improved while ensuring the dielectric strength of the insulator provided in the space between conductive layer 52Ap and conductive layer 52B.

[0119] 2.3 Modified Examples of the Second Embodiment The second embodiment can be modified in various ways.

[0120] 2.3.1 First Modification of the Second Embodiment In the second embodiment, a case was described in which the wiring portions, 52B, and 52C of multiple conductive layers 52Ap arranged in the Y direction are arranged at equal intervals P1, but the embodiment is not limited to this. For example, the pitch between adjacent conductive layers 52Ap and 52C, and the pitch between adjacent conductive layers 52B and 52C, may be shorter than the pitch P1 between other wirings. Below, configurations different from the second embodiment will be mainly described. Configurations equivalent to the second embodiment will be omitted from the description as appropriate.

[0121] Figure 13 is a plan view showing an example of a planar layout of wiring near the low decoder module of a Mori Device according to a first modified example of the second embodiment. Figure 13 corresponds to Figure 12 in the second embodiment.

[0122] As shown in Figure 13, in layer D0, the multiple conductive layers 52 may include multiple conductive layers 52Ap, 52B, and 52Cn.

[0123] A conductive layer 52Cn is provided between conductive layer 52Ap and a plurality of conductive layers 52B arranged at a pitch P1. Conductive layer 52Cn is a wiring that is not subjected to a predetermined voltage during write and read operations (i.e., is in a floating state). Conductive layer 52Cn and the wiring portion of conductive layer 52Ap adjacent to conductive layer 52Cn are arranged at a pitch P2 shorter than pitch P1 in the Y direction. Conductive layer 52Cn and conductive layer 52B adjacent to conductive layer 52Cn are arranged at a pitch P2 in the Y direction. Conductive layer 52Cn has a line width W2. That is, the space between adjacent conductive layers 52Ap and conductive layer 52Cn, and the space between adjacent conductive layers 52B and conductive layer 52Cn are both (P2-W1 / 2-W2 / 2). As described above, the conductive layer 52Cn is a floating wiring and, unlike conductive layers 52Ap and 52B, is not subject to constraints regarding wiring resistance. Therefore, the pitch P2 and line width W2 of the conductive layer 52Cn can be shorter than the pitch P1 and line width W1 of conductive layers 52A and 52B, which are subject to constraints regarding wiring resistance.

[0124] The space between adjacent conductive layers 52Ap and 52B, separated by conductive layer 52Cn (excluding the line width of conductive layer 52Cn), is (P2 - W1 / 2 - W2 / 2) × 2. This space (P2 - W1 / 2 - W2 / 2) × 2 between conductive layer 52Ap and conductive layer 52B is designed such that the dielectric strength of the insulator provided in this space exceeds the potential difference that may occur between conductive layer 52Ap and conductive layer 52B.

[0125] As described above, by making the pitch P2 shorter than the pitch P1 between the conductive layer 52Ap and the conductive layer 52Cn, and between the conductive layer 52B and the conductive layer 52Cn, the layout size of the conductive layer 52 in layer D0 can be reduced within the range that satisfies the dielectric strength constraints.

[0126] 2.3.2 Second Modification of the Second Embodiment In the first modification of the second embodiment, the case in which the line width W3 of the pad portion of the conductive layer 52Ap is longer than the line width W1 of the conductive layer 52B was described, but the invention is not limited to this case. Below, configurations different from the first modification of the second embodiment will be mainly described. Configurations equivalent to the first modification of the second embodiment will be omitted from the description as appropriate.

[0127] Figure 14 is a plan view showing an example of a planar layout of wiring near the low decoder module of the Mori Device according to a second modified example of the second embodiment. Figure 14 corresponds to Figure 13 in the first modified example of the second embodiment.

[0128] As shown in Figure 14, the line width W3 of the pad portion of the conductive layer 52Ap may be equal to the line width W1 of the conductive layer 52B. In this case, the contact C1 connected to the pad portion of the conductive layer 52Ap may have a portion that does not overlap with the pad portion when viewed in the Z direction.

[0129] At the connection point with contact C1, the space between the conductive layer 52Ap and the conductive layer 52B (excluding the conductive layer 52Cn) is shorter than the space (P2-W1 / 2-W2 / 2)×2 by the length t by which contact C1 extends beyond the pad portion of the conductive layer 52Ap. Therefore, when contact C1 is connected with the contact extending beyond the pad portion of the conductive layer 52Ap, the dielectric strength of the insulator provided in the space ((P2-W1 / 2-W2 / 2)×2-t) between the conductive layer 52Ap and the conductive layer 52B at the connection point with contact C1 is designed to exceed the potential difference that may occur between the conductive layer 52Ap and the conductive layer 52B.

[0130] 2.3.3 Third Modified Example of the Second Embodiment In the second modification of the second embodiment, a case was described in which the dielectric strength of the insulator provided in the space between the conductive layer 52Ap and the conductive layer 52B at the connection portion with contact C1 ((P2-W1 / 2-W2 / 2)×2-t) is designed to exceed the potential difference that may occur between the conductive layer 52Ap and the conductive layer 52B, but the invention is not limited to this. Below, configurations different from the second modification of the second embodiment will be mainly described. Configurations equivalent to the second modification of the second embodiment will be omitted from the description as appropriate.

[0131] Figure 15 is a plan view showing an example of a planar layout of wiring near the low decoder module of the Mori Device according to a third modified example of the second embodiment. Figure 15 corresponds to Figure 14 in the second modified example of the second embodiment.

[0132] As shown in Figure 15, in the region between the conductive layer 52Ap and conductive layer 52B at the connection portion with contact C1, the conductive layer 52Cn may be divided in the X direction. Such a divided structure of the conductive layer 52Cn can be realized by using SRAF (sub-resolution assist feature) in the mask pattern used when forming the wiring pattern of layer D0.

[0133] In this case, the space between the conductive layer 52Ap and the conductive layer 52B at the connection point with contact C1 is longer by the line width W2 of the conductive layer 52Cn than the area where the conductive layer 52Cn is provided. As a result, the thickness of the insulator provided in the space between the conductive layer 52Ap and the conductive layer 52B in the area where the conductive layer 52Cn is not provided can be set to ((P2-W1 / 2-W2 / 2)×2-t+W2). Therefore, the dielectric strength of the insulator can be locally increased by the line width W2 of the conductive layer 52Cn. Consequently, the effects of contact C1 protruding from the conductive layer 52Ap can be mitigated.

[0134] 3. Third Embodiment Next, a memory device according to the third embodiment will be described. In the third embodiment, a planar layout is shown in which wiring that does not generate a large potential difference with respect to the pads is arranged around the wiring that functions as pads. The following description will mainly focus on configurations that differ from the second embodiment. Configurations equivalent to those in the second embodiment will be omitted as appropriate.

[0135] 3.1 Configuration Figure 16 is a plan view showing an example of a planar layout of wiring near the raw decoder module of a memory device according to the third embodiment. Figure 16 corresponds to Figure 12 in the second embodiment.

[0136] As shown in Figure 16, in layer D0, the plurality of conductive layers 52 include the plurality of conductive layers 52Ap and 52A.

[0137] The multiple conductive layers 52A are a group of wires that do not generate a relatively large potential difference between them during write and read operations. The multiple conductive layers 52A are arranged in the Y direction, flanking the conductive layer 52Ap. Adjacent conductive layers 52A are arranged at equal intervals in the Y direction with a pitch P1. Each of the multiple conductive layers 52A has a line width W1. That is, the space between two adjacent conductive layers 52A is (P1-W1).

[0138] In a given operation, a relatively large potential difference does not occur between the voltage applied to multiple conductive layers 52A and the voltage applied to conductive layer 52Ap. For example, if a high voltage is applied to conductive layer 52Ap, a high voltage may also be applied to multiple conductive layers 52A. If a low voltage is applied to conductive layer 52Ap, a low voltage may also be applied to multiple conductive layers 52A.

[0139] The wiring portion of conductive layer 52Ap and the conductive layer 52A adjacent to conductive layer 52Ap are aligned in the Y direction with a pitch P1. That is, the space between adjacent conductive layers 52Ap and conductive layer 52A is (P1-W1).

[0140] 3.2 Effects of the Third Embodiment According to the third embodiment, the conductive layer 52Ap having a pad portion and the plurality of conductive layers 52A are arranged at equal intervals with a pitch P1. This makes it possible to improve the lithography margin compared to the case where the pitch between the conductive layer 52Ap and the conductive layer 52A is different from the pitch between the plurality of conductive layers 52.

[0141] The above arrangement is valid when no relatively large potential difference occurs between the conductive layer 52Ap and the adjacent conductive layer 52A. When a relatively large potential difference occurs between the conductive layer 52Ap and the adjacent conductive layer, as in the second embodiment, a floating conductive layer 52C can be interposed between the conductive layer 52Ap and the adjacent conductive layer to suppress a decrease in the lithography margin while satisfying the dielectric strength requirement.

[0142] 4. Fourth Embodiment Next, a memory device according to the fourth embodiment will be described. In the fourth embodiment, a planar layout is shown in which the conductive layer 52 has a portion that functions as a current path and a portion that does not function as a current path. The following description will mainly focus on configurations that differ from the second embodiment. Configurations equivalent to those in the second embodiment will be omitted as appropriate.

[0143] 4.1 Configuration Figure 17 is a plan view showing an example of a planar layout of wiring near the raw decoder module of a memory device according to the fourth embodiment. Figure 17 corresponds to Figure 12 in the second embodiment.

[0144] As shown in Figure 17, in layer D0, the plurality of conductive layers 52 include conductive layer 52Ap'. Conductive layer 52Ap' includes two pad portions, an active wiring portion, and a plurality of inactive wiring portions.

[0145] The two pad sections are aligned in the Y direction relative to each other.

[0146] The active wiring section extends in the Y direction and connects the two pad sections. The active wiring section functions as a path for the current flowing between the two pad sections.

[0147] Each of the multiple inactive wiring sections extends in the X direction and has a first end connected to an active wiring section. The multiple inactive wiring sections are parts that do not function as a path for current flowing between the two pad sections. In other words, the multiple inactive wiring sections are parts that do not contribute to the function of the conductive layer 52Ap' as wiring.

[0148] Multiple inactive wiring sections are arranged at equal intervals in the Y direction with a pitch P2. Each of the multiple inactive wiring sections has a line width W2. That is, the space between two adjacent inactive wiring sections is (P2-W2).

[0149] 4.2 Effects of the Fourth Embodiment According to the fourth embodiment, the inactive wiring sections are arranged at equal intervals in the Y direction with a pitch P2 shorter than the pitch P1. This makes it possible to suppress the reduction in lithography margin compared to when the inactive wiring sections are arranged with a pitch P1.

[0150] 5. Others The above-described embodiments can be modified in various ways.

[0151] In the fourth embodiment described above, the case in which the inactive wiring section is connected to the active wiring section was explained, but the invention is not limited to this. For example, the inactive wiring section may be separated from the active wiring section. In this case, the inactive wiring section becomes a floating wiring. This separates the unnecessary portion other than the current path from the conductive layer 52Ap', thereby reducing the wiring capacitance of the conductive layer 52Ap'. However, when the inactive wiring section is separated from the active wiring section, the lithography margin at the separation point may decrease. For this reason, from the viewpoint of improving the lithography margin, it is preferable that the inactive wiring section is connected to the active wiring section.

[0152] In the first, second, third, and fourth embodiments described above, memory devices such as NAND flash memory were described as examples of semiconductor devices to which the above-described wiring layout is applied, but the invention is not limited to these. For example, the above-described wiring layout can be applied to memory devices other than NAND flash memory. Furthermore, the above-described wiring layout is not limited to memory devices, but can be applied to any semiconductor device that has a line-and-space wiring layout.

[0153] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0154] 1…Memory system 2…Memory controller 3…Memory devices 10…Memory cell array 11... Command Register 12…Address Register 13… Sequencer 14…Driver module 15… Raw Decoder Module 16…Sense Amp Module 50... Circuit board 21… Semiconductor layer 22,23,24...wiring layer 25,26,27,52,52A,52Ap,52Ap',52B,52C,52Cn,53,54,55...Conductor layer 30…Protective layer 31, 32, 33, 34, 35, 51… Insulating layer 41… Core film 42… Semiconductor film 43…Multilayer film 44...Tunnel insulating film 45...Charge storage film 46…Block Insulating Film 100...memory chips 200... Circuit chips

Claims

1. A control circuit provided on the circuit board, A plurality of conductors provided in a first layer located away from the substrate in a first direction, Equipped with, The plurality of conductors include a first conductor, a second conductor, a third conductor, and a fourth conductor arranged in this order in the second direction. The aforementioned control circuit is When a first voltage is applied to the first conductor, a second voltage different from the first voltage is applied to the third conductor and the fourth conductor. Insulated from the aforementioned second conductor, It is configured in such a way, The third conductor and the fourth conductor are arranged in the second direction at a first pitch, The first conductor, the second conductor, and the third conductor are arranged in the second direction at a second pitch less than or equal to the first pitch. Semiconductor equipment.

2. The aforementioned second pitch is equal to the aforementioned first pitch. The semiconductor device according to claim 1.

3. The aforementioned second pitch is shorter than the aforementioned first pitch. The semiconductor device according to claim 1.

4. The space between the first conductor and the third conductor is greater than or equal to a threshold based on the potential difference between the first voltage and the second voltage. The space between the first conductor and the second conductor, and the space between the third conductor and the second conductor are less than the threshold. The semiconductor device according to claim 1.

5. The first pitch is 120 nm or less. The second pitch is 110 nm or less. The semiconductor device according to claim 3.

6. The line widths of the first conductor, the third conductor, and the fourth conductor are 60 nm or less. The line width of the second conductor is 55 nm or less. The semiconductor device according to claim 3.

7. The first conductor includes a pad portion having a line width that is an odd multiple of the line width of the third conductor. The semiconductor device according to claim 2.

8. The first conductor includes a pad portion having a line width that is an odd multiple of the line width of the third conductor. The semiconductor device according to claim 3.

9. The device further comprises a contact extending in the first direction and connecting to the pad portion of the first conductor, The contact has a portion that does not overlap with the first conductor when viewed in the first direction. The semiconductor device according to claim 8.

10. The second conductor is divided in a third direction intersecting the second direction in the region between the connection portion between the pad portion of the first conductor and the contact and the third conductor. The semiconductor device according to claim 9.

11. The aforementioned potential difference is 15V or more. The semiconductor device according to claim 4.

12. A plurality of wiring layers arranged apart from each other in the first direction, A memory pillar extending in the first direction, the portion of which intersects each of the plurality of wiring layers functions as a memory cell, Furthermore, The control circuit is connected to the plurality of wiring layers via the plurality of conductors. The semiconductor device according to claim 1.

13. A control circuit provided on the circuit board, Multiple wiring layers arranged apart from each other in the first direction, A memory pillar extending in the first direction, the portion of which intersects each of the plurality of wiring layers functions as a memory cell, A plurality of conductors are provided in the first layer located between the substrate and the plurality of wiring layers, and each conductor connects the control circuit to the plurality of wiring layers, Equipped with, The plurality of conductors includes a plurality of first conductors and second conductors arranged in a first pitch in a second direction, The second conductor includes a pad portion having a line width that is an odd multiple of the line width of each of the plurality of first conductors. Semiconductor equipment.

14. A control circuit provided on the circuit board, A plurality of conductors provided in a first layer located away from the substrate in a first direction, Equipped with, The plurality of conductors includes a plurality of first conductors and second conductors, each connected to the control circuit. The plurality of first conductors are arranged in a first pitch in the second direction, The second conductor is The first pad section and The first pad portion and the second pad portion, which is aligned in the second direction, A first wiring section connecting the first pad section and the second pad section and extending in the second direction, Each of the second wiring sections extends from the first wiring section in a third direction intersecting the second direction, and in the second direction, a plurality of second wiring sections are arranged with a second pitch shorter than the first pitch, including, Semiconductor equipment.

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