Semiconductor device and method for manufacturing the same

Abstract

To improve the performance of semiconductor devices. [Solution] The semiconductor chip CP has an n-type semiconductor layer NS1, an n-type semiconductor layer NS2 formed on the upper surface of the n-type semiconductor layer NS1, and an n-type semiconductor region NS3 formed within the n-type semiconductor layer NS2. A groove TR1 is formed within the n-type semiconductor region NS3, an insulating film CZ is formed on the upper surface of the n-type semiconductor layer NS1 including the inner surface of the groove TR1, and a polysilicon electrode PE is formed on the insulating film CZ so as to fill the groove TR1. A metal surface electrode HE is formed on the polysilicon electrode PE, and a metal back surface electrode BE is formed on the lower surface of the n-type semiconductor layer NS1. The n-type impurity concentration of the n-type semiconductor layer NS2 between the n-type semiconductor region NS3 and the n-type semiconductor layer NS1 is lower than the n-type impurity concentrations of the n-type semiconductor layer NS1 and the n-type semiconductor region NS3, respectively.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used, for example, for a semiconductor device having a capacitor element and a method for manufacturing the same.

Background Art

[0002] Japanese Patent Application Laid-Open No. 2019-195013 (Patent Document 1) describes a semiconductor chip in which a power transistor and a snubber capacitor are formed.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When forming a power transistor and a snubber capacitor on one semiconductor chip, there is a limit to increasing the capacitance value of the snubber capacitor. For this reason, the inventor of the present invention is considering forming a snubber circuit not in a power semiconductor chip including a power transistor but in a semiconductor chip different from the power semiconductor chip. Even when forming a snubber circuit with a semiconductor chip different from the power semiconductor chip, it is desired to improve the performance of the semiconductor chip (semiconductor device) including the snubber circuit and the semiconductor package (semiconductor device) using the semiconductor chip.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] According to one embodiment, the semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type formed on the upper surface of the first semiconductor layer, and a first semiconductor region of the first conductivity type formed within the second semiconductor layer. The semiconductor device further includes a trench formed within the first semiconductor region, a first insulating film formed on the upper surface of the second semiconductor layer including the inner surface of the trench, a first electrode formed on the first insulating film to fill the trench, a surface electrode formed on the first electrode, and a back electrode formed on the lower surface of the first semiconductor layer. Each of the surface electrode and the back electrode is made of metal. The impurity concentration of the second semiconductor layer between the first semiconductor region and the first semiconductor layer is lower than the impurity concentration of the first semiconductor layer and the first semiconductor region, respectively. [Effects of the Invention]

[0007] According to one embodiment, the performance of a semiconductor device can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] This is a circuit diagram showing an example of a circuit using the semiconductor chip of Embodiment 1. [Figure 2] This is a circuit diagram showing an example of a circuit using the semiconductor chip of Embodiment 1. [Figure 3] This is a schematic cross-sectional view showing a semiconductor chip according to Embodiment 1. [Figure 4] This is a cross-sectional view of the semiconductor chip during the manufacturing process of Embodiment 1. [Figure 5] This is a cross-sectional view of the semiconductor chip manufacturing process, following Figure 4. [Figure 6] Figure 5 is a cross-sectional view of the semiconductor chip manufacturing process. [Figure 7] This is a cross-sectional view of the semiconductor chip manufacturing process, following Figure 6. [Figure 8] Figure 7 shows a cross-sectional view of the semiconductor chip manufacturing process. [Figure 9] This is a cross-sectional view of the semiconductor chip manufacturing process, following Figure 8. [Figure 10] It is a cross-sectional view during the manufacturing process of the semiconductor chip following FIG. 9. [Figure 11] It is a cross-sectional view during the manufacturing process of the semiconductor chip following FIG. 10. [Figure 12] It is a cross-sectional view during the manufacturing process of the semiconductor chip of Embodiment 1. [Figure 13] It is a cross-sectional view during the manufacturing process of the semiconductor chip following FIG. 12. [Figure 14] It is a cross-sectional view during the manufacturing process of the semiconductor chip following FIG. 13. [Figure 15] It is a cross-sectional view during the manufacturing process of the semiconductor chip following FIG. 14. [Figure 16] It is a cross-sectional view during the manufacturing process of the semiconductor chip following FIG. 15. [Figure 17] It is a cross-sectional view during the manufacturing process of the semiconductor chip following FIG. 16. [Figure 18] It is a plan perspective view showing the semiconductor package of Embodiment 1. [Figure 19] It is a cross-sectional view showing the semiconductor package of Embodiment 1. [Figure 20] It is a cross-sectional view showing the semiconductor package of Embodiment 1. [Figure 21] It is a plan view showing the power semiconductor chip of Embodiment 1. [Figure 22] It is a cross-sectional view of the main part showing the power semiconductor chip of Embodiment 1. [Figure 23] It is a partially enlarged cross-sectional view showing the semiconductor package of Embodiment 1. [Figure 24] It is a partially enlarged cross-sectional view showing a modified example of the semiconductor package of Embodiment 1. [Figure 25] It is a cross-sectional view schematically showing the semiconductor chip of the first study example. [Figure 26] It is a cross-sectional view schematically showing the semiconductor chip of the second study example. [Figure 27] It is a cross-sectional view schematically showing the first modified example of the semiconductor chip of Embodiment 1. [Figure 28]This is a schematic cross-sectional view showing a second modified example of the semiconductor chip of Embodiment 1. [Figure 29] This is a planar perspective view showing the semiconductor package of Embodiment 2. [Figure 30] This is a cross-sectional view showing a semiconductor package according to Embodiment 2. [Figure 31] This is a planar perspective view showing a first modified example of the semiconductor package of Embodiment 2. [Figure 32] This is a cross-sectional view showing a first modified example of the semiconductor package according to Embodiment 2. [Figure 33] This is a cross-sectional view showing a second modified example of the semiconductor package according to Embodiment 2. [Figure 34] This is a plan view of a power semiconductor chip to which IPD (Integrated Plane Deposition) has been applied. [Modes for carrying out the invention]

[0009] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. Unless otherwise specified, these are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, when referring to the number of elements, etc. (including number, numerical value, quantity, range, etc.) in the following embodiments, unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and may be greater than or less than that number. Moreover, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered essential in principle. Similarly, when referring to the shape, positional relationship, etc. of constituent elements, etc. in the following embodiments, unless otherwise specified or clearly considered not to be so in principle, it shall include those that substantially approximate or resemble that shape, etc. The same applies to the numerical values ​​and ranges mentioned above.

[0010] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, components having the same function will be denoted by the same reference numeral, and repeated descriptions will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless particularly necessary.

[0011] Furthermore, in the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to improve readability. Conversely, hatching may be added to plan views to improve readability.

[0012] Furthermore, in this application, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) includes not only MOSFETs using an oxide film as the gate insulating film, but also MOSFETs using insulating films other than oxide films as the gate insulating film.

[0013] (Embodiment 1) <Regarding the circuit configuration> Figure 1 is a circuit diagram showing an example of a circuit using the semiconductor chip CP of this embodiment.

[0014] The circuit shown in Figure 1 includes a power MOSFET 1, a snubber circuit 2, and a body diode 3. The power MOSFET 1, the snubber circuit (RC snubber circuit) 2, and the body diode 3 are connected in parallel between terminals TE1 and TE2. The snubber circuit 2 consists of a series-connected capacitor (capacitive element, snubber capacitance) 2a and a resistor (resistive element, snubber resistor) 2b. The snubber circuit 2 is formed by a semiconductor chip CP, which will be described later. The power MOSFET 1 and the body diode 3 are formed by a power semiconductor chip PC, which will be described later.

[0015] Specifically, the drain D1 of power MOSFET 1 is connected to terminal TE1, and the source S1 of power MOSFET 1 is connected to terminal TE2. Of the two electrodes (capacitor electrodes) that make up capacitor 2a, one electrode is connected to the source S1 of power MOSFET 1, and the other electrode is connected to the drain D1 of power MOSFET 1 via resistor 2b. Body diode 3 is a diode that is parasitic due to the device structure of power MOSFET 1.

[0016] In the circuit shown in Figure 1, the positions of capacitor 2a and resistor 2b may be swapped, and the circuit diagram in that case is shown in Figure 2. In the circuit shown in Figure 2, of the two electrodes (capacitor electrodes) that make up capacitor 2a, one electrode is connected to the drain D1 of power MOSFET 1, and the other electrode is connected to the source S1 of power MOSFET 1 via resistor 2b.

[0017] By applying a gate voltage above the threshold voltage to the gate G1 of power MOSFET 1 from a control circuit (not shown), power MOSFET 1 turns ON (conducts), and current (drain current) flows between the source S1 and drain D1 of power MOSFET 1. Consequently, current flows between terminals TE1 and TE2 via power MOSFET 1. If the potential of terminal TE1 is higher than the potential of terminal TE2, current flows from terminal TE1 to terminal TE2 via power MOSFET 1.

[0018] Consider the case where the gate voltage of power MOSFET 1 is reduced from a voltage above the threshold voltage to a voltage below the threshold voltage (for example, 0V) (turn-off). In this case, power MOSFET 1 transitions from the ON state to the OFF state (non-conducting state). When power MOSFET 1 turns off, no current flows through power MOSFET 1, so a back electromotive force (surge voltage) is generated that suppresses the rate of current change.

[0019] As shown in Figure 1, when power MOSFET 1 and snubber circuit 2 are connected in parallel, when power MOSFET 1 turns off, the charge stored in capacitor 2a of snubber circuit 2 is released. This mitigates the abrupt current change that occurs when power MOSFET 1 turns off. As a result, compared to when power MOSFET 1 is not connected to snubber circuit 2, the rate of current change when power MOSFET 1 turns off is smaller when power MOSFET 1 and snubber circuit 2 are connected in parallel, thus reducing the magnitude of the surge voltage generated when power MOSFET 1 turns off. This suppresses the generation of electromagnetic noise caused by the surge voltage generated when power MOSFET 1 turns off.

[0020] <About the structure of semiconductor chips (CP)> Figure 3 is a schematic cross-sectional view of the semiconductor chip CP of this embodiment. The semiconductor chip CP can be considered a semiconductor device.

[0021] As shown in Figure 3, the semiconductor chip (semiconductor device) CP of this embodiment includes an n-type semiconductor layer NS1, an n-type semiconductor layer NS2, an n-type semiconductor region NS3, a groove TR1, an insulating film CZ, a polysilicon electrode PE, an insulating film PA, a surface electrode HE, and a back surface electrode BE.

[0022] n-type semiconductor layers NS1 and NS2 can be formed from a semiconductor substrate SB1. In this case, n-type semiconductor layers NS1 and NS2 are formed within the semiconductor substrate SB1, and an n-type semiconductor region NS3 is formed within n-type semiconductor layer NS2. That is, the semiconductor chip CP comprises a semiconductor substrate SB1 having n-type semiconductor layers NS1 and NS2 and an n-type semiconductor region NS3, a groove TR1, an insulating film CZ, a polysilicon electrode PE, an insulating film PA, a surface electrode HE, and a back electrode BE.

[0023] The n-type semiconductor layer (n-type semiconductor region) NS1 has an upper surface and a lower surface opposite to the upper surface. The thickness of the n-type semiconductor layer NS1 is approximately constant. A back electrode BE is formed on the lower surface of the n-type semiconductor layer NS1. The n-type semiconductor layer NS1 and the back electrode BE are in contact with each other. Specifically, the back electrode BE is formed on the entire lower surface of the n-type semiconductor layer NS1 and has approximately constant thickness. The back electrode BE is made of a metallic material. Specifically, the back electrode BE consists of a single-layer metal film or a laminated film of multiple metal films. For example, the back electrode BE consists of a laminated film of a titanium (Ti) film in contact with the n-type semiconductor layer NS1, a nickel (Ni) film on the titanium film, and a gold (Au) film on the nickel film. The back electrode BE is electrically connected to the n-type semiconductor layer NS1.

[0024] The n-type semiconductor layer (n-type semiconductor region) NS2 has an upper surface and a lower surface opposite to the upper surface. The n-type semiconductor layer NS2 is formed on the upper surface of the n-type semiconductor layer NS1. The n-type semiconductor layer NS1 and the n-type semiconductor layer NS2 are in contact with each other. That is, the lower surface of the n-type semiconductor layer NS2 is in contact with the upper surface of the n-type semiconductor layer NS1. The n-type semiconductor layer NS2 is not in contact with the back electrode BE, and the n-type semiconductor layer NS1 is interposed between the n-type semiconductor layer NS2 and the back electrode BE. The planar dimensions (planar area) of the n-type semiconductor region NS2 are the same as the planar dimensions (planar area) of the n-type semiconductor layer NS1, and in a plan view, the n-type semiconductor layer NS2 overlaps with the n-type semiconductor layer NS1. The outer peripheral side surface of the n-type semiconductor layer NS2 is aligned with the outer peripheral side surface of the n-type semiconductor layer NS1. The outer peripheral side surface of the n-type semiconductor layer NS2 and the outer peripheral side surface of the n-type semiconductor layer NS1 each constitute a part of the outer peripheral side surface of the semiconductor chip CP.

[0025] When referring to the components of a semiconductor chip CP in a planar view, it corresponds to viewing the components from a plane approximately parallel to the top or bottom surface of the n-type semiconductor layer NS2, or the top or bottom surface of the n-type semiconductor layer NS1.

[0026] The n-type semiconductor region (n-type semiconductor layer) NS3 is formed within the n-type semiconductor layer NS2. Specifically, the n-type semiconductor region NS3 is formed within the n-type semiconductor layer NS2 from its upper surface, and extends to a predetermined depth from the upper surface of the n-type semiconductor layer NS2. The planar dimensions (planar area) of the n-type semiconductor region NS3 are smaller than the planar dimensions (planar area) of the n-type semiconductor layer NS2, and in a plan view, the n-type semiconductor region NS3 is contained within the n-type semiconductor layer NS2. In a plan view, the outer peripheral surface of the n-type semiconductor region NS3 is separated from the outer peripheral surface of the n-type semiconductor layer NS2. The lower surface (bottom surface) of the n-type semiconductor region NS3 is shallower than the lower surface of the n-type semiconductor layer NS2, and therefore does not reach the n-type semiconductor layer NS1. In other words, in a cross-sectional view, the n-type semiconductor region NS3 is formed within the n-type semiconductor layer NS2 such that the lower surface (bottom surface) of the n-type semiconductor region NS3 does not reach the n-type semiconductor layer NS1. Therefore, the n-type semiconductor region NS3 is not in contact with the n-type semiconductor layer NS1.

[0027] When referring to the depth of the components of a semiconductor chip CP, the side closer to the back electrode BE is considered the deeper side, and the side further from the back electrode BE is considered the shallower side.

[0028] The portion of the n-type semiconductor layer NS2 in which the n-type semiconductor region NS3 is not formed is called the n-type semiconductor region (n-type semiconductor layer) NS2a. The bottom surface (bottom surface) and sides of the n-type semiconductor region NS3 are covered by the n-type semiconductor region NS2a. That is, the bottom surface and sides of the n-type semiconductor region NS3 are in contact with the n-type semiconductor region NS2a. The planar dimensions (planar area) of the n-type semiconductor region NS3 are smaller than the planar dimensions (planar area) of the n-type semiconductor region NS2a, and in a planar view, the n-type semiconductor region NS3 is contained within the n-type semiconductor region NS2a.

[0029] An n-type semiconductor region NS2a exists below the n-type semiconductor region NS3. That is, the n-type semiconductor region NS2a exists between the n-type semiconductor region NS3 and the n-type semiconductor layer NS1. The lower surface of the n-type semiconductor layer NS2 is formed by the lower surface of the n-type semiconductor region NS2a. The lower surface of the n-type semiconductor region NS2a is in contact with the upper surface of the n-type semiconductor layer NS1. The outer peripheral surface of the n-type semiconductor layer NS2 is formed by the outer peripheral surface of the n-type semiconductor region NS2a. The upper surface of the n-type semiconductor layer NS2 is formed by the upper surface of the n-type semiconductor region NS2a and the upper surface of the n-type semiconductor region NS3. In a plan view, the upper surface of the n-type semiconductor region NS3 is surrounded by the upper surface of the n-type semiconductor region NS2a.

[0030] The n-type impurity concentration in n-type semiconductor layer NS1 is higher than that of n-type semiconductor layer NS2, and the n-type impurity concentration in n-type semiconductor region NS3 is higher than that of n-type semiconductor layer NS2. In other words, the n-type impurity concentration in n-type semiconductor layer NS1 is higher than that of n-type semiconductor region NS2a, and the n-type impurity concentration in n-type semiconductor region NS3 is higher than that of n-type semiconductor region NS2a.

[0031] A trench TR1 is formed from the upper surface of the n-type semiconductor layer NS2 into the n-type semiconductor layer NS2 (within the n-type semiconductor region NS3). The trench TR1 is formed from the upper surface of the n-type semiconductor layer NS2 to a predetermined depth. The trench TR1 does not penetrate the n-type semiconductor layer NS2, and the bottom surface of the trench TR1 is shallower than the bottom surface of the n-type semiconductor layer NS2, and therefore does not reach the n-type semiconductor layer NS2. Although not shown in the figures, the trench TR1 is formed in a grid, stripe, or island pattern in a plan view, for example. In a plan view, the trench TR1 is contained within the n-type semiconductor region NS3.

[0032] In Figure 3, the groove TR1 is formed within the n-type semiconductor region NS3, and the depth of the bottom surface of the groove TR1 is shallower than the depth of the bottom surface of the n-type semiconductor region NS3. Therefore, the bottom and sides of the groove TR1 are covered by the n-type semiconductor region NS3, and the n-type semiconductor region NS3 is located beneath the bottom surface of the groove TR1.

[0033] A polysilicon electrode PE is formed on the n-type semiconductor region NS3 via an insulating film (capacitive insulating film) CZ. A portion of the polysilicon electrode PE is embedded in the groove TR1 via the insulating film CZ.

[0034] The insulating film CZ is formed on the upper surface of the n-type semiconductor layer NS2, including the bottom and side surfaces of the groove TR. That is, the insulating film CZ is formed on the inner surface (bottom and side surfaces) of the groove TR1 and on the upper surface of the n-type semiconductor region NS3 outside the groove TR1. The insulating film CZ is in contact with the n-type semiconductor region NS3 (n-type semiconductor layer NS2) and also in contact with the polysilicon electrode PE. The insulating film CZ is made of, for example, a silicon oxide film.

[0035] The polysilicon electrode PE is formed on the insulating film CZ so as to fill the groove TR. The polysilicon electrode PE consists of a conductive film, which in this case is a doped polysilicon film. Because the insulating film CZ is interposed between the polysilicon electrode PE and the n-type semiconductor region NS3 (n-type semiconductor layer NS2), the polysilicon electrode PE is not in contact with the n-type semiconductor region NS3 (n-type semiconductor layer NS2).

[0036] The polysilicon electrode PE integrally comprises a portion located within the groove TR1 (i.e., a portion embedded within the groove TR1 via the insulating film CZ) and a portion located on the upper surface of the n-type semiconductor region NS3 outside the groove TR1. In a plan view, the groove TR1 is contained within the n-type semiconductor region NS3. Therefore, in a plan view, the polysilicon electrode PE is contained within the n-type semiconductor region NS3.

[0037] An insulating film PA is formed on the upper surface of the n-type semiconductor layer NS2. The insulating film PA is made of, for example, a silicon oxide film. The insulating film PA has an opening OP1. A portion of the polysilicon electrode PE is exposed through the opening OP1 of the insulating film PA. The portion of the upper surface of the n-type semiconductor layer NS2 that is not covered by the insulating film CZ is covered by the insulating film PA. In a plan view, the opening OP1 is enclosed within the polysilicon electrode PE. A portion of the polysilicon electrode PE (the outer periphery) is covered by the insulating film PA.

[0038] A surface electrode HE is formed on the polysilicon electrode PE, which is exposed through the opening OP1 of the insulating film PA.

[0039] The surface electrode HE is made of a metallic material. Specifically, the surface electrode HE consists of a single layer of metal film or a laminate of multiple metal films. In a plan view, the opening OP1 is enclosed within the surface electrode HE. The surface electrode HE is in contact with the polysilicon electrode PE and is electrically connected to the polysilicon electrode PE. The outer periphery of the surface electrode HE is located on the insulating film PA.

[0040] The back surface of the semiconductor chip CP is composed of the surface of the back electrode BE, while the front surface of the semiconductor chip CP is composed of the surface (top surface) of the front electrode HE and the surface (top surface) of the insulating film PA. The surface of the back electrode BE is the side opposite to the side in contact with the n-type semiconductor layer NS1. The side surface of the semiconductor chip CP is composed of the side surface of the back electrode BE, the side surface of the n-type semiconductor layer NS1, the side surface of the n-type semiconductor layer NS2, and the side surface of the insulating film PA.

[0041] A capacitor (capacitive element) 2a (see Figures 1 and 2) is formed by a polysilicon electrode PE, an n-type semiconductor region NS3 (n-type semiconductor layer NS2), and an insulating film CZ. The insulating film CZ functions as a capacitance insulating film (dielectric film) of the capacitor 2a, the polysilicon electrode PE functions as one electrode (capacitor electrode) of the capacitor 2a, and the n-type semiconductor region NS3 (n-type semiconductor layer NS2) functions as the other electrode (capacitor electrode) of the capacitor 2a. By embedding the polysilicon electrode PE in the groove TR1 via the insulating film CZ, the effective electrode area of ​​the capacitor 2a can be increased, and thus the capacitance value of the capacitor 2a can be efficiently increased.

[0042] The surface electrode HE is electrically connected to the polysilicon electrode PE. The back electrode BE is electrically connected to the n-type semiconductor layer NS1. Therefore, the back electrode BE is electrically connected to the n-type semiconductor region NS2a via the n-type semiconductor layer NS1, and further electrically connected to the n-type semiconductor region NS3 via the n-type semiconductor region NS2a.

[0043] Therefore, a series circuit of capacitor 2a and resistor 2b is formed between the surface electrode HE and the back electrode BE. Resistor 2b (see Figures 1 and 2) is formed by n-type semiconductor region NS3, n-type semiconductor region NS2a, and n-type semiconductor layer NS1. The resistance value of resistor 2b is mainly determined by n-type semiconductor region NS2a. This is because the n-type impurity concentration of n-type semiconductor region NS2a is lower than that of n-type semiconductor region NS3 and also lower than that of n-type semiconductor layer NS1. Therefore, the resistivity of n-type semiconductor region NS2a is higher than that of n-type semiconductor region NS3 and also higher than that of n-type semiconductor layer NS1.

[0044] To realize the circuit shown in Figure 1, the surface electrode HE of the semiconductor chip CP is electrically connected to the source S1 of the power MOSFET 1, and the back electrode BE of the semiconductor chip CP is electrically connected to the drain D1 of the power MOSFET 1. To realize the circuit shown in Figure 2, the surface electrode HE of the semiconductor chip CP is electrically connected to the drain D1 of the power MOSFET 1, and the back electrode BE of the semiconductor chip CP is electrically connected to the source S1 of the power MOSFET 1.

[0045] <About the manufacturing process of semiconductor chips (CP)> The manufacturing process of the semiconductor chip CP of this embodiment will be described with reference to Figures 4 to 11. Figures 4 to 11 are cross-sectional views of the manufacturing process of the semiconductor chip CP of this embodiment.

[0046] As shown in Figure 4, an n-type semiconductor substrate (semiconductor wafer) SB1 made of, for example, n-type single-crystal silicon is prepared. The semiconductor substrate SB1 has a main surface and a back surface opposite to the main surface.

[0047] Next, as shown in Figure 5, an n-type semiconductor region NS3 is formed in the semiconductor substrate SB1 using ion implantation. The n-type semiconductor region NS3 is formed to a predetermined depth from the main surface of the semiconductor substrate SB1.

[0048] Next, as shown in Figure 6, grooves TR1 are formed on the main surface of the semiconductor substrate SB1. The grooves TR1 can be formed using photolithography and etching techniques.

[0049] The groove TR is formed within the n-type semiconductor region NS3 from the main surface of the semiconductor substrate SB1. The bottom surface of the groove TR is shallower than the bottom surface of the n-type semiconductor region NS3, and a portion of the n-type semiconductor region NS3 exists below the bottom surface of the groove TR. In a plan view, the groove TR is contained within the n-type semiconductor region NS3.

[0050] Next, as shown in Figure 7, an insulating film CZ is formed on the main surface of the semiconductor substrate SB1, including the inner surface (bottom and side surfaces) of the groove TR, using, for example, a thermal oxidation method. The insulating film CZ consists of a thin silicon oxide film or the like, and is formed on the bottom and side surfaces of the groove TR1, and on the main surface of the semiconductor substrate SB1 outside the groove TR1.

[0051] Next, as shown in Figure 7, a polysilicon film PS is formed on the main surface of the semiconductor substrate SB1, i.e., on the insulating film CZ, using a CVD method or the like, so as to fill the groove TR1.

[0052] Next, a photoresist pattern (not shown) is formed on the polysilicon film PS, and then the polysilicon film PS is patterned by etching using the photoresist pattern as an etching mask. As a result, a polysilicon electrode PE is formed from the patterned polysilicon film PS, as shown in Figure 8. The polysilicon electrode PE is formed on the insulating film CZ so as to fill the groove TR.

[0053] Next, as shown in Figure 9, an insulating film PA is formed on the main surface of the semiconductor substrate SB1 so as to cover the polysilicon electrode PE. Then, an opening OP1 is formed in the insulating film PA by etching the insulating film PA using a photoresist pattern (not shown) formed on the insulating film PA as an etching mask.

[0054] Next, as shown in Figure 9, a surface electrode HE is formed on the polysilicon electrode PE exposed from the opening OP1 of the insulating film PA.

[0055] For example, an aluminum film is formed on the polysilicon electrode PE exposed through the opening OP1 of the insulating film PA and on the insulating film PA, and then a photoresist pattern is formed on this aluminum film. Subsequently, an electroplated film is formed on the aluminum film exposed through the opening of the photoresist pattern. After that, the photoresist pattern is removed. This makes it possible to form a surface electrode HE consisting of a laminated film of aluminum film and electroplated film.

[0056] Next, as shown in Figure 10, an n-type semiconductor layer NS1 is formed within the semiconductor substrate SB1 by ion implantation of n-type impurities into the semiconductor substrate SB1 from the back surface. The n-type semiconductor layer NS1 is formed from the back surface of the semiconductor substrate SB1 to a predetermined depth. The bottom surface of the n-type semiconductor layer NS1 corresponds to the back surface of the semiconductor substrate SB1. The portion of the semiconductor substrate SB1 located on the n-type semiconductor layer NS1 corresponds to the n-type semiconductor layer NS2. The top surface of the n-type semiconductor layer NS2 corresponds to the main surface of the semiconductor substrate SB1. The bottom surface of the n-type semiconductor region NS3 does not reach the n-type semiconductor layer NS1.

[0057] Next, as shown in Figure 11, a back electrode BE is formed on the back surface of the semiconductor substrate SB1. The back electrode BE can be formed, for example, using a sputtering method.

[0058] Subsequently, the semiconductor substrate SB1 is cut by dicing. At this time, the back electrode BE and insulating film PA are also cut along with the semiconductor substrate SB1.

[0059] In this way, the semiconductor chip CP shown in Figure 3 above can be manufactured.

[0060] <Regarding variations in the manufacturing process of semiconductor chips (CP)> A modified example of the semiconductor chip CP manufacturing process of this embodiment will be described with reference to Figures 12 to 17. Figures 12 to 17 are cross-sectional views of the semiconductor chip CP manufacturing process of this embodiment.

[0061] As shown in Figure 12, a semiconductor substrate (semiconductor wafer) SB1 is prepared. In the modified example, the semiconductor substrate SB1 is a so-called epitaxial wafer. Therefore, as shown in Figure 12, the semiconductor substrate SB1 has an n-type substrate body SB1a made of n-type single crystal silicon and an n-type semiconductor layer EP made of n-type single crystal silicon formed on the n-type substrate body SB1a by epitaxial growth. The n-type semiconductor layer EP and the n-type substrate body SB1a are in contact with each other. The n-type impurity concentration of the n-type semiconductor layer EP is lower than the n-type impurity concentration of the n-type substrate body SB1a.

[0062] The main surface of semiconductor substrate SB1 is synonymous with the main surface of the n-type semiconductor layer EP. Furthermore, the back surface of semiconductor substrate SB1 is synonymous with the back surface of the n-type substrate body SB. The main surface and the back surface of semiconductor substrate SB1 are located on opposite sides of each other.

[0063] The n-type substrate body SB1a corresponds to the n-type semiconductor layer NS1. The n-type semiconductor layer EP corresponds to the n-type semiconductor layer NS2.

[0064] The subsequent steps are almost identical to those shown in Figures 5 to 11, except that the ion implantation step for forming the n-type semiconductor layer NS1 is omitted.

[0065] Specifically, as shown in Figure 13, an n-type semiconductor region NS3 is formed within the n-type semiconductor layer EP of the semiconductor substrate SB1 using ion implantation. The bottom surface of the n-type semiconductor region NS3 does not reach the main n-type substrate body SB1a.

[0066] Next, as shown in Figure 14, grooves TR1 are formed on the main surface of the semiconductor substrate SB1.

[0067] Next, as shown in Figure 15, an insulating film CZ is formed on the main surface of the semiconductor substrate SB1, including the inner surface (bottom and side surfaces) of the groove TR1.

[0068] Next, a polysilicon film PS is formed on the main surface of the semiconductor substrate SB1, i.e., on the insulating film CZ, so as to fill the groove TR1. Then, the polysilicon electrode PE is formed by patterning the polysilicon film PS.

[0069] Next, as shown in Figure 16, after forming the insulating film PA, an opening OP1 is formed in the insulating film PA.

[0070] Next, as shown in Figure 16, a surface electrode HE is formed on the polysilicon electrode PE exposed from the opening OP1 of the insulating film PA.

[0071] Next, as shown in Figure 17, a back electrode BE is formed on the back surface of the semiconductor substrate SB1.

[0072] Subsequently, the semiconductor substrate SB1, the back electrode BE, and the insulating film PA are cut by dicing.

[0073] In this way, the semiconductor chip CP shown in Figure 3 above can be manufactured.

[0074] <About the structure of semiconductor packages (PKG)> Figure 18 is a plan view showing a semiconductor package (semiconductor device, electronic device) PKG using the semiconductor chip CP of this embodiment. In Figure 18, the sealing portion MR is viewed through. Figures 19 and 20 are cross-sectional views of a semiconductor package (PKG). Figure 19 corresponds to a cross-sectional view along line A1-A1 in Figure 18, and Figure 20 corresponds to a cross-sectional view along line A2-A2 in Figure 18. Figure 21 is a plan view (top view) of a power semiconductor chip (PC) used in the semiconductor package (PKG). In Figure 21, the outer periphery of the source electrode (SE) is indicated by a dashed line. A semiconductor package (PKG) can be considered a semiconductor device or electronic device.

[0075] As shown in Figures 18, 19, 20, and 21, the semiconductor package PKG of this embodiment includes a semiconductor chip CP, a power semiconductor chip PC, a die pad DP, a plurality of conductive wires (bonding wires) BW, a plurality of leads LD, a lead connecting portion LB, and a sealing portion (sealing resin portion) MR that seals these together.

[0076] The sealing portion MR is made of a resin material, such as a thermosetting resin material, and may also contain fillers.

[0077] The die pad DP, lead connector LB, and multiple leads LD are made of a metallic material such as copper (Cu) or a copper alloy.

[0078] The multiple lead LDs include a gate lead LDG and multiple source leads LDS. The multiple source leads LDS are connected to a common lead connector LB. The multiple source leads LDS and the lead connector LB are integrally formed. The lead connector LB is sealed within a sealing section MR. A portion of each lead LD is sealed within the sealing section MR, while another portion of each lead LD is exposed from the sealing section MR.

[0079] A portion of the die pad DP is sealed within the sealing portion MR, and the lower surface of the die pad DP is exposed from the lower surface of the sealing portion MR. A portion of the die pad DP may also protrude from the side of the sealing portion MR.

[0080] A power semiconductor chip PC is mounted on the upper surface of the die pad DP via a conductive bonding material (die bonding material) BD1. The die pad DP is the chip mounting section on which the power semiconductor chip PC is mounted.

[0081] The power semiconductor chip PC is a semiconductor chip that includes the power MOSFET 1 described above. The power semiconductor chip PC has a top surface and a back surface opposite to the top surface. On the top surface side, it has a gate pad (gate bonding pad) BPG, a plurality of source pads (source bonding pads) BPS, and a pad (chip mounting bonding pad) BPC. On the back surface side, it has a back electrode RE. The gate pad BPG is electrically connected to the gate of the power MOSFET 1 formed within the power semiconductor chip PC. The plurality of source pads BPS and pad BPC are electrically connected to the source of the power MOSFET 1 formed within the power semiconductor chip PC. The back electrode RE is electrically connected to the drain of the power MOSFET 1 formed within the power semiconductor chip PC.

[0082] The power semiconductor chip PC is positioned on the upper surface of the die pad DP via a conductive bonding material BD1, such that the back electrode RE of the power semiconductor chip PC faces the upper surface of the die pad DP via the bonding material BD1. The bonding material BD1 consists of, for example, solder, silver (Ag) paste, or sintered Ag (sintered silver). Therefore, the back electrode RE of the power semiconductor chip PC is electrically connected to the die pad DP via the conductive bonding material BD1. The power semiconductor chip PC is sealed within a sealing portion MR and is not exposed from the sealing portion MR.

[0083] Each of the multiple wires BW is a conductive connecting member. The multiple wires BW include a gate wire BWG and multiple source wires BWS and wire BWC. The multiple wires BW are sealed within a sealing portion MR and are not exposed from the sealing portion MR.

[0084] The gate pad BPG and gate lead LDG of the power semiconductor chip PC are electrically connected via the gate wire BWG. The gate lead LDG functions as an external terminal electrically connected to the gate of the power MOSFET 1.

[0085] Multiple source pads BPS and lead connectors LB of the power semiconductor chip PC are electrically connected to each other via multiple source wires BWS. Therefore, multiple source leads LDS are electrically connected to multiple source pads BPS via the lead connectors LB and multiple source wires BWS. Multiple source leads LDS function as external terminals electrically connected to the source of power MOSFET 1. In Figure 20, each of the multiple source wires BWS is connected to the lead connector LB via a conductive bonding material BD3 such as solder, and is also connected to the source pad BPS via the conductive bonding material BD3.

[0086] The diameter of each of the multiple source wires BWS is larger than the diameter of the gate wire BWG and also larger than the diameter of the wire BWC. In other words, the diameters of the gate wire BWG and wire BWC are smaller than the diameter of the source wire BWS. This allows the size of the gate pad BPG to which the gate wire BWG is joined and the pad BPC to which the wire BWC is joined to be relatively smaller, while the size of the source pad BPS to which the source wire BWS is joined can be relatively larger. Since multiple source wires BWS with large diameters can be joined to the source pad BPS, the width of the path (current path) between multiple source leads LDS and multiple source pads BPS of the power semiconductor chip PC can be increased. That is, the resistance between the drain and source of the power semiconductor chip PC can be reduced, and the on-resistance of the power MOSFET 1 can be reduced. Consequently, conduction losses can be reduced in the semiconductor package PKG.

[0087] A semiconductor chip CP is mounted on the pad BPC of a power semiconductor chip PC via a conductive bonding material (die bonding material) BD2. The semiconductor chip CP is positioned on the pad BPC of the power semiconductor chip PC via the conductive bonding material BD2 such that the surface electrodes HE of the semiconductor chip CP face the pad BPC of the power semiconductor chip PC via the bonding material BD2. The bonding material BD2 consists of, for example, solder, silver (Ag) paste, or sintered Ag (sintered silver). Therefore, the surface electrodes HE of the semiconductor chip CP are electrically connected to the pad BPC of the power semiconductor chip PC via the conductive bonding material BD2. The semiconductor chip CP is sealed within a sealing portion MR and is not exposed from the sealing portion MR.

[0088] The back electrode BE of the semiconductor chip CP and the die pad DP are electrically connected via a wire BWC. Specifically, one end of the wire BWC is connected to the back electrode BE of the semiconductor chip CP, and the other end of the wire BWC is connected to the top surface of the die pad DP. Therefore, the back electrode BE of the semiconductor chip CP is electrically connected to the die pad DP via the wire BWC, and further electrically connected to the back electrode RE of the power semiconductor chip PC via a conductive bonding material BD1.

[0089] The lower surface of the die pad DP is exposed from the lower surface of the sealing portion MR. The die pad DP exposed from the lower surface of the sealing portion MR functions as an external terminal electrically connected to the drain of the power MOSFET 1. The conduction current (on current) of the power MOSFET 1 formed within the power semiconductor chip PC flows between the die pad DP and the multiple source leads LDS. The heat generated during the operation of the power MOSFET 1 can be dissipated to the outside of the semiconductor package PKG mainly from the back surface of the power MOSFET 1 through the bonding material BD1 and the die pad DP.

[0090] <Regarding the manufacturing process of semiconductor packages (PKG)> This section explains the manufacturing process for semiconductor packages (PKG).

[0091] A lead frame is prepared, which integrally includes a die pad DP, multiple leads LD, and a lead connector LB. In the lead frame, the die pad DP and the multiple leads LD are each integrally connected to the frame (not shown) of the lead frame.

[0092] Next, a die bonding process is performed to mount the power semiconductor chip PC onto the upper surface of the die pad DP of the lead frame via a conductive bonding material BD1. This bonds the surface electrode BE of the power semiconductor chip PC to the die pad DP via the conductive bonding material BD1.

[0093] Next, a die bonding process is performed to mount the semiconductor chip CP onto the pad BPC of the power semiconductor chip PC via a conductive bonding material BD2. This bonds the back electrode BE of the semiconductor chip CP to the pad BPC of the power semiconductor chip PC via the conductive bonding material BD2.

[0094] Next, the wire bonding process is performed. Specifically, the gate pad BPG and gate lead LDG of the power semiconductor chip PC are electrically connected via the gate wire BWG, multiple source pads BPS and lead connection parts LB of the power semiconductor chip PC are electrically connected via multiple source wires BWS, and the back electrode BE and die pad DP of the semiconductor chip CP are electrically connected via the wire BWC.

[0095] Next, a molding process is performed to form the sealing portion (MR). After that, the die pad (DP) and lead (LD) are separated from the lead frame. This allows for the manufacture of the semiconductor package (PKG).

[0096] <About the structure of power semiconductor chips (PCs)> Figure 22 is a cross-sectional view of the main part of a power semiconductor chip PC.

[0097] The semiconductor chip PC is a semiconductor chip that includes a power MOSFET 1, and the power MOSFET 1 is formed on the semiconductor substrate SB2 that constitutes the semiconductor chip PC.

[0098] As shown in Figure 22, the power semiconductor chip PC comprises a semiconductor substrate SB2, an interlayer insulating film IL, a back electrode RE, a source electrode SE, a gate electrode GE, a gate wiring GEW, an insulating film PV, a trench gate electrode TG, a gate insulating film GF, a gate lead-out wiring section TGL, and an n-type semiconductor region NR and a p-type semiconductor region PR formed within the semiconductor substrate SB.

[0099] The semiconductor substrate SB2 is an n-type semiconductor substrate, such as n-type single-crystal silicon. A semiconductor substrate (so-called epitaxial wafer) having a substrate body made of n-type single-crystal silicon and an epitaxial layer made of n-type single-crystal silicon formed on the substrate body can also be used as the semiconductor substrate SB2.

[0100] The semiconductor substrate SB2 has a main surface and a back surface located opposite the main surface. An interlayer insulating film IL is formed on the main surface of the semiconductor substrate SB2, and a back surface electrode RE is formed on the back surface of the semiconductor substrate SB.

[0101] A trench-gate type MOSFET is formed on the semiconductor substrate SB2. The trench-gate type MOSFET has a trench-type gate structure. The trench-type gate structure corresponds to a gate electrode structure embedded in a groove formed in the substrate.

[0102] The specific configuration of the trench gate type MOSFET formed on the semiconductor substrate SB2 is described below.

[0103] A trench-gate type MOSFET constituting the power MOSFET 1 is formed on the main surface of the semiconductor substrate SB2. Specifically, multiple unit transistor cells Q1 are formed on the main surface of the semiconductor substrate SB2, and the power MOSFET 1 is formed by connecting multiple unit transistor cells Q1 formed on the semiconductor substrate SB2 in parallel. Each unit transistor cell Q1 is composed of a trench-gate type MOSFET. Here, the planar region on the main surface of the semiconductor substrate SB2 in which multiple unit transistor cells Q1 constituting the power MOSFET 1 are formed is called the transistor cell region.

[0104] The semiconductor substrate SB2 functions as the drain region of the unit transistor cell Q1. A back electrode RE for draining is formed on the back surface of the semiconductor substrate SB2. The back electrode RE is formed on the entire back surface of the semiconductor substrate SB2. The back electrode RE consists of a multilayer film, for example, a titanium (Ti) film in contact with the semiconductor substrate SB2, a nickel (Ni) film on the titanium film, and gold (Au) on the nickel film. The back electrode RE is electrically connected to the drain regions of multiple unit transistor cells Q1. Therefore, the back electrode RE can function as a drain electrode electrically connected to the drain of the power MOSFET 1.

[0105] A p-type semiconductor region PR is formed within the semiconductor substrate SB2 of the transistor cell region. The p-type semiconductor region PR can function as a channel formation region for the unit transistor cell Q1.

[0106] Within the semiconductor substrate SB2, an n-type semiconductor region (source region) NR is formed on a p-type semiconductor region PR. The n-type semiconductor region NR can function as the source region of the unit transistor cell Q1. A p-type semiconductor region PR exists beneath the n-type semiconductor region NR. The semiconductor substrate SB2 interposed between the p-type semiconductor region PR and the back electrode RE maintains an n-type conductivity and can function as the drain region of the unit transistor cell Q1.

[0107] Within the semiconductor substrate SB2, a superjunction structure (not shown) can also be formed beneath the p-type semiconductor region PR.

[0108] A trench TR2 is formed on the main surface of the semiconductor substrate SB2, and a trench gate electrode TG is embedded in the trench TR2 via a gate insulating film GF. The trench gate electrode TG is made of, for example, a doped polysilicon film. The gate insulating film GF is made of, for example, a silicon oxide film and is formed on the inner surface (bottom and sides) of the trench TR2. Although not shown in the figures, the trench TR2 is formed in a grid or striped pattern, for example, in a plan view.

[0109] When referring to the components of a power semiconductor chip PC in a planar view, it refers to a view taken from a plane approximately parallel to the main surface or back surface of the semiconductor substrate SB2 that constitutes the power semiconductor chip PC.

[0110] The groove TR2 is formed from the main surface of the semiconductor substrate SB2, penetrating through the n-type semiconductor region NR and the p-type semiconductor region PR. The bottom surface of the groove TR2 is deeper than the bottom surface of the n-type semiconductor region NR and also deeper than the bottom surface of the p-type semiconductor region PR. The n-type semiconductor region NR is adjacent to the trench gate electrode TG via the gate insulating film GF. The p-type semiconductor region PR is adjacent to the trench gate electrode TG via the gate insulating film GF.

[0111] Next, we will describe the structure of the layer above the semiconductor substrate SB2.

[0112] An interlayer insulating film IL is formed on the main surface of the semiconductor substrate SB2 so as to cover the trench gate electrode TG. The interlayer insulating film IL is made of, for example, a silicon oxide film.

[0113] The trench gate electrodes TG of multiple unit transistor cells Q1 are integrally connected in a region not shown in the cross-sectional view of Figure 22. A gate lead-out wiring section TGL, integrally formed with the trench gate electrode TG, is formed outside the groove TR2 on the main surface of the semiconductor substrate SB2 via a gate insulating film GF.

[0114] The interlayer insulating film IL has a source contact hole CT1 and a gate contact hole CT2 formed within it. In a plan view, contact hole CT1 is located between adjacent grooves TR2. Contact hole CT2 is located on the gate lead-out wiring section TGL.

[0115] A source electrode SE, a gate electrode GE, and gate wiring GEW are formed on the interlayer insulating film IL. The gate electrode GE is formed integrally with the gate wiring GEW. The source electrode SE is separated from the gate electrode GE and also separated from the gate wiring GEW. In a plan view, the source electrode SE is formed to cover the entire transistor cell region.

[0116] The source electrode SE, gate electrode GE, and gate wiring GEW are each made of a metal film, such as an aluminum alloy film. A portion of the source electrode SE is embedded in the source contact hole CT1. The portion of the source electrode SE embedded in the source contact hole CT1 is called the source via portion. A portion of the gate wiring GEW is embedded in the gate contact hole CT2. The portion of the gate wiring GEW embedded in the gate contact hole CT2 is called the gate via portion.

[0117] The source contact hole CT1 penetrates the interlayer insulating film IL and the n-type semiconductor region NR, reaching the p-type semiconductor region PR. Therefore, the source via embedded within the source contact hole CT1 penetrates the interlayer insulating film IL and the n-type semiconductor region NR, reaching the p-type semiconductor region PR. Since the source via is in contact with both the n-type semiconductor region NR and the p-type semiconductor region PR, it is electrically connected to both the n-type semiconductor region NR and the p-type semiconductor region PR.

[0118] The source regions (n-type semiconductor region NR) and channel formation regions (p-type semiconductor region PR) of multiple unit transistor cells Q1 arranged in the transistor cell region are electrically connected to a common source electrode SE via multiple source vias. In this case, the source electrode SE also serves as the source wiring that electrically connects the source regions (n-type semiconductor region NR) of the multiple unit transistor cells Q1. Therefore, the source electrode SE can function as a source electrode electrically connected to the source of the power MOSFET 1.

[0119] The gate wiring GEW is electrically connected to the gate lead wiring TGL via the gate via. Therefore, the trench gate electrodes TG of multiple unit transistor cells Q1 are electrically connected to the gate electrode GE via the gate lead wiring TGL and the gate wiring GEW. Thus, the gate electrode GE can function as a gate electrode electrically connected to the gate of the power MOSFET 1.

[0120] An insulating film PV is formed on the interlayer insulating film IL as a passivation film, covering a portion of the source electrode SE, a portion of the gate electrode GE, and the gate wiring GEW. The insulating film PV is made of a resin film, such as polyimide resin.

[0121] Multiple source openings (OPS) and gate openings (OPG) are formed in the insulating film PV. A portion of the gate electrode (GE) is exposed through the gate openings (OPG) of the insulating film PV. The gate electrode (GE) exposed through the gate openings (OPG) of the insulating film PV forms a gate pad (BPG). The gate pad (BPG, gate electrode GE) is electrically connected to the trench gate electrodes (TG) of multiple unit transistor cells Q1 via gate wiring (GEW) and gate lead wiring (TGL).

[0122] A portion of the source electrode SE is exposed from multiple source openings OPS in the insulating film PV. That is, multiple source openings OPS are arranged on a common source electrode SE, and the common source electrode SE is exposed from each of the multiple source openings OPS. Each of the pad BPC and the multiple source pads BPS consists of a source electrode SE exposed from the source openings OPS in the insulating film PV. In other words, the pad BPC and the multiple source pads BPS are electrically connected to each other because they are formed by a common source electrode SE. The pad BPC and the multiple source pads BPS are electrically connected to the source regions (n-type semiconductor regions NR) of multiple unit transistor cells Q1 via the source electrode SE.

[0123] A plating film (not shown) may be formed on the source electrode SE exposed from the multiple source openings OPS of the insulating film PV, and on the gate electrode GE exposed from the gate opening OPG of the insulating film PV. The plating film consists, for example, a nickel plating film and a gold plating film on the nickel plating film. In this case, each of the pad BPC and the multiple source pads BPS consists of a source electrode SE and a plating film on the source electrode SE, and the gate pad BPG consists of a gate electrode GE and a plating film on the gate electrode GE.

[0124] In a power semiconductor chip PC having such a configuration, the operating current of the power MOSFET 1 flows between the source electrode SE and the back electrode RE for draining. That is, the operating current of the trench-gate type MOSFET formed in the transistor cell region flows in the thickness direction of the semiconductor substrate SB2. For this reason, the trench-gate type MOSFET formed in the transistor cell region is a vertical transistor. Here, a vertical transistor corresponds to a transistor in which the operating current flows in the thickness direction of the semiconductor substrate SB2.

[0125] The body diode 3 described above (see Figures 1 and 2) corresponds to a parasitic PN diode composed of a p-type semiconductor region PR and an n-type semiconductor substrate SB2.

[0126] <Regarding the mounting of semiconductor chips (CP) on power semiconductor chip PCs> Figure 23 is a partially enlarged cross-sectional view showing an enlarged portion of Figure 19. Note that the sealing portion MR is not shown in Figure 23.

[0127] As shown in Figures 19 and 23 above, a semiconductor chip CP is mounted on the pad BPC (source electrode SE) of the power semiconductor chip PC via a conductive bonding material BD2. The semiconductor chip CP is positioned on the pad BPC of the power semiconductor chip PC via the conductive bonding material BD2 such that the surface electrode HE of the semiconductor chip CP faces the pad BPC (source electrode SE) of the power semiconductor chip PC via the bonding material BD2. Therefore, the surface electrode HE of the semiconductor chip CP is bonded to the source electrode SE of the power semiconductor chip PC via the conductive bonding material BD2 and electrically connected. The back electrode BE of the semiconductor chip CP is electrically connected to the die pad DP via wire BWC, and further electrically connected to the back electrode RE of the power semiconductor chip PC via the die pad DP and the conductive bonding material BD1.

[0128] Therefore, the surface electrode HE of the semiconductor chip CP is electrically connected to the source of the power MOSFET 1 formed within the power semiconductor chip PC via the conductive bonding material BD2 and the pad BPC (source electrode SE) of the power semiconductor chip PC. The back electrode BE of the semiconductor chip CP is electrically connected to the drain of the power MOSFET 1 formed within the power semiconductor chip PC via the wire BWC, the die pad DP, the conductive bonding material BD1, and the back electrode RE. As a result, as shown in Figure 1, the power MOSFET 1 formed within the power semiconductor chip PC and the snubber circuit 2 formed within the semiconductor chip CP are connected in parallel.

[0129] Furthermore, when a semiconductor chip CP is mounted on the pad BPC (source electrode SE) of a power semiconductor chip PC via the bonding material BD2, the excessive expansion of the bonding material BD2 can be prevented by the side of the aperture OPS of the insulating film PA.

[0130] Figure 24 is a partially enlarged cross-sectional view showing an enlarged portion of a modified semiconductor package (PKG), corresponding to Figure 23 above. In Figure 24, the sealing portion (MR) is not shown. The modified semiconductor package (PKG) shown in Figure 24 is referred to as semiconductor package (PKG1).

[0131] The difference between the modified semiconductor package PKG1 shown in Figure 24 and the semiconductor package PKG shown in Figure 23 lies in the orientation in which the semiconductor chip CP is mounted. The differences between the modified semiconductor package PKG1 shown in Figure 24 and the semiconductor package PKG shown in Figure 23 are explained below.

[0132] As shown in Figure 24, in the modified semiconductor package PKG1, the semiconductor chip CP is positioned on the pad BPC of the power semiconductor chip PC via the conductive bonding material BD2, such that the back electrode BE of the semiconductor chip CP faces the pad BPC (source electrode SE) of the power semiconductor chip PC via the bonding material BD2. Therefore, the back electrode BE of the semiconductor chip CP is bonded to and electrically connected to the source electrode SE of the power semiconductor chip PC via the conductive bonding material BD2. The front electrode HE of the semiconductor chip CP is electrically connected to the die pad DP via the wire BWC. Specifically, one end of the wire BWC is connected to the back electrode BE of the semiconductor chip CP, and the other end of the wire BWC is connected to the upper surface of the die pad DP. Therefore, the back electrode BE of the semiconductor chip CP is electrically connected to the back electrode RE of the power semiconductor chip PC via the wire BWC, the die pad DP, and the conductive bonding material BD1.

[0133] Therefore, in the case of the modified semiconductor package PKG1 shown in Figure 24, the surface electrode HE of the semiconductor chip CP is electrically connected to the drain of the power MOSFET 1 formed in the power semiconductor chip PC via the wire BWC, die pad DP, conductive bonding material BD1, and back electrode RE. The back electrode BE of the semiconductor chip CP is electrically connected to the source of the power MOSFET 1 formed in the power semiconductor chip PC via the conductive bonding material BD2 and the pad BPC (source electrode SE) of the power semiconductor chip PC. As a result, as shown in Figure 2, the power MOSFET 1 formed in the power semiconductor chip PC and the snubber circuit 2 formed in the semiconductor chip CP are connected in parallel. That is, the circuit configuration in Figure 1 corresponds to the semiconductor package PKG shown in Figure 23, and the circuit configuration in Figure 2 corresponds to the semiconductor package PKG1 shown in Figure 24.

[0134] <Main Features and Effects> In this embodiment, instead of forming the snubber circuit 2 within the power semiconductor chip PC containing the power MOSFET 1, the snubber circuit 2 is formed by a separate semiconductor chip CP. Since it is not necessary to form the components required for the snubber circuit 2 within the power semiconductor chip PC, the structure of the power semiconductor chip PC can be optimized to suit the power MOSFET 1. Furthermore, the structure of the semiconductor chip CP can be optimized to suit the snubber circuit 2.

[0135] The semiconductor chip CP of this embodiment has a front electrode HE and a back electrode BE, and a snubber circuit 2 (a series circuit of a capacitor 2a and a resistor 2b) is formed between the front electrode HE and the back electrode BE.

[0136] Unlike this embodiment, let's assume that both electrodes at both ends of the snubber circuit 2 are placed on the surface side of the semiconductor chip. In that case, the planar dimensions (planar area) of the semiconductor chip including the snubber circuit 2 will increase, which raises concerns about increased manufacturing costs for the semiconductor chip including the snubber circuit 2. In addition, it will become more difficult to independently control the capacitance value of capacitor 2a and the resistance value of resistor 2b.

[0137] In contrast, in this embodiment, the electrodes at both ends of the snubber circuit 2 (here, the surface electrode HE and the back electrode BE) are arranged on opposite sides of the semiconductor chip CP. That is, the surface electrode HE is placed on the front side of the semiconductor chip CP, and the back electrode BE is placed on the back side of the semiconductor chip CP. As a result, the planar dimensions (planar area) of the semiconductor chip CP can be reduced compared to the case where both electrodes at both ends of the snubber circuit 2 are placed on the front side of the semiconductor chip, and thus the manufacturing cost of the semiconductor chip CP including the snubber circuit 2 can be reduced. In addition, the capacitance value of capacitor 2a and the resistance value of resistor 2b can be controlled independently.

[0138] The inventors investigated a semiconductor chip having a front electrode and a back electrode located on opposite sides of each other, with a snubber circuit formed between the front and back electrodes. As a result, they found that the structure of the semiconductor chip CP described above is superior. This will be explained in detail below.

[0139] In the semiconductor chip CP of this embodiment, a polysilicon electrode PE is embedded in the groove TR1 via an insulating film CZ. This increases the effective electrode area of ​​the capacitor 2a, thereby efficiently increasing the capacitance value of the capacitor 2a.

[0140] Figure 25 is a cross-sectional view of the semiconductor chip CP101 of the first study example investigated by the present inventors, and corresponds to Figure 3 above.

[0141] In the semiconductor chip CP101 of the first study example shown in Figure 25, a groove TR101 is formed on the main surface of an n-type semiconductor substrate SB101 having a nearly uniform n-type impurity concentration. An insulating film CZ101 is formed on the main surface of the n-type semiconductor substrate SB101, including the inner surface of the groove TR101. A polysilicon electrode PE101 is formed on the insulating film CZ101 so as to fill the groove TR101. A metal surface electrode HE101 is formed on the polysilicon electrode PE101 that is exposed from an opening OP101 in the insulating film PA101, and a metal back surface electrode BE101 is formed on the back surface of the n-type semiconductor substrate SB101.

[0142] In the case of the semiconductor chip CP101 of the first study example shown in Figure 25, the capacitor 2a is formed by the polysilicon electrode PE101, the n-type semiconductor substrate SB101, and the insulating film CZ101, and the resistor 2b is formed by the n-type semiconductor substrate SB101. In this case, in order to increase the capacitance value of capacitor 2a, it is necessary to increase the n-type impurity concentration of the n-type semiconductor substrate SB101. This is because if the n-type impurity concentration of the n-type semiconductor substrate SB101 is low, the depletion layer tends to spread more easily within the n-type semiconductor substrate SB101, resulting in a smaller capacitance value for capacitor 2a. Conversely, if the n-type impurity concentration of the n-type semiconductor substrate SB101 is high, the depletion layer does not spread as easily within the n-type semiconductor substrate SB101, resulting in a larger capacitance value for capacitor 2a.

[0143] However, if the n-type impurity concentration of the n-type semiconductor substrate SB101 is high, the resistivity of the n-type semiconductor substrate SB101 decreases, and therefore the resistance value of resistor 2b decreases. In other words, if the n-type impurity concentration of the n-type semiconductor substrate SB101 is high, the capacitance value of capacitor 2a increases, but the resistance value of resistor 2b decreases, and if the n-type impurity concentration of the n-type semiconductor substrate SB101 is low, the resistance value of resistor 2b increases, but the capacitance value of capacitor 2a decreases. Therefore, in the case of the semiconductor chip CP101 of the first study example shown in Figure 25, optimizing both the capacitance value of capacitor 2a and the resistance value of resistor 2b is more difficult than in the semiconductor chip CP of this embodiment.

[0144] Figure 26 is a cross-sectional view of the semiconductor chip CP201 ​​of the second study example investigated by the present inventors, and corresponds to Figures 3 and 25 above.

[0145] In the semiconductor chip CP201 ​​of the second study example shown in Figure 26, an n-type semiconductor region NS203 having a higher n-type impurity concentration than the n-type semiconductor substrate SB201 is formed within the n-type semiconductor substrate SB201 from the main surface of the n-type semiconductor substrate SB201. A groove TR201 is formed within the n-type semiconductor region NS203, and an insulating film CZ201 is formed on the main surface of the n-type semiconductor substrate SB201, including the inner surface of the groove TR201. A polysilicon electrode PE201 is formed on the insulating film CZ201 so as to fill the groove TR201. A metal surface electrode HE201 is formed on the polysilicon electrode PE201 exposed from the opening OP201 of the insulating film PA201, and a metal back surface electrode BE201 is formed on the back surface of the n-type semiconductor substrate SB201.

[0146] In the semiconductor chip CP201 ​​of the second study example shown in Figure 26, the capacitor 2a is formed by the polysilicon electrode PE201, the n-type semiconductor region NS203, and the insulating film CZ201, and the resistor 2b is formed by the n-type semiconductor region NS203 and the n-type semiconductor substrate SB201 beneath the n-type semiconductor region NS203. In this case, the capacitance value of the capacitor 2a can be increased by increasing the n-type impurity concentration of the n-type semiconductor region NS203.

[0147] However, if the n-type impurity concentration of the n-type semiconductor substrate SB201 is low, the connection between the back electrode BE201 and the n-type semiconductor substrate SB201 becomes a Schottky connection. When the connection between the back electrode BE201 and the n-type semiconductor substrate SB201 becomes a Schottky connection, the resistance value of resistor 2b is mainly determined by the Schottky connection between the back electrode BE201 and the n-type semiconductor substrate SB201, making the resistance value of resistor 2b prone to fluctuation and making it difficult to obtain the resistance value of resistor 2b as designed. For this reason, it is desirable to prevent the formation of a Schottky connection between the back electrode BE201 and the n-type semiconductor substrate SB201. On the other hand, if the n-type impurity concentration of the n-type semiconductor substrate SB201 is high, the connection between the back electrode BE201 and the n-type semiconductor substrate SB201 becomes an ohmic connection, and the resistance value of resistor 2b is mainly determined by the n-type semiconductor substrate SB201, but since the resistivity of the n-type semiconductor substrate SB201 becomes low, the resistance value of resistor 2b becomes small.

[0148] In other words, when the n-type impurity concentration of the n-type semiconductor substrate SB201 is low, a Schottky connection is formed between the back electrode BE201 and the n-type semiconductor substrate SB201, causing the resistance value of resistor 2b to fluctuate easily. When the n-type impurity concentration of the n-type semiconductor substrate SB101 is high, the connection between the back electrode BE201 and the n-type semiconductor substrate SB201 becomes an ohmic connection, but the resistance value of resistor 2b decreases. Therefore, in the case of the semiconductor chip CP201 ​​of the second study example shown in Figure 26, it is more difficult to achieve both a high resistance value for resistor 2b and suppress fluctuations in the resistance value of resistor 2b than in the semiconductor chip CP of this embodiment. For this reason, it is difficult to form a capacitor 2a with an optimal capacitance value and a resistor 2b with an optimal resistance value within the semiconductor chip CP201 ​​of the second study example shown in Figure 26.

[0149] In contrast, the semiconductor chip CP of this embodiment has an n-type semiconductor layer NS1, an n-type semiconductor layer NS2 formed on the upper surface of the n-type semiconductor layer NS1, and an n-type semiconductor region NS3 formed within the n-type semiconductor layer NS2 from the upper surface of the n-type semiconductor layer NS2. The n-type impurity concentration of the n-type semiconductor layer NS2 (n-type semiconductor region NS2a) between the n-type semiconductor region NS3 and the n-type semiconductor layer NS1 is lower than the n-type impurity concentrations of the n-type semiconductor region NS3 and the n-type semiconductor layer NS1, respectively. A groove TR1 is formed within the n-type semiconductor region NS3, an insulating film CZ is formed on the upper surface of the n-type semiconductor layer NS2 including the inner surface of the groove TR1, and a polysilicon electrode PE is formed on the insulating film CZ so as to fill the groove TR1. A metal surface electrode HE is formed on the polysilicon electrode PE exposed from an opening OP1 in the insulating film PA, and a metal back surface electrode BE is formed on the lower surface of the n-type semiconductor layer NS1.

[0150] In the semiconductor chip CP of this embodiment, the capacitor 2a is formed by the polysilicon electrode PE, the n-type semiconductor region NS3, and the insulating film CZ, and the resistor 2b is formed by the n-type semiconductor region NS, the n-type semiconductor layer NS2 (n-type semiconductor region NS2a) below the n-type semiconductor region NS3, and the n-type semiconductor layer NS.

[0151] By increasing the n-type impurity concentration in the n-type semiconductor region NS3, the capacitance value of capacitor 2a can be increased. Furthermore, by increasing the n-type impurity concentration in the n-type semiconductor layer NS1, Schottky connections are prevented from forming between the back electrode BE and the n-type semiconductor layer NS1, and an ohmic connection can be established between the back electrode BE and the n-type semiconductor layer NS1. As a result, fluctuations in the resistance value of resistor 2b can be suppressed. Additionally, by lowering the n-type impurity concentration in the n-type semiconductor layer NS2 (n-type semiconductor region NS2a) between the n-type semiconductor region NS3 and the n-type semiconductor layer NS1, the resistivity of the n-type semiconductor layer NS2 (n-type semiconductor region NS2a) between the n-type semiconductor region NS3 and the n-type semiconductor layer NS1 can be increased, thereby increasing the resistance value of resistor 2b.

[0152] In other words, to increase the capacitance value of capacitor 2a, it is desirable to increase the n-type impurity concentration of the n-type semiconductor region NS3; to prevent the formation of Schottky connections between the back electrode BE and the n-type semiconductor layer NS1, it is desirable to increase the n-type impurity concentration of the n-type semiconductor layer NS1; and to increase the resistance value of resistor 2b, it is desirable to decrease the n-type impurity concentration of the n-type semiconductor region NS2a. Based on this technical concept, in this embodiment, the n-type impurity concentration of the n-type semiconductor layer NS2 (n-type semiconductor region NS2a) between the n-type semiconductor region NS3 and the n-type semiconductor layer NS1 is lower than the n-type impurity concentrations of the n-type semiconductor region NS3 and the n-type semiconductor layer NS1, respectively. This makes it possible to increase the capacitance value of capacitor 2a, prevent the formation of Schottky connections between the back electrode BE and the n-type semiconductor layer NS1, suppress fluctuations in the resistance value of resistor 2b, and increase the resistance value of resistor 2b. As a result, a capacitor 2a with an optimal capacitance value and a resistor 2b with an optimal resistance value can be formed within the semiconductor chip CP. This makes it possible to improve the performance of the semiconductor chip CP and the performance of the semiconductor package PKG that uses the semiconductor chip CP.

[0153] Furthermore, since the capacitance value of capacitor 2a and the resistance value of resistor 2b can be controlled independently, it becomes easier to manufacture semiconductor chips CP with the electrical characteristics (capacitance and resistance values) as designed. This simplifies the control of the semiconductor chip CP manufacturing process.

[0154] The n-type impurity concentration of the n-type semiconductor layer NS1 is, for example, 1E16 / cm³. 3 It can be set to a certain extent. The n-type impurity concentration in the n-type semiconductor region NS2a is, for example, 1E20 / cm³. 3 It can be set to a certain extent. The n-type impurity concentration in the n-type semiconductor region NS3 is, for example, 1E20 / cm³. 3 It can be considered to be of a certain degree.

[0155] Furthermore, it is preferable that the distance L1 (see Figure 3) from the outer periphery (outer side surface) of the n-type semiconductor region NS3 to the outer periphery (outer side surface) of the n-type semiconductor layer NS2 in a plan view is greater than the distance L2 (see Figure 3) from the bottom surface (lower surface) of the n-type semiconductor region NS3 to the top surface of the n-type semiconductor layer NS1 (i.e., L1 > L2). This prevents leakage current from occurring through the outer side surface of the semiconductor chip CP.

[0156] Furthermore, in this embodiment, the electrodes at both ends of the snubber circuit 2 (here, the surface electrode HE and the back electrode BE) are arranged on opposite sides of the semiconductor chip CP. Therefore, as shown in Figure 23 or Figure 24, if the semiconductor chip CP is placed on the pad BPC (source electrode SE) of the power semiconductor chip PC via a conductive bonding material BD2, one of the surface electrode HE and the back electrode BE can be electrically connected to the source electrode SE of the power semiconductor chip PC. The other of the surface electrode HE and the back electrode BE can then be electrically connected to the drain back electrode RE of the power semiconductor chip PC via a wire BWC, a die pad DP, and a conductive bonding material BD1. This makes it easy to connect the power MOSFET 1 formed in the power semiconductor chip PC and the snubber circuit 2 formed in the semiconductor chip CP in parallel.

[0157] <Regarding variations of semiconductor chips (CP)> Figure 27 is a cross-sectional view showing a first modified example of the semiconductor chip CP of this embodiment. Figure 28 is a cross-sectional view showing a second modified example of the semiconductor chip CP of this embodiment. The semiconductor chip CP of the first modified example is referred to as semiconductor chip CP1. The semiconductor chip CP of the second modified example is referred to as semiconductor chip CP2.

[0158] The differences between the first modified semiconductor chip CP1 shown in Figure 27 and the semiconductor chip CP shown in Figure 3 are explained below.

[0159] In the semiconductor chip CP shown in Figure 3, groove TR1 is formed within the n-type semiconductor region NS3, and the depth of the bottom surface of groove TR1 is shallower than the depth of the bottom surface of the n-type semiconductor region NS3. Therefore, the bottom and sides of groove TR1 are covered by the n-type semiconductor region NS3, and the n-type semiconductor region NS3 exists below the bottom surface of groove TR1. Alternatively, groove TR1 does not penetrate the n-type semiconductor region NS3 and does not reach the n-type semiconductor region NS2a.

[0160] In the semiconductor chip CP1 shown in Figure 27, the groove TR1 is formed within the n-type semiconductor region NS3 and the n-type semiconductor region NS2a. The depth of the bottom surface of the groove TR1 is deeper than the depth of the bottom surface of the n-type semiconductor region NS3, and shallower than the depth of the top surface of the n-type semiconductor layer NS1. Therefore, the upper side surface of the groove TR1 is covered by the n-type semiconductor region NS3, while the lower side surface and bottom surface of the groove TR1 are covered by the n-type semiconductor region NS2a. Alternatively, the groove TR1 penetrates the n-type semiconductor region NS3 and reaches the n-type semiconductor region NS2a. Therefore, the corner TR1a of the groove TR1 is covered by the n-type semiconductor region NS2a, not the n-type semiconductor region NS3. Here, the corner TR1a of the groove TR1 corresponds to the corner where the side surface and bottom surface of the groove TR1 intersect.

[0161] Therefore, when manufacturing the semiconductor chip CP1 shown in Figure 27, if groove TR1 is formed as shown in Figure 6 or Figure 14, groove TR1 penetrates the n-type semiconductor region NS3, and the bottom surface of groove TR becomes deeper than the bottom surface of the n-type semiconductor region NS3.

[0162] When a potential difference exists between the surface electrode HE and the back electrode BE, electric field concentration is likely to occur near the corner TR1a of the groove TR1. In the semiconductor chip CP1 shown in Figure 27, the corner TR1a of the groove TR1 is covered not by the n-type semiconductor region NS3, but by an n-type semiconductor region NS2a having a lower n-type impurity concentration than the n-type semiconductor region NS3. Therefore, electric field concentration near the corner TR1a of the groove TR1 can be mitigated. As a result, the breakdown voltage of the semiconductor chip CP1 can be improved.

[0163] On the other hand, in the semiconductor chip CP shown in Figure 3, the entire groove TR1 is covered with an n-type semiconductor region NS3 having a higher n-type impurity concentration than the n-type semiconductor region NS2a, thus efficiently increasing the capacitance value of capacitor 2a.

[0164] The differences between the semiconductor chip CP2 of the second modified example shown in Figure 28 and the semiconductor chip CP shown in Figure 3 are explained below.

[0165] In the semiconductor chip CP2 shown in Figure 28, an n-type semiconductor region NS3a is formed within the n-type semiconductor layer NS2 (more specifically, within the n-type semiconductor region NS3) along the side surface of the groove TR1. The n-type impurity concentration in the n-type semiconductor region NS3a is higher than that in the n-type semiconductor region NS3.

[0166] The n-type semiconductor region NS3a can be formed, for example, by implanting n-type impurities into the semiconductor substrate SB1 from the side of the groove TR1 using oblique ion implantation, after forming the groove TR1 as shown in Figure 6 or Figure 14, but before forming the insulating film CZ.

[0167] In the semiconductor chip CP2 shown in Figure 28, an n-type semiconductor region NS3a is formed which has a higher n-type impurity concentration than the n-type semiconductor region NS3, thereby further increasing the capacitance value of capacitor 2a.

[0168] On the other hand, in the semiconductor chip CP shown in Figure 3, the oblique ion implantation process for forming the n-type semiconductor region NS3a is unnecessary, thus reducing the number of manufacturing steps for the semiconductor chip CP.

[0169] (Embodiment 2) Figure 29 is a planar perspective view showing the semiconductor package (semiconductor device, electronic device) PKG2 of this second embodiment. Figure 30 is a cross-sectional view of the semiconductor package PKG2. Figure 30 corresponds to the cross-sectional view along the line B1-B1 in Figure 29.

[0170] The differences between the semiconductor package PKG2 of this second embodiment and the semiconductor package PKG of the first embodiment described above will be explained below.

[0171] In the semiconductor package PKG of the above embodiment 1, the semiconductor chip CP is mounted on the pad BPC (source electrode SE) of the power semiconductor chip PC via a conductive bonding material BD2.

[0172] In the semiconductor package PKG of this second embodiment, as shown in Figures 29 and 30, the semiconductor chip CP is arranged on the upper surface of the die pad DP via a conductive bonding material BD2. That is, the power semiconductor chip PC and the semiconductor chip CP are arranged on the upper surface of the die pad DP, and the power semiconductor chip PC and the semiconductor chip CP do not overlap in a plan view.

[0173] In the case of Figure 30, the semiconductor chip CP is positioned on the upper surface of the die pad DP via a conductive bonding material BD2, such that the back electrode BE of the semiconductor chip CP faces the upper surface of the die pad DP via the bonding material BD2. Therefore, the back electrode BE of the semiconductor chip CP is electrically connected to the die pad DP via the conductive bonding material BD2, and further electrically connected to the back electrode RE of the power semiconductor chip PC via the die pad DP and the conductive bonding material BD1. Since the semiconductor chip CP is not mounted on the power semiconductor chip PC, there is no need to provide a pad BPC for mounting the semiconductor chip CP in the power semiconductor chip PC.

[0174] The surface electrode HE of the semiconductor chip CP is electrically connected to the source pad BPS (source electrode SE) of the power semiconductor chip PC via a wire BWC. Specifically, one end of the wire BWC is connected to the surface electrode HE of the semiconductor chip CP, and the other end of the wire BWC is connected to the source pad BPS (source electrode SE) of the power semiconductor chip PC.

[0175] Therefore, in the case of Figure 30, the back electrode BE of the semiconductor chip CP is electrically connected to the drain of the power MOSFET 1 formed within the power semiconductor chip PC via the die pad DP, the conductive bonding material BD1, and the back electrode RE of the power semiconductor chip PC. Then, the front electrode HE of the semiconductor chip CP is electrically connected to the source of the power MOSFET 1 formed within the power semiconductor chip PC via the wire BWC and the source pad BPS (source electrode SE) of the power semiconductor chip PC. As a result, the power MOSFET 1 formed within the power semiconductor chip PC and the snubber circuit 2 formed within the semiconductor chip CP are connected in parallel, as shown in Figure 1. In other words, the case of Figure 30 corresponds to the circuit configuration in Figure 1.

[0176] In this second embodiment, the semiconductor chip CP is placed on the die pad DP rather than on the power semiconductor chip PC. Therefore, when connecting wires BW to the multiple source pads BPS and gate pads BPG of the power semiconductor chip PC, the semiconductor chip CP does not get in the way. Consequently, the wire bonding process becomes easier.

[0177] In the above embodiment 1, the semiconductor chip CP is placed on the power semiconductor chip PC, rather than on the die pad DP. This is advantageous for miniaturizing the semiconductor package PKG.

[0178] Figure 31 is a planar perspective view showing a first modified example of the semiconductor package PKG2 of this second embodiment. Figure 32 corresponds to a cross-sectional view along the line B2-B2 in Figure 31. The semiconductor package PKG2 of the first modified example is referred to as semiconductor package PKG2a.

[0179] The differences between the semiconductor package PKG2a shown in Figures 31 and 32 and the semiconductor package PKG2 shown in Figures 29 and 30 are explained below.

[0180] In the semiconductor package PKG2a, as shown in Figures 31 and 32, the surface electrode HE of the semiconductor chip CP is electrically connected to the source pad BPS (source electrode SE) of the power semiconductor chip PC via source wire BWS1, one of the multiple source wires BWS. Specifically, one end of source wire BWS1 is connected to the lead connection part LB via a conductive bonding material BD3 such as solder, the central part of source wire BWS1 is connected to the source pad BPS (source electrode SE) of the power semiconductor chip PC via the conductive bonding material BD3, and the other end of source wire BWS1 is connected to the surface electrode HE of the semiconductor chip CP via the conductive bonding material BD3.

[0181] Therefore, in the case of Figure 32, the back electrode BE of the semiconductor chip CP is electrically connected to the drain of the power MOSFET 1 formed in the power semiconductor chip PC via the die pad DP, the conductive bonding material BD1, and the back electrode RE. Then, the front electrode HE of the semiconductor chip CP is electrically connected to the source of the power MOSFET 1 formed in the power semiconductor chip PC via the source wire BWS1 and the source pad BPS (source electrode SE) of the power semiconductor chip PC. As a result, as shown in Figure 1, the power MOSFET 1 formed in the power semiconductor chip PC and the snubber circuit 2 formed in the semiconductor chip CP are connected in parallel.

[0182] Figure 33 is a cross-sectional view showing a second modified example of the semiconductor package PKG2 of this second embodiment. The semiconductor package PKG2 of the second modified example is referred to as semiconductor package PKG2b.

[0183] The semiconductor package PKG2b shown in Figure 33 differs from the semiconductor package PKG2 shown in Figure 30 in the orientation of the semiconductor chip CP. The differences between the semiconductor package PKG2b shown in Figure 33 and the semiconductor package PKG2 shown in Figure 30 are explained below.

[0184] As shown in Figure 33, in the semiconductor package PKG2b, the semiconductor chip CP is positioned on the upper surface of the die pad DP via a conductive bonding material BD2, such that the surface electrode HE of the semiconductor chip CP faces the upper surface of the die pad DP via the bonding material BD2. Therefore, the surface electrode HE of the semiconductor chip CP is electrically connected to the die pad DP via the conductive bonding material BD2, and further electrically connected to the back electrode RE of the power semiconductor chip PC via the die pad DP and the conductive bonding material BD1. The back electrode BE of the semiconductor chip CP is electrically connected to the source pad BPS (source electrode SE) of the power semiconductor chip PC via a wire BWC. Specifically, one end of the wire BWC is connected to the back electrode BE of the semiconductor chip CP, and the other end of the wire BWC is connected to the source pad BPS (source electrode SE) of the power semiconductor chip PC.

[0185] Therefore, in the case of Figure 33, the surface electrode HE of the semiconductor chip CP is electrically connected to the drain of the power MOSFET 1 formed in the power semiconductor chip PC via the die pad DP, the conductive bonding material BD1, and the back electrode RE. Then, the back electrode HE of the semiconductor chip CP is electrically connected to the source of the power MOSFET 1 formed in the power semiconductor chip PC via the wire BWC and the source pad BPS (source electrode SE) of the power semiconductor chip PC. As a result, the power MOSFET 1 formed in the power semiconductor chip PC and the snubber circuit 2 formed in the semiconductor chip CP are connected in parallel, as shown in Figure 2. In other words, the case of Figure 33 corresponds to the circuit configuration in Figure 2.

[0186] The semiconductor package PKG2a of the first modified example and the semiconductor package PKG2b of the second modified example can also be combined. In that case, the semiconductor chip CP in the semiconductor package PKG2a of the first modified example shown in Figure 32 should be inverted. In that case, the surface electrode HE of the semiconductor chip CP is electrically connected to the die pad DP via the conductive bonding material BD2, and the back electrode BE of the semiconductor chip CP is electrically connected to the source pad BPS (source electrode SE) of the power semiconductor chip PC via the source wire BWS1.

[0187] (Embodiment 3) Figure 34 is a plan view showing a case where an IPD (Intelligent Power Device) is used as the power semiconductor chip PC. The power semiconductor chip PC to which the IPD is applied is referred to as power semiconductor chip PC1. In Figure 34, the source electrode SE is shown by a dashed line, and the control circuit section CNT is shown by a dashed line. The differences between this embodiment 3 and embodiments 1 and 2 described above will be explained below.

[0188] The power semiconductor chip PC1 shown in Figure 34 contains a power MOSFET 1 (not shown here) and a control circuit section CNT (Central Transistor Unit), as described in Embodiment 1 above. As described with reference to Figure 22 above, the power MOSFET 1 is formed by connecting multiple unit transistor cells Q1 formed on the semiconductor substrate constituting the power semiconductor chip PC1 in parallel. The source electrode SE is formed to cover almost the entire transistor cell region where the multiple unit transistor cells Q1 are formed.

[0189] Figure 34 also shows the semiconductor chip CP placed on the power semiconductor chip PC1. Since one of the surface electrodes HE and back electrode BE of semiconductor chip CP needs to be electrically connected to the source electrode SE of power semiconductor chip PC1, semiconductor chip CP is positioned so as to overlap with the source electrode SE of power semiconductor chip PC1 in a plan view. In other words, semiconductor chip CP is positioned so as to overlap with the transistor cell region where multiple unit transistor cells Q1 are formed, but not with the control circuit section CNT.

[0190] The present invention has been described in detail above based on its embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0191] 1 Power MOSFET 2. Snubber Circuit 2a Capacitor 2b resistance 3 Body Diode BD1, BD2, BD3 bonding material BE,BE101,BE201 Back electrode BPC Pad BPG Gate Pad BPS Source Pad BW, BWC, BWG, BWS, BWS1 wire CNT control circuit section CP, CP1, CP2, CP101, CP201 ​​semiconductor chips CT1, CT2 contact holes CZ, CZ101, CZ201 Insulating Film D1 Drain DP Die Pad EP semiconductor layer G1 Gate GE Terminal GEW gate wiring GF gate insulating film HE,HE101,HE201 Surface electrode IL interlayer film LB lead connection section LD Lead LDG gate lead LDS source lead MR sealing part NR n-type semiconductor region NS1, NS2 n-type semiconductor layer NS2a, NS3, NS3a, NS203 n-type semiconductor region OP1, OP101, OP201, OPG, OPS opening PA, PA101, PA201, PV insulating film PC, PC1 Power Semiconductor Chip PE, PE101, PE201 Polysilicon electrodes PKG, PKG1, PKG2, PKG2a, PKG2b Semiconductor Packages PR p-type semiconductor region PS polysilicon film Q1 Unit transistor cell RE back electrode S1 Source SB1, SB2, SB101, SB201 Semiconductor Substrates SB1a n-type circuit board main unit SE source electrode TE1, TE2 terminals TG Trench Gridgate TGL wiring section TR1,TR2,TR101,TR201 Groove TR1a Corner

Claims

1. A first semiconductor layer of a first conductivity type having a first upper surface and a first lower surface opposite to the first upper surface, A second semiconductor layer of the first conductivity type formed on the first upper surface of the first semiconductor layer, A first semiconductor region of the first conductivity type formed within the second semiconductor layer from the second upper surface of the second semiconductor layer, A trench formed within the first semiconductor region, A first insulating film formed on the second upper surface of the second semiconductor layer, including the bottom surface of the trench and the side surface of the trench, A first electrode is formed on the first insulating film so as to fill the trench, A surface electrode formed on the first electrode and electrically connected to the first electrode, A back electrode formed on the first lower surface of the first semiconductor layer and electrically connected to the first semiconductor layer, It has, The first semiconductor region is formed within the second semiconductor layer such that, in a cross-sectional view, the bottom surface of the first semiconductor region does not reach the first semiconductor layer. Each of the aforementioned surface electrode and the aforementioned back electrode is made of metal. A semiconductor device wherein the impurity concentration of the second semiconductor layer between the first semiconductor region and the first semiconductor layer is lower than the impurity concentrations of the first semiconductor layer and the first semiconductor region, respectively.

2. In the semiconductor device described in claim 1, The first electrode is a semiconductor device made of polysilicon.

3. In the semiconductor device described in claim 1, The bottom surface of the trench is shallower than the bottom surface of the first semiconductor region. A semiconductor device in which the bottom surface of the trench is covered by the first semiconductor region.

4. In the semiconductor device described in claim 1, The bottom surface of the trench is deeper than the bottom surface of the first semiconductor region. The trench penetrates the first semiconductor region, and is a semiconductor device.

5. In the semiconductor device described in claim 1, Within the first semiconductor region, a second semiconductor region of the first conductivity type is formed along the side surface of the trench. A semiconductor device wherein the impurity concentration in the second semiconductor region is higher than the impurity concentration in the first semiconductor region.

6. In the semiconductor device described in claim 1, A semiconductor device in which the distance from the outer periphery of the first semiconductor region to the outer periphery of the second semiconductor layer in a plan view is greater than the distance from the bottom surface of the first semiconductor region to the first top surface of the first semiconductor layer.

7. In the semiconductor device described in claim 1, A semiconductor device in which a capacitive element is formed by the surface electrode, the first insulating film, and the first semiconductor region.

8. In the semiconductor device according to claim 7, The aforementioned capacitive element is a semiconductor device that constitutes a snubber circuit.

9. (a) A step of preparing a semiconductor substrate of a first conductivity type having a main surface and a back surface opposite to the main surface, (b) A step of forming a first semiconductor region of the first conductivity type within the semiconductor substrate from the main surface of the semiconductor substrate, (c) A step of forming a trench in the first semiconductor region, (d) A step of forming a first insulating film on the main surface of the semiconductor substrate, including the bottom surface of the trench and the side surface of the trench. (e) A step of forming a first electrode on the first insulating film so as to fill the trench, (f) A step of forming a surface electrode on the first electrode that is electrically connected to the first electrode, (g) A step of forming the first semiconductor layer of the first conductivity type within the semiconductor substrate from the back surface of the semiconductor substrate, (h) After step (g), a step of forming a back electrode on the back surface of the semiconductor substrate, It has, The first semiconductor layer has a lower surface that coincides with the back surface and an upper surface that is opposite to the lower surface. The bottom surface of the first semiconductor region does not reach the first semiconductor layer. Each of the aforementioned surface electrode and the aforementioned back electrode is made of metal. A method for manufacturing a semiconductor device, wherein the impurity concentrations of the first semiconductor layer and the first semiconductor region are higher than the impurity concentrations of the semiconductor substrate.

10. In the method for manufacturing a semiconductor device according to claim 9, The first electrode is made of polysilicon, and the method for manufacturing a semiconductor device.

11. In the method for manufacturing a semiconductor device according to claim 9, A method for manufacturing a semiconductor device, wherein the bottom surface of the trench is shallower than the bottom surface of the first semiconductor region.

12. In the method for manufacturing a semiconductor device according to claim 9, A method for manufacturing a semiconductor device, wherein the bottom surface of the trench is deeper than the bottom surface of the first semiconductor region.

13. In the method for manufacturing a semiconductor device according to claim 9, After the step (c) and before the step (d), (c1) A step of forming a second semiconductor region of the first conductivity type in the semiconductor substrate by oblique ion implantation, so as to be along the side surface of the trench. It further possesses, A method for manufacturing a semiconductor device, wherein the impurity concentration in the second semiconductor region is higher than the impurity concentration in the first semiconductor region.

14. The chip mounting section, Displaced on the chip mounting portion via a conductive first bonding material, and comprising a first semiconductor chip including a power MOSFET, A second semiconductor chip is disposed on the first semiconductor chip via a conductive second bonding material, It has, The first semiconductor chip has a source electrode and a back surface drain electrode formed on the opposite side of the source electrode. The back surface drain electrode of the first semiconductor chip is electrically connected to the chip mounting portion via the first bonding material. The second semiconductor chip is A first semiconductor layer of a first conductivity type having a first upper surface and a first lower surface opposite to the first upper surface, A second semiconductor layer of the first conductivity type formed on the first upper surface of the first semiconductor layer, A first semiconductor region of the first conductivity type formed within the second semiconductor layer from the second upper surface of the second semiconductor layer, A trench formed within the first semiconductor region, A first insulating film formed on the second upper surface of the second semiconductor layer, including the bottom surface of the trench and the side surface of the trench, A first electrode is formed on the first insulating film so as to fill the trench, A surface electrode formed on the first electrode and electrically connected to the first electrode, A back electrode formed on the first lower surface of the first semiconductor layer and electrically connected to the first semiconductor layer, It has, The first semiconductor region is formed within the second semiconductor layer such that, in a cross-sectional view, the bottom surface of the first semiconductor region does not reach the first semiconductor layer. Each of the aforementioned surface electrode and the aforementioned back electrode is made of metal. The impurity concentration of the second semiconductor layer between the first semiconductor region and the first semiconductor layer is lower than the impurity concentrations of the first semiconductor layer and the first semiconductor region, respectively. The second semiconductor chip is placed on the source electrode of the first semiconductor chip via the first bonding material, A semiconductor device in which one of the surface electrode and the back electrode of the first semiconductor chip is electrically connected to the source electrode of the first semiconductor chip via the second bonding material.

15. In the semiconductor device according to claim 14, A semiconductor device further comprising a conductive connecting member for electrically connecting the surface electrode and the other of the back electrode of the first semiconductor chip to the chip mounting portion.

16. In the semiconductor device according to claim 15, A semiconductor device in which a capacitive element is formed by the surface electrode, the first insulating film, and the first semiconductor region.

17. In the semiconductor device according to claim 16, The aforementioned capacitive element is a semiconductor device that constitutes a snubber circuit.

18. In the semiconductor device according to claim 14, The first electrode is a semiconductor device made of polysilicon.

19. In the semiconductor device according to claim 14, The bottom surface of the trench is shallower than the bottom surface of the first semiconductor region. A semiconductor device in which the bottom surface of the trench is covered by the first semiconductor region.

20. In the semiconductor device according to claim 14, The bottom surface of the trench is deeper than the bottom surface of the first semiconductor region. The trench penetrates the first semiconductor region, and is a semiconductor device.

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