Semiconductor equipment

Abstract

The objective is to provide a semiconductor device that can reduce on-resistance while suppressing an increase in threshold voltage. [Solution] The semiconductor device of the embodiment has a plurality of first trenches recessed on one side in the thickness direction of a semiconductor substrate and accommodating a first electrode. It has a second trench recessed on one side in the thickness direction and accommodating a second electrode. It has a base layer surrounding the first electrode. It has a source layer in contact with the base layer and surrounding the first electrode. It has a drift layer of second conductivity type in contact with the base layer. It has a plurality of source electrodes electrically connected to the plurality of first electrodes and the source layer. Viewed from the thickness direction, the second trenches surround each of the plurality of first trenches. The second trenches have a plurality of first extensions extending in a first direction perpendicular to the thickness direction, and a plurality of second extensions extending in a second direction perpendicular to the thickness direction and intersecting the first direction. The width of each of the plurality of second extensions is narrower than the width of each of the plurality of first extensions.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] A semiconductor device with a trench-type field plate electrode structure is known to increase the cell breakdown voltage, and this configuration involves embedding field plate electrodes in trenches arranged in a dot pattern. In such a semiconductor device, reducing the on-resistance requires reducing the spacing between field plate electrodes. However, reducing the spacing between field plate electrodes by shortening the distance between the carrier-vacuum layer and the insulating film that insulates the gate electrode may increase the threshold voltage of the semiconductor device. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 5580150 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor device that can reduce on-resistance while suppressing an increase in threshold voltage. [Means for solving the problem]

[0005] The semiconductor device of the embodiment has a plurality of first trenches recessed from the surface of a semiconductor substrate to one side in the thickness direction of the semiconductor substrate, and housing a first electrode inside. It has a second trench recessed from the surface to one side in the thickness direction, and housing a second electrode inside. It has a base layer of first conductivity type located between the first and second trenches and surrounding the first electrode. It has a source layer of second conductivity type located to the other side in the thickness direction of the base layer, in contact with the base layer, and surrounding the first electrode. It has a drift layer of second conductivity type located to one side in the thickness direction of the base layer and in contact with the base layer. It has a source electrode located to one side in the thickness direction of the semiconductor substrate and electrically connected to the plurality of first electrodes and the source layer. Viewed from the thickness direction, the second trench surrounds each of the plurality of first trenches. The second trench has a plurality of first extensions extending in a first direction perpendicular to the thickness direction, and a plurality of second extensions extending in a second direction perpendicular to the thickness direction and intersecting the first direction. The width of each of the multiple second extensions is narrower than the width of each of the multiple first extensions. [Brief explanation of the drawing]

[0006] [Figure 1] A plan view showing a mechanism of the first embodiment. [Figure 2] A cross-sectional view showing a semiconductor device of the first embodiment, the II-II cross-sectional view of Figure 1. [Figure 3] A cross-sectional view showing a semiconductor device of the first embodiment, the III-III cross-sectional view of Figure 1. [Figure 4] A first cross-sectional view showing the manufacturing process of a semiconductor device according to an embodiment. [Figure 5] A second cross-sectional view showing the manufacturing process of a semiconductor device according to the embodiment. [Figure 6] A third cross-sectional view showing the manufacturing process of a semiconductor device according to the embodiment. [Figure 7] A fourth cross-sectional view showing the manufacturing process of the semiconductor device of the embodiment. [Figure 8] A fifth cross-sectional view showing the manufacturing process of the semiconductor device according to the embodiment. [Figure 9] A plan view showing a semiconductor device of the second embodiment. [Figure 10]A plan view showing a semiconductor device of the third embodiment. [Figure 11] A plan view showing a mechanism of the fourth embodiment. [Modes for carrying out the invention]

[0007] The semiconductor device of the embodiment will be described below with reference to the drawings.

[0008] The direction in which the Z-axis extends in each drawing is the thickness direction of the semiconductor device. The side in which the Z-axis arrow points (+Z side) is the bottom side of the semiconductor device. The side opposite to the direction in which the Z-axis arrow points (-Z side) is the top side of the semiconductor device. In the following explanation, the bottom side of the semiconductor device will be referred to as the "bottom side" or "one side in the thickness direction," the top side of the semiconductor device will be referred to as the "top side" or "the other side in the thickness direction," and the thickness direction of the semiconductor device will simply be referred to as the "thickness direction." Note that "top side" and "bottom side" are not terms that indicate a relationship to the direction of gravity.

[0009] The first direction D1 shown in each drawing is the direction perpendicular to the thickness direction. The second direction D2 shown in each drawing is perpendicular to the thickness direction and intersects with the first direction D1.

[0010] In this specification, terms such as "orthogonal," "identical," and "similar," as well as values ​​of length and angle, which specify the shape of each part constituting a semiconductor device and the degree of the relative arrangement between each part, shall not be bound by their strict meaning, but shall be interpreted to include a range within which similar functions can be expected and the range of design tolerances.

[0011] In this specification, N + , N - , P + , and P - The notation indicates the relative magnitudes of carrier concentrations in each conductivity type. + is N - This indicates that the concentration of N-type carriers is relatively higher than that of P. + P -It indicates that the P-type carrier concentration is relatively higher. Also, in this specification, the P-type is the first conductivity type and the N-type is the second conductivity type.

[0012] (First Embodiment) FIG. 1 is a plan view showing the semiconductor device 10 of this embodiment. In FIG. 1, the description of the insulating layer 30 and the source electrode 32, which will be described later, is omitted. FIG. 2 is a cross-sectional view showing the semiconductor device 10 of this embodiment, which is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view showing the semiconductor device 10 of this embodiment, which is a cross-sectional view taken along line III-III in FIG. 1. The semiconductor device 10 of this embodiment is a semiconductor device such as a MOSFET (metal-oxide-semiconductor field-effect transistor) and an IGBT (Insulated Gate Bipolar Transistor). As shown in FIG. 1, the semiconductor device 10 includes a plurality of first trenches 11 and a second trench 20. As shown in FIG. 2, the semiconductor device 10 includes a semiconductor substrate 40, an insulating layer 30, and a source electrode 32.

[0013] Each of the plurality of first trenches 11 is a depression that depresses downward from the surface 40a of the semiconductor substrate 40, that is, one side (+Z side) in the thickness direction. As shown in FIG. 1, when viewed from the thickness direction, each first trench 11 is substantially circular in shape. When viewed from the thickness direction, the shape of each first trench 11 may be other shapes such as a rectangular shape and a hexagonal shape. Each first trench 11 is arranged in a staggered manner in a direction orthogonal to the thickness direction. More specifically, a plurality of first trench columns each composed of a plurality of first trenches 11 arranged at intervals in the second direction D2 are arranged at intervals in the first direction D1. In this embodiment, when viewed from the first direction D1, the first trenches 11 included in each of the two first trench columns arranged adjacent to each other in the first direction D1 are arranged at positions shifted in the second direction D2. In this embodiment, the second direction D2 is orthogonal to the first direction D1. Note that the plurality of first trenches 11 constituting the first trench column may be arranged at intervals in a direction different from the second direction D2.

[0014] The virtual line V2 shown in FIG. 1 is a virtual line that extends in the second direction D2 and passes through the centers of the plurality of first trenches 11. In the present embodiment, the interval in the first direction D1 between the virtual lines V2 adjacent to each other in the first direction D1 among the plurality of virtual lines V2, that is, the interval P11 between the first trenches 11 in the first direction D1, is smaller than the interval P12 between the first trenches 11 in the second direction D2. Also, in the present embodiment, when viewed from the thickness direction, the lengths Pc of the three sides of the triangle having the centers of three adjacent first trenches 11 as vertices are the same as each other. Therefore, the intervals Pc between each of the first trenches 11 are all the same length.

[0015] As shown in FIGS. 2 and 3, inside each of the first trenches 11, a first insulating film 12 and a first electrode 13 are accommodated. The first insulating film 12 is formed on the inner surface of the first trench 11. The first insulating film 12 insulates the first electrode 13 from each of the drift layer 14, the base layer 15, and the carrier extraction layer 16. As the material constituting the first insulating film 12, for example, silicon oxide, silicon nitride, or the like can be used. As shown in FIG. 1, when viewed from the thickness direction, the first insulating film 12 is substantially annular and surrounds the first electrode 13.

[0016] As shown in FIG. 2, the first electrode 13 is substantially cylindrical and extends in the thickness direction inside the first trench 11. As shown in FIG. 1, when viewed from the thickness direction, the first insulating film 12 is substantially circular. When viewed from the thickness direction, the shape of the first electrode 13 may be other shapes such as a rectangular shape and a hexagonal shape. As shown in FIG. 2, the first electrode 13 is insulated from each of the drift layer 14, the base layer 15, and the carrier extraction layer 16 by the first insulating film 12. In the present embodiment, the first electrode 13 is a field plate electrode. In the present embodiment, the first electrode 13 is made of, for example, polysilicon. The first electrode 13 has conductivity. The upper end of the first electrode 13 is connected to the source electrode 32.

[0017] As shown in FIGS. 2 and 3, the base layer 15 is disposed between the first trench 11 and the second trench 20. The base layer 15 surrounds the first electrode 13. Although not shown, the base layer 15 is cylindrical and extends in the thickness direction. The base layer 15 contacts the first insulating film 12 and the second insulating film 24. In the present embodiment, the base layer 15 is formed by implanting P-type impurity ions such as boron into a part of the drift layer 14 made of an N-type silicon layer and performing thermal diffusion, that is, a first conductivity type of P - type silicon layer.

[0018] The carrier extraction layer 16 surrounds a portion including the upper end of the first insulating film 12. The carrier extraction layer 16 is electrically connected to the base layer 15. The carrier extraction layer 16 is connected to the source electrode 32. The carrier extraction layer 16 is cylindrical and extends in the thickness direction. As shown in FIG. 1, when viewed from the thickness direction, the carrier extraction layer 16 surrounds each first trench 11. The dimension of the carrier extraction layer 16 in the second direction D2 is larger than the dimension of the first trench 11 in the second direction D2. The dimension of the carrier extraction layer 16 in the first direction D1 is substantially the same as the dimension of the first trench 11 in the first direction D1. The dimension of the carrier extraction layer 16 in the first direction D1 may be larger than the dimension of the first trench 11 in the first direction D1. In the present embodiment, the carrier extraction layer 16 is formed by implanting P-type impurity ions such as boron into a part of each of the base layer 15 and the source layer 17 and performing thermal diffusion, that is, P + type silicon layer.

[0019] As shown in FIG. 2, the source layer 17 is disposed above the base layer 15. The source layer 17 contacts the base layer 15. The source layer 17 contacts the source electrode 32. Thereby, the source layer 17 is electrically connected to the source electrode 32. As shown in FIG. 1, when viewed from the thickness direction, the source layer 17 surrounds the first electrode 13. When viewed from the thickness direction, the source layer 17 surrounds the carrier extraction layer 16. In the present embodiment, the source layer 17 is formed by implanting N-type impurity ions such as high-concentration phosphorus and arsenic into a part of the base layer 15 and performing thermal diffusion, that is, a second conductivity type of N +This is a molded silicon layer. In this embodiment, the dimension S2 in the second direction D2 of the source layer 17 shown in Figure 2 and the dimension S1 in the first direction D1 of the source layer 17 shown in Figure 3 are the same.

[0020] The drift layer 14 is positioned below the base layer 15. The drift layer 14 is in contact with the base layer 15. The drift layer 14 is in contact with the first insulating film 12 and the second insulating film 24, respectively. In this embodiment, the drift layer 14 is N - This is a molded silicon layer.

[0021] As shown in Figure 2, the second trench 20 is a depression that extends downward from the surface 40a of the semiconductor substrate 40, i.e., to one side in the thickness direction (+Z side). The thickness dimension of the second trench 20 is smaller than the thickness dimension of each first trench 11. As shown in Figure 1, viewed from the thickness direction, the second trench 20 surrounds each of the multiple first trenches 11. More specifically, viewed from the thickness direction, the second trench 20 surrounds the source layer 17 surrounding each first electrode 13. The second trench 20 has a plurality of first extensions 21 and a plurality of second extensions 22.

[0022] Each first extension 21 is a portion of the second trench 20 that extends in the first direction D1. In this embodiment, each first extension 21 extends linearly in the first direction D1. Each of the multiple first extensions 21 is positioned between adjacent first trenches 11 that are arranged in the second direction D2.

[0023] Each second extension 22 is a portion of the second trench 20 that extends in the second direction D2. In this embodiment, each second extension 22 extends linearly in the second direction D2. Each of the multiple second extensions 22 is positioned between adjacent first trenches 11 arranged in the first direction D1. Both ends of each first extension 21 in the first direction D1 are connected to different second extensions 22. Thus, each first extension 21 is connected to each other via each second extension 22. Also, each second extension 22 is connected to each other via each first extension 21. The width W12 of each of the multiple second extensions 22 is narrower than the width W11 of each of the multiple first extensions 21. In other words, the width W11 of each of the multiple first extensions 21 is wider than the width W12 of each of the multiple second extensions 22.

[0024] As shown in Figures 2 and 3, the second insulating film 24 and the second electrode 25 are housed inside the second trench 20. The second insulating film 24 is formed on the inner surface of the second trench 20. The second insulating film 24 insulates the second electrode 25 from the drift layer 14, the base layer 15, and the source layer 17, respectively. As the material constituting the second insulating film 24, for example, silicon oxide and silicon nitride can be used. As shown in Figure 1, viewed from the thickness direction, the second insulating film 24 surrounds the source layer 17. Viewed from the thickness direction, the second insulating film 24 formed on the inner surface of the first stretched portion 21 extends in the first direction D1, and the second insulating film 24 formed on the inner surface of the second stretched portion 22 extends in the second direction D2.

[0025] As shown in Figure 2, the second electrode 25 is stretched in the thickness direction within the second trench 20. The second electrode 25 is insulated from the drift layer 14, the base layer 15, and the source layer 17, respectively, by the second insulating film 24. In this embodiment, the second electrode 25 is a gate electrode. In this embodiment, the second electrode 25 is made of, for example, polysilicon. The second electrode 25 is conductive.

[0026] As shown in Figure 1, the second electrode 25 is provided inside the entire second trench 20. Viewed from the thickness direction, the portion of the second electrode 25 that is housed inside each first extension portion 21 extends in the first direction D1. Viewed from the thickness direction, the portion of the second electrode 25 that is housed inside each second extension portion 22 extends in the second direction D2.

[0027] As shown in Figure 1, a conductive portion 26 is located in the second trench 20. More specifically, a conductive portion 26 is located in each of the multiple first extensions 21. No conductive portion 26 is located in each of the multiple second extensions 22. As shown in Figure 2, the conductive portion 26 extends upward from the inside of the first extension 21. The lower portion of the conductive portion 26 is located inside the portion of the second electrode 25 located in the first extension 21 and is connected to the second electrode 25. Thus, the conductive portion 26 is electrically connected to the second electrode 25. The upper portion of the conductive portion 26 is located inside the insulating layer 30. Thus, the conductive portion 26 is insulated from the source electrode 32. The conductive portion 26 is also insulated from the drift layer 14, the base layer 15, the source layer 17, and the source electrode 32 by the second insulating film 24.

[0028] In this embodiment, the conductive portion 26 is made of metal. The conductive portion 26 is made of, for example, tungsten. The conductive portion 26 is conductive. Therefore, a portion of the gate current, which is the current flowing through the second electrode 25, flows through the conductive portion 26. This makes it possible to increase the cross-sectional area through which the gate current flows compared to the case where the conductive portion 26 is not provided on each first extension portion 21, and thus reduces the gate resistance Rg, which is the electrical resistance between one end of the second electrode 25 and the other end of the second electrode 25.

[0029] Furthermore, in this embodiment, the resistivity of the conductive portion 26 is smaller than that of the second electrode 25. This makes it easier to make the electrical resistance of the conductive portion 26 smaller than that of the second electrode 25, thus allowing for a more favorable reduction of the gate resistance Rg.

[0030] As will be described later, in this embodiment, tungsten is supplied by chemical vapor deposition to the interior of the recess 25a (see Figure 5) and the third hole 65 (see Figure 5), which are formed by etching the second insulating film 24 and the second electrode 25 respectively using the resist 71 as a mask, to form the conductive portion 26. Therefore, in order to reliably connect the second electrode 25 and the conductive portion 26, the width of the second electrode 25 needs to be wider than a predetermined width. Consequently, it is difficult to narrow the width of the portion of the second trench 20 in which the conductive portion 26 is located.

[0031] In contrast, in this embodiment, as described above, a conductive portion 26 is provided in each first extended portion 21, while a conductive portion 26 is not provided in each second extended portion 22. Therefore, in this embodiment, the width W12 of each second extended portion 22 can be made narrower than the width W11 of each first extended portion 21. This makes it possible to make the dimension S2 in the second direction D2 and the dimension S1 in the first direction D1 of the source layer 17 the same, while making the spacing P11 between the first trenches 11 in the first direction D1 smaller than the spacing P12 between the first trenches 11 in the second direction D2. Consequently, the spacing Pc between each first trench 11 can be reduced.

[0032] In this embodiment, the dimension S1 of the source layer 17 in the first direction D1 is the same as the first distance L1, which is the distance between the carrier void layer 16 and the second insulating film 24 in the first direction D1. Also, the dimension S2 of the source layer 17 in the second direction D2 is the same as the second distance L2, which is the distance between the carrier void layer 16 and the second insulating film 24 in the second direction D2. As described above, in this embodiment, since the dimension S1 of the source layer 17 in the first direction D1 and the dimension S2 of the source layer 17 in the second direction D2 are the same, the first distance L1 and the second distance L2 are the same. Therefore, in this embodiment, by making the width W12 of each second extension portion 22 narrower than the width W11 of each first extension portion 21, the distance Pc between each first trench 11 can be reduced while keeping the first distance L1 and the second distance L2 the same. This prevents the first distance L1 from becoming too short, and thus prevents the threshold voltage of the semiconductor device 10 from rising. Furthermore, since the spacing Pc between each of the first trenches 11 can be reduced, the on-resistance of the semiconductor device 10 can be reduced. In other words, in this embodiment, since the width W12 of each second extension 22 is narrower than the width W11 of each first extension 21, the on-resistance can be reduced while suppressing an increase in the threshold voltage of the semiconductor device 10.

[0033] As shown in Figures 2 and 3, the insulating layer 30 covers a portion of the source layer 17 and the conductive portion 26 from above. The insulating layer 30 insulates the conductive portion 26 from the source electrode 32. In this embodiment, the insulating layer 30 is a silicon oxide film.

[0034] The source electrode 32 is positioned above the semiconductor substrate 40. The source electrode 32 covers each of the first insulating films 12, each of the first electrodes 13, and the insulating layer 30, etc. The source electrode 32 is connected to each of the first electrodes 13, the carrier removal layer 16, and the source layer 17. As a result, each of the first electrodes 13, the carrier removal layer 16, and the source layer 17 is electrically connected to the source electrode 32. As described above, the carrier removal layer 16 is electrically connected to the base layer 15. Thus, the source electrode 32 electrically connects each of the multiple first electrodes 13 to the base layer 15. In this embodiment, the source electrode 32 is made of a metallic material such as aluminum.

[0035] Figure 4 is a first cross-sectional view showing the manufacturing process of the semiconductor device 10 of this embodiment. Figure 5 is a second cross-sectional view showing the manufacturing process of the semiconductor device 10 of this embodiment. Figure 6 is a third cross-sectional view showing the manufacturing process of the semiconductor device 10 of this embodiment. Figure 7 is a fourth cross-sectional view showing the manufacturing process of the semiconductor device 10 of this embodiment. Figure 8 is a fifth cross-sectional view showing the manufacturing process of the semiconductor device 10 of this embodiment. Next, the manufacturing method of the semiconductor device 10 of this embodiment will be described. In the following description, "workers, etc." includes workers and assembly equipment, etc., who perform the work in each process. The work in each process may be performed by workers alone, by assembly equipment alone, or by workers and assembly equipment.

[0036] First, the workers form a plurality of first trenches 11 in the semiconductor substrate 40, as shown in Figure 4. After forming an oxide film (not shown) on the surface 40a of the semiconductor substrate 40, the workers etch the oxide film using a resist patterned by lithography as a mask, and then etch the semiconductor substrate 40 using the patterned oxide film as a mask to form a plurality of first trenches 11. Next, the workers form a first insulating film 12, composed of silicon oxide and silicon nitride, etc., on the inner surface of each first trench 11 by thermal oxidation or chemical vapor deposition (CVD). Next, the workers form a first electrode 13, composed of polysilicon, inside each first trench 11 by chemical vapor deposition. Next, the workers form a silicon oxide film (not shown) on the surface of each first insulating film 12 and each first electrode 13.

[0037] Next, the workers form the second trench 20, the second insulating film 24, and the second electrode 25. After forming an oxide film (not shown) on the surface 40a of the semiconductor substrate 40, the workers etch the oxide film using a resist patterned by lithography as a mask, and then etch the semiconductor substrate 40 using the patterned oxide film as a mask to form the second trench 20. Next, the workers form the second insulating film 24, composed of silicon oxide and silicon nitride, etc., on the inner surface of the second trench 20 by thermal oxidation or chemical vapor deposition. Next, the workers form the second electrode 25, composed of polysilicon, inside each second trench 20 by chemical vapor deposition. Next, the workers remove the silicon oxide film formed on the surface of the semiconductor substrate 40 by etching.

[0038] Next, the workers form the base layer 15 and the source layer 17. The workers form the base layer 15 by implanting P-type impurity ions such as boron into a portion of the surface of the drift layer 14, which is made of N-type silicon, and performing thermal diffusion. Next, the workers form the source layer 17, which is made of N+ silicon, by implanting high concentrations of N-type impurity ions such as phosphorus and arsenic into the surface of the base layer 15 and performing thermal diffusion.

[0039] Next, the workers form a first insulating layer 61 that covers each of the first trenches 11, the second trench 20, and the source layer 17, as shown in Figure 4. The workers form the first insulating layer 61, which is made of a silicon oxide film, by thermal oxidation or chemical vapor deposition.

[0040] Next, as shown in Figure 5, the worker performs etching using the patterned resist 71 as a mask. In this embodiment, the etching is reactive ion etching (RIE). The resist 71 has a plurality of first holes 71a and a plurality of second holes 71c formed therein. Viewed from the thickness direction, the outer edge of each first hole 71a overlaps with the source layer 17. Therefore, a portion of the first insulating layer 61 and a portion of the source layer 17 are removed by etching. As a result, a contact opening Ac is formed, and the first insulating film 12 and the first electrode 13 are exposed on the upper side. In addition, the upper end portions of each first electrode 13 and each first insulating film 12 are also removed by the etching.

[0041] Viewed from the thickness direction, each second hole 71c overlaps with the center of two different second electrodes 25. The portions of the second insulating film 24 and the first insulating layer 61 that overlap with each second hole 71c when viewed from the thickness direction are removed by etching, forming a third hole 65 that penetrates the second insulating film 24 and the first insulating layer 61 in the thickness direction. Furthermore, the portions of the upper part of the second electrode 25 that overlap with each second hole 71c when viewed from the thickness direction are removed by etching. As a result, a recess 25a is formed on the lower side of the second electrode 25.

[0042] Next, the workers form the carrier removal layer 16 as shown in Figure 6. First, the workers remove the resist 71 by etching. Next, the workers form the carrier removal layer 16 by implanting P-type impurity ions such as boron into a portion of the base layer 15 through each contact opening Ac and performing thermal diffusion.

[0043] Next, the workers form a conductive layer ML that covers each of the first insulating films 12, each of the first electrodes 13, and the first insulating layer 61, etc. The workers form the conductive layer ML, which is made of tungsten, by chemical vapor deposition. A portion of the conductive layer ML penetrates into the recess 25a of the second electrode 25 through the third hole 65. The portion of the conductive layer ML formed inside the third hole 65 and inside the recess 25a forms a conductive portion 26.

[0044] Next, the workers remove a portion of the conductive layer ML by etching. More specifically, the workers remove the portion of the conductive layer ML that is not located inside the third hole 65 and inside the recess 25a by etching. As shown in Figure 7, the upper portion of the conductive layer ML formed inside the third hole 65 is removed by etching. This forms the conductive portion 26.

[0045] Next, the workers form a second insulating layer 62 that covers each of the first insulating films 12, each of the first electrodes 13, and the first insulating layer 61, etc. The workers form the second insulating layer 62, which is made of a silicon oxide film, by thermal oxidation or chemical vapor deposition.

[0046] Next, the worker performs etching using the patterned resist 72 as a mask. Multiple fourth holes 72a are formed in the resist 72. Viewed from the thickness direction, the outer edge of each fourth hole 72a overlaps with the source layer 17. Therefore, as shown in Figure 8, the portion of the second insulating layer 62 that overlaps with the first trench 11 when viewed from the thickness direction is removed by etching. As a result, the upper ends of each first insulating film 12 and each first electrode 13 are exposed on the upper side. In addition, a portion of the first insulating layer 61 is removed by etching. As a result, a portion of the source layer 17 is exposed on the upper side. The first insulating layer 61 and the second insulating layer 62 that were not removed by etching constitute the insulating layer 30. In this embodiment, the etching is reactive ion etching (RIE).

[0047] Next, the worker removes the resist 72 by etching, then deposits a wiring layer (not shown) by sputtering or the like, and then forms the source electrode 32 shown in Figure 2 using the resist patterned by lithography as a mask. In this embodiment, the source electrode 32 is made of metal. In this embodiment, the source electrode 32 is made of a metal material such as aluminum. Once the mask (not shown) is removed by etching, the semiconductor device 10 of this embodiment is completed, and the manufacturing process of the semiconductor device 10 is finished.

[0048] According to this embodiment, the semiconductor device 10 comprises a plurality of first trenches 11 recessed below the surface 40a of the semiconductor substrate 40, i.e., on one side in the thickness direction (+Z side), and housing a first electrode 13 inside; a second trench 20 recessed below the surface 40a, and housing a second electrode 25 inside; a first conductivity type, i.e., a P-type base layer 15 disposed between the first trenches 11 and the second trenches 20 and surrounding the first electrode 13; a second conductivity type, i.e., an N-type source layer 17 disposed above the base layer 15, in contact with the base layer 15, and surrounding the first electrode 13; an N-type drift layer 14 disposed below the base layer 15 and in contact with the base layer 15; and a source electrode 32 disposed above the semiconductor substrate 40 and electrically connected to the plurality of first electrodes 13 and the source layer 17. Viewed from the thickness direction, the second trench 20 surrounds each of the multiple first trenches 11, and the second trench 20 has multiple first extensions 21 extending in the first direction D1 and multiple second extensions 22 extending in the second direction D2, with the width W12 of each of the multiple second extensions 22 being narrower than the width W11 of each of the multiple first extensions 21. As a result, as described above, the first distance L1, which is the distance between the carrier vacancy layer 16 and the second insulating film 24 in the first direction D1, and the second distance L2, which is the distance between the carrier vacancy layer 16 and the second insulating film 24 in the second direction D2, can be made the same while reducing the spacing (cell pitch) Pc between each of the first trenches 11. Therefore, it is possible to suppress the first distance L1 from becoming too short, and thus suppress the rise in the threshold voltage of the semiconductor device 10. In addition, it is easier to make the first distance L1 the optimal length, and thus it is possible to suppress the width of the base layer 15 from becoming too wide. This suppresses a decrease in the avalanche withstand capability of the semiconductor device 10. Furthermore, as described above, the spacing Pc between each of the first trenches 11 can be reduced, thereby reducing the on-resistance of the semiconductor device 10. Therefore, the on-resistance can be reduced while suppressing an increase in the threshold voltage of the semiconductor device 10.

[0049] According to this embodiment, each of the multiple first extensions 21 is provided with a conductive portion 26 connected to a second electrode 25. As a result, as described above, the width W12 of each of the multiple second extensions 22 can be made narrower than the width W11 of each of the multiple first extensions 21. Therefore, as described above, the spacing Pc between each of the first trenches 11 can be reduced while keeping the first distance L1 and the second distance L2 the same. Consequently, the first distance L1 can be prevented from becoming too short, and the threshold voltage of the semiconductor device 10 can be prevented from rising. In addition, since the spacing Pc between each of the first trenches 11 can be made smaller more easily, the on-resistance of the semiconductor device 10 can be more effectively reduced.

[0050] Furthermore, in this embodiment, since a conductive portion 26 connected to the second electrode 25 is provided in each first extended portion 21, the gate resistance Rg can be reduced compared to the case where a conductive portion 26 is not provided in each first extended portion 21, as described above. Therefore, the potential of the entire second electrode 25 can be uniformly achieved.

[0051] According to this embodiment, the resistivity of the conductive portion 26 is smaller than the resistivity of the second electrode 25. Therefore, it is easier to make the electrical resistance of the conductive portion 26 smaller than the electrical resistance of the second electrode 25, and thus the gate resistance Rg can be more effectively reduced. Consequently, the potential of the entire second electrode 25 can be more effectively made uniform.

[0052] According to this embodiment, the distance in the first direction D1 between adjacent virtual lines V2 in the first direction D1, among the multiple virtual lines V2 that extend in the second direction D2 and pass through the centers of the multiple first trenches 11, that is, the distance P11 between the first trenches 11 in the first direction D1, is smaller than the distance P12 between the first trenches 11 in the second direction D2. Therefore, in the first direction D1, the first trenches 11 can be placed closer together, and the distance Pc between the first trenches 11 can be more suitably reduced. Consequently, the on-resistance of the semiconductor device 10 can be more suitably reduced.

[0053] According to this embodiment, when viewed from the thickness direction, the lengths of the three sides of the triangles whose vertices are the centers of each of the three adjacent first trenches 11 are the same. Therefore, the spacing between each first electrode 13 can be made the same. Consequently, the breakdown voltage between each first electrode 13 can be made uniform, and the breakdown voltage of the semiconductor device 10 can be increased.

[0054] According to this embodiment, each of the plurality of first extensions 21 is positioned between adjacent first trenches 11 arranged in the second direction D2, and each of the plurality of second extensions 22 is positioned between adjacent first trenches 11 arranged in the first direction D1 and extends in the second direction D2 which is perpendicular to the first direction D1. Therefore, it is possible to suppress the gap between the second electrode 25 housed inside the second trench 20 and each first electrode 13 housed inside each first trench 11 from becoming too large. As a result, the concentration of the electric field on a part of the second electrode 25 can be suitably suppressed, and thus the avalanche withstand capability of the semiconductor device 10 can be suitably increased.

[0055] (Second Embodiment) Figure 9 is a plan view showing the semiconductor device 210 of the embodiment. The width W21 of the first extension portion 221 of this embodiment is wider than the width W11 of the first extension portion 21 of the first embodiment described above, and the width W22 of the second extension portion 222 of this embodiment is wider than the width W12 of the second extension portion 22 of the first embodiment described above. In the following description, components that are the same as those of the first embodiment described above are denoted by the same reference numerals and their descriptions are omitted. The semiconductor device 210 of this embodiment includes a plurality of first trenches 211 and a second trench 220. The semiconductor device 210 includes a semiconductor substrate 40 (see Figure 2), an insulating layer 30 (see Figure 2), and a source electrode 32 (see Figure 2).

[0056] As shown in Figure 9, each first trench 211 is arranged in a staggered pattern in a direction perpendicular to the thickness direction. Viewed from the first direction D1, the first trenches 211 contained in each of two adjacent rows of first trenches arranged in the first direction D1 are positioned offset from each other in the second direction D2. In this embodiment, the second direction D2 is perpendicular to the first direction D1.

[0057] In Figure 9, the spacing between adjacent virtual lines V2 in the first direction D1, i.e., the spacing P21 between first trenches 211 in the first direction D1, is smaller than the spacing P22 between first trenches 211 in the second direction D2. The spacing P21 in this embodiment is larger than the spacing P11 in the first embodiment described above, and the spacing P22 in this embodiment is larger than the spacing P12 in the first embodiment described above. In this embodiment, when viewed from the thickness direction, the lengths Pc of the three sides of the triangles whose vertices are the centers of each of the three adjacent first trenches 211 are all the same length. Therefore, the spacing Pc between each first trench 211 is all the same length. Inside each first trench 211, a first insulating film 12 and a first electrode 13 are housed. Other configurations of the first trench 211 in this embodiment are the same as other configurations of the first trench 11 in the first embodiment described above.

[0058] The carrier-removed layer 216 is a roughly rectangular tube extending in the thickness direction. Viewed from the thickness direction, the carrier-removed layer 216 surrounds the first insulating film 12. In this embodiment, the dimension of the carrier-removed layer 216 in the second direction D2 is approximately the same as the dimension of the first trench 211 in the second direction D2. The dimension of the carrier-removed layer 216 in the first direction D1 is approximately the same as the dimension of the first trench 211 in the first direction D1. The other configurations of the carrier-removed layer 216 in this embodiment are the same as the other configurations of the carrier-removed layer 16 in the first embodiment described above.

[0059] The source layer 217 is a roughly rectangular tube extending in the thickness direction. Viewed from the thickness direction, the source layer 217 surrounds the first electrode 13. Viewed from the thickness direction, the source layer 217 surrounds the carrier removal layer 216. The source layer 217 is in contact with the carrier removal layer 216. The dimension S2 of the source layer 217 in the second direction D2 and the dimension S1 of the source layer 217 in the first direction D1 are the same. Therefore, the first distance L1 and the second distance L2 are the same. Other configurations of the source layer 217 in this embodiment are the same as those of the source layer 217 in the first embodiment described above.

[0060] Viewed from the thickness direction, the second trench 220 surrounds each of the multiple first trenches 211. The second trench 220 has multiple first extensions 221 and multiple second extensions 222.

[0061] Each first extension 221 is a portion of the second trench 220 that extends in the first direction D1. The first extension 221 extends linearly in the first direction D1. Each of the multiple first extensions 221 is positioned between adjacent first trenches 211 in the second direction D2. The width W21 of each first extension 221 is wider than the width W11 of each first extension 21 in the first embodiment described above.

[0062] Each second extension 222 is a portion of the second trench 220 that extends in the second direction D2. The second extension 222 extends linearly in the second direction D2. Each of the multiple second extensions 222 is positioned between adjacent first trenches 211 arranged in the first direction D1. The width W22 of each second extension 222 is wider than the width W12 of each second extension 22 in the first embodiment described above. The width W22 of each second extension 222 is narrower than the width W21 of each first extension 221. In other words, the width W21 of each of the multiple first extensions 221 is wider than the width W22 of each of the multiple second extensions 222. The other configurations of the second trench 220 in this embodiment are the same as the other configurations of the second trench 20 in the first embodiment described above.

[0063] The second trench 220 houses the second insulating film 224 and the second electrode 225. The second insulating film 224 is formed on the inner surface of the second trench 220. The other configurations of the second insulating film 224 in this embodiment are the same as those of the second insulating film 24 in the first embodiment described above.

[0064] The second electrode 225 is provided inside the entire second trench 220. Viewed from the thickness direction, the width of the portion of the second electrode 225 that is housed inside each first extension portion 221 is wider than the width of the portion of the second electrode 25 housed inside each first extension portion 21 in the first embodiment described above. Viewed from the thickness direction, the width of the portion of the second electrode 225 that is housed inside each second extension portion 222 is wider than the width of the portion of the second electrode 25 housed inside each second extension portion 22 in the first embodiment described above. In other words, the width of the second electrode 225 is wider than the width of the second electrode 25 in the first embodiment. Therefore, the electrical resistance of the second electrode 225 is smaller than the electrical resistance of the second electrode 25 in the first embodiment. The other configurations of the second electrode 225 in this embodiment are the same as the other configurations of the second electrode 25 in the first embodiment described above.

[0065] In this embodiment, a conductive portion 226 is provided in each of the multiple first extended portions 221. The width of the conductive portion 226 in this embodiment is wider than the width of the conductive portion 26 in the first embodiment described above. Therefore, the cross-sectional area of ​​the conductive portion 226 is wider than the cross-sectional area of ​​the conductive portion 26 in the first embodiment, and thus the electrical resistance of the conductive portion 226 is smaller than the electrical resistance of the conductive portion 26 in the first embodiment. As described above, the electrical resistance of the second electrode 225 is smaller than the electrical resistance of the second electrode 25 in the first embodiment. Therefore, in this embodiment, the gate resistance Rg can be reduced compared to the gate resistance Rg in the first embodiment, and thus the potential uniformity of the entire second electrode 225 can be more favorably achieved. Other configurations of the conductive portion 226 in this embodiment are the same as other configurations of the conductive portion 26 in the first embodiment described above.

[0066] In this embodiment, a second conductive portion 226b is provided in each of the multiple second extended portions 222. Although not shown in the figures, the second conductive portion 226b extends upward from the inside of the second extended portion 222. The second conductive portion 226b is electrically connected to the second electrode 225. The upper portion of the second conductive portion 226b is located inside the insulating layer 30. As a result, the second conductive portion 226b is insulated from the source electrode 32. Furthermore, the second conductive portion 226b is insulated from the drift layer 14, the base layer 15, the source layer 217, and the source electrode 32 by the second insulating film 224.

[0067] The second conductive portion 226b is connected to the conductive portion 226. Therefore, a portion of the gate current, which is the current flowing through the second electrode 225, flows through the conductive portion 226 and the second conductive portion 226b. As a result, in this embodiment, the gate resistance Rg can be more favorably reduced compared to the case in which the second conductive portion 226b is not provided in each second extended portion 222. The other configurations of the second conductive portion 226b are the same as the other configurations of the conductive portion 226 described above. The other configurations of the semiconductor device 210 in this embodiment are the same as the other configurations of the semiconductor device 10 in the first embodiment described above.

[0068] Furthermore, in this embodiment, as described above, the first distance L1 and the second distance L2 are the same dimension. Therefore, similar to the first embodiment described above, it is possible to suppress the first distance L1 from becoming too short, and thus it is possible to suppress the threshold voltage of the semiconductor device 210 from rising.

[0069] Furthermore, in this embodiment, as described above, since the distance Pc between each first trench 211 is the same length, the distance between each first electrode 13 can be made the same. Therefore, the withstand voltage between each first electrode 13 can be made uniform, and thus the withstand voltage of the semiconductor device 210 can be increased.

[0070] (Third embodiment) Figure 10 is a plan view showing a semiconductor device 310 of the third embodiment. In this embodiment, when viewed from the thickness direction, the rectangle whose vertices are the centers of each of the four adjacent first trenches 311 is square in shape. In the following description, components that are the same as those in the first embodiment described above are denoted by the same reference numerals and their descriptions are omitted. The semiconductor device 310 of this embodiment comprises a plurality of first trenches 311 and a second trench 320. The semiconductor device 310 comprises a semiconductor substrate 40 (see Figure 2), an insulating layer 30 (see Figure 2), and a source electrode 32 (see Figure 2).

[0071] As shown in Figure 10, in this embodiment, each first trench 311 is arranged in a row in the first direction D1 and the second direction D2, respectively. When viewed from the first direction D1, the first trenches 311 included in each of the two rows of first trenches arranged adjacent to each other in the first direction D1 are arranged to overlap. In this embodiment, the second direction D2 is perpendicular to the first direction D1.

[0072] In this embodiment, the spacing P31 between the first trenches 311 in the first direction D1 and the spacing P32 between the first trenches 311 in the second direction D2 are the same. When viewed from the thickness direction, the lengths Pc of the four sides of the rectangle formed by the centers of the four adjacent first trenches 311 are the same. When viewed from the thickness direction, the rectangle formed by the centers of the four adjacent first trenches 311 is square. Inside each first trench 311, a first insulating film 12 and a first electrode 13 are housed. Other configurations of the first trenches 311 in this embodiment are the same as other configurations of the first trenches 11 in the first embodiment described above.

[0073] The carrier-depositing layer 316 is a roughly rectangular tube extending in the thickness direction. Viewed from the thickness direction, the carrier-depositing layer 316 surrounds the first insulating film 12. In this embodiment, the dimension of the carrier-depositing layer 316 in the first direction D1 is larger than the dimension in the second direction D2. The other configurations of the carrier-depositing layer 316 in this embodiment are the same as the other configurations of the carrier-depositing layer 16 in the first embodiment described above.

[0074] The source layer 317 is a roughly rectangular tube extending in the thickness direction. Viewed from the thickness direction, the source layer 317 surrounds the first electrode 13. Viewed from the thickness direction, the source layer 317 surrounds the carrier removal layer 316. The dimension S2 of the source layer 317 in the second direction D2 and the dimension S1 of the source layer 317 in the first direction D1 are the same. Therefore, the first distance L1 and the second distance L2 are the same. The other configurations of the source layer 317 in this embodiment are the same as the other configurations of the source layer 17 in the first embodiment described above.

[0075] Viewed from the thickness direction, the second trench 320 surrounds each of the multiple first trenches 311. The second trench 320 has multiple first extensions 321 and multiple second extensions 322.

[0076] Each first extension 321 is a portion of the second trench 320 that extends in the first direction D1. Each first extension 321 extends linearly in the first direction D1. Each of the multiple first extensions 321 is positioned between adjacent first trenches 311 that are arranged in the second direction D2.

[0077] Each second extension 322 is a portion of the second trench 320 that extends in the second direction D2. Each second extension 322 extends linearly in the second direction D2. Each of the multiple second extensions 322 is positioned between adjacent first trenches 311 arranged in the first direction D1. The width W32 of each second extension 322 is narrower than the width W31 of each first extension 321. In other words, the width W31 of each of the multiple first extensions 321 is wider than the width W32 of each of the multiple second extensions 322. The other configurations of the second trench 320 in this embodiment are the same as the other configurations of the second trench 20 in the first embodiment described above.

[0078] The second trench 320 houses the second insulating film 324 and the second electrode 325. The second insulating film 324 is formed on the inner surface of the second trench 320. The other configurations of the second insulating film 324 in this embodiment are the same as those of the second insulating film 24 in the first embodiment described above.

[0079] The second electrode 325 is provided inside the entire second trench 320. Viewed from the thickness direction, the width of the portion of the second electrode 325 that is housed inside each first extension portion 321 is wider than the width of the portion that is housed inside each second extension portion 322. The other configurations of the second electrode 325 in this embodiment are the same as the other configurations of the second electrode 25 in the first embodiment described above.

[0080] A conductive portion 326 is provided in each of the multiple first extended portions 321. A conductive portion 326 is not provided in each of the multiple second extended portions 322. As a result, the width W32 of each second extended portion 322 can be made narrower than the width W31 of each first extended portion 321, so that the dimension of the carrier-removed layer 316 in the first direction D1 can be made larger than the dimension in the second direction D2. The other configurations of the conductive portion 326 in this embodiment are the same as the other configurations of the conductive portion 26 in the first embodiment described above. The other configurations of the semiconductor device 310 in this embodiment are the same as the other configurations of the semiconductor device 10 in the first embodiment described above.

[0081] In this embodiment, the spacing P31 between the first trenches 311 in the first direction D1 and the spacing P32 between the first trenches 311 in the second direction D2 are the same dimension. Therefore, it is easy to reduce the difference in spacing between each first electrode 13. Consequently, it is easy to make the withstand voltage between each first electrode 13 uniform, and thus the withstand voltage of the semiconductor device 310 can be increased.

[0082] According to this embodiment, when viewed from the thickness direction, the rectangle formed by the centers of each of the four adjacent first trenches 311 is square in shape. Therefore, it is easier to more favorably reduce the difference in spacing between each first electrode 13. Consequently, it is easier to more favorably uniformize the breakdown voltage between each first electrode 13, and thus the breakdown voltage of the semiconductor device 310 can be more favorably increased.

[0083] Furthermore, in this embodiment, a conductive portion 326 is provided in each first extended portion 321, while a conductive portion 326 is not provided in each second extended portion 322. As a result, as described above, the width W32 of each second extended portion 322 can be made narrower than the width W31 of each first extended portion 321, so that the dimension of the carrier void layer 316 in the first direction D1 can be made larger than the dimension in the second direction D2. Therefore, it is possible to prevent the cross-sectional area of ​​the carrier void layer 316 from becoming too small, and thus prevent a decrease in avalanche withstand capability. In addition, the spacing Pc between each first trench 311 can be reduced, which reduces the on-resistance of the semiconductor device 310. Therefore, it is possible to reduce the on-resistance while preventing a decrease in the avalanche withstand capability of the semiconductor device 310.

[0084] Furthermore, in this embodiment, as described above, the width W32 of each second extension portion 322 can be made narrower than the width W31 of each first extension portion 321. This makes it easier to reduce the spacing between each first trench 311 while keeping the first distance L1 and the second distance L2 the same. Therefore, it is possible to suppress the first distance L1 from becoming too short, and thus suppress the rise in the threshold voltage of the semiconductor device 310. This is because it is possible to suppress the excessive diffusion of P-type impurities in the carrier removal layer 316 towards the second electrode 325, thereby suppressing an increase in the P-type impurity concentration in the carrier removal layer 316. In addition, it is easier to reduce the spacing between each first trench 311, which reduces the on-resistance of the semiconductor device 310. Therefore, it is possible to reduce the on-resistance while suppressing the rise in the threshold voltage of the semiconductor device 310.

[0085] (Fourth Embodiment) Figure 11 is a plan view showing a semiconductor device 410 of the fourth embodiment. In this embodiment, when viewed from the thickness direction, the second trench 420 has a honeycomb shape that surrounds each of the multiple first trenches 11. In the following description, components that are the same as those in the first embodiment described above are denoted by the same reference numerals and their descriptions are omitted. The semiconductor device 410 of this embodiment comprises a plurality of first trenches 11 and a second trench 420. The semiconductor device 410 comprises a semiconductor substrate 40 (see Figure 2), an insulating layer 30 (see Figure 2), and a source electrode 32 (see Figure 2).

[0086] As shown in Figure 11, each first trench 11 is arranged in a staggered pattern perpendicular to the thickness direction. In this embodiment, the arrangement of each first trench 11 is the same as that of each first trench 11 in the first embodiment. Therefore, when viewed from the thickness direction, the lengths of the three sides Pc of the triangles whose vertices are the centers of each of the three adjacent first trenches 11 are all the same. Thus, the spacing Pc between each first trench 11 is all the same length. Inside each first trench 11 are the first insulating film 12 and the first electrode 13.

[0087] The carrier-deposited layer 416 is a substantially hexagonal tubular shape extending in the thickness direction. Viewed from the thickness direction, the carrier-deposited layer 416 is a substantially regular hexagonal annular shape. Viewed from the thickness direction, the carrier-deposited layer 416 surrounds the first insulating film 12. The other configurations of the carrier-deposited layer 416 in this embodiment are the same as the other configurations of the carrier-deposited layer 16 in the first embodiment described above.

[0088] The source layer 417 is a substantially hexagonal tubular shape extending in the thickness direction. Viewed from the thickness direction, the source layer 417 is a substantially regular hexagonal ring. Viewed from the thickness direction, the source layer 417 surrounds the first electrode 13. Viewed from the thickness direction, the source layer 417 surrounds the carrier void layer 416. The source layer 417 is in contact with the carrier void layer 416. Viewed from the thickness direction, the width of the source layer 417 is substantially the same around the circumference. Therefore, the distance between the carrier void layer 416 and the second insulating film 424 is substantially the same around the circumference. Other configurations of the source layer 417 in this embodiment are the same as other configurations of the source layer 17 in the first embodiment described above.

[0089] Viewed from the thickness direction, the second trench 420 surrounds each of the multiple first trenches 11. The second trench 420 has multiple first extensions 421, multiple second extensions 422, and multiple third extensions 423.

[0090] Each first extension 421 is a portion of the second trench 420 that extends in the first direction D1. Each first extension 421 extends linearly in the first direction D1. Each of the multiple first extensions 421 is positioned between adjacent first trenches 11 that are arranged in directions perpendicular to both the thickness direction and the first direction D1.

[0091] Each second extension 422 is a portion of the second trench 420 that extends in the second direction D2. In this embodiment, the second direction D2 is the direction that intersects the first direction D1. The angle between the second direction D2 and the first direction D1 is approximately 120°. Each second extension 422 extends linearly in the second direction D2. Each of the multiple second extensions 422 is positioned between adjacent first trenches 11 that are arranged in a direction perpendicular to the second direction D2. The width W42 of each second extension 422 is narrower than the width W41 of each first extension 421.

[0092] Each third extension 423 is a portion of the second trench 420 that extends in the third direction D3. In this embodiment, the third direction D3 is perpendicular to the thickness direction and intersects both the first direction D1 and the second direction D2. The angle between the third direction D3 and the first direction D1 is approximately 120°. The angle between the third direction D3 and the second direction D2 is approximately 120°. Each third extension 423 extends linearly in the third direction D3. Each of the multiple third extensions 423 is positioned between adjacent first trenches 11 that are arranged in a direction perpendicular to the third direction D3. The width W43 of each third extension 423 is narrower than the width W41 of each first extension 421. The width W43 of each third extension 423 is approximately the same as the width W42 of each second extension 422. The ends of each second extension 422 in the second direction D2 are connected to the ends of different first extensions 421 in the first direction D1. The ends of each third extension 423 in the third direction D3 are connected to the ends of different first extensions 421 in the first direction D1. As a result, when viewed from the thickness direction, the second trench 420 has a honeycomb shape that surrounds each of the multiple first trenches 11. The other configurations of the second trench 420 in this embodiment are the same as the other configurations of the second trench 20 in the first embodiment described above.

[0093] The second trench 420 houses the second insulating film 424 and the second electrode 425. The second insulating film 424 is formed on the inner surface of the second trench 420. Viewed from the thickness direction, the second insulating film 424 is substantially a regular hexagonal ring. The other configurations of the second insulating film 424 in this embodiment are the same as the other configurations of the second insulating film 24 in the first embodiment described above.

[0094] The second electrode 425 is provided inside the entire second trench 420. Viewed in the thickness direction, the width of the portion of the second electrode 425 that is housed inside each first extension portion 421 is wider than the width of the portion housed inside each second extension portion 422 and the width of the portion housed inside each third extension portion 423. The other configurations of the second electrode 425 in this embodiment are the same as the other configurations of the second electrode 25 in the first embodiment described above.

[0095] A conductive portion 426 is provided in each of the multiple first extended portions 421. Conductive portions 426 are not provided in each of the multiple second extended portions 422 and the multiple third extended portions 423. As a result, the gate resistance Rg can be reduced compared to the case in which no conductive portion 426 is provided in each first extended portion 421, as in the first embodiment described above. Therefore, the potential of the entire second electrode 425 can be uniformly achieved. The other configurations of the conductive portion 426 in this embodiment are the same as the other configurations of the conductive portion 26 in the first embodiment described above. The other configurations of the semiconductor device 410 in this embodiment are the same as the other configurations of the semiconductor device 10 in the first embodiment described above.

[0096] Furthermore, in this embodiment, as described above, a conductive portion 426 is provided in each first extended portion 421. No conductive portion 426 is provided in each second extended portion 422 or each third extended portion 423. As a result, the width W42 of each second extended portion 422 and the width W43 of each third extended portion 423 can be made narrower than the width W41 of each first extended portion 321, so that the dimension of the carrier removal layer 416 in the first direction D1 can be made larger than the dimension in the second direction D2.

[0097] According to this embodiment, the second trench 420 includes a third extension 423 extending in a third direction D3, each of the plurality of first extensions 421 is positioned between adjacent first trenches 11 arranged in directions perpendicular to both the thickness direction and the first direction D1, each of the plurality of second extensions 422 is positioned between adjacent first trenches 11 arranged in directions perpendicular to the second direction D2, each of the plurality of second extensions 422 is positioned between adjacent first trenches 11 arranged in directions perpendicular to the second direction D2, and each of the plurality of third extensions 423 is positioned between adjacent first trenches 11 arranged in directions perpendicular to the third direction D3, and when viewed from the thickness direction, the second trench 420 has a honeycomb shape surrounding each of the plurality of first trenches 11. Therefore, it is possible to suppress the gap between the second electrode 425 housed inside the second trench 420 and each first electrode 13 housed inside each first trench 11 from becoming too large. As a result, the concentration of the electric field on a part of the second electrode 425 can be suitably suppressed, and thus the avalanche withstand capability of the semiconductor device 410 can be suitably increased.

[0098] Furthermore, in this embodiment, a conductive portion 426 is provided in each first extended portion 421, while a conductive portion 426 is not provided in each second extended portion 422 and each third extended portion 423. Therefore, similar to the first embodiment described above, the width W42 of each second extended portion 422 and the width W43 of each third extended portion 423 can be made narrower than the width W41 of each first extended portion 421. This makes it easier to reduce the spacing between each first trench 311 while keeping the distance between the carrier void layer 416 and the second insulating film 424 approximately the same over the entire circumference. Consequently, the on-resistance can be reduced while suppressing an increase in the threshold voltage of the semiconductor device 410.

[0099] Furthermore, in this embodiment, a conductive portion 426 is provided in each first extension portion 421, while a conductive portion 426 is not provided in each second extension portion 422 and each third extension portion 423. As a result, as described above, the width W42 of each second extension portion 422 and the width W43 of each third extension portion 423 can be made narrower than the width W41 of each first extension portion 321, thereby reducing the spacing Pc between each first trench 11. This reduces the on-resistance of the semiconductor device 410. Therefore, the on-resistance can be reduced while suppressing a decrease in the avalanche withstand capability of the semiconductor device 410.

[0100] According to at least one embodiment described above, by making the width of each of the multiple second extensions narrower than the width of each of the multiple first extensions, it is possible to provide a semiconductor device that can reduce on-resistance while suppressing an increase in threshold voltage.

[0101] The semiconductor device of the embodiment includes the following appended aspects. (Note 1) A plurality of first trenches are recessed from the surface of the semiconductor substrate on one side in the thickness direction of the semiconductor substrate, and house a first electrode inside. A second trench is recessed from the surface on one side in the thickness direction, and houses a second electrode inside. Displaced between the first trench and the second trench, surrounding the first electrode, is a first-conductivity type base layer, A second conductive source layer is positioned on the other side of the thickness direction from the base layer, in contact with the base layer, and surrounding the first electrode. A second conductive drift layer is provided, which is positioned on one side of the base layer in the thickness direction and in contact with the base layer. A plurality of first electrodes and a source electrode electrically connected to the source layer are arranged on one side in the thickness direction of the semiconductor substrate, Equipped with, Viewed from the thickness direction, the second trench surrounds each of the multiple first trenches, The second trench has a plurality of first extensions extending in a first direction perpendicular to the thickness direction, and a plurality of second extensions extending in a second direction perpendicular to the thickness direction and intersecting the first direction. A semiconductor device in which the width of each of the plurality of second extensions is narrower than the width of each of the plurality of first extensions. (Note 2) The semiconductor device according to Appendix 1, wherein each of the plurality of first extensions is provided with a conductive portion connected to the second electrode. (Note 3) The semiconductor device according to Appendix 2, wherein the resistivity of the conductive portion is smaller than the resistivity of the second electrode. (Note 4) The conductive portion is made of tungsten, as described in Appendix 2 or Appendix 3, for the semiconductor device. (Note 5) A semiconductor device according to any one of the appendices 1 to 4, wherein the spacing in the first direction between adjacent imaginary lines in the first direction, among a plurality of imaginary lines extending in the second direction and passing through the centers of a plurality of first trenches, is smaller than the spacing between the first trenches in the second direction. (Note 6) The semiconductor device according to any one of the appendices 1 to 5, wherein, when viewed from the thickness direction, the lengths of the three sides of a triangle whose vertices are the centers of each of the three adjacent first trenches are the same length. (Note 7) The semiconductor device according to any one of the appendices 1 to 4, wherein the spacing between the first trenches in the first direction and the spacing between the first trenches in the second direction are the same dimension. (Note 8) The semiconductor device according to Appendix 1 or Appendix 7, wherein, when viewed from the thickness direction, the quadrilateral formed by the centers of each of the four adjacent first trenches is square in shape. (Note 9) Each of the plurality of first extensions is positioned between the first trenches which are arranged adjacent to each other in the second direction. Each of the plurality of second extensions is located between the first trenches which are adjacent to each other in the first direction and extends in the second direction which is perpendicular to the first direction, according to any one of the appendices 1 to 8. (Note 10) The second trench includes a third extension that extends in a third direction perpendicular to the thickness direction and intersects both the first and second directions. Each of the plurality of first extensions is positioned between the first trenches which are adjacent to each other in directions perpendicular to both the thickness direction and the first direction, The plurality of second extensions are arranged between the first trenches which are arranged adjacent to each other in a direction perpendicular to the second direction, The plurality of third extensions are arranged between the first trenches which are arranged adjacent to each other in a direction perpendicular to the third direction, The semiconductor device according to any one of the appendices 1 to 4, wherein, when viewed from the thickness direction, the second trench has a honeycomb shape surrounding each of the plurality of first trenches.

[0102] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0103] 10,210,310,410…Semiconductor equipment, 11,211,311…First trench, 13…First electrode, 14…Drift layer, 15…Base layer, 17,217,317,417…Source layer, 20,220,320,420…Second trench, 21,221,321,421…First extension, 22,222,322,422…Second extension, 25,225,325,4 25...Second electrode, 26, 226, 326, 426...Conductive part, 32...Source electrode, 40...Semiconductor substrate, 423...Third extension part, P11, P21, P31...Spacing between first trenches in the first direction, P12, P22, P32...Spacing between first trenches in the second direction, W11, W21, W31, W41...Width of first extension part, W12, W22, W32, W42...Width of second extension part

Claims

1. A plurality of first trenches are recessed from the surface of the semiconductor substrate on one side in the thickness direction of the semiconductor substrate, and house a first electrode inside. A second trench is recessed from the surface on one side in the thickness direction, and houses the second electrode inside. A first conductivity type base layer is disposed between the first trench and the second trench and surrounds the first electrode, A second conductive source layer is positioned on the other side of the thickness direction from the base layer, in contact with the base layer, and surrounding the first electrode. A second conductive drift layer is provided, which is positioned on one side of the base layer in the thickness direction and in contact with the base layer. A plurality of first electrodes and a source electrode electrically connected to the source layer are arranged on one side in the thickness direction of the semiconductor substrate, Equipped with, Viewed from the thickness direction, the second trench surrounds each of the multiple first trenches, The second trench has a plurality of first extensions extending in a first direction perpendicular to the thickness direction, and a plurality of second extensions extending in a second direction perpendicular to the thickness direction and intersecting the first direction. A semiconductor device in which the width of each of the plurality of second extensions is narrower than the width of each of the plurality of first extensions.

2. The semiconductor device according to claim 1, wherein each of the plurality of first extension portions is provided with a conductive portion connected to the second electrode.

3. The semiconductor device according to claim 2, wherein the resistivity of the conductive portion is smaller than the resistivity of the second electrode.

4. The semiconductor device according to claim 2, wherein the conductive portion is made of tungsten.

5. The semiconductor device according to claim 1, wherein the spacing in the first direction between adjacent imaginary lines in the first direction, among a plurality of imaginary lines extending in the second direction and passing through the centers of a plurality of first trenches, is smaller than the spacing between the first trenches in the second direction.

6. The semiconductor device according to claim 1, wherein, when viewed from the thickness direction, the lengths of the three sides of a triangle whose vertices are the centers of each of the three adjacent first trenches are the same.

7. The semiconductor device according to claim 1, wherein the spacing between the first trenches in the first direction and the spacing between the first trenches in the second direction are the same dimension.

8. The semiconductor device according to claim 1, wherein, when viewed from the thickness direction, the quadrilateral whose vertices are the centers of each of the four adjacent first trenches is square in shape.

9. Each of the plurality of first extensions is positioned between the first trenches which are arranged adjacent to each other in the second direction. The semiconductor device according to any one of claims 1 to 8, wherein each of the plurality of second extensions is located between first trenches arranged adjacent to each other in the first direction and extends in a second direction perpendicular to the first direction.

10. The second trench includes a third extension that extends in a third direction perpendicular to the thickness direction and intersects both the first and second directions. Each of the plurality of first extensions is positioned between the first trenches which are adjacent to each other in directions perpendicular to both the thickness direction and the first direction, The plurality of second extensions are arranged between the first trenches which are arranged adjacent to each other in a direction perpendicular to the second direction, The plurality of third extensions are arranged between the first trenches which are arranged adjacent to each other in a direction perpendicular to the third direction, The semiconductor device according to any one of claims 1 to 4, wherein, when viewed from the thickness direction, the second trench has a honeycomb shape surrounding each of the plurality of first trenches.

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