Semiconductor equipment

Abstract

To provide a semiconductor device that can suppress the generation of leakage current. [Solution] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a gate electrode, and a second electrode. The second electrode includes a contact portion that contacts the third semiconductor region in a second direction. The contact portion includes a first conductive layer, a second conductive layer, and a third conductive layer. The second conductive layer is provided between the first conductive layer and the second semiconductor region and between the first conductive layer and the third semiconductor region. The third conductive layer is provided between the second conductive layer and the second semiconductor region and between the second conductive layer and the third semiconductor region. The thermal expansion coefficient of the first conductive layer is smaller than that of the second conductive layer and smaller than that of the third conductive layer. The electrical resistivity of the second conductive layer is smaller than that of the first conductive layer and smaller than that of the third conductive layer.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used in applications such as power conversion. There is a need for technologies that can suppress the generation of leakage current in these semiconductor devices. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 6125420 [Overview of the project] [Problems that the invention aims to solve]

[0004] The problem that the embodiments of the present invention aim to solve is to provide a semiconductor device that can suppress the generation of leakage current. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The gate electrode faces the second semiconductor region via a first insulating layer in a second direction perpendicular to a first direction toward the first semiconductor region from the first electrode. The second electrode includes a contact portion that contacts the third semiconductor region in the second direction. The second electrode is provided on the second semiconductor region and the third semiconductor region. The contact portion includes a first conductive layer, a second conductive layer, and a third conductive layer. The second conductive layer is provided between the first conductive layer and the second semiconductor region and between the first conductive layer and the third semiconductor region. The third conductive layer is provided between the second conductive layer and the second semiconductor region, and between the second conductive layer and the third semiconductor region. The thermal expansion coefficient of the first conductive layer is smaller than that of the second conductive layer and smaller than that of the third conductive layer. The electrical resistivity of the second conductive layer is smaller than that of the first conductive layer and smaller than that of the third conductive layer. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment. [Figure 2] Figure 2 is an enlarged cross-sectional view of a portion of Figure 1. [Figure 3] Figures 3(a) and 3(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] Figures 4(a) and 4(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] Figures 5(a) and 5(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 6]Figures 6(a) and 6(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] Figure 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] Figure 8 is a cross-sectional view showing a part of a semiconductor device according to a first modified example of the embodiment. [Figure 9] Figure 9 is a cross-sectional view showing a part of a semiconductor device according to a second modified example of the embodiment. [Figure 10] Figure 10 is a cross-sectional view showing a part of a semiconductor device according to a third modified example of the embodiment. [Modes for carrying out the invention]

[0007] The embodiments of the present invention will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes of the parts, etc., are not necessarily the same as those of reality. Furthermore, even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In this specification and each drawing, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the following description and drawings, n + , n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation without either "+" or "-", and a notation with "-" indicates a relatively lower impurity concentration than a notation without either. When both p-type and n-type impurities are present in each region, these notations represent the relative level of the net impurity concentration after the impurities have compensated for each other. Each embodiment described below may be implemented by reversing the p-type and n-type of each semiconductor region.

[0008] Figure 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment. The semiconductor device 100 according to the embodiment is a MOSFET. As shown in FIG. 1, the semiconductor device 100 includes an n - -type (first conductivity type) drift region 1 (first semiconductor region), a p-type (second conductivity type) base region 2 (second semiconductor region), an n + -type source region 3 (third semiconductor region), a p + -type contact region 4 (fourth semiconductor region), an n + -type drain region 5, a gate electrode 10, a first insulating layer 11, a second insulating layer 12, a drain electrode 21 (first electrode), and a source electrode 22 (second electrode). In FIG. 1, the source electrode 22 is shown transparently with a dashed line.

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. The direction from the drain electrode 21 toward the n - -type drift region 1 is defined as the Z direction (first direction). Two directions perpendicular to the Z direction and orthogonal to each other are defined as the X direction (second direction) and the Y direction (third direction). Also, for the sake of explanation, the direction from the drain electrode 21 toward the n - -type drift region 1 is referred to as "up", and the opposite direction is referred to as "down". These directions are independent of the direction of gravity based on the relative positional relationship between the drain electrode 21 and the n - -type drift region 1.

[0010] The drain electrode 21 is provided on the lower surface of the semiconductor device 100. The n + -type drain region 5 is provided above the drain electrode 21 and is electrically connected to the drain electrode 21. The n - -type drift region 1 is provided above the n + -type drain region 5. The n - -type drift region 1 is electrically connected to the drain electrode 21 through the n + -type drain region 5. The n-type impurity concentration in the n - -type drift region 1 is lower than the n-type impurity concentration in the n + -type drain region 5.

[0011] The gate electrode 10 is an n -It is provided on the shaped drift region 1 via a first insulating layer 11. Multiple gate electrodes 10 are provided in the X direction, and these gate electrodes 10 are spaced apart from each other.

[0012] A p-shaped base region 2 is provided between adjacent gate electrodes 10. The p-shaped base region 2 is n - It is located above the p-shaped drift region 1. The p-shaped base region 2 and the gate electrode 10 are arranged alternately in the X direction. The gate electrode 10 faces the p-shaped base region 2 in the X direction via the first insulating layer 11.

[0013] n + The p-shaped source region 3 is provided on the p-shaped base region 2. The gate electrode 10 has n in the X direction. - Part of the shape drift region 1 and n + A portion of the source region 3 may be facing the first insulating layer 11.

[0014] The source electrode 22 has a p-type base region 2, n + It is provided on the p-type source region 3 and the gate electrode 10. The source electrode 22 is located on the upper surface of the semiconductor device 100 and is provided on the p-type base region 2 and n + The second insulating layer 12 is electrically connected to the source region 3. The second insulating layer 12 is provided between the gate electrode 10 and the source electrode 22 in the Z direction. The source electrode 22 is electrically isolated from the gate electrode 10 by the second insulating layer 12.

[0015] The source electrode 22 includes a contact portion C. The contact portion C extends downward and in the X direction is part of the p-shaped base region 2 and n + It is in contact with the shape source region 3. + The p-shaped contact region 4 is provided between the p-shaped base region 2 and the contact portion C. + The concentration of p-type impurities in the contact region 4 is higher than the concentration of p-type impurities in the p-type base region 2.

[0016] For example, p-type base region 2, n +Shape source region 3, p + Each of the p-shaped contact region 4, gate electrode 10, and contact portion C extends in the Y direction. A pair of n-shaped base regions 2 are located on one p-shaped base region 2. + Shape source region 3, one p + A p-shaped contact area 4 and one contact portion C are provided. p-shaped base area 2, n + Shape source region 3, p + Multiple contact regions 4, gate electrodes 10, and contact portions C are provided in the X direction, and these are arranged in a stripe pattern.

[0017] An example of the materials used for each component is described below. n - Shape drift region 1, p-shaped base region 2, n + Shape source region 3, p + Shaped contact area 4, and n + The drain region 5 contains silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as n-type impurities. Boron can be used as a p-type impurity. The gate electrode 10 contains a conductive material such as polysilicon. The first insulating layer 11 and the second insulating layer 12 contain insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 21 and the source electrode 22 contain a metallic material.

[0018] The operation of the semiconductor device 100 will be explained. With a positive voltage applied to the drain electrode 21 relative to the source electrode 22, a voltage above a threshold is applied to the gate electrode 10. As a result, a channel (inversion layer) is formed in the p-type base region 2. Electrons pass through the channel from the source electrode 22 to n - The current flows into the p-type drift region 1, and the semiconductor device 100 turns on. Subsequently, when the voltage applied to the gate electrode 10 falls below a threshold, the channel in the p-type base region 2 disappears, and the semiconductor device 100 turns off.

[0019] Figure 2 is an enlarged cross-sectional view of a portion of Figure 1. As shown in Figure 2, the contact portion C includes a first conductive layer 22a, a second conductive layer 22b, and a third conductive layer 22c. The second conductive layer 22b is located between the first conductive layer 22a and the p-type base region 2, and between the first conductive layer 22a and n + It is provided between the type source region 3. The third conductive layer 22c is between the second conductive layer 22b and the p-type base region 2, and between the second conductive layer 22b and n + It is provided between the shape source region 3 and the source region 3.

[0020] For example, the second conductive layer 22b and the third conductive layer 22c are on the surface of the p-type base region 2, n + Surface of the shape source region 3, and p + It is provided along the surface of the contact region 4. In the contact portion C of the XZ cross section, the area of ​​the first conductive layer 22a is larger than the area of ​​the third conductive layer 22c. The area of ​​the first conductive layer 22a may be larger than the area of ​​the second conductive layer 22b.

[0021] The first conductive layer 22a comprises one or more first materials selected from the first group consisting of silicon, carbon, chromium, and lanthanum. The silicon may be single-crystal silicon or polysilicon. The first conductive layer 22a may also contain a silicon-carbon compound. When silicon or carbon is used, impurities are added to reduce the electrical resistivity of the first conductive layer 22a.

[0022] The second conductive layer 22b comprises one or more second materials selected from the second group consisting of tungsten and molybdenum. The third conductive layer 22c comprises one or more third materials selected from the third group consisting of titanium and cobalt.

[0023] The thermal expansion coefficient of the first material is smaller than that of the second material and smaller than that of the third material. Therefore, the thermal expansion coefficient of the first conductive layer 22a is smaller than that of the second conductive layer 22b and smaller than that of the third conductive layer 22c.

[0024] For example, the thermal expansion coefficient of polysilicon with impurities added is approximately 3.0 × 10⁻⁶.-6 It is / K. The coefficient of thermal expansion of chromium is approximately 4.5 × 10⁻⁶. -6 It is / K. The coefficient of thermal expansion of tungsten is approximately 5.0 × 10⁻⁶. -6 It is / K. The thermal expansion coefficient of molybdenum is approximately 5.5 × 10⁻⁶. -6 It is / K. The coefficient of thermal expansion of titanium or titanium nitride is approximately 8.5 × 10⁻⁶. -6 It is / K. The thermal expansion coefficient of cobalt is approximately 13 × 10⁻⁶. -6 It is / K.

[0025] The electrical resistivity of the second material is lower than that of the first material and lower than that of the third material. Therefore, the electrical resistivity of the second conductive layer 22b is lower than that of the first conductive layer 22a and lower than that of the third conductive layer 22c.

[0026] For example, the electrical resistivity of chromium is approximately 13 × 10⁻⁶. -8 It is Ω·m. The electrical resistivity of tungsten is approximately 5.5 × 10⁻⁶. -8 It is Ω·m. The electrical resistivity of molybdenum is approximately 5.5 × 10⁻⁶. -8 It is Ω·m. The electrical resistivity of titanium or titanium nitride is approximately 45 × 10⁻⁶. -8 It is Ω·m. The electrical resistivity of cobalt is approximately 5.8 × 10⁻⁶. -8 It is Ω·m. The electrical resistivity of polysilicon depends on the concentration of added impurities. For example, the concentration of n-type or p-type impurities is 1.0 × 10⁻⁶. 18 atom / cm 3 The above is 1.0 × 10 21 atom / cm 3 The following applies. In this case, the electrical resistivity of polysilicon is 1.0 × 10⁻⁶. -6 ~1.0×10 -3 It is approximately Ω·m.

[0027] Titanium or titanium nitride provides a barrier function to the semiconductor material contained in each semiconductor region. The provision of the third conductive layer 22c suppresses the diffusion of semiconductor material from the semiconductor region to the source electrode 22, thereby improving the reliability of the semiconductor device 100.

[0028] Each of the first to third conductive layers may be composed of multiple layers. For example, the third conductive layer 22c may be composed of a titanium layer and a titanium nitride layer provided thereon.

[0029] As shown in Figure 2, the second conductive layer 22b and the third conductive layer 22c may also be provided in parts other than the contact portion C. For example, the second conductive layer 22b and the third conductive layer 22c are n + It is provided along the upper surface of the source region 3 and the upper surface of the second insulating layer 12. The source electrode 22 further includes a fourth conductive layer 22d located above the contact portion C. The fourth conductive layer 22d is located above the first conductive layer 22a, the second conductive layer 22b, and the third conductive layer 22c.

[0030] The fourth conductive layer 22d includes one or more fourth materials selected from the fourth group consisting of aluminum and copper. The electrical resistivity of the fourth material is smaller than the electrical resistivity of each of the first to third materials. Therefore, the electrical resistivity of the fourth conductive layer 22d is smaller than the electrical resistivity of each of the first to third conductive layers 22a to 22c. By providing the fourth conductive layer 22d, the electrical resistivity of the source electrode 22 can be reduced. The thermal expansion coefficient of the fourth material is larger than that of the first material. The thermal expansion coefficient of the fourth material may be larger than that of the second material, and may also be larger than that of the third material.

[0031] If the second conductive layer 22b is also provided in parts other than the contact portion C, the thickness of the second conductive layer 22b provided in parts other than the contact portion C may be smaller than the thickness of the second conductive layer 22b included in the contact portion C. For example, n + The thickness of the second conductive layer 22b in the Z direction between the shaped source region 3 and the fourth conductive layer 22d is n + The thickness of the second conductive layer 22b in the X direction between the shaped source region 3 and the first conductive layer 22a is smaller than the thickness of the second conductive layer 22b.

[0032] As shown in Figure 2, n +The p-shaped source region 3 may include a first portion 3a and a second portion 3b. The first portion 3a is the portion in contact with the p-shaped base region 2. In the X direction, the first portion 3a is located between the gate electrode 10 and the contact portion C, and between the second insulating layer 12 and the contact portion C. The second portion 3b is located above the first portion 3a and is in contact with the second insulating layer 12.

[0033] The first part 3a has an upper surface S1. The upper surface S1 is in contact with the source electrode 22 in the Z direction. The second part 3b has an inclined surface S2. The inclined surface S2 is in contact with the source electrode 22 and is inclined with respect to the Z direction. For example, the inclination of the upper surface S1 with respect to the X direction is 0 degrees or more and 15 degrees or less. The inclination of the inclined surface S2 with respect to the X direction is greater than 15 degrees and 85 degrees or less. The inclination of at least a portion of the inclined surface S2 with respect to the X direction is 60 degrees or more.

[0034] The width W2 of the second part 3b is narrower than the width W1 of the first part 3a. "Width" is the length in the X direction. For example, width W1 is measured at the height of the upper end of the gate electrode 10. "Height" is the position in the Z direction. Width W2 is measured at the height of the boundary between the upper surface S1 and the inclined surface S2.

[0035] The length L2 of the second part 3b in the Z direction is shorter than the length L1 of the first part 3a in the Z direction. Length L2 may be 0.5 times or less of length L1, and may also be 0.3 times or less of length L1.

[0036] For example, the distance D1 in the Z direction from the upper surface S1 to the lower end E1 of the gate electrode 10 is between 600 nm and 1200 nm. The pitch P of the multiple gate electrodes 10 is between 450 nm and 1000 nm. The pitch P corresponds to the distance between the center of the first gate electrode 10a in the X direction and the center of the second gate electrode 10b in the X direction. The first gate electrode 10a is one of the multiple gate electrodes 10. The second gate electrode 10b is another of the multiple gate electrodes 10 and is adjacent to the first gate electrode 10a in the X direction.

[0037] Figures 3(a), 3(b), 4(a), 4(b), 5(a), 5(b), 6(a), 6(b), and 7 are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. First, n + Semiconductor layer 5x and n - A semiconductor substrate containing a shaped semiconductor layer 1x is prepared. - The semiconductor layer 1x is n + It is provided on a shaped semiconductor layer 5x. By photolithography and reactive ion etching (RIE), as shown in Figure 3(a), n - Multiple apertures OP1 are formed on the upper surface of a shaped semiconductor layer 1x. The multiple apertures OP1 are separated from each other in the X direction, and each aperture OP1 extends in the Y direction.

[0038] Due to thermal oxidation, n - An insulating layer 11x is formed along the surface of a semiconductor layer 1x. A conductive layer is formed on the insulating layer 11x by chemical vapor deposition (CVD). The conductive layer contains, for example, polysilicon. The opening OP1 is filled by the conductive layer. The upper surface of the conductive layer is etched by wet etching. As a result, the conductive layer is divided into multiple parts, as shown in Figure 3(b), and a gate electrode 10 is formed inside each opening OP1.

[0039] A CVD (Chemical Vapor Deposition) process forms an insulating layer 12x on the gate electrode 10. The opening OP1 is filled by the insulating layer 12x. - Chemical dry etching (CDE) is performed until the upper surface of the semiconductor layer 1x is exposed. As a result, as shown in Figure 4(a), a portion of the insulating layer 11x and a portion of the insulating layer 12x are removed, n - The upper surface of the shaped semiconductor layer 1x is exposed.

[0040] CDE allows n between the insulating layers 12x. -A portion of the semiconductor layer 1x is removed. In CDE, a gas is selected in which the etching rate for the semiconductor is higher than the etching rate for the insulating layer. For example, HBr (hydrogen bromide) is used as the gas. When CDE is performed, a difference in etching rate occurs between the part near the insulating layer 12x and the part away from the insulating layer 12x. Near the insulating layer 12x, n - The semiconductor layer 1x is difficult to remove. As a result, as shown in Figure 4(b), the upper surface of the portion near the insulating layer 12x is sloped. The upper surface of the portion near the insulating layer 12x is located above the upper surface of the portion further away from the insulating layer 12x.

[0041] n - p-type and n-type impurities are sequentially ion-implanted onto the upper surface of the p-type semiconductor layer 1x, forming a p-type semiconductor region 2x and n + A semiconductor region 3x is formed by CVD, as shown in Figure 5(a). + An insulating layer 13x is formed to cover the shaped semiconductor region 3x and the insulating layer 12x. For example, the insulating layer 13x contains an insulating material such as silicon oxide or silicon nitride. The material of the insulating layer 13x can be changed as appropriate, as long as it can be used as a mask when etching the semiconductor layer.

[0042] A portion of the insulating layer 13x is n + It is located above both ends of the shaped semiconductor region 3x in the X direction. Another part of the insulating layer 13x is n + It is located above the center of the semiconductor region 3x in the X direction. The thickness (dimension in the Z direction) of this portion of the insulating layer 13x is greater than the thickness of this other portion of the insulating layer 13x.

[0043] Anisotropic etching, n + The insulating layer 13x is removed until a portion of the upper surface of the semiconductor region 3x is exposed. At this time, as shown in Figure 5(b), the thinner portion of the insulating layer 13x is removed, and the thicker portion remains. As a result, n + An insulating layer 13x remains on both ends of the shaped semiconductor region 3x, while the rest of the insulating layer 13x is removed. This forms a mask 13y consisting of the insulating layer 13x. The mask 13y is n+ It covers the vicinity of the insulating layer 12x of the shaped semiconductor region 3x. + The central portion of the shaped semiconductor region 3x in the X direction is exposed.

[0044] RIE using mask 13y, n + A portion of the p-type semiconductor region 3x and a portion of the p-type semiconductor region 2x are removed. This forms an opening OP2. As shown in Figure 6(a), p-type impurities are ion-implanted into the bottom surface of the opening OP2 through the opening OP2, and p + A contact region 4 is formed.

[0045] Remove mask 13y. Sputtering is performed on the surface of the p-type semiconductor region 2x and n + A third material is deposited on the surface of the semiconductor region 3x to form a third conductive layer 22c. A second material is deposited on the third conductive layer 22c by sputtering to form a second conductive layer 22b. As shown in Figure 6(b), a first material is deposited on the second conductive layer 22b to form a first conductive layer 22a that fills the opening OP2.

[0046] If the first conductive layer 22a contains single-crystal silicon, the first conductive layer 22a is formed by epitaxial growth. If the first conductive layer 22a contains polysilicon or carbon, the first conductive layer 22a is formed by CVD. If the first conductive layer 22a contains lanthanum or chromium, the first conductive layer 22a is formed by sputtering or vapor deposition.

[0047] The first conductive layer 22a is selectively removed by CDE or wet etching. The amount of etching of the second conductive layer 22b is sufficiently smaller than the amount of etching of the first conductive layer 22a. As a result, the first conductive layer 22a is formed inside each opening OP2. Also, due to etching, the thickness of the second conductive layer 22b provided outside the opening OP2 becomes smaller than the thickness of the second conductive layer 22b provided inside the opening OP2. As shown in Figure 7(a), the fourth conductive layer 22d is formed on the first conductive layer 22a and the third conductive layer 22c by sputtering.

[0048] n + Until the n-type semiconductor layer 5x reaches a predetermined thickness, the lower surface of the n-type semiconductor layer 5x is ground. As shown in FIG. 7(b), a metal layer 21x is formed on the lower surface of the ground n-type semiconductor layer 5x by sputtering. The metal layer 21x contains titanium. A metal layer 21y is formed on the metal layer 21x by plating. The metal layer 21y contains silver. Alternatively, the metal layer 21y may contain a eutectic of gold and tin. Through the above steps, the semiconductor device 100 according to the embodiment is manufactured.

[0049] The n-type semiconductor layer 1x shown in FIG. 7(b) corresponds to the n-type drift region 1 shown in FIG. 1. The p-type semiconductor region 2x corresponds to the p-type base region 2. The n-type semiconductor region 3x corresponds to the n-type source region 3. + 形ソース領域3に対応する。n + 形半導体層5xは、n + 形ドレイン領域5に対応する。絶縁層11xは、第1絶縁層11に対応する。絶縁層12xは、第2絶縁層12に対応する。金属層21x及び21yは、ドレイン電極21に対応する。

[0050] Explain the advantages of the embodiment. 半導体装置100は、n - 形ドリフト領域1、p形ベース領域2、及びn + 形ソース領域3からなる寄生トランジスタを含む。例えば、半導体装置100がターンオフされた際、アバランシェ降伏によってキャリア(電子及び正孔)が発生する。電子は、n + 形ドレイン領域5を通ってドレイン電極21へ排出される。正孔は、p形ベース領域2及びp + 形コンタクト領域4を通ってソース電極22へ排出される。このとき、p形ベース領域2の電位が上昇すると、寄生トランジスタが動作しうる。寄生トランジスタが動作すると、半導体装置100に大電流が流れ、半導体装置100が破壊される。

[0051] ​​​​​​​​​​To suppress the operation of parasitic transistors, it is desirable that holes be efficiently discharged to the source electrode 22. By discharging holes to the source electrode 22, the rise in potential of the p-type base region 2 is suppressed. By providing the contact portion C, the contact area between the p-type base region 2 and the source electrode 22 and p + The contact area between the p-type contact region 4 and the source electrode 22 increases. As a result, the rise in potential of the p-type base region 2 is suppressed, making it difficult for parasitic transistors to operate.

[0052] On the other hand, the contact portion C includes electrode material (metal). The thermal expansion coefficient of the contact portion C is greater than that of the semiconductor region. Heat is generated when the semiconductor device 100 is in operation. When the temperature of the semiconductor device 100 rises, stress due to thermal expansion is applied from the contact portion C to each semiconductor region. Repeated stress is applied to the semiconductor region due to temperature cycling, which can cause crystal defects to occur in the semiconductor region. Crystal defects increase the leakage current between the drain electrode 21 and the source electrode 22.

[0053] In embodiments of the present invention, the contact portion C includes a first conductive layer 22a, a second conductive layer 22b, and a third conductive layer 22c. The thermal expansion coefficient of the first conductive layer 22a is smaller than that of the second conductive layer 22b and smaller than that of the third conductive layer 22c. By providing the first conductive layer 22a, the amount of thermal expansion of the contact portion C can be suppressed, and the stress applied to the semiconductor region can be reduced. Furthermore, the electrical resistivity of the second conductive layer 22b is smaller than that of the first conductive layer 22a and smaller than that of the third conductive layer 22c. By providing the second conductive layer 22b, the increase in electrical resistance due to the first conductive layer 22a can be suppressed, and the decrease in hole discharge efficiency can be suppressed. The third conductive layer 22c is provided between each semiconductor region and the second conductive layer 22b and functions as a barrier layer.

[0054] According to this embodiment, the thermal expansion coefficient of the contact portion C can be reduced while suppressing the increase in electrical resistance in the contact portion C. In other words, according to this embodiment, the operation of parasitic transistors can be suppressed while suppressing the generation of leakage current caused by crystal defects.

[0055] The first material included in the first conductive layer 22a is preferably silicon. This is because silicon has a smaller coefficient of thermal expansion than chromium and lanthanum. Furthermore, compared to chromium and lanthanum, silicon is less likely to cause contamination of the manufacturing equipment during the formation of the first conductive layer 22a, and it is also easier to fill the opening OP2.

[0056] The second material contained in the second conductive layer 22b is preferably tungsten. This is because tungsten has a smaller coefficient of thermal expansion compared to molybdenum.

[0057] The third material included in the third conductive layer 22c is preferably titanium. This is because titanium has a smaller coefficient of thermal expansion compared to cobalt.

[0058] As shown in Figure 2, n + The morphological source region 3 may include a first portion 3a and a second portion 3b. For example, the concentration of n-type impurities in the second portion 3b is lower than that in the first portion 3a. This is because the width W2 of the second portion 3b is shorter than the width W1 of the first portion 3a, allowing the n-type impurities in the second portion 3b to diffuse more easily into the surroundings. In this case, the electrical resistivity of the second portion 3b is higher than that of the first portion 3a.

[0059] From the viewpoint of reducing on-resistance, the second portion 3b is undesirable. On the other hand, since the electrical resistivity of the second portion 3b is higher than that of the first portion 3a, the voltage drop when current flows through the second portion 3b is greater than the voltage drop when current flows through the first portion 3a. For example, when the semiconductor device 100 is short-circuited, a large current flows through the semiconductor device 100. At this time, the voltage drop by the second portion 3b is large, which can suppress the current flowing through the semiconductor device 100. By providing the second portion 3b, which is narrower than the first portion 3a, it is possible to reduce the current density during a short circuit while suppressing the increase in the on-resistance of the semiconductor device 100.

[0060] In the semiconductor device 100, a small pitch P is preferable. The smaller the pitch P, the greater the number of gate electrodes 10 that can be arranged per unit area. As a result, the channel density increases. The greater the channel density, the greater the current path in the ON state. Therefore, the on-resistance of the semiconductor device 100 can be reduced. For example, from the viewpoint of reducing on-resistance, the pitch P is preferably 450 nm or more and 1000 nm or less.

[0061] On the other hand, the more gate electrodes 10 arranged per unit area there are, the greater the stress applied to the semiconductor region from the gate electrodes 10, the first insulating layer 11, the second insulating layer 12, etc. As a result, crystal defects are more likely to occur in the semiconductor region. According to this embodiment, even when the pitch P is small, the stress applied to the semiconductor region from the contact portion C can be reduced. The occurrence of crystal defects in the semiconductor region can be suppressed. For this reason, this embodiment is suitable for semiconductor devices with a pitch P of 1000 nm or less.

[0062] To stabilize the operation of the semiconductor device 100, the depth of the gate electrode 10 (distance D1 shown in Figure 2) is preferably 600 nm or more. On the other hand, the larger the distance D1, the larger the volume of the gate electrode 10. When the thickness of the semiconductor region in the Z direction (distance between the drain electrode 21 and the source electrode 22) is constant, the larger the volume of the gate electrode 10, the larger the proportion of the volume of the gate electrode 10. The thermal expansion coefficient of the material contained in the semiconductor region (e.g., silicon) is different from the thermal expansion coefficient of the material contained in the gate electrode 10 (e.g., polysilicon). Multiple heat treatments are performed in the manufacturing process of the semiconductor device 100. The larger the proportion of the volume of the gate electrode 10, the greater the stress generated during heating and cooling, which can cause crystal defects. For this reason, from the viewpoint of reducing crystal defects, it is preferable that the distance D1 is 1200 nm or less. Furthermore, according to the embodiment of the present invention, the occurrence of crystal defects can be suppressed, so even if the distance D1 is 600 nm or more, crystal defects in the semiconductor device 100 can be sufficiently reduced.

[0063] Furthermore, as shown in Figure 2, if the second conductive layer 22b is also provided in parts other than the contact portion C, it is preferable that the thickness of the second conductive layer 22b provided in parts other than the contact portion C is smaller than the thickness of the second conductive layer 22b included in the contact portion C. When the thickness of the source electrode 22 is constant, the smaller the thickness of the second conductive layer 22b, the larger the thickness of the fourth conductive layer 22d. The electrical resistivity of the fourth conductive layer 22d is smaller than the electrical resistivity of the second conductive layer 22b. In the source electrode 22, the larger the proportion of the thickness of the fourth conductive layer 22d, the smaller the electrical resistance of the source electrode 22 can be, and the lower the on-resistance of the semiconductor device 100 can be.

[0064] (First variation) Figure 8 is a cross-sectional view showing a part of a semiconductor device according to a first modified example of the embodiment. In the semiconductor device 110 shown in Figure 8, the source electrode 22 further comprises a fifth conductive layer 22e. The same configuration as that of the semiconductor device 100 can be applied to other components of the semiconductor device 110.

[0065] The fifth conductive layer 22e is provided between the first conductive layer 22a and the fourth conductive layer 22d. The contact portion C may include the fifth conductive layer 22e, or the fifth conductive layer 22e may be located above the contact portion C. As shown in Figure 8, the fifth conductive layer 22e may be further provided between the second conductive layer 22b and the fourth conductive layer 22d.

[0066] The fifth conductive layer 22e includes one or more fifth materials selected from group 5, consisting of tungsten and molybdenum. The fifth material may be the same as the second material or may be different from the second material.

[0067] When the first conductive layer 22a and the fourth conductive layer 22d are in contact, the first material contained in the first conductive layer 22a and the fourth material contained in the fourth conductive layer 22d may react. For example, if the first conductive layer 22a contains silicon and the fourth conductive layer 22d contains aluminum, the aluminum may diffuse into the silicon layer.

[0068] The fifth material has a barrier function similar to the third material (titanium or cobalt). By providing the fifth conductive layer 22e, which contains the fifth material, between the first conductive layer 22a and the fourth conductive layer 22d, the reaction between the first and fourth materials can be suppressed. Furthermore, the thermal expansion coefficient of the fifth material is smaller than that of the third material, and the electrical resistivity of the fifth material is smaller than that of the third material. Therefore, even when the fifth conductive layer 22e is provided, the increase in the thermal expansion coefficient and electrical resistivity of the source electrode 22 can be suppressed.

[0069] (Second variation) Figure 9 is a cross-sectional view showing a part of a semiconductor device according to a second modified example of the embodiment. In the semiconductor device 120 shown in Figure 9, the contact portion C includes an air gap V. The first conductive layer 22a is not provided in the contact portion C. The second conductive layer 22b and the third conductive layer 22c are located between the air gap V and the p-type base region 2 and between the air gap V and n + It is provided between the source region 3. The same configuration as that of semiconductor device 100 can be applied to other components of semiconductor device 120.

[0070] For example, in the process shown in Figure 6(b), after forming the third conductive layer 22c and the second conductive layer 22b, the fourth conductive layer 22d can be formed at a high deposition rate to create a void V. By increasing the deposition rate, the upper part of the opening OP2 is closed without the opening OP2 being filled with material.

[0071] When heat is generated in the semiconductor device 120, the second conductive layer 22b and the third conductive layer 22c can expand thermally toward the void V. Therefore, the semiconductor device 120 can reduce the stress applied from the contact portion C to each semiconductor region due to thermal expansion. Compared to the semiconductor device 100, the semiconductor device 120 can further suppress the occurrence of crystal defects.

[0072] The pressure in the void V is, for example, less than atmospheric pressure. The low pressure in the void V allows the second conductive layer 22b and the third conductive layer 22c to expand more easily towards the void V. This further reduces the stress applied from the contact area C to each semiconductor region.

[0073] Furthermore, the air gap V functions as an insulator. Therefore, from the viewpoint of reducing the electrical resistance of the contact portion C, semiconductor device 100 is more preferable than semiconductor device 120.

[0074] (Third variation) Figure 10 is a cross-sectional view showing a part of a semiconductor device according to a third modified example of the embodiment. The semiconductor device 130 shown in Figure 10 further includes a field plate electrode 15 (FP electrode, third electrode) and an insulating layer 16 compared to the semiconductor device 100. The same configuration as that of the semiconductor device 100 can be applied to other components of the semiconductor device 130.

[0075] The FP electrode 15 is n - It is provided in the drift region 1 via an insulating layer 16. The gate electrode 10 is located on the FP electrode 15 via an insulating layer 17. The FP electrode 15 extends in the Y direction.

[0076] For example, the end of the FP electrode 15 in the Y direction is pulled upward and connected to the source electrode 22. Alternatively, the insulating layer 17 may be omitted, and the FP electrode 15 may be connected to the gate electrode 10.

[0077] The FP electrode 15 contains a conductive material such as polysilicon. The insulating layers 16 and 17 contain an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0078] When the semiconductor device 130 is switched to the off state, the positive voltage applied to the drain electrode 21 relative to the source electrode 22 increases. The potential of the FP electrode 15 is substantially the same as the potential of the gate electrode 10 or the source electrode 22. The drain electrode 21 is electrically connected to n -A potential difference is generated between the drift region 1 and the FP electrode 15. This causes the insulating layer 16 and n - From the interface with the shape drift region 1, n - The depletion layer expands toward the drift region 1. This expansion of the depletion layer can increase the breakdown voltage of the semiconductor device 130. Alternatively, while maintaining the breakdown voltage of the semiconductor device 130, n - By increasing the n-type impurity concentration in the drift region 1, the on-resistance of the semiconductor device 130 can be reduced.

[0079] Embodiments of the present invention include the following features. (Feature 1) First electrode and, A first semiconductor region of a first conductivity type provided on the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on the second semiconductor region, In a second direction perpendicular to the first direction toward the first semiconductor region from the first electrode, a gate electrode facing the second semiconductor region via the first insulating layer, A second electrode provided on the second semiconductor region and the third semiconductor region, including a contact portion that contacts the third semiconductor region in the second direction, wherein the contact portion is First conductive layer and A second conductive layer is provided between the first conductive layer and the second semiconductor region and between the first conductive layer and the third semiconductor region, A third conductive layer is provided between the second conductive layer and the second semiconductor region and between the second conductive layer and the third semiconductor region, The second electrode includes a first conductive layer whose thermal expansion coefficient is smaller than that of the second conductive layer and smaller than that of the third conductive layer, and whose electrical resistivity is smaller than that of the first conductive layer and smaller than that of the third conductive layer. A semiconductor device equipped with the following features. (Feature 2) The second electrode includes a fourth conductive layer located on the contact portion, The semiconductor device according to feature 1, wherein the electrical resistivity of the fourth conductive layer is smaller than the electrical resistivity of the first conductive layer and smaller than the electrical resistivity of the second conductive layer. (Feature 3) First electrode and, A first semiconductor region of a first conductivity type provided on the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on the second semiconductor region, In a second direction perpendicular to the first direction toward the first semiconductor region from the first electrode, a gate electrode facing the second semiconductor region via the first insulating layer, A second electrode provided on the second semiconductor region and the third semiconductor region, including a contact portion that contacts the third semiconductor region in the second direction, wherein the contact portion is A first conductive layer comprising one or more first materials selected from the first group consisting of silicon, carbon, chromium, and lanthanum, A second conductive layer is provided between the first conductive layer and the second semiconductor region and between the first conductive layer and the third semiconductor region, and comprises one or more second materials selected from the second group consisting of tungsten and molybdenum. A third conductive layer is provided between the second conductive layer and the second semiconductor region and between the second conductive layer and the third semiconductor region, and comprises one or more third materials selected from the third group consisting of titanium and cobalt. The second electrode includes, A semiconductor device equipped with the following features. (Feature 4) The second electrode includes a fourth conductive layer located on the contact portion, The semiconductor device according to feature 3, wherein the fourth conductive layer comprises one or more fourth materials selected from the fourth group consisting of aluminum and copper. (Feature 5) The second electrode includes a fifth conductive layer located between the contact portion and the fourth conductive layer. The semiconductor device according to feature 4, wherein the fifth conductive layer comprises one or more fifth materials selected from group 5 consisting of tungsten and molybdenum. (Feature 6) The first material is silicon, The second material is tungsten, The semiconductor device according to any one of features 3 to 5, wherein the third material is titanium. (Feature 7) First electrode and, A first semiconductor region of a first conductivity type provided on the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on the second semiconductor region, In a second direction perpendicular to the first direction toward the first semiconductor region from the first electrode, a gate electrode facing the second semiconductor region via the first insulating layer, A second electrode provided on the second and third semiconductor regions, including a contact portion that contacts the third semiconductor region in the second direction, wherein the contact portion has a gap between the second electrode and the third semiconductor region. A semiconductor device equipped with the following features. (Feature 8) The present invention further comprises a second insulating layer provided between the gate electrode and the second electrode in the first direction, The aforementioned third semiconductor region is, The first portion in contact with the second semiconductor region, A second portion is provided on the first portion, has a length in the second direction shorter than that of the first portion, and is in contact with the second insulating layer, Includes, The inclination of the upper surface of the first portion with respect to the second direction is 0 degrees or more and 15 degrees or less. The semiconductor device according to any one of features 1 to 7, wherein the second part has an inclined surface whose inclination with respect to the second direction is greater than 15 degrees and 85 degrees or less. (Feature 9) Multiple gate electrodes are provided in the second direction. The plurality of gate electrodes include a first gate electrode and a second gate electrode that are adjacent to each other in the second direction. The distance between the center of the first gate electrode in the second direction and the center of the second gate electrode in the second direction is 450 nm or more and 1000 nm or less. The semiconductor device according to feature 8, wherein the distance in the first direction from the upper surface of the first portion to the lower end of the gate electrode is 600 nm or more and 1200 nm or less. (Feature 10) The invention further comprises a third electrode provided in the first semiconductor region via an insulating layer, The aforementioned hot air terminal is located on the third electrode, The semiconductor device according to any one of features 1 to 9, wherein the third electrode is electrically connected to the second electrode or the gate electrode.

[0080] The embodiments described above may be implemented in appropriate combinations. For example, the semiconductor device 110 or 120 may be provided with FP electrodes 15.

[0081] In this specification, "or" indicates that "at least one" of the items listed in the text may be adopted.

[0082] Energy-dispersive X-ray spectroscopy (EDX) can be used to distinguish between the first to fifth conductive layers 22a to 22e in the source electrode 22. For example, the semiconductor device is cut along the XZ plane. The cut surface is observed with a scanning electron microscope (SEM) to confirm the contact portion C of the source electrode 22. By spot analysis of the contact portion C using EDX, the composition of each part of the contact portion C can be measured. Based on the measurement results, the presence of the first to fifth conductive layers 22a to 22e can be determined.

[0083] The relative levels of impurity concentrations between semiconductor regions in each embodiment described above can be confirmed, for example, using a scanning capacitance microscope (SCM). The carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between semiconductor regions can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS).

[0084] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of Symbols]

[0085] 1:n - Shape of drift region, 1x:n - 1:p-type semiconductor layer, 2:p-type base region, 2x:p-type semiconductor region, 3:n + shape source area, 3a: first part, 3b: second part, 3x:n + Semiconductor region, 4:p + Shape of contact area, 5:n + Shape of drain region, 5x:n +Semiconductor layer, 10: gate electrode, 10a: first gate electrode, 10b: second gate electrode, 11: first insulating layer, 12: second insulating layer, 11x, 12x, 13x: insulating layers, 13y: mask, 15: field plate electrode, 16, 17: insulating layers, 21: drain electrode, 21x, 21y: metal layers, 22: source electrode, 22a: first conductive layer, 22b: second conductive layer, 22c: third conductive layer, 22d: fourth conductive layer, 22e: fifth conductive layer, 100~130: semiconductor device, C: contact area, V: air gap, OP1, OP2: opening, P: pitch, S1: top surface, S2: inclined surface

Claims

1. First electrode and, A first semiconductor region of a first conductivity type provided on the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on the second semiconductor region, In a second direction perpendicular to the first direction toward the first semiconductor region from the first electrode, a gate electrode facing the second semiconductor region via the first insulating layer, A second electrode provided on the second semiconductor region and the third semiconductor region, including a contact portion that contacts the third semiconductor region in the second direction, wherein the contact portion is First conductive layer and A second conductive layer is provided between the first conductive layer and the second semiconductor region and between the first conductive layer and the third semiconductor region, A third conductive layer is provided between the second conductive layer and the second semiconductor region and between the second conductive layer and the third semiconductor region, The second electrode includes a first conductive layer whose thermal expansion coefficient is smaller than that of the second conductive layer and smaller than that of the third conductive layer, and whose electrical resistivity is smaller than that of the first conductive layer and smaller than that of the third conductive layer. A semiconductor device equipped with the following features.

2. The second electrode includes a fourth conductive layer located on the contact portion, The semiconductor device according to claim 1, wherein the electrical resistivity of the fourth conductive layer is smaller than the electrical resistivity of the first conductive layer and smaller than the electrical resistivity of the second conductive layer.

3. First electrode and, A first semiconductor region of a first conductivity type provided on the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on the second semiconductor region, In a second direction perpendicular to the first direction toward the first semiconductor region from the first electrode, a gate electrode facing the second semiconductor region via the first insulating layer, A second electrode provided on the second semiconductor region and the third semiconductor region, including a contact portion that contacts the third semiconductor region in the second direction, wherein the contact portion is A first conductive layer comprising one or more first materials selected from the first group consisting of silicon, carbon, chromium, and lanthanum, A second conductive layer is provided between the first conductive layer and the second semiconductor region and between the first conductive layer and the third semiconductor region, and comprises one or more second materials selected from the second group consisting of tungsten and molybdenum. A third conductive layer is provided between the second conductive layer and the second semiconductor region and between the second conductive layer and the third semiconductor region, and comprises one or more third materials selected from a third group consisting of titanium and cobalt. The second electrode includes, A semiconductor device equipped with the following features.

4. The second electrode includes a fourth conductive layer located on the contact portion, The semiconductor device according to claim 3, wherein the fourth conductive layer comprises one or more fourth materials selected from the fourth group consisting of aluminum and copper.

5. The second electrode includes a fifth conductive layer located between the contact portion and the fourth conductive layer. The semiconductor device according to claim 4, wherein the fifth conductive layer comprises one or more fifth materials selected from the fifth group consisting of tungsten and molybdenum.

6. The first material is silicon, The second material is tungsten, The semiconductor device according to claim 3, wherein the third material is titanium.

7. First electrode and, A first semiconductor region of a first conductivity type provided on the first electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on the second semiconductor region, In a second direction perpendicular to the first direction toward the first semiconductor region from the first electrode, a gate electrode facing the second semiconductor region via the first insulating layer, A second electrode provided on the second semiconductor region and the third semiconductor region, including a contact portion that contacts the third semiconductor region in the second direction, wherein the contact portion has a gap between the second electrode and the third semiconductor region. A semiconductor device equipped with the following features.

8. The present invention further comprises a second insulating layer provided between the gate electrode and the second electrode in the first direction, The third semiconductor region is, The first portion in contact with the second semiconductor region, A second portion is provided on the first portion, has a length in the second direction shorter than that of the first portion, and is in contact with the second insulating layer, Includes, The inclination of the upper surface of the first portion with respect to the second direction is 0 degrees or more and 15 degrees or less. The semiconductor device according to any one of claims 1 to 7, wherein the second portion has an inclined surface whose inclination with respect to the second direction is greater than 15 degrees and 85 degrees or less.

9. Multiple gate electrodes are provided in the second direction. The plurality of gate electrodes include a first gate electrode and a second gate electrode that are adjacent to each other in the second direction. The distance between the center of the first gate electrode in the second direction and the center of the second gate electrode in the second direction is 450 nm or more and 1000 nm or less. The semiconductor device according to claim 8, wherein the distance in the first direction from the upper surface of the first portion to the lower end of the gate electrode is 600 nm or more and 1200 nm or less.

10. The invention further comprises a third electrode provided in the first semiconductor region via an insulating layer, The aforementioned electrode is located on the third electrode, The semiconductor device according to any one of claims 1 to 7, wherein the third electrode is electrically connected to the second electrode or the gate electrode.

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