Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same that suppress electrical short circuits and other problems between a resistive element formed on a trench insulating film and columnar residue. [Solution] The trench TRC includes a first trench TRC1 having a first bottom surface BS1 located at a first depth, a second trench TRC2 having a second bottom surface BS2 that slopes from the first depth toward a second depth shallower than the first depth, and a third trench TRC3 having a third bottom surface located at the second depth. The trench insulating film TIF includes a first part TIF1 located in the first trench TRC1, a second part TIF2 located in the second trench TRC2, and a third part TIF3 located in the third trench TRC3. The resistive element REL includes a first resistive element REL1 formed to be in contact with the upper surface of the first part TIF1.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used, for example, for a semiconductor device having a resistance element formed so as to contact a trench insulating film.

Background Art

[0002] As one of the element isolation structures for electrically isolating semiconductor elements such as transistors formed in a semiconductor substrate, there is a trench isolation structure. The trench isolation structure is formed by forming a trench in a semiconductor layer (semiconductor substrate) and embedding an insulating film (trench insulating film) in the trench. A resistance element is formed so as to contact the surface of the trench insulating film. The resistance element is electrically connected to a semiconductor element, such as a gate wiring electrically connected to a transistor, and current flows through the resistance element (Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When forming a trench of the trench isolation structure, in order to suppress the occurrence of crystal defects in the semiconductor layer, the semiconductor layer is subjected to an etching process such that the side walls of the trench are inclined. At this time, columnar residues may occur in the trench due to this etching process. When the trench insulating film is formed in a state where columnar residues are generated, the resistance element may be formed directly above the columnar residues.

[0005] When a resistive element is located directly above a columnar residue, the thickness of the trench insulating film between the resistive element and the columnar residue becomes thinner compared to when there is no columnar residue. Therefore, when a voltage is applied to the resistive element against the semiconductor layer (semiconductor substrate) while the trench insulating film is thin, there is a higher risk of electrical short circuits or current leakage occurring between the resistive element and the columnar residue.

[0006] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment comprises a semiconductor substrate having a main surface, a semiconductor layer having trenches, a trench insulating film, and at least one resistive element. The semiconductor layer having trenches is formed to cover the main surface of the semiconductor substrate. The trench insulating film is formed to fill the trenches in the semiconductor layer. At least one resistive element is formed to be in contact with the trench insulating film. The trenches include a first trench, a second trench, and a third trench. The first trench has a first bottom surface located at a first depth from the top surface of the semiconductor layer. The second trench has a second bottom surface that slopes from the first depth toward a second depth shallower than the first depth. The third trench has a third bottom surface located at the second depth. The trench insulating film includes a first part, a second part, and a third part. The first part is located in the first trench. The second part is located in the second trench. The third part is located in the third trench. At least one resistive element includes a first resistive element formed to be in contact with the first part.

[0008] A method for manufacturing a semiconductor device according to another embodiment comprises the following steps: A semiconductor substrate having a main surface is prepared. A first semiconductor layer is formed by growing a first crystal on the main surface of the semiconductor substrate. A first recess is formed that is recessed toward the semiconductor substrate by performing a first etching treatment on the first upper surface of the first semiconductor layer. A second semiconductor layer having a trench is formed. The step of forming the second semiconductor layer having a trench includes the step of growing a second crystal on the first upper surface of the first semiconductor layer having the first recess. A trench insulating film is formed so as to fill the trench. At least one resistive element is formed so as to be in contact with the trench insulating film. The step of forming the second semiconductor layer having a trench includes the step of forming a first trench having a first bottom surface located at a first depth from the second upper surface of the second semiconductor layer, and a second trench having a second bottom surface that is inclined from the first depth toward a position shallower than the first depth. The step of forming the trench insulating film includes the step of forming a first part that fills the first trench and a second part that fills the second trench. The step of forming at least one resistive element includes the step of forming a first resistive element so as to be in contact with the first part. [Effects of the Invention]

[0009] According to one embodiment of the semiconductor device, electrical short circuits or current leakage between the resistive element and the semiconductor substrate can be suppressed.

[0010] According to the semiconductor device manufacturing method of another embodiment, it is possible to manufacture a semiconductor device in which electrical short circuits or current leakage between the resistive element and the semiconductor substrate are suppressed. [Brief explanation of the drawing]

[0011] [Figure 1] This is a partial plan view of an element region showing one step in the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 2] This is a partial plan view of the scribe region in the process shown in Figure 1, in Embodiment 1. [Figure 3]In Embodiment 1, Figure 1 shows a partial cross-sectional view of the element region along the cross-sectional line IIIa-IIIa and Figure 2 shows a partial cross-sectional view of the scribe region along the cross-sectional line IIIb-IIIb. [Figure 4] This is a partial plan view of the element region showing a process performed after the process shown in Figure 1 in Embodiment 1. [Figure 5] In Embodiment 1, this is a partial plan view of the scribe region in the process shown in Figure 4. [Figure 6] In Embodiment 1, Figure 4 shows a partial cross-sectional view that combines the element region along the cross-sectional line VIa-VIa and the scribe region along the cross-sectional line VIb-VIb shown in Figure 5. [Figure 7] This is a partial plan view of the element region showing the process performed after the process shown in Figure 4 in Embodiment 1. [Figure 8] In Embodiment 1, this is a partial cross-sectional view of the element region along the cross-sectional line VIII-VIII shown in Figure 7. [Figure 9] This is a partial cross-sectional view of the element region showing a process performed after the process shown in Figure 8 in Embodiment 1. [Figure 10] This is a partial cross-sectional view of the element region showing a process performed after the process shown in Figure 9 in Embodiment 1. [Figure 11] This is a partial cross-sectional view of the element region showing a process performed after the process shown in Figure 10 in Embodiment 1. [Figure 12] This is a partial plan view of the element region showing the process performed after the process shown in Figure 11 in Embodiment 1. [Figure 13] In Embodiment 1, Figure 12 is a partially enlarged plan view of the element region shown. [Figure 14] In Embodiment 1, Figure 12 shows a partial cross-sectional view of the element region along the cross-sectional line XIV-XIV. [Figure 15] This is a partial cross-sectional view of an element region showing one step in the manufacturing process of a semiconductor device according to a comparative example. [Figure 16]It is a partial cross-sectional view of an element region showing the process performed after the process shown in FIG. 15. [Figure 17] It is a partial cross-sectional view of an element region showing the process performed after the process shown in FIG. 16. [Figure 18] It is a partial cross-sectional view of an element region showing the process performed after the process shown in FIG. 17. [Figure 19] It is a partial cross-sectional view of an element region showing the process performed after the process shown in FIG. 18. [Figure 20] It is a partial cross-sectional view of an element region showing the process performed after the process shown in FIG. 19. [Figure 21] It is a partial cross-sectional view of an element region showing a step in a method for manufacturing a semiconductor device according to Embodiment 2. [Figure 22] In Embodiment 2, it is a partial cross-sectional view of an element region showing the process performed after the process shown in FIG. 21. [Figure 23] In Embodiment 2, it is a partial cross-sectional view of an element region showing the process performed after the process shown in FIG. 22. [Figure 24] In Embodiment 2, it is a partial cross-sectional view of an element region showing the process performed after the process shown in FIG. 23. [Figure 25] It is a partial cross-sectional view of an element region in a semiconductor device according to Embodiment 3. [Figure 26] It is a partial cross-sectional view of an element region in a semiconductor device according to Embodiment 4. [Figure 27] In Embodiment 4, it is a partial cross-sectional view of an element region in a semiconductor device for comparison. [Figure 28] It is a partial cross-sectional view of an element region in a semiconductor device according to Embodiment 5.

MODE FOR CARRYING OUT THE INVENTION

[0012] Embodiment 1 A method for manufacturing a semiconductor device according to Embodiment 1 and an example of a semiconductor device will be described. First, the method for manufacturing a semiconductor device will be described. First, a semiconductor substrate SUB is prepared (see Figure 1, etc.). An element region EFR and a scribe region SCR are defined on the main surface of the prepared semiconductor substrate SUB (see Figures 1 and 2). Next, a first semiconductor layer EP1 is formed on the main surface of the semiconductor substrate SUB, for example, by an epitaxial growth method of silicon (first crystal) (see Figures 1 and 2).

[0013] Next, as shown in Figures 1, 2, and 3, the first semiconductor layer EP1 is subjected to an etching process (first etching process). This etching process forms a first recess RSS on the upper surface US1 (first upper surface) of the first semiconductor layer EP1 located in the device region EFR, recessed toward the semiconductor substrate SUB. Grooves GRS1 and GRS2 are formed on the upper surface US1 of the first semiconductor layer EP1 located in the scribe region SCR. The depths of the first recess RSS, groove GRS1, and groove GRS2 are, for example, approximately 200 nm.

[0014] In Figure 3, the left side shows the cross-sectional structure of the first semiconductor layer EP1 located in the device region EFR along the cross-sectional line IIIa-IIIa shown in Figure 1, and the right side shows the cross-sectional structure of the first semiconductor layer EP1 located in the scribe region SCR along the cross-sectional line IIIb-IIIb shown in Figure 2.

[0015] Next, as shown in Figures 4, 5, and 6, a second semiconductor layer EP2 is formed on the upper surface US1 of the first semiconductor layer EP1, for example, by an epitaxial growth method of silicon (second crystal). The thickness of the second semiconductor layer EP2 is, for example, 5 μm or more and 10 μm or less. In the device region EFR, a second recess TRSS having a bottom surface and an inclined surface is formed by the growth of silicon crystals on the surface of the first recess RSS, etc. The inclined surface is formed to connect the bottom surface of the second semiconductor layer EP2 and the surface (uppermost layer surface) of the second semiconductor layer EP2 where the second recess TRSS is not formed.

[0016] In the scribe region (SCR), silicon crystals grow on the surface of the groove GRS1, forming an alignment pattern AM (alignment mark) for mask positioning. Furthermore, silicon crystals grow on the surface of the groove GRS2, forming a misalignment confirmation pattern MA for measuring the misalignment of the alignment pattern AM. Figure 6 shows a representative cross-sectional view of the alignment pattern AM. The scribe region will not be mentioned again for subsequent steps.

[0017] Next, a silicon nitride film SN1 (see Figure 8) is formed on the second semiconductor layer EP2 so as to cover the upper surface US2 (second upper surface) of the second semiconductor layer EP2. Then, a photoresist pattern (not shown), which is a mask for forming trenches, is formed by performing a predetermined photolithography process. Next, the silicon nitride film SN1 is etched using the photoresist pattern as an etching mask. As a result, as shown in Figures 7 and 8, a silicon nitride film SN1 is formed that exposes the upper surface US2 of the second semiconductor layer EP2, which includes the region where the second recess TRSS is formed.

[0018] Next, as shown in Figure 9, the upper surface US2 of the second semiconductor layer EP2 is etched using the silicon nitride film SN1 as an etching mask, thereby forming trenches TRC. At this time, the upper surface US2 of the second semiconductor layer EP2 recedes toward the semiconductor substrate SUB while reflecting the surface shape of the second recess TRSS. This forms trenches TRC including the first trench TRC1, the second trench TRC2, and the third trench TRC3.

[0019] The first trench TRC1 is formed in the same position as the second recess TRSS in a plan view (see Figures 8 and 9). The second recess TRSS is in the same position as the first recess RSS in a plan view. The first trench TRC1 is located directly above the first recess RSS. The first trench TRC1 has a first bottom surface BS1. The first bottom surface BS1 is located at a depth D1 (first depth) from the upper surface US2 of the second semiconductor layer EP2. The depth D1 is, for example, approximately 400 nm or more and 500 nm or less.

[0020] The second trench TRC2 has a second bottom surface BS2. The second bottom surface BS2 slopes from a depth D1 to a depth D2 (second depth) that is shallower than depth D1. The third trench TRC3 has a third bottom surface BS3. The third bottom surface BS3 is located at a depth D2 (second depth). The depth D2 is, for example, approximately 200 nm or more and 300 nm or less. The difference between depth D1 and depth D2 is, for example, approximately 200 nm.

[0021] Furthermore, in order to suppress the occurrence of crystal defects within the second semiconductor layer EP2, the second semiconductor layer EP2 is etched so that the side walls of the trench TRC are inclined. As a result, columnar residue CR may be generated within the trench TRC due to this etching process.

[0022] Next, as shown in Figure 10, an insulating film IF is formed to fill the trench TRC, covering the upper surface US2 (silicon nitride film SN1, etc.) of the second semiconductor layer EP2. Then, by applying chemical mechanical polishing (CMP) to the insulating film IF, the portion of the insulating film IF located on the upper surface of the silicon nitride film SN1 is removed. As a result, the portion of the insulating film IF remains within the trench TRC. The insulating film IF becomes the trench insulating film TIF.

[0023] As shown in Figure 11, the silicon nitride film SN and insulating film IF located above the upper surface US2 of the second semiconductor layer EP2 are gradually removed in subsequent processes, forming the trench insulating film TIF within the trench TRC.

[0024] The trench insulating film TIF comprises a first part TIF1, a second part TIF2, and a third part TIF3. The first part TIF1 is formed in the first trench TRC1. The second part TIF2 is formed in the second trench TRC2. The third part TIF3 is formed in the third trench TRC3.

[0025] Next, as shown in Figure 12, a resistive element REL is formed so as to be in contact with the upper surface of the trench insulating film TIF, and is electrically connected to the semiconductor element, allowing current to flow. The resistive element REL includes, for example, gate wiring that is electrically connected to the transistor (semiconductor element).

[0026] A polysilicon film (not shown) is formed on the upper surface US2 of the second semiconductor layer EP2 with a thermal oxide film (not shown) interposed between them. Next, the polysilicon film is subjected to a predetermined photogravure and etching process. Then, an insulating film (not shown) is formed to cover the patterned polysilicon film. Next, the insulating film is subjected to a predetermined etching process, so that the insulating film covering the side walls of the polysilicon film is left intact, while the rest of the insulating film is removed.

[0027] As a result, as shown in Figures 12, 13, and 14, multiple resistive elements REL are formed so as to be in contact with the upper surface of the trench insulating film TIF. Here, each of the multiple resistive elements REL is formed so as to be in contact with the upper surface of the first part TIF1 of the trench insulating film TIF. For the sake of explanation, Figure 14 shows two resistive elements REL, including a first resistive element REL1 and a second resistive element REL2, which are formed so as to be in contact with the upper surface of the first part TIF1.

[0028] Each of the multiple resistor elements REL includes a resistor body REB, an insulating film RIF, and a sidewall insulating film SIF. The resistor body REB is formed by interposing the insulating film RIF on a trench insulating film TIF. The sidewall insulating film SIF is formed on each of the sidewall surfaces of the resistor body REB.

[0029] Subsequently, interlayer insulating films and wiring layers (not shown) are formed to cover multiple resistor elements (RELs), completing the semiconductor device (SED).

[0030] In the semiconductor device SED described above, the resistive element REL is formed to be in contact with the upper surface of the first trench insulating film TIF1. This prevents electrical short circuits or current leakage between the resistive element REL and the columnar residue CR, even if the columnar residue CR is located directly below it. This will be explained in comparison with a semiconductor device relating to a comparative example.

[0031] In the semiconductor device manufacturing method of the comparative example, first, as shown in Figure 15, an element region CEFR and a scribe region (not shown) are defined on the main surface of the semiconductor substrate CSUB. Next, a first semiconductor layer CEP1 is formed on the main surface of the semiconductor substrate CSUB by an epitaxial growth method of silicon.

[0032] Next, the first semiconductor layer CEP1 is subjected to etching. At this time, grooves are formed in the scribed region (not shown). On the other hand, as shown in Figure 15, the first semiconductor layer CEP1 is not etched in the device region CEFR, and the original surface state is maintained.

[0033] Next, as shown in Figure 16, a second semiconductor layer CEP2 is formed on the upper surface CUS1 of the first semiconductor layer CEP1 by an epitaxial growth method of silicon. Then, as shown in Figure 17, a silicon nitride film CSN is formed so as to cover the upper surface CUS2 of the second semiconductor layer EP2. Next, by subjecting the silicon nitride film CSN to predetermined photolithography and etching processes, a pattern of the silicon nitride film CSN, which serves as a mask for forming trenches, is formed.

[0034] Next, as shown in Figure 18, a trench CTRC is formed by etching the upper surface CUS2 of the second semiconductor layer CEP2 using the silicon nitride film CSN as an etching mask. The depth CD of the trench CTRC from the upper surface CUS2 is, for example, approximately 200 nm or more and 300 nm or less. At this time, columnar residue CCR may be generated in the trench CTRC due to the etching process.

[0035] Next, as shown in Figure 19, an insulating film CIF is formed to fill the trench CTRC. Of the insulating film CIF, the portion located above the upper surface CUS2 of the second semiconductor layer CEP2 is gradually removed in subsequent processes along with the silicon nitride film CSN, so that a trench insulating film CTIF is formed within the trench CTRC, as shown in Figure 20.

[0036] Next, a resistive element CREL is formed so as to contact the upper surface of the trench insulating film CTIF. For the sake of explanation, Figure 20 shows two resistive elements CREL, including a first resistive element CREL1 and a second resistive element CREL2, both formed to contact the upper surface of the trench insulating film CTIF. Subsequently, an interlayer insulating film and wiring layers (not shown) are formed to cover the resistive elements CREL, completing the semiconductor device SED according to the comparative example.

[0037] As described above, in the comparative example semiconductor device CSED, the trench CTRC is formed in the flat second semiconductor layer CEP2. Therefore, the trench CTRC has a nearly constant depth CD throughout its entire length (see Figure 18).

[0038] Within the trench CTRC, columnar residue CCR may be generated as a result of the etching process during the formation of the trench CTRC. Therefore, it is conceivable that some of the multiple resistive elements CREL formed in contact with the upper surface of the trench insulating film CTIF may be formed directly above the columnar residue CCR. In other words, it is conceivable that the columnar residue CCR may be located directly below the resistive elements CREL.

[0039] Consequently, the distance CCL between the columnar residue CCR and the resistive element CREL becomes shorter compared to the case where the columnar residue CCR is not located directly beneath the resistive element CREL. In other words, the thickness of the trench insulating film CTIF that electrically insulates the columnar residue CCR and the resistive element CREL becomes thinner, corresponding to the distance CCL. As a result, it is anticipated that an electrical short circuit or current leakage may occur between the resistive element CREL and the columnar residue CCR.

[0040] In contrast to the comparative example semiconductor device CSED, in the semiconductor device SED according to Embodiment 1, the trench TRC is formed in the portion of the second semiconductor layer EP2 where the second recess TRSS is formed. Therefore, the trench TRC is formed having a bottom surface that reflects the surface shape of the second semiconductor layer EP2 before the etching process is performed.

[0041] Specifically, as shown in Figure 9, the first trench TRC1 and the second trench TRC2 are formed in the portion of the second semiconductor layer EP2 where the second recess TRSS was formed, and the third trench TRC3 is formed in the portion of the second semiconductor layer EP2 where the second recess TRSS was not formed. The depth D1 of the first trench TRC1 is deeper than the depth D2 of the third trench TRC3. The depth D2 of the third trench TRC3 corresponds to the depth CD of the trench CTRC in the comparative example (see Figure 18).

[0042] Therefore, even when the columnar residue CR is located directly beneath the resistive element REL, the distance CL between the columnar residue CR and the resistive element REL (see Figure 14) is longer than the distance CCL between the columnar residue CCR and the resistive element CREL in the semiconductor device CSED of the comparative example (see Figure 20). As a result, the thickness of the trench insulating film TIF corresponding to distance CL is greater than the thickness of the trench insulating film CTIF corresponding to distance CCL.

[0043] In other words, the thickness of the trench insulating film TIF (distance CL) that electrically insulates the columnar residue CR from the resistive element REL becomes greater than the thickness of the trench insulating film CTIF (distance CCL). As a result, electrical short circuits or current leakage between the resistive element REL and the columnar residue CR can be suppressed. Furthermore, the initial failure rate of the semiconductor device SED can be reduced.

[0044] The depth and thickness values ​​mentioned above for the semiconductor device SED are merely examples and are not exhaustive.

[0045] Embodiment 2 A method for manufacturing a semiconductor device and an example of a semiconductor device according to Embodiment 2 will be described. Here, the second recess TRSS described above is used as a trench TRC in that state. First, the method for manufacturing the semiconductor device will be described. Components identical to those in the semiconductor device SED according to Embodiment 1 will be denoted by the same reference numerals, and their descriptions will not be repeated unless necessary.

[0046] First, after going through the same process as shown in Figures 1 to 7, a silicon nitride film SN2, which is a mask for forming trenches in the device region EFR, is formed as shown in Figure 21. At this time, in the region of the second semiconductor layer EP2 where the second recess TRSS is formed, the silicon nitride film SN2 is maintained to cover the portion of the second semiconductor layer EP2 so that no trenches are formed thereon. Next, using the silicon nitride film SN2 as an etching mask, a trench (not shown) is formed in a predetermined region of the device region EFR. After that, the silicon nitride film SN2 is removed.

[0047] Next, as shown in Figure 22, a silicon nitride film SN1 is formed so as to cover the upper surface of the second semiconductor layer EP2. Next, a photoresist pattern (not shown) that defines the region for forming the trench insulating film is formed by performing a predetermined photolithography process. Next, the silicon nitride film SN1 is etched using the photoresist pattern as an etching mask. This forms a pattern of silicon nitride film SN1 that exposes the second recess TRSS. Here, the exposed second recess TRSS is referred to as the trench TRC. The trench TRC includes a first trench TRC1 having a first bottom surface BS1 and a second trench TRC2 having a second bottom surface BS2.

[0048] Next, an insulating film (not shown) is formed to fill the trench TRC. Then, as shown in Figure 23, the insulating film is subjected to chemical mechanical polishing, which removes the portion of the insulating film IF located on the upper surface of the silicon nitride film SN1, leaving the portion of the insulating film IF within the trench TRC. The insulating film IF becomes the trench insulating film TIF. The portions of the silicon nitride film SN1 and insulating film IF located above the upper surface of the second semiconductor layer EP2 are gradually removed in subsequent processes.

[0049] Next, following a process similar to that shown in Figure 14, multiple resistive element RELs are formed so as to be in contact with the upper surface of the trench insulating film TIF, as shown in Figure 24. Figure 24 shows two resistive element RELs, including a first resistive element REL1 and a second resistive element REL2, which are formed so as to be in contact with the upper surface of the trench insulating film TIF. Subsequently, an interlayer insulating film and wiring layers (not shown) are formed to cover the multiple resistive element RELs, completing the semiconductor device SED.

[0050] In the semiconductor device SED described above, the second recess TRSS is used as a trench TRC, and a trench insulating film TIF is formed to fill the trench TRC. The second recess TRSS, which becomes the trench TRC, is formed on the upper surface US2 of the second semiconductor layer EP2, which is formed on the surface of the first recess RSS in the first semiconductor layer EP1 by the silicon epitaxial growth method.

[0051] Therefore, the first bottom surface BS1 and the second bottom surface BS2 of the trench TRC are the same as the upper surface US2 of the second semiconductor layer EP2 located in the second recess TRSS. As a result, compared to the case where the trench TRC is formed by etching the first semiconductor layer EP1, no columnar residue is generated on the first bottom surface BS1 and the second bottom surface BS2 of the trench TRC. Consequently, electrical short circuits or current leakage between the resistive element REL and the second semiconductor layer EP2 can be suppressed. Furthermore, the initial failure rate of the semiconductor device SED can be reduced.

[0052] Embodiment 3 An example of a semiconductor device according to Embodiment 3 will be described. Here, an example of a semiconductor device SED will be described in which a trench insulating film TIF is formed in an n-type well region NWR, and a voltage corresponding to the voltage applied to the resistive element REL is applied to the n-type well region NWR.

[0053] As shown in Figure 25, an n-type well region (NWR) is formed within the second semiconductor layer EP2, extending to a predetermined depth from the upper surface US2 of the second semiconductor layer EP2. A trench (TRC) is formed within the n-type well region (NWR). A trench insulating film (TIF) is formed to fill the trench (TRC).

[0054] In the trench insulating film TIF, two resistive elements REL, including a first resistive element REL1 and a second resistive element REL2, are formed so as to be in contact with the upper surface of the first part TIF1. A voltage VR (first voltage) is applied to each of the first resistive element REL1 and the second resistive element REL2. A voltage VW (second voltage) is applied to the n-type well region NWR according to the voltage VR.

[0055] Furthermore, the configuration other than that is the same as that of the semiconductor device SED shown in Figure 14, so the same reference numerals are used for the same components, and their descriptions will not be repeated unless necessary.

[0056] Next, the manufacturing method of the semiconductor device SED described above will be explained. After going through the same process as shown in Figures 1 to 6, an n-type well region NWR is formed by injecting n-type impurities into a predetermined region including the second recess TRSS in the second semiconductor layer EP2. Subsequently, the semiconductor device SED shown in Figure 25 is formed by going through the same process as shown in Figures 7 to 14.

[0057] In the semiconductor device SED described above, a voltage VW is applied to the n-type well region NWR according to the voltage VR applied to the resistive element REL. This makes it possible to limit the potential difference between the resistive element REL and the n-type well region NWR. For example, consider the case where the resistive element REL is used as gate wiring for a transistor.

[0058] In this case, the gate voltage applied to the gate wiring is applied to the resistor REL as voltage VR. The voltage VW is applied to the n-type well region NWR such that the absolute value of the difference between the voltage VW applied to the n-type well region NWR and the gate voltage (voltage VR) is less than or equal to the gate voltage.

[0059] As a result, when the columnar residue CR is located directly beneath the resistive element REL, it is possible to suppress electrical short circuits or current leakage between the resistive element REL and the columnar residue CR. Furthermore, the initial failure rate of the semiconductor device SED can be reduced.

[0060] Although the above-mentioned semiconductor device SED was explained using an n-type well region NWR as an example, a p-type well region may also be used.

[0061] Embodiment 4 An example of a semiconductor device according to Embodiment 4 will be described. Here, an example of a semiconductor device SED will be described in which a plurality of resistive elements REL are formed to be in contact not only with the first part TIF1 of the trench insulating film TIF, but also with the upper surface of the second part TIF2, etc.

[0062] As shown in Figure 26, in the semiconductor device SED, two resistive elements REL, including a first resistive element REL1 and a second resistive element REL2, are formed so as to be in contact with the upper surface of the first part TIF1 of the trench insulating film TIF. Furthermore, two more resistive elements REL, including a third resistive element REL3 and a fourth resistive element REL4, are formed so as to be in contact with the upper surfaces of the second part TIF2 and the third part TIF3 of the trench insulating film TIF.

[0063] Furthermore, the configuration other than that is the same as that of the semiconductor device SED shown in Figure 14, so the same reference numerals are used for the same components, and their descriptions will not be repeated unless necessary.

[0064] Next, the manufacturing method of the semiconductor device SED described above will be explained. After going through the same process as shown in Figures 1 to 11, a plurality of resistive element RELs, including a first resistive element REL1, a second resistive element REL2, a third resistive element REL3, and a fourth resistive element REL4, are formed so as to be in contact with the upper surface of the trench insulating film TIF. Subsequently, by forming an interlayer insulating film and wiring layers (none of which are shown) to cover the plurality of resistive element RELs, the semiconductor device SED shown in Figure 26 is completed.

[0065] In the semiconductor device SED described above, when multiple resistive elements REL are formed so as to be in contact with the upper surface of the trench insulating film TIF, the area of ​​the region where the multiple resistive elements REL are arranged can be suppressed by arranging the multiple resistive elements REL so as to be in contact with the upper surfaces of the second part TIF2 and the third part TIF3 of the trench insulating film TIF, in addition to the first part TIF1. This will be explained.

[0066] Figure 26 illustrates, for the sake of explanation, the case in which four resistive elements REL, including the first resistive element REL1, the second resistive element REL2, the third resistive element REL3, and the fourth resistive element REL4, are formed in contact with the trench insulating film TIF.

[0067] For comparison, Figure 27 shows a semiconductor device SED equipped with four resistive elements REL formed to contact the upper surface of the first part TIF1 of the trench insulating film TIF. As shown in Figure 27, the four resistive elements REL, including the first resistive element REL1, the second resistive element REL2, the third resistive element REL3, and the fourth resistive element REL4, are formed to contact the upper surface of the first part TIF1 located in the deepest first trench TRC1. In this case, the first part TIF1 has an area S2 (width W2 × depth L2) that can accommodate the four resistive elements REL.

[0068] In contrast, in the semiconductor device SED shown in Figure 26, two resistive elements REL, the first resistive element REL1 and the second resistive element REL2, are formed to be in contact with the upper surface of the first part TIF1. Two resistive elements REL, the third resistive element REL3 and the fourth resistive element REL4, are formed to be in contact with the upper surfaces of the second part TIF2 and the third part TIF3.

[0069] Since the two resistive elements REL, the first resistive element REL1 and the second resistive element REL2, are formed to be in contact with the upper surface of the first part TIF1, the first part TIF1 has an area S1 (width W1 × depth L1) that can accommodate the two resistive elements REL. This area S1 is smaller than the area S2 required for the first part TIF1 to accommodate four resistive elements REL. As a result, when multiple resistive elements REL are placed on the trench insulating film TIF, the area of ​​the trench insulating film TIF can be kept from expanding.

[0070] On the other hand, with respect to the third resistive element REL3 and the fourth resistive element REL4, which are formed to be in contact with the upper surfaces of the second part TIF2 and the third part TIF3, if columnar residue CR is located directly beneath the third resistive element REL3 and the fourth resistive element REL4, it is anticipated that the risk of electrical short circuits and the like may be somewhat increased.

[0071] However, compared to the case where four resistive elements REL are formed in contact with the upper surface of the third part TIF3 located in the shallowest third trench TRC3, the risk can be kept low. In other words, compared to the semiconductor device CSED (comparative example) in which four resistive elements CREL are formed in contact with the trench insulating film CTIF (see Figure 20) corresponding to the thickness of the third part TIF3, the risk of electrical short circuits and the like can be kept low.

[0072] Embodiment 5 An example of a semiconductor device according to Embodiment 5 will be described. Here, an example of a semiconductor device SED will be described in which each of the multiple resistive elements REL is arranged to be in contact with a predetermined position on the upper surface of the trench insulating film TIF, according to the voltage applied to each of the multiple resistive elements REL and the thickness of the trench insulating film TIF.

[0073] As shown in Figure 28, in the semiconductor device SED, a first resistive element REL1 and a second resistive element REL2 are formed so as to be in contact with the upper surface of the first part TIF1 of the trench insulating film TIF. A third resistive element REL3 and a fourth resistive element REL4 are formed so as to be in contact with the upper surfaces of the second part TIF2 and the third part TIF3.

[0074] A voltage VH is applied to the first resistive element REL1 and the second resistive element REL2, respectively. A voltage VL is applied to the third resistive element REL3 and the fourth resistive element REL4, respectively. Voltage VH is higher than voltage VL. Note that the other configurations are the same as those of the semiconductor device SED shown in Figure 14, so the same reference numerals are used for the same components, and their descriptions are not repeated unless necessary.

[0075] Next, the manufacturing method of the semiconductor device SED described above will be explained. After going through the same process as shown in Figures 1 to 11, four resistive elements REL, including the first resistive element REL1, the second resistive element REL2, the third resistive element REL3, and the fourth resistive element REL4, are formed so as to be in contact with the upper surface of the trench insulating film TIF. Subsequently, by forming an interlayer insulating film and wiring layers (not shown) so as to cover the resistive elements REL, the semiconductor device SED shown in Figure 28 is completed.

[0076] In the semiconductor device SED described above, the first resistive element REL1 and the second resistive element REL2, to which voltage VH is applied, are formed to be in contact with the upper surface of the first trench insulating film TIF1, which has the thickest trench insulating film TIF. The third resistive element REL3 and the fourth resistive element REL4, to which voltage VL lower than voltage VH is applied, are formed to be in contact with the upper surfaces of the second trench insulating film TIF2 and the third trench insulating film TIF3, which have a thinner thickness than the first trench insulating film TIF1.

[0077] Here, let's assume that the columnar residue CR is located directly beneath the first resistive element REL1 or the second resistive element REL2, and that the columnar residue CR is located directly beneath the third resistive element REL3 or the fourth resistive element REL4. In this case, the distance CL1 between the first resistive element REL1 or the second resistive element REL2 and the columnar residue CR will be longer than the distance CL2 between the third resistive element REL3 or the fourth resistive element REL4 and the columnar residue CR.

[0078] Therefore, the thickness of the trench insulating film TIF located between the first resistive element REL1 or the second resistive element REL2 and the columnar residue CR is greater than the thickness of the trench insulating film TIF located between the third resistive element REL3 or the fourth resistive element REL4 and the columnar residue CR.

[0079] In the semiconductor device SED described above, a third resistive element REL3 (or a fourth resistive element REL4) is positioned so as to be in contact with the upper surface of the third part TIF3 (or second part TIF2), where the thickness of the trench insulating film TIF located between the columnar residue DR and the resistive element REL becomes thinner, and to which a low voltage VL is applied.

[0080] On the other hand, a second resistive element REL2 (or first resistive element REL1) is positioned so as to be in contact with the upper surface of the first part TIF1, where the thickness of the trench insulating film TIF located between the columnar residue DR and the resistive element REL increases, and to which a high voltage VH is applied.

[0081] This reduces the risk of electrical short circuits between the resistive element REL and the columnar residue CR, even when the columnar residue CR is located directly beneath the resistive element REL.

[0082] Furthermore, the semiconductor devices described in each embodiment can be combined in various ways as needed.

[0083] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0084] SED semiconductor device, SUB semiconductor substrate, EP1 first semiconductor layer, US1 top surface, RSS first recess, GRS, GRS1, GRS2 groove, EP2 second semiconductor layer, US2 top surface, TRSS second recess, TRC trench, TRC1 first trench, TRC2 second trench, TRC3 third trench, BS1 first bottom surface, BS2 second bottom surface, BS3 third bottom surface, CR columnar residue, IF insulating film, TIF trench insulating film, TIF1 first part, TIF2 second part, TIF3 third part, REL resistive element, REB resistor body, RIF insulating film, SIF sidewall insulating film, REL1 first resistive element, REL2 second resistive element, REL3 third resistive element, REL4 fourth resistive element, SN1, SN2 silicon nitride film, NWR n-type well region, VR, VW, VH, VL voltage, EFR element region, SCR Scribing area, AM alignment pattern, MAM misalignment confirmation pattern, D1, D2 depth, CL, CL1, CL2 distance, W1, W2 width.

Claims

1. A semiconductor substrate having a main surface, A semiconductor layer having trenches is formed to cover the main surface of the semiconductor substrate, A trench insulating film formed in the trench of the semiconductor layer, At least one resistive element formed in contact with the trench insulating film, Equipped with, The trench mentioned above is A first trench having a first bottom surface located at a first depth from the upper surface of the semiconductor layer, A second trench having a second bottom surface that slopes from the first depth toward a second depth shallower than the first depth, A third trench having a third bottom surface located at the second depth, Includes, The trench dielectric is The first part located within the first trench, The second part located within the second trench, The third part located within the third trench, Includes, A semiconductor device in which the at least one resistive element includes a first resistive element formed to be in contact with the first part.

2. Within the semiconductor layer, a semiconductor region of a first conductivity type is formed extending from the upper surface of the semiconductor layer to a position deeper than the first depth. The trench and the trench insulating film are formed within the semiconductor region. A first voltage is applied to at least one of the resistive elements. The semiconductor device according to claim 1, wherein a second voltage different from the first voltage is applied to the semiconductor region.

3. The semiconductor device according to claim 2, wherein the absolute value of the difference between the first voltage and the second voltage is less than or equal to the gate voltage applied to the semiconductor region when the at least one resistive element is used as gate wiring.

4. The semiconductor device according to claim 1, wherein the at least one resistive element includes a second resistive element formed to be in contact with the second part.

5. A third voltage is applied to the first resistive element. The semiconductor device according to claim 4, wherein a fourth voltage lower than the third voltage is applied to the second resistive element.

6. The aforementioned semiconductor layer is A first semiconductor layer formed to cover the main surface of the semiconductor substrate, A second semiconductor layer formed to cover the first upper surface of the first semiconductor layer, Includes, Within the first semiconductor layer, a recess is formed that is recessed from the first upper surface toward the semiconductor substrate. The second semiconductor layer is formed to cover the recess, The semiconductor device according to claim 1, wherein the trench is located in the portion of the second semiconductor layer located directly above the recess.

7. A process for preparing a semiconductor substrate having a main surface, The process involves forming a first semiconductor layer by growing a first crystal on the main surface of the semiconductor substrate, A step of forming a first recess that recedes toward the semiconductor substrate by performing a first etching process on the first upper surface of the first semiconductor layer, A step of forming a second semiconductor layer having a trench by growing a second crystal on the first upper surface of the first semiconductor layer having the first recess, The steps include forming a trench insulating film so as to fill the trench, A step of forming at least one resistive element so as to be in contact with the trench insulating film, Equipped with, The step of forming the second semiconductor layer having the trench is, A first trench having a first bottom surface located at a first depth from the second upper surface of the second semiconductor layer, A second trench having a second bottom surface that slopes from the first depth toward a second depth shallower than the first depth, The process includes forming The step of forming the trench insulating film is, The first part that embeds the first trench, The second part embeds the second trench, The process includes forming A method for manufacturing a semiconductor device, wherein the step of forming the at least one resistive element includes the step of forming a first resistive element so as to be in contact with the first part.

8. The step of forming the second semiconductor layer having the trench is, A step of forming the second semiconductor layer having the second recess by growing the second crystal in the first recess, By performing a second etching process on the second upper surface of the second semiconductor layer having the second recess, The second trench has a second bottom surface that slopes from the first depth toward a second depth shallower than the first depth, A third trench having a third bottom surface located at the second depth and connected to the second trench, The process of forming, The method for manufacturing a semiconductor device according to claim 7, wherein the step of forming the trench insulating film includes the step of forming a third portion that fills the third trench.

9. The process includes forming an impurity region of a first conductivity type within the second semiconductor layer, extending from the second upper surface of the second semiconductor layer to a position deeper than the first depth, The method for manufacturing a semiconductor device according to claim 8, wherein in the step of forming the second semiconductor layer having the trench, the trench is formed within the impurity region.

10. The method for manufacturing a semiconductor device according to claim 8, wherein the step of forming the at least one resistive element includes the step of forming a second resistive element so as to be in contact with the second part.

11. In the step of forming the second semiconductor layer having the trench, the second semiconductor layer having the second recess is formed by growing the second crystal in the first recess. The method for manufacturing a semiconductor device according to claim 7, wherein the second recess is a trench comprising the first trench and the second trench.

12. The semiconductor substrate comprises a process for defining an element region and a scribe region on the main surface, In the step of forming the first recess, the first recess, which is recessed from the first upper surface toward the semiconductor substrate, is formed within the first semiconductor layer located in the element region, and a groove, which is recessed from the first upper surface toward the semiconductor substrate, is formed simultaneously with the first recess within the first semiconductor layer located in the scribe region. The method for manufacturing a semiconductor device according to claim 7, wherein in the step of forming the second semiconductor layer, an alignment mark is formed in the second semiconductor layer located directly above the groove, recessed from the second upper surface toward the groove.

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