Semiconductor equipment

Abstract

The present invention provides a semiconductor device that enables the monolithic formation of multiple capacitive elements without increasing the chip area. [Solution] The semiconductor devices (DEV1, DEV2) of this disclosure include a semiconductor substrate (SUB) having an element formation area (EFP) and a composite capacitor (CC) formed to surround the element formation area in a plan view. The composite capacitor has a plurality of capacitive elements (C1, C2, C3, C4, C5) that are electrically connected in parallel.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Japanese Patent Application Laid-Open No. 2017-174887 (Patent Document 1) discloses a semiconductor device. The semiconductor device disclosed in Patent Document 1 has a semiconductor substrate, a polysilicon layer, and an insulating film. Trenches are formed on the upper surface of the semiconductor substrate. The semiconductor substrate has a well layer. The well layer is formed in the semiconductor substrate and on the upper surface of the semiconductor substrate so as to surround the trenches. The polysilicon layer is formed in the trenches. The insulating film is disposed between the polysilicon layer and the inner wall surface and bottom surface of the trenches. The well layer, the polysilicon layer, and the insulating film located between the well layer and the polysilicon layer constitute a trench capacitor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the trench capacitor is formed inside the outer peripheral edge of the element formation portion of the semiconductor substrate in plan view, the area of the element formation portion has to be increased in plan view, and the chip area of the semiconductor device increases. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0005] The semiconductor device of this disclosure comprises a semiconductor substrate having an element formation portion and a composite capacitor formed so as to surround the element formation portion in a plan view. The composite capacitor has a plurality of capacitive elements electrically connected in parallel. [Effects of the Invention]

[0006] According to the semiconductor device of this disclosure, multiple capacitive elements can be formed monolithically without increasing the chip area. [Brief explanation of the drawing]

[0007] [Figure 1] This is a plan view of semiconductor device DEV1. [Figure 2] This is a cross-sectional view of semiconductor device DEV1 in line II-II in Figure 1. [Figure 3] This is a schematic equivalent circuit diagram of a composite capacitance CC. [Figure 4A] This is a schematic diagram of the arrangement of multiple circuits in semiconductor device DEV1. [Figure 4B] This is a circuit diagram of a bootstrap circuit. [Figure 5] This is a manufacturing process diagram for semiconductor device DEV1. [Figure 6] This is a cross-sectional view illustrating the ion implantation process S2. [Figure 7] This is a cross-sectional view illustrating the first insulating film formation step S3. [Figure 8] This is a cross-sectional view illustrating the first wiring formation process S4. [Figure 9] This is a cross-sectional view illustrating the second insulating film formation step S5. [Figure 10] This is a cross-sectional view illustrating the second wiring formation process S6. [Figure 11] This is a cross-sectional view illustrating the interlayer insulating film formation process S7. [Figure 12] This is a cross-sectional view illustrating the plug formation process S8. [Figure 13] This is a cross-sectional view illustrating the third wiring formation process S9. [Figure 14]It is a plan view of the semiconductor device DEV1 according to a modified example. [Figure 15] It is a cross-sectional view of the semiconductor device DEV1 according to the modified example taken along XV-XV in FIG. 14. [Figure 16] It is a cross-sectional view of the semiconductor device DEV2. [Figure 17] It is an equivalent circuit diagram of the composite capacitor CC in the semiconductor device DEV2.

Embodiments for Carrying Out the Invention

[0008] Details of embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First Embodiment) The semiconductor device DEV1 according to the first embodiment will be described.

[0010] <Configuration of the semiconductor device DEV1> As shown in FIGS. 1 and 2, the semiconductor device DEV1 has a semiconductor substrate SUB. The semiconductor substrate SUB has an upper surface F1 and a lower surface F2 located on the opposite side of the upper surface F1. In a plan view, the semiconductor substrate SUB has an element formation portion EFP and an outer peripheral portion PER surrounding the element formation portion EFP. The semiconductor substrate SUB is formed of, for example, single crystal silicon. The semiconductor device DEV1 further has a composite capacitor CC. The composite capacitor CC surrounds the element formation portion EFP in a plan view. In other words, from another perspective, the composite capacitor CC overlaps the outer peripheral portion PER in a plan view.

[0011] The composite capacitance CC has an impurity diffusion layer IDL1 and an impurity diffusion layer IDL2. The impurity diffusion layer IDL1 and the impurity diffusion layer IDL2 are formed in a semiconductor substrate SUB. The impurity diffusion layer IDL1 is disposed on the upper surface F1. The impurity diffusion layer IDL2 is disposed under the impurity diffusion layer IDL1 so as to be in contact with the impurity diffusion layer IDL1. However, a part of the impurity diffusion layer IDL2 is disposed on the upper surface F1. The conductivity type of the impurity diffusion layer IDL1 is opposite to that of the impurity diffusion layer IDL2. For example, when the conductivity type of the impurity diffusion layer IDL1 is p-type, the conductivity type of the impurity diffusion layer IDL2 is n-type.

[0012] The composite capacitance CC further has an insulating film IF1. The insulating film IF1 is formed on the upper surface F1 so as to overlap the impurity diffusion layer IDL1 in plan view. The insulating film IF1 is formed of, for example, silicon oxide. The semiconductor device DEV1 further has a wiring WL1. The wiring WL1 is formed on the insulating film IF1. In other words, from another perspective, the insulating film IF1 is disposed between the wiring WL1 and the impurity diffusion layer IDL1. The wiring WL1 is formed of, for example, polycrystalline silicon containing a dopant.

[0013] The composite capacitance CC further has an insulating film IF2. The insulating film IF2 is formed on the wiring WL1. The insulating film IF2 has, for example, a first silicon oxide film, a silicon nitride film formed on the first silicon oxide film, and a second silicon oxide film formed on the silicon nitride film. In other words, from another perspective, the insulating film IF2 is an ONO (Oxide Nitride Oxide) film.

[0014] The composite capacitance CC further has a wiring WL2. The wiring WL2 is formed on the insulating film IF2. In other words, from another perspective, the insulating film IF2 is disposed between the wiring WL2 and the wiring WL1. The wiring WL2 is formed of, for example, a metal silicide such as tungsten silicide.

[0015] The semiconductor device DEV1 further includes interlayer insulating films ILD1, ILD2, ILD3, ILD4, and ILD5. Interlayer insulating film ILD1 is formed on the upper surface F1 so as to cover insulating film IF1, wiring WL1, insulating film IF2, and wiring WL2. Interlayer insulating film ILD2 is formed on interlayer insulating film ILD1. Interlayer insulating film ILD3 is formed on interlayer insulating film ILD2. Interlayer insulating film ILD4 is formed on interlayer insulating film ILD3. Interlayer insulating film ILD5 is formed on interlayer insulating film ILD4. Interlayer insulating films ILD1, ILD2, ILD3, ILD4, and ILD5 are formed of, for example, silicon oxide.

[0016] The composite capacitance CC further comprises an insulating film IF3, a plurality of conductive laminates CLB1, and a plurality of conductive laminates CLB2. The insulating film IF3 comprises an interlayer insulating film ILD2 and an interlayer insulating film ILD3. The plurality of conductive laminates CLB1 and CLB2 are formed within the insulating film IF3.

[0017] Each of the multiple conductive laminates CLB1 has wirings WL3aa, WL3ab, and WL3ac, and plugs PG1aa and PG1ab. Wiring WL3aa is formed on the interlayer insulating film ILD1 and covered by the interlayer insulating film ILD2. Wiring WL3ab is formed on the interlayer insulating film ILD2 and covered by the interlayer insulating film ILD3. Wiring WL3ac is formed on the interlayer insulating film ILD3 and covered by the interlayer insulating film ILD4. Wirings WL3aa, WL3ab, and WL3ac extend along the outer peripheral PER in a plan view. Wirings WL3aa, WL3ab, and WL3ac overlap each other in a plan view.

[0018] Plugs PG1aa and PG1ab extend along the outer periphery PER in a plan view. Plug PG1aa is formed within the interlayer insulating film ILD2. Plug PG1aa is located between wiring WL3aa and wiring WL3ab, connecting wiring WL3aa and wiring WL3ab. Plug PG1ab is formed within the interlayer insulating film ILD3. Plug PG1ab is located between wiring WL3ab and wiring WL3ac, connecting wiring WL3ab and wiring WL3ac. Plugs PG1aa and PG1ab overlap each other in a plan view. Thus, each of the multiple conductive laminates CLB1 has multiple wirings and multiple plugs, and the multiple wirings are stacked such that one of the multiple plugs is located between two adjacent wirings.

[0019] Each of the multiple conductive laminates CLB2 has wirings WL3ba, WL3bb, and WL3bc, and plugs PG1ba and PG1bb. Wiring WL3ba is formed on the interlayer insulating film ILD1 and covered by the interlayer insulating film ILD2. Wiring WL3bb is formed on the interlayer insulating film ILD2 and covered by the interlayer insulating film ILD3. Wiring WL3bc is formed on the interlayer insulating film ILD3 and covered by the interlayer insulating film ILD4. Wirings WL3ba, WL3bb, and WL3bc extend along the outer periphery PER in a plan view. Wirings WL3ba, WL3bb, and WL3bc overlap each other in a plan view.

[0020] Plugs PG1ba and PG1bb extend along the outer periphery PER in a plan view. Plug PG1ba is formed within the interlayer insulating film ILD2. Plug PG1ba is located between wiring WL3ba and wiring WL3bb, connecting wiring WL3ba and wiring WL3bb. Plug PG1bb is formed within the interlayer insulating film ILD3. Plug PG1bb is located between wiring WL3bb and wiring WL3bc, connecting wiring WL3bb and wiring WL3bc. Plugs PG1ba and PG1bb overlap each other in a plan view. Thus, each of the multiple conductive laminates CLB2 has multiple wirings and multiple plugs, and the multiple wirings are overlapped such that one of the multiple plugs is located between two adjacent wirings.

[0021] Wirings WL3aa, WL3ab, and WL3ac are formed of, for example, aluminum or an aluminum alloy. Plugs PG1aa and PG1ab are formed of, for example, tungsten. Wirings WL3ba, WL3bb, and WL3bc are formed of, for example, aluminum or an aluminum alloy. Plugs PG1ba and PG1bb are formed of, for example, tungsten.

[0022] The conductive laminates CLB1 and CLB2 are arranged alternately with gaps between them, along the direction from the inner edge to the outer edge of the outer peripheral PER. From another perspective, a portion of the insulating film IF3 is positioned between adjacent conductive laminates CLB1 and CLB2.

[0023] The semiconductor device DEV1 further includes a conductive laminate CLB3. In a plan view, the conductive laminate CLB3 surrounds a composite capacitance CC. The conductive laminate CLB3 includes wiring WL4aa, WL4ab, WL4ac, WL4ad, and WL4ae, and plugs PG2aa, PG2ab, PG2ac, PG2ad, and PG2ae.

[0024] Wirings WL4aa, WL4ab, WL4ac, WL4ad, and WL4ae extend along the outer periphery PER in a plan view. Wiring WL4aa is formed on interlayer insulating film ILD1 and covered by interlayer insulating film ILD2. Wiring WL4ab is formed on interlayer insulating film ILD2 and covered by interlayer insulating film ILD3. Wiring WL4ac is formed on interlayer insulating film ILD3 and covered by interlayer insulating film ILD4. Wiring WL4ad is formed on interlayer insulating film ILD4 and covered by interlayer insulating film ILD5. Wiring WL4ae is formed on interlayer insulating film ILD5. Wirings WL4aa, WL4ab, WL4ac, WL4ad, and WL4ae overlap each other in a plan view.

[0025] Plugs PG2aa, PG2ab, PG2ac, PG2ad, and PG2ae extend along the outer peripheral PER in a plan view. Plug PG2aa is formed within the interlayer insulating film ILD1. Plug PG2aa is positioned between wiring WL4aa and the semiconductor substrate SUB, connecting wiring WL4aa and the impurity diffusion layer IDL2. Plug PG2ab is formed within the interlayer insulating film ILD2. Plug PG2ab is positioned between wiring WL4aa and wiring WL4ab, connecting wiring WL4aa and wiring WL4ab.

[0026] Plug PG2ac is formed within the interlayer insulating film ILD3. Plug PG2ac is positioned between wiring WL4ab and wiring WL4ac, connecting wiring WL4ab and wiring WL4ac. Plug PG2ad is formed within the interlayer insulating film ILD4. Plug PG2ad is positioned between wiring WL4ac and wiring WL4ad, connecting wiring WL4ac and wiring WL4ad. Plug PG2ae is formed within the interlayer insulating film ILD5. Plug PG2ae is positioned between wiring WL4ad and wiring WL4ae, connecting wiring WL4ad and wiring WL4ae. Plugs PG2aa, PG2ab, PG2ac, PG2ad, and PG2ae overlap each other in a plan view. Thus, the conductive laminate CLB3 has multiple wirings and multiple plugs, and the multiple wirings are stacked such that one of the multiple plugs is positioned between two adjacent wirings and between the bottommost wiring and the top surface F1.

[0027] Wirings WL4aa, WL4ab, WL4ac, WL4ad, and WL4ae are formed of, for example, aluminum or an aluminum alloy. Plugs PG2aa, PG2ab, PG2ac, PG2ad, and PG2ae are formed of, for example, tungsten.

[0028] The semiconductor device DEV1 further includes a conductive laminate CLB4. In a plan view, the conductive laminate CLB4 is surrounded by a composite capacitance CC. The conductive laminate CLB4 includes wiring WL4ba, WL4bb, WL4bc, WL4bd and WL4be, and plugs PG2ba, PG2bb, PG2bc, PG2bd and PG2be.

[0029] Wirings WL4ba, WL4bb, WL4bc, WL4bd, and WL4be extend along the outer periphery PER in a plan view. Wiring WL4ba is formed on the interlayer insulating film ILD1 and covered by the interlayer insulating film ILD2. Wiring WL4bb is formed on the interlayer insulating film ILD2 and covered by the interlayer insulating film ILD3. Wiring WL4bc is formed on the interlayer insulating film ILD3 and covered by the interlayer insulating film ILD4. Wiring WL4bd is formed on the interlayer insulating film ILD4 and covered by the interlayer insulating film ILD5. Wiring WL4be is formed on the interlayer insulating film ILD5. Wirings WL4ba, WL4bb, WL4bc, WL4bd, and WL4be overlap each other in a plan view.

[0030] Plugs PG2ba, PG2bb, PG2bc, PG2bd, and PG2be extend along the outer peripheral PER in a plan view. Plug PG2ba is formed within the interlayer insulating film ILD1. Plug PG2ba is positioned between wiring WL4ba and the semiconductor substrate SUB, connecting wiring WL4ba and the impurity diffusion layer IDL2. Plug PG2bb is formed within the interlayer insulating film ILD2. Plug PG2bb is positioned between wiring WL4ba and wiring WL4bb, connecting wiring WL4ba and wiring WL4bb.

[0031] Plug PG2bc is formed within the interlayer insulating film ILD3. Plug PG2bc is positioned between wiring WL4bb and wiring WL4bc, connecting wiring WL4bb and wiring WL4bc. Plug PG2bd is formed within the interlayer insulating film ILD4. Plug PG2bd is positioned between wiring WL4bc and wiring WL4bd, connecting wiring WL4bc and wiring WL4bd. Plug PG2be is formed within the interlayer insulating film ILD5. Plug PG2be is positioned between wiring WL4bd and wiring WL4be, connecting wiring WL4bd and wiring WL4be. Plugs PG2ba, PG2bb, PG2bc, PG2bd, and PG2be overlap each other in a plan view. Thus, the conductive laminate CLB4 has multiple wirings and multiple plugs, and the multiple wirings are stacked such that one of the multiple plugs is positioned between two adjacent wirings and between the bottommost wiring and the top surface F1.

[0032] Wirings WL4ba, WL4bb, WL4bc, WL4bd, and WL4be are formed of, for example, aluminum or an aluminum alloy. Plugs PG2ba, PG2bb, PG2bc, PG2bd, and PG2be are formed of, for example, tungsten.

[0033] The semiconductor device DEV1 further includes wiring WL5a and a plurality of plugs PG3a. Wiring WL5a is formed on the interlayer insulating film ILD4 and covered by the interlayer insulating film ILD5. In a plan view, wiring WL5a extends along the outer peripheral PER and overlaps with a plurality of conductive laminates CLB1 and a plurality of conductive laminates CLB2. However, in a plan view, wiring WL5a does not overlap with the conductive laminate CLB2 located closest to the outer peripheral edge of the outer peripheral PER, nor does it overlap with the conductive laminate CLB2 located closest to the inner peripheral edge of the outer peripheral PER. The plurality of plugs PG3a are formed within the interlayer insulating film ILD4. Each of the plurality of plugs PG3a connects wiring WL5a to each of the wiring WL3ac of the plurality of conductive laminates CLB1. Wiring WL5a is formed of, for example, aluminum or an aluminum alloy, and the plurality of plugs PG3a are formed of, for example, tungsten.

[0034] The semiconductor device DEV1 further includes wiring WL5b and WL5c, and plugs PG3b and PG3c. Wiring WL5b and WL5c are formed on the interlayer insulating film ILD4 and covered by the interlayer insulating film ILD5. In a plan view, wiring WL5b overlaps with the conductive laminate CLB2 located closest to the outer edge of the outer peripheral PER, and wiring WL5c overlaps with the conductive laminate CLB2 located closest to the inner edge of the outer peripheral PER. Plugs PG3b and PG3c are formed within the interlayer insulating film ILD4.

[0035] Plug PG3b is located between wiring WL3bc and wiring WL5b of the conductive laminate CLB2, which is closest to the outer edge of the outer periphery of the outer periphery PER, and connects wiring WL3bc and wiring WL5b of the conductive laminate CLB2, which is closest to the outer edge of the outer periphery of the outer periphery PER. Plug PG3c is located between wiring WL3bc and wiring WL5c of the conductive laminate CLB2, which is closest to the inner edge of the outer periphery of the outer periphery PER, and connects wiring WL3bc and wiring WL5c of the conductive laminate CLB2, which is closest to the inner edge of the outer periphery PER.

[0036] Wiring WL5b and WL5c are made of, for example, aluminum or an aluminum alloy, and plugs PG3b and PG3c are made of, for example, tungsten.

[0037] The semiconductor device DEV1 further includes a plug PG4a. The plug PG4a is formed within the interlayer insulating film ILD1. The plug PG4a is positioned between one of the multiple conductive laminates CLB1 wirings WL3aa and WL1, connecting the two wirings. The plug PG4a is made of, for example, tungsten.

[0038] The semiconductor device DEV1 further has a plurality of plugs PG4b. The plurality of plugs PG4b are formed within the interlayer insulating film ILD1. Each of the plurality of plugs PG4b is positioned between each wiring WL3ba and wiring WL2 of the plurality of conductive laminates CLB2, connecting each wiring WL3ba and wiring WL2 of the plurality of conductive laminates CLB2. The plurality of plugs PG4b are formed of, for example, tungsten.

[0039] The semiconductor device DEV1 further includes plugs PG4c and PG4d. The wiring WL3ba of the conductive laminate CLB2 located closest to the outer edge of the outer peripheral PER has a projection WL3baa that protrudes toward the outer peripheral edge of the outer peripheral PER. The wiring WL3ba of the conductive laminate CLB2 located closest to the inner peripheral edge of the outer peripheral PER has a projection WL3bab that protrudes toward the inner peripheral edge of the outer peripheral PER.

[0040] Plug PG4c overlaps with the protrusion WL3baa in a plan view. Plug PG4c is formed within the interlayer insulating film ILD1. Plug PG4c is positioned between the protrusion WL3baa and the impurity diffusion layer IDL1, connecting the protrusion WL3baa and the impurity diffusion layer IDL1. Plug PG4d is formed within the interlayer insulating film ILD1. Plug PG4d overlaps with the protrusion WL3bab in a plan view. Plug PG4d is positioned between the protrusion WL3bab and the impurity diffusion layer IDL1, connecting the protrusion WL3bab and the impurity diffusion layer IDL1. Plugs PG4c and PG4d are made of, for example, tungsten.

[0041] The semiconductor device DEV1 further comprises wiring WL6a, wiring WL6b, and wiring WL6c, and plugs PG5a, plugs PG5b, and plugs PG5c. Wiring WL6a, wiring WL6b, and wiring WL6c are formed on the interlayer insulating film ILD5. In a plan view, wiring WL6a overlaps with wiring WL5a. In a plan view, wiring WL6b partially overlaps with wiring WL5b, and wiring WL6c partially overlaps with the wiring WL5c conductive laminate CLB2.

[0042] Plugs PG5a, PG5b, and PG5c are formed within the interlayer insulating film ILD5. Plug PG5a is positioned between wiring WL6a and wiring WL5a, connecting wiring WL6a and wiring WL5a. Plug PG5b is positioned between wiring WL6b and wiring WL5b, connecting wiring WL6b and wiring WL5b. Plug PG5c is positioned between wiring WL6c and wiring WL5c, connecting wiring WL6c and wiring WL5c.

[0043] Wirings WL6a, WL6b, and WL6c are made of, for example, aluminum or an aluminum alloy. Plugs PG5a, PG5b, and PG5c are made of, for example, tungsten.

[0044] A composite capacitance CC has multiple capacitance elements. More specifically, as shown in Figure 3, a composite capacitance CC has capacitance elements C1, C2, C3, and C4. Capacitor element C1 has an impurity diffusion layer IDL1, an insulating film IF1, and wiring WL1. Capacitor element C2 has wiring WL1, an insulating film IF2, and wiring WL2. Capacitor element C3 has adjacent conductive laminates CLB1 and CLB2, and a part of the insulating film IF3 located between adjacent conductive laminates CLB1 and CLB2. Capacitor element C4 has an impurity diffusion layer IDL1 and an impurity diffusion layer IDL2. Note that a composite capacitance CC only needs to have at least two of the capacitance elements C1, C2, C3, and C4.

[0045] Capacitive elements C1, C2, C3, and C4 are connected in parallel to each other. A first potential is applied to wirings WL6a, WL4ae, and WL4be, and a second potential different from the first potential is applied to wirings WL6b and WL6c. As a result, charge is accumulated in the composite capacitance CC. The width of the composite capacitance CC is measured between the center of wiring WL4ae and the center of wiring WL4be in the direction from the inner edge to the outer edge of the outer peripheral PER. The length of the composite capacitance CC is measured along the direction in which the outer peripheral PER extends in a plan view. The area of ​​the composite capacitance CC in a plan view is the product of the length and width mentioned above. The capacitance per unit area of ​​the composite capacitance CC, i.e., the capacitance of the composite capacitance CC divided by the area mentioned above, is, for example, 3.3 nF / mm². 2 The above and 4nF / mm 2 The following applies:

[0046] As shown in Figure 1, the semiconductor device DEV1 has a plurality of pads PD. The plurality of pads PD are formed on the interlayer insulating film ILD5. The plurality of pads PD are arranged in a row along the outer edge of the element formation area EFP. The plurality of pads PD are formed of, for example, aluminum or an aluminum alloy. Adjacent pads PD1 and PD2 of the plurality of pads PD are spaced apart. A portion of the composite capacitance CC may be located between pads PD1 and PD2 in a plan view. A portion of the composite capacitance CC may be formed in a layer below the plurality of pads PD so as to overlap them in a plan view.

[0047] As shown in Figure 4A, the semiconductor device DEV1 includes, for example, a logic circuit block LCB and a plurality of analog circuit blocks ACB. The logic circuit block LCB and the plurality of analog circuit blocks ACB are arranged inside the outer edge of the element formation area EFP, for example, such that in a plan view the logic circuit block LCB is surrounded by the plurality of analog circuit blocks ACB. In other words, in a plan view the plurality of analog circuit blocks ACB are arranged along the outer edge of the element formation area EFP.

[0048] Among the multiple analog circuit blocks ACB, analog circuit block ACB1 is an analog circuit block that includes, for example, multiple LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistors. The analog circuit included in analog circuit block ACB1 is, for example, a bootstrap circuit. As shown in Figure 4B, the bootstrap circuit has transistors Tr1 and Tr2. The source of transistor Tr1 is connected to the drain of transistor Tr2. That is, transistor Tr1 is connected in series with transistor Tr2. The source of transistor Tr1 and the drain of transistor Tr2 are connected to the switch terminal SW.

[0049] The drain of transistor Tr1 is connected to the input terminal VIN. The source of transistor Tr2 is connected to the ground terminal GND. The input terminal VIN is connected to the boot terminal BT. The boot terminal BT is connected to the switch terminal SW. The ground terminal GND is connected to the switch terminal SW. The bootstrap circuit further includes an inductor L and a capacitor C. The inductor L connects the switch terminal SW to the output terminal VOUT. The capacitor C connects the output terminal VOUT to ground potential.

[0050] The bootstrap circuit further includes a diode DI. The anode of diode DI is connected between the input terminal VIN and the drain of transistor Tr1, and the cathode of diode DI is connected to the boot terminal BT. The bootstrap circuit further includes pre-driver PRD1 and pre-driver PRD2. Pre-driver PRD1 is connected to the gate of transistor Tr1, the boot terminal BT, and the switch terminal SW. Pre-driver PRD2 is connected to the gate of transistor Tr2. The bootstrap circuit further includes a bootstrap capacitor BSC. One electrode of bootstrap capacitor BSC is connected to the boot terminal BT, and the other electrode of bootstrap capacitor BSC is connected between the switch terminal SW and inductor L.

[0051] In the first state, transistor Tr2 is turned ON. As a result, the switch terminal SW becomes ground potential, and the potential of the input terminal VIN is applied to the bootstrap capacitor BSC via diode DI and boot terminal BT, thereby charging the bootstrap capacitor BSC. In the second state, transistor Tr2 is turned OFF. As a result, the potential of the boot terminal BT becomes higher than the potential of the input terminal VIN, and the charge discharged from the charged bootstrap capacitor BSC turns transistor Tr1 ON. The bootstrap circuit operates by alternating between the first and second states.

[0052] The composite capacitance CC is connected to multiple analog circuit blocks ACB. For example, the composite capacitance CC is connected to analog circuit block ACB1 and used as the bootstrap capacitor BSC in a bootstrap circuit. Among the multiple analog circuit blocks ACB, analog circuit block ACB2 is, for example, a circuit block containing a small-signal analog circuit. Analog circuit blocks ACB1 and ACB2 are arranged so that they are not adjacent in a plan view. For example, in a plan view, a logic circuit block LCB is located between analog circuit blocks ACB1 and ACB2.

[0053] The composite capacitance CC may be divided. For example, the composite capacitance CC may be divided at one point opposite the analog circuit block ACB2 in a plan view. The composite capacitance CC may be divided at two or more points. For example, the portion of the composite capacitance CC that surrounds the analog circuit block ACB1 in a plan view may be separated from the portion of the composite capacitance CC that surrounds the analog circuit block ACB2 in a plan view.

[0054] <Manufacturing method for semiconductor device DEV1> As shown in Figure 5, the manufacturing method for semiconductor device DEV1 includes a preparation step S1, an ion implantation step S2, a first insulating film formation step S3, a first wiring formation step S4, a second insulating film formation step S5, a second wiring formation step S6, an interlayer insulating film formation step S7, a plug formation step S8, a third wiring formation step S9, and a piece formation step S10.

[0055] In preparation step S1, the semiconductor substrate SUB is prepared. As shown in Figure 6, in ion implantation step S2, impurity diffusion layers IDL1 and IDL2 are formed in the semiconductor substrate SUB located at the outer peripheral PER by ion implantation. As shown in Figure 7, in first insulating film formation step S3, insulating film IF1 is formed on the upper surface F1 located at the outer peripheral PER by, for example, thermal oxidation.

[0056] As shown in Figure 8, in the first wiring formation step S4, wiring WL1 is formed on the insulating film IF1. In the first wiring formation step S4, firstly, the constituent material of wiring WL1 is formed on the insulating film IF1 by, for example, the CVD (Chemical Vapor Deposition) method. Secondly, a resist pattern is formed on the constituent material of wiring WL1. The resist pattern is formed by coating the constituent material of wiring WL1 with photoresist, and then exposing and developing the photoresist. Thirdly, the constituent material of wiring WL1 is patterned by dry etching through the openings in the resist pattern, thereby forming wiring WL1.

[0057] As shown in Figure 9, in the second insulating film formation step S5, an insulating film IF2 is formed on the wiring WL1. In the second insulating film formation step S5, firstly, the constituent materials of the insulating film IF2, namely the constituent materials of the first silicon oxide film, the constituent materials of the silicon nitride film, and the constituent materials of the second silicon oxide film, are sequentially deposited on the wiring WL1, for example by CVD, to form the insulating film IF2.

[0058] As shown in Figure 10, in the second wiring formation step S6, wiring WL2 is formed on the insulating film IF2. In the second wiring formation step S6, firstly, the constituent material of wiring WL2 is formed on the insulating film IF1, for example by sputtering. Secondly, a resist pattern is formed on the constituent material of wiring WL1. The resist pattern is formed by coating the constituent material of wiring WL1 with photoresist, and then exposing and developing the photoresist. Thirdly, the constituent material of wiring WL2 and the constituent material of insulating film IF2 are patterned by dry etching through the openings in the resist pattern, thereby forming wiring WL2.

[0059] As shown in Figure 11, in the interlayer insulating film formation step S7, the interlayer insulating film ILD1 is formed on the upper surface F1 so as to cover the insulating film IF1, wiring WL1, insulating film IF2, and wiring WL2. In the interlayer insulating film formation step S7, firstly, the constituent material of the interlayer insulating film ILD1 is formed on the upper surface F1 so as to cover the insulating film IF1, wiring WL1, insulating film IF2, and wiring WL2, for example by the CVD method. Secondly, the upper surface of the constituent material of the interlayer insulating film ILD1 is planarized, for example by the CMP (Chemical Mechanical Polishing) method. Through the above steps, the interlayer insulating film ILD1 is formed.

[0060] As shown in Figure 12, in the plug formation step S8, plugs PG2aa, PG2ba, PG4a, multiple plugs PG4b, plugs PG4c, and plugs PG4d are formed within the interlayer insulating film ILD1. In the plug formation step S8, firstly, a resist pattern is formed on the interlayer insulating film ILD1. The resist pattern is formed by coating the interlayer insulating film ILD1 with photoresist, and then exposing and developing the photoresist. Secondly, multiple through holes are formed within the interlayer insulating film ILD1 by dry etching through the openings in the resist pattern. Thirdly, constituent materials such as plugs PG2aa are embedded in the multiple through holes, for example by CVD, and constituent materials such as plugs PG2aa are formed on the interlayer insulating film ILD1. Fourthly, constituent materials such as plugs PG2aa formed outside the multiple through holes are removed, for example by CMP. As a result, plugs PG2aa, PG2ba, PG4a, multiple plugs PG4b, plugs PG4c, and plugs PG4d are formed.

[0061] As shown in Figure 13, in the third wiring formation step S9, multiple wirings WL3aa, multiple wirings WL3ba, wirings WL4aa and WL4ba are formed on the interlayer insulating film ILD1. In the third wiring formation step S9, firstly, constituent materials such as wiring WL3aa are formed on the interlayer insulating film ILD1, for example by sputtering. Secondly, a resist pattern is formed on the constituent materials such as wiring WL2aa. Thirdly, the constituent materials such as wiring WL2aa are patterned by dry etching through the openings in the resist pattern, thereby forming multiple wirings WL3aa, multiple wirings WL3ba, wirings WL4aa and WL4ba.

[0062] The same process as in the interlayer insulating film formation process S7, the same process as in the plug formation process S8, and the same process as in the third wiring formation process S9 are repeated to form wiring WL3aa, multiple wirings WL3ba, wiring WL4aa, wiring located above wiring WL4ba, interlayer insulating film, and multiple pads PD. Subsequently, the individualization process S10 is performed to form the structure of the semiconductor device DEV1 shown in Figures 1 and 2.

[0063] <Variation> As shown in Figures 14 and 15, the semiconductor device DEV1 may further have a seal ring SR. In a plan view, the seal ring SR surrounds the composite capacitance CC. That is, in a plan view, the seal ring SR is formed outside the conductive laminate CLB1. The seal ring SR has conductors CN1, CN2, CN3, CN4 and CN5, and plugs PG6a, PG6b, PG6c, PG6d and PG6e.

[0064] Conductor CN1 is formed on interlayer insulating film ILD1 and covered by interlayer insulating film ILD2. Conductor CN2 is formed on interlayer insulating film ILD2 and covered by interlayer insulating film ILD3. Conductor CN3 is formed on interlayer insulating film ILD3 and covered by interlayer insulating film ILD4. Conductor CN4 is formed on interlayer insulating film ILD4 and covered by interlayer insulating film ILD5. Conductor CN5 is formed on interlayer insulating film ILD1. Conductors CN1, CN2, CN3, CN4, and CN5 overlap each other in a plan view and extend along the outer periphery PER in a plan view. Conductors CN1, CN2, CN3, CN4, and CN5 are formed of, for example, aluminum or an aluminum alloy.

[0065] Plug PG6a is formed within the interlayer insulating film ILD1. Plug PG6b is formed within the interlayer insulating film ILD2. Plug PG6c is formed within the interlayer insulating film ILD3. Plug PG6d is formed within the interlayer insulating film ILD4. Plug PG6e is formed within the interlayer insulating film ILD5. Plugs PG6a, PG6b, PG6c, PG6d, and PG6e overlap each other in a plan view and extend along the outer peripheral PER.

[0066] Plug PG6a is positioned between the top surface F1 and conductor CN1, connecting top surface F1 and conductor CN1. Plug PG6b is positioned between conductor CN1 and conductor CN2, connecting conductor CN1 and conductor CN2. Plug PG6c is positioned between conductor CN2 and conductor CN3, connecting conductor CN2 and conductor CN3. Plug PG6d is positioned between conductor CN3 and conductor CN4, connecting conductor CN3 and conductor CN4. Plug PG6e is positioned between conductor CN4 and conductor CN5, connecting conductor CN4 and conductor CN5.

[0067] <Effects of Semiconductor Device DEV1> If we want to avoid using external high-capacitance capacitors such as bootstrap capacitors (BSCs), it is necessary to monolithically form multiple capacitive elements on the semiconductor device DEV1. However, if multiple capacitive elements are formed inside the outer edge of the element formation area (EFP) in a plan view, the area of ​​the element formation area (EFP) in a plan view increases, and consequently, the chip area of ​​the semiconductor device DEV1 increases.

[0068] In this regard, in semiconductor device DEV1, a composite capacitance CC is formed so as to surround the element formation area EFP in a plan view. That is, in semiconductor device DEV1, the composite capacitance CC is formed so as to overlap with the outer peripheral area PER in a plan view. Since no circuit elements are formed in the position that overlaps with the outer peripheral area PER in a plan view, semiconductor device DEV1 does not compress the area of ​​the element formation area EFP due to the composite capacitance CC, and thus the increase in chip area can be suppressed.

[0069] A trench capacitor has a trench formed on the upper surface of a semiconductor substrate, a well layer formed within the semiconductor substrate surrounding the trench, a polysilicon layer formed within the trench, and an insulating film interposed between the polysilicon layer and the inner wall and bottom surfaces of the trench. Because a special process is required to form such a trench capacitor, the manufacturing cost increases when multiple trench capacitors are formed instead of a composite capacitance capacitor (CC).

[0070] A planar MOS capacitor has a well layer formed within a semiconductor substrate and located on the upper surface of the semiconductor substrate, an insulating film formed on the upper surface of the semiconductor substrate so as to overlap the well layer in a plan view, and a polysilicon layer formed on the insulating film. Compared to trench capacitors, planar MOS capacitors have a smaller capacitance per unit area. Also, to prevent malfunctions due to capacitive coupling, wiring cannot be placed above a planar MOS capacitor. Therefore, when forming multiple planar MOS capacitors instead of composite capacitance CCs, the chip area increases, and the number of chips that can be obtained from a single wafer decreases, thus increasing manufacturing costs.

[0071] Since the composite capacitance CC is formed during the process of forming the impurity diffusion layer, wiring, and plug that constitute the circuit elements other than the composite capacitance CC, no special process is required to form the composite capacitance CC. In the composite capacitance CC, capacitance elements C1, C2, C3, and C4 are connected in parallel to each other. Furthermore, since the wiring that constitutes the circuit elements other than the composite capacitance CC does not cross the outer peripheral area in a plan view, the wiring, impurity diffusion layer, and plug that overlap with the outer peripheral area in a plan view can be effectively utilized as capacitance resources. As a result, the capacitance per unit area can be increased in the composite capacitance CC, and the increase in the manufacturing cost of the semiconductor device DEV1 can be suppressed.

[0072] In semiconductor device DEV1, the conductive laminate CLB3 not only supplies potential to the impurity diffusion layer IDL2 but also plays a role in stopping crack propagation during dicing, making it possible to further reduce the chip area by omitting the seal ring SR. Furthermore, even if the conductive laminate CLB3 is damaged due to crack propagation, potential can be supplied from the conductive laminate CLB4 to the impurity diffusion layer IDL2, thus ensuring the functionality of the composite capacitance CC even if the conductive laminate CLB3 is damaged due to crack propagation.

[0073] In semiconductor device DEV1, the composite capacitance CC is formed so that it overlaps with the outer peripheral portion PER in a plan view, resulting in a short distance from the junction capacitance CC to the connection destination of the composite capacitance CC, i.e., the distance from the junction capacitance CC to the analog circuit block ACB. Therefore, in semiconductor device DEV1, the wiring between the composite capacitance CC and the analog circuit block ACB can be shortened.

[0074] Analog circuit block ACB1 is prone to becoming a noise source, while analog circuit block ACB2 is sensitive to noise. Therefore, if the composite capacitance CC surrounding analog circuit block ACB1 in a plan view is separated from the composite capacitance CC surrounding analog circuit block ACB2 in a plan view, noise generated in analog circuit block ACB1 will have difficulty propagating to analog circuit block ACB2 via the composite capacitance CC. Furthermore, if the junction capacitance CC is divided at one point facing analog circuit block ACB2, the distance that noise generated in analog circuit block ACB1 has to travel through the junction capacitance CC to reach analog circuit block ACB2 will be longer, thus reducing the impact of noise generated in analog circuit block ACB1 on analog circuit block ACB2.

[0075] If a portion of the composite capacitance CC is located between pad PD1 and pad PD2 in a plan view, the area of ​​the composite capacitance CC in a plan view becomes even larger, and the capacitance of the composite capacitance CC becomes even larger.

[0076] (Second Embodiment) The semiconductor device DEV2 according to the second embodiment will be described. Here, we will mainly explain the differences from the semiconductor device DEV1, and will avoid repeating redundant explanations.

[0077] As shown in Figure 16, in the semiconductor device DEV2, the interlayer insulating film ILD5 has a first layer ILD5a and a second layer ILD5b. The first layer ILD5a is formed on the interlayer insulating film ILD4 so as to cover wiring WL5a, wiring WL5b, wiring WL5c, wiring WL4ae and wiring WL4be. The second layer ILD5b is formed on the first layer ILD5a. The semiconductor device DEV2 further has wiring WL7. Wiring WL7 is formed on the first layer ILD5a and covered by the second layer ILD5b. In other words, a portion of the first layer ILD5a is located between wiring WL5a and wiring WL7. Wiring WL7 is formed of, for example, titanium nitride.

[0078] The semiconductor device DEV2 further includes plugs PG7a and PG7b. Plugs PG7a and PG7b are formed within the second layer ILD5b. Wiring WL6b partially overlaps with wiring WL7 in a plan view. Wiring WL6c partially overlaps with wiring WL7 in a plan view. Plug PG7a is positioned between wiring WL6b and wiring WL7 and connects wiring WL6b and wiring WL7. Plug PG7b is positioned between wiring WL6c and wiring WL7 and connects wiring WL6c and wiring WL7. Plugs PG7a and PG7b are formed of, for example, tungsten.

[0079] In the manufacturing method of semiconductor device DEV2, the process up to forming wiring WL5a, wiring WL5b, wiring WL5c, wiring WL4ae, and wiring WL4be on the interlayer insulating film ILD4 is the same as in the manufacturing method of semiconductor device DEV1.

[0080] The first layer ILD5a is formed after the wiring WL5a, WL5b, WL5c, WL4ae, and WL4be. In forming the first layer ILD5a, firstly, the constituent material of the first layer ILD5a is formed on the interlayer insulating film ILD4 so as to cover the wiring WL5a, WL5b, WL5c, WL4ae, and WL4be, for example by CVD. Secondly, the upper surface of the formed constituent material of the first layer ILD5a is planarized, for example by CMP. Thus, the first layer ILD5a is formed.

[0081] In forming the wiring WL7, firstly, after the first layer ILD5a is formed, the constituent material of the wiring WL7 is formed on the first layer ILD5a, for example by sputtering. Secondly, a resist pattern is formed on the constituent material of the wiring WL7. The resist pattern is formed by coating the constituent material of the wiring WL7 with photoresist, and then exposing and developing the photoresist. Thirdly, the constituent material of the wiring WL7 is patterned by dry etching through the openings in the resist pattern, thereby forming the wiring WL7.

[0082] In forming the second layer ILD5b, firstly, after the wiring WL7 is formed, the constituent material of the second layer ILD5b is formed on the first layer ILD5a so as to cover the wiring WL7, for example by CVD. Secondly, the upper surface of the formed constituent material of the second layer ILD5b is flattened, for example by CMP. Thus, the second layer ILD5b is formed. The subsequent steps are carried out in the same manner as the manufacturing method of semiconductor device DEV1, thereby forming the structure of semiconductor device DEV2 shown in Figure 17.

[0083] As shown in Figure 17, in semiconductor device DEV2, the composite capacitance CC further includes capacitance element C5 in addition to capacitance elements C1, C2, C3, and C4. Capacitor element C5 is connected in parallel with capacitance elements C1, C2, C3, and C4. Capacitor element C5 has wiring WL5a, wiring WL7, and the first layer ILD5a.

[0084] With the formation of the capacitive element C5, the area of ​​the composite capacitance CC in a plan view does not increase compared to the case where the capacitive element C5 is not formed. Therefore, according to the semiconductor device DEV2, the capacitance of the composite capacitance CC per unit area can be further increased.

[0085] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0086] ACB Analog circuit block, ACB1, ACB2 Analog circuit block, BSC Bootstrap capacitor, BT Boot terminal, C1, C2, C3, C4, C5 Capacitor elements, CLB1, CLB2, CLB3, CLB4 Conductive laminate, CN1, CN2, CN3, CN4, CN5 Conductor, C Capacitor, DEV1, DEV2 Semiconductor equipment, DI Diode, EFP Element formation area, F1 Top surface, F2 Bottom surface, GND Ground terminal, IDL1, IDL2 Impurity diffusion layer, IF1, IF2, IF3 Insulating film, ILD1, ILD2, ILD3, ILD4, ILD5 Interlayer insulating film, ILD5a First layer, ILD5b Second layer, L Inductor, LCB Logic circuit block, MOS Planar type, PD, PD1, PD2 Pads, PRD1, PRD2 Pre-driver, PER Outer perimeter, PG1aa, PG1ab Plugs: PG1ba, PG1bb; PG2aa, PG2ab, PG2ac, PG2ad, PG2ae; PG2ba, PG2bb, PG2bc, PG2bd, PG2be; PG3a, PG3b, PG3c; PG4a, PG4b, PG4c, PG4d; PG5a, PG5b, PG5c; PG6a, PG6b, PG6c, PG6d, PG6e; PG7a; PG7b; S1 Preparation process; S2 Ion implantation process; S3 First insulating film formation process; S4 First wiring formation process; S5 Second insulating film formation process; S6 Second wiring formation process; S7 Interlayer insulating film formation process; S8 Plug formation process; S9 Third wiring formation process; S10 Piece formation process; SR Seal ring; SUB Semiconductor substrate; SW Switch terminal; Tr1, Tr2 Transistor; VIN Input terminal; VOUT Output terminals, WL1 wiring, WL2 wiring, WL3aa, WL3ab, WL3ac wiring, WL3ba, WL3bb, WL3bc wiring, WL4aa, WL4ab, WL4ac, WL4ad, WL4ae wiring, WL4ba, WL4bb, WL4bc, WL4bd, WL4be wiring, WL5a, WL5b, WL5c wiring, WL6a, WL6b, WL6c wiring, WL7 wiring, WL3baa, WL3bab protrusions.

Claims

1. A semiconductor substrate having an element formation area, It comprises a composite capacitor formed so as to surround the element forming portion in a plan view, The composite capacitance is a semiconductor device having a plurality of capacitive elements electrically connected in parallel.

2. The semiconductor substrate has an upper surface, The semiconductor device according to claim 1, wherein the first capacitance element among the plurality of capacitance elements comprises a first impurity diffusion layer formed in the semiconductor substrate and disposed on the upper surface, a first insulating film formed on the upper surface so as to overlap with the first impurity diffusion layer in a plan view, and a first wiring formed on the first insulating film.

3. The semiconductor device according to claim 2, wherein the first wiring is formed of polycrystalline silicon.

4. The semiconductor substrate has an upper surface, The semiconductor device according to claim 1, wherein the second capacitance element among the plurality of capacitance elements has a first wiring formed above the upper surface, a second insulating film formed on the first wiring, and a second wiring formed on the second insulating film.

5. The first wiring is formed of polycrystalline silicon, The second insulating film comprises a first silicon oxide film, a silicon nitride film formed on the first silicon oxide film, and a second silicon oxide film formed on the silicon nitride film. The semiconductor device according to claim 4, wherein the second wiring is formed of metal silicide.

6. The semiconductor substrate has an upper surface, The semiconductor substrate has an outer peripheral portion that surrounds the element formation portion in a plan view, The third capacitance element among the plurality of capacitance elements comprises a third insulating film formed above the upper surface, a first conductive laminate formed within the third insulating film, and a second conductive laminate formed within the third insulating film so as to face the first conductive laminate with a portion of the third insulating film interposed in the direction from the inner edge of the outer periphery toward the outer edge of the outer periphery, The first conductive laminate has a plurality of third wirings and a plurality of first plugs, The plurality of third wires are superimposed such that one of the plurality of first plugs is located between two adjacent third wires. The second conductive laminate has a plurality of fourth wirings and a plurality of second plugs, The semiconductor device according to claim 1, wherein the plurality of fourth wires are superimposed such that one of the plurality of second plugs is located between two adjacent fourth wires.

7. The semiconductor substrate has an upper surface, The fourth capacitance element among the plurality of capacitance elements has a first impurity diffusion layer formed in the semiconductor substrate and positioned on the upper surface, and a second impurity diffusion layer formed in the semiconductor substrate and positioned below the first impurity diffusion layer so as to be in contact with the first impurity diffusion layer. The semiconductor device according to claim 1, wherein the conductivity type of the first impurity diffusion layer is the opposite of the conductivity type of the second impurity diffusion layer.

8. The semiconductor substrate has an upper surface, The semiconductor device according to claim 1, wherein the fifth capacitance element among the plurality of capacitance elements has a fifth wiring formed above the upper surface, a fourth insulating film formed on the fifth wiring, and a sixth wiring formed on the fourth insulating film.

9. The fifth wiring is made of aluminum or an aluminum alloy. The semiconductor device according to claim 8, wherein the sixth wiring is made of titanium nitride.

10. The system further comprises a third conductive laminate electrically connected to the plurality of capacitive elements, The semiconductor substrate has an upper surface, The third conductive laminate is formed on the upper surface and has a plurality of seventh wirings and a plurality of third plugs, The semiconductor device according to claim 1, wherein the plurality of seventh wirings are stacked such that one of the plurality of third plugs is positioned between two adjacent seventh wirings and between the bottommost seventh wiring and the top surface.

11. The semiconductor device according to claim 10, wherein the third conductive laminate surrounds the composite capacitance in a plan view.

12. The system further comprises a fourth conductive laminate electrically connected to the plurality of capacitive elements, The fourth conductive laminate is formed on the upper surface and has a plurality of eighth wirings and a plurality of fourth plugs, The plurality of eighth wires are stacked such that one of the plurality of fourth plugs is positioned between two adjacent eighth wires and between the bottommost eighth wire and the top surface. The semiconductor device according to claim 11, wherein the fourth conductive laminate is surrounded by the composite capacitance and surrounds the element forming portion in a plan view.

13. It also includes a sealing ring, The semiconductor device according to claim 1, wherein the sealing ring surrounds the composite capacitance in a plan view.

14. It also features multiple bonding pads, The plurality of bonding pads are arranged in a row along the outer edge of the element forming portion in a plan view. The plurality of bonding pads include a first bonding pad and a second bonding pad that is spaced apart from the first bonding pad and arranged next to the first bonding pad. The semiconductor device according to claim 1, wherein a portion of the composite capacitance is located between the first bonding pad and the second bonding pad in a plan view.

15. It also features multiple bonding pads, The plurality of bonding pads are arranged in a row along the outer edge of the element forming portion in a plan view. The semiconductor device according to claim 1, wherein a portion of the composite capacitance is formed below the plurality of bonding pads so as to overlap with the plurality of bonding pads in a plan view.

16. The element forming section has an analog circuit block located on the outer periphery of the element forming section in a plan view, and on which an analog circuit is formed. The semiconductor device according to claim 1, wherein the composite capacitance is electrically connected to the analog circuit block.

17. The semiconductor device according to claim 16, wherein the composite capacitance is divided at at least one location facing the analog circuit block in a plan view.

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