Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device that is less susceptible to destruction even when avalanche yielding occurs, and a method for manufacturing the same. [Solution] The semiconductor device comprises a first electrode, a semiconductor portion disposed on the first electrode, a second electrode disposed on the cell region of the semiconductor portion, a third electrode disposed on the terminal region of the semiconductor portion, a fourth electrode disposed between the first electrode and the third electrode within the semiconductor portion and connected to the third electrode, and a first insulating film disposed between the semiconductor portion and the fourth electrode.

Description

[Technical Field]

[0001] The embodiments relate to semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] In vertical power control semiconductor devices, the semiconductor portion is being made thinner to reduce on-resistance and switching losses. However, thinning the semiconductor portion presents a problem: the semiconductor device is more susceptible to damage when avalanche breakdown occurs. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 5969927 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The objective of this embodiment is to provide a semiconductor device that is less susceptible to destruction even when avalanche yielding occurs, and a method for manufacturing the same. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a semiconductor portion disposed on the first electrode, a second electrode disposed on the cell region of the semiconductor portion, a third electrode disposed on the terminal region of the semiconductor portion, a fourth electrode disposed between the first electrode and the third electrode within the semiconductor portion and connected to the third electrode, and a first insulating film disposed between the semiconductor portion and the fourth electrode.

[0006] A method for manufacturing a semiconductor device according to an embodiment includes the steps of: forming a second semiconductor layer of a second conductivity type within the terminal region of a first semiconductor layer by ion implanting impurities into a first semiconductor layer of a first conductivity type; forming a third semiconductor layer on the second semiconductor layer within the first semiconductor layer by ion implanting impurities into the first semiconductor layer, the third semiconductor layer being of a second conductivity type and having a carrier concentration higher than that of the second semiconductor layer, exposed on the upper surface of the first semiconductor layer; forming a first trench penetrating the third semiconductor layer and reaching the second semiconductor layer; forming a first insulating film on the inner surface of the first trench; forming a fourth electrode in contact with the first insulating film within the first trench; and forming a first electrode connected to the first semiconductor layer, a second electrode arranged on the cell region of the first semiconductor layer, and a third electrode connected to the fourth electrode. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a top view showing a semiconductor device according to the first embodiment. [Figure 2] Figure 2(a) is a cross-sectional view taken along the line A-A' shown in Figure 1, and Figure 2(b) is a cross-sectional view taken along the line B-B' shown in Figure 1. [Figure 3] Figure 3(a) is a partially enlarged cross-sectional view showing region C in Figure 2, and Figure 3(b) is a partially enlarged cross-sectional view showing region D in Figure 2. [Figure 4] Figures 4(a) to 4(d) are cross-sectional views showing the manufacturing method of a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a cross-sectional view showing the operation of the semiconductor device according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 7] Figure 7 is a cross-sectional view showing a semiconductor device according to the third embodiment. [Figure 8] Figure 8 is a cross-sectional view showing a semiconductor device according to a reference example. [Figure 9] Figure 9 is a cross-sectional view showing a semiconductor device according to a comparative example. [Figure 10] Figs. 10(a) to (d) are cross-sectional process diagrams showing a method for manufacturing a semiconductor device according to a comparative example. [Figure 11] Fig. 11 is a graph showing the I-V characteristics of the semiconductor device in a test example, with the voltage applied to the source electrode and drain electrode of the semiconductor device on the horizontal axis and the current flowing through the source electrode and drain electrode of the semiconductor device on the vertical axis.

Embodiments for Carrying Out the Invention

[0008] <First Embodiment> Fig. 1 is a top view showing the semiconductor device according to the present embodiment. Fig. 2(a) is a cross-sectional view taken along line A-A' shown in Fig. 1, and Fig. 2(b) is a cross-sectional view taken along line B-B' shown in Fig. 1. Fig. 3(a) is a partially enlarged cross-sectional view showing region C of Fig. 2(a), and Fig. 3(b) is a partially enlarged cross-sectional view showing region D of Fig. 2(b).

[0009] As shown in Fig. 1, Fig. 2(a) and (b), and Fig. 3(a) and (b), in the semiconductor device 1 according to the present embodiment, a semiconductor portion 50, a drain electrode 11, a source electrode 12, a field plate electrode (hereinafter also referred to as "FP electrode") 13, a trench electrode 14, a gate electrode 15, a gate pad 16, a termination electrode 17, a trench insulating film 21, a gate insulating film 22, a termination insulating film 23, and a cell insulating film 24 are provided.

[0010] In the present embodiment, an example in which the semiconductor device 1 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) will be described, but it is not limited thereto. As described in the third embodiment, the semiconductor device may be an IGBT (insulated gate bipolar transistor), or other types of semiconductor devices.

[0011] The semiconductor portion 50 is a chip made of a semiconductor material, such as single-crystal silicon (Si), and its conductivity type is set to n-type or p-type by introducing impurities into each part. The thickness of the semiconductor portion 50 is, for example, 50 μm or more and 150 μm or less. The semiconductor portion 50 has a cell region Rc through which current flows in the vertical direction and a termination region Rt surrounding the cell region Rc.

[0012] The drain electrode 11 is positioned over the entire lower surface of the semiconductor portion 50 and is in contact with the semiconductor portion 50. The source electrode 12 and gate pad 16 are positioned on the upper surface of the cell region Rc of the semiconductor portion 50.

[0013] The FP electrode 13 is positioned on the termination region Rt of the semiconductor portion 50. The FP electrode 13 includes, for example, three FP electrodes 13a, 13b, and 13c. Viewed from above, the FP electrode 13a is an annular shape surrounding the source electrode 12, the FP electrode 13b is an annular shape surrounding the FP electrode 13a, and the FP electrode 13c is an annular shape surrounding the FP electrode 13b. The FP electrode 13 is electrically floating. The number of FP electrodes 13 is not particularly limited.

[0014] The trench electrodes 14 are positioned between the drain electrode 11 and each FP electrode 13 within the semiconductor portion 50. Therefore, the trench electrodes 14 are located within the termination region Rt. The depth of the trench electrodes 14 is, for example, about 5 μm.

[0015] The trench electrode 14 includes trench electrodes 14a, 14b, and 14c. Trench electrode 14a is located directly below FP electrode 13a and is connected to FP electrode 13a. Trench electrode 14b is located directly below FP electrode 13b and is connected to FP electrode 13b. Trench electrode 14c is located directly below FP electrode 13c and is connected to FP electrode 13c. In this specification, "connection" means electrical connection.

[0016] Viewed from above, each trench electrode 14 is annular in shape, surrounding the source electrode 12. In this embodiment, two trench electrodes 14 are connected to one FP electrode 13. However, this is not limited to this configuration; one trench electrode 14 may be connected to one FP electrode 13, or three or more trench electrodes 14 may be connected.

[0017] The trench insulating film 21 is placed between the semiconductor portion 50 and each trench electrode 14. As a result, the trench electrodes 14 are insulated from the semiconductor portion 50 by the trench insulating film 21. The trench electrodes 14 are connected only to the FP electrodes 13. Therefore, the trench electrodes 14 are also electrically floating.

[0018] The trench insulating film 21 includes trench insulating films 21a, 21b, and 21c. Trench insulating film 21a is disposed between the semiconductor portion 50 and the trench electrode 14a, trench insulating film 21b is disposed between the semiconductor portion 50 and the trench electrode 14b, and trench insulating film 21c is disposed between the semiconductor portion 50 and the trench electrode 14c.

[0019] The gate electrode 15 is positioned between the drain electrode 11 and the source electrode 12 within the semiconductor portion 50. Therefore, the gate electrode 15 is located in the cell region Rc. Multiple gate electrodes 15 are provided, for example, extending in the same direction. The gate electrodes 15 are connected to a gate pad 16. As a result, a gate potential is applied to each gate electrode 15 via the gate pad 16.

[0020] The gate insulating film 22 is positioned between the semiconductor portion 50 and each gate electrode 15. As a result, each gate electrode 15 is insulated from the semiconductor portion 50 by the gate insulating film 22.

[0021] The termination electrode 17 is located on the outermost edge of the semiconductor portion 50. Therefore, the termination electrode 17 is located within the termination region Rt. The termination electrode 17 is electrically floating.

[0022] The terminating insulating film 23 is partially positioned in the terminating region Rt between the semiconductor portion 50 and the FP electrode 13, and between the semiconductor portion 50 and the terminating electrode 17. This limits the portion of the semiconductor portion 50 to which the FP electrode 13 and the terminating electrode 17 are connected.

[0023] The cell insulating film 24 is positioned in the cell region Rc between the gate electrode 15 and the source electrode 12, and between the gate insulating film 22 and the source electrode 12. As a result, the gate electrode 15 is insulated from the source electrode 12 by the cell insulating film 24.

[0024] In the semiconductor portion 50, the conductivity type is n + Drain layer 51 of type n - Type 1 drift layer 52, p-type guard ring layer 53, p-type connection layer 54, n + Type terminating layer 55, p-type base layer 56, n + A source layer 57 of a specific type is provided. The guard ring layer 53 includes guard ring layers 53a, 53b, and 53c. The connection layer 54 includes connection layers 54a, 54b, and 54c.

[0025] Note that "n + "Type" is "n - This indicates a higher carrier concentration than the "p-type" type. The same applies to the p-type. "Carrier concentration" refers to the effective impurity concentration that contributes to the conductivity of a semiconductor. When both donor and acceptor impurities are present in a given region, it refers to the net concentration after deducting the canceling-out portion.

[0026] The drain layer 51 constitutes the entire lower surface of the semiconductor portion 50, is in contact with the drain electrode 11, and is connected to the drain electrode 11. The drift layer 52 is arranged across the entire surface of the drain layer 51 and is in contact with the drain layer 51. The drain layer 51 and the drift layer 52 constitute the first semiconductor layer.

[0027] The termination region Rt of the semiconductor portion 50 will be described. As shown in Figures 2(b) and 3(b), the guard ring layer 53 is located within the drift layer 52 in the termination region Rt. Viewed from above, the guard ring layer 53a is an annular shape surrounding the source electrode 12. The connecting layer 54a is located on the guard ring layer 53a and is in contact with the guard ring layer 53a. Viewed from above, the connecting layer 54a is an annular shape surrounding the source electrode 12.

[0028] Viewed from above, the guard ring layer 53b is an annular shape surrounding the guard ring layer 53a. The connecting layer 54b is located on the guard ring layer 53b and is in contact with it. Viewed from above, the guard ring layer 53c is an annular shape surrounding the guard ring layer 53b. The connecting layer 54c is located on the guard ring layer 53c and is in contact with it. The upper surface of the connecting layer 54 forms part of the upper surface of the semiconductor portion 50.

[0029] The connecting layer 54 is in contact with the FP electrode 13 in the region on the upper surface of the semiconductor portion 50 that is not covered by the terminating insulating film 23. Therefore, the guard ring layer 53 is connected to the FP electrode 13 via the connecting layer 54. The carrier concentration of the connecting layer 54 is higher than that of the guard ring layer 53.

[0030] The number of guard ring layers 53 and the number of connection layers 54 are the same as the number of FP electrodes 13. In this embodiment, for example, there are three of each guard ring layer 53, connection layer 54, and FP electrode 13. Also, in the horizontal direction, the distance L1 between adjacent connection layers 54 is longer than the distance L2 between adjacent guard ring layers 53. That is, L1 > L2.

[0031] The termination layer 55 is located on the uppermost layer of the outermost part of the semiconductor portion 50. The termination layer 55 is connected to the drift layer 52 and the termination electrode 17.

[0032] In the terminal region Rt, the lower part of the trench insulating film 21 is covered by the guard ring layer 53, and the upper part of the trench insulating film 21 is covered by the connecting layer 54. As shown in Figure 3(b), in the vertical direction, the distance D1 between the lower end of the trench insulating film 21 and the FP electrode 13 is longer than the distance D2 between the center of the guard ring layer 53 and the FP electrode 13. That is, D1 > D2.

[0033] The cell region Rc of the semiconductor part 50 will be described. As shown in Figures 2(a) and 3(a), the base layer 56 is located on the drift layer 52 in the cell region Rc. As will be described later, the base layer 56 is formed in the same process as the connecting layer 54. Therefore, the carrier concentration distribution of the base layer 56 in the vertical direction is approximately equal to that of the connecting layer 54, and the carrier concentration of the base layer 56 is higher than that of the guard ring layer 53.

[0034] The source layer 57 is positioned on a portion of the base layer 56 and is separated from the drift layer 52 via the base layer 56. The base layer 56 and the source layer 57 constitute a portion of the upper surface of the semiconductor portion 50 in the cell region Rc and are connected to the source electrode 12 between the cell insulating film 24. In the cell region Rc, the lower part of the gate insulating film 22 is covered by the drift layer 52, the central part in the vertical direction is in contact with the base layer 56, and the upper part is in contact with the source layer 57.

[0035] Next, a method for manufacturing the semiconductor device 1 according to this embodiment will be described. Figures 4(a) to 4(d) are cross-sectional views showing the manufacturing process of a semiconductor device according to this embodiment. Note that Figures 4(a) to 4(d) show only the terminal region Rt.

[0036] First, as shown in Figures 2(a) and (b), and Figure 4(a), n + n -Prepare a laminate 59 in which a drift layer 52 of a 12 cm -2 or more and less than 1×10 13 cm -2 is formed. As a result, a guard ring layer 53 is formed in the terminal region Rt of the drift layer 52. The guard ring layer 53 is not exposed on the upper surface of the drift layer 52.

[0037] Next, as shown in FIGS. 2(a) and (b) and FIG. 4(b), an impurity serving as an acceptor is ion-implanted into the drift layer 52. The acceleration voltage of this ion implantation is lower than the acceleration voltage of the ion implantation for forming the guard ring layer 53. Also, the dose amount of this ion implantation is made larger than the dose amount of the ion implantation for forming the guard ring layer 53, for example, higher than 1×10 12 cm -2 and less than 1×10 13 cm -2 or less.

[0038] As a result, in the terminal region Rt, a p-type connection layer 54 is formed on the guard ring layer 53 in the drift layer 52. The connection layer 54 is in contact with the guard ring layer 53 and is exposed on the upper surface of the drift layer 52. Also, in the cell region Rc, a p-type base layer 56 is formed on the drift layer 52. The carrier concentrations of the connection layer 54 and the base layer 56 are higher than the carrier concentration of the guard ring layer 53. In the process of forming the guard ring layer 53, the connection layer 54, and the base layer 56, an impurity diffusion process is not performed.

[0039] Next, as shown in FIGS. 2(a) and (b) and FIG. 4(c), for example, by a lithography method and a RIE (Reactive Ion Etching) method, an FP trench 61 is formed in the terminal region Rt and a gate trench 62 is formed in the cell region Rc. The FP trench 61 penetrates the connection layer 54 and reaches the guard ring layer 53. The gate trench 62 penetrates the base layer 56 and reaches the drift layer 52.

[0040] Next, for example, a trench insulating film 21 is formed on the inner surface of the FP trench 61 by thermal oxidation, and a gate insulating film 22 is formed on the inner surface of the gate trench 62. Then, conductive material is embedded in the FP trench 61 and the gate trench 62. For example, silicon containing impurities is deposited by CVD (Chemical Vapor Deposition), and then a planarization treatment such as CMP (Chemical Mechanical Polishing) is performed to remove the silicon deposited on the upper surface of the laminate 59. As a result, a trench electrode 14 in contact with the trench insulating film 21 is formed in the FP trench 61, and a gate electrode 15 in contact with the gate insulating film 22 is formed in the gate trench 62.

[0041] Next, by ion implanting the donor impurities, n in the terminal region Rt + A terminal layer 55 of type 55 is formed, and in the cell region Rc, a portion of the base layer 56 is n + A molded source layer 57 is formed. In this way, the semiconductor portion 50 is formed.

[0042] Next, as shown in Figures 2(a) and (b) and Figure 4(d), a termination insulating film 23 is formed on the termination region Rt of the semiconductor portion 50 where the drift layer 52 is exposed. In addition, a cell insulating film 24 is formed on the cell region Rc of the semiconductor portion 50 where the gate electrode 15 and the gate insulating film 22 are exposed.

[0043] Next, as shown in Figures 1, 2(a) and (b), and 4(d), a drain electrode 11 is formed over the entire surface of the lower surface of the semiconductor portion 50. A source electrode 12 and a gate pad 16 are formed on the upper surface of the cell region Rc of the semiconductor portion 50, and an FP electrode 13 and a termination electrode 17 are formed on the upper surface of the termination region Rt. The drain electrode 11 is connected to the drain layer 51, the source electrode 12 is connected to the base layer 56 and the source layer 57, the gate pad 16 is connected to the gate electrode 15, the FP electrode 13 is connected to the connection layer 54, and the termination electrode 17 is connected to the termination layer 55. In this way, the semiconductor device 1 is manufactured.

[0044] The order of the above steps may be changed. For example, the FP trench 61 and gate trench 62, the trench insulating film 21 and gate insulating film 22, the trench electrode 14 and gate electrode 15 may be formed before forming the guard ring layer 53, or after forming the guard ring layer 53 but before forming the connection layer 54 and base layer 56, or after forming the termination layer 55 and source layer 57.

[0045] Next, the operation of the semiconductor device 1 according to this embodiment will be described. Figure 5 is a cross-sectional view showing the operation of the semiconductor device according to this embodiment. As shown in Figure 2, when a positive potential is applied to the drain electrode 11 and a negative potential to the source electrode 12, a depletion layer expands starting from the interface between the drift layer 52 and the base layer 56. In this state, when a potential above a threshold is applied to the gate electrode 15 via the gate pad 16, an inversion layer is formed in the portion of the base layer 56 that is in contact with the gate insulating film 22. As a result, current flows from the drain electrode 11 to the source electrode 12 in the cell region Rc. This turns on the semiconductor device 1. At this time, the thinner the semiconductor portion 50, the lower the on-resistance.

[0046] When a potential below the threshold is applied to the gate electrode 15 via the gate pad 16, the inversion layer disappears, and the semiconductor device 1 turns off. In the off state, a strong electric field is applied to the depletion layer, which may cause avalanche breakdown. The location where avalanche breakdown occurs can be controlled to some extent by the design of the semiconductor device 1; for example, it can be controlled to occur at the lower end of the trench insulating film 21.

[0047] As shown in Figure 5, when avalanche breakdown occurs at a position 70 in a guard ring layer 53 that is in contact with the lower end of the trench insulating film 21, a hole-electron pair is generated at position 70, and an electron current 71 flows from position 70 toward the drain electrode 11. As the outer edge 80 of the depletion layer curves toward the cell region Rc as it approaches the drain electrode 11, the electron current 71 is tilted toward the end of the semiconductor device 1 as it approaches the drain electrode 11.

[0048] Meanwhile, a hole current 72 flows from position 70 toward the source electrode 12. The hole current 72 attempts to flow along the upper surface of the drift layer 52, taking the shortest route to the source electrode 12, but is blocked by the trench insulating film 21 extending downward from the upper surface of the semiconductor portion 50. Therefore, it flows through the connecting layer 54 and the guard ring layer 53, bypassing the trench insulating film 21. As a result, the path length of the hole current 72 increases, and the resistance increases.

[0049] Next, the effects of this embodiment will be described. As described above, in this embodiment, when avalanche breakdown occurs, a trench insulating film 21 is interposed in the path of the hole current 72 to increase its resistance. By applying a predetermined resistance to the hole current 72, the generation of negative resistance can be suppressed even when avalanche breakdown occurs. As a result, the concentration of current in the part where avalanche breakdown occurs can be suppressed, and the destruction of the semiconductor device 1 can be suppressed. Thus, according to this embodiment, a semiconductor device that is less likely to be destroyed even when avalanche breakdown occurs can be realized.

[0050] Furthermore, in this embodiment, the carrier concentration of the guard ring layer 53 is lower than that of the connecting layer 54. As a result, the resistance of the hole current 72 increases when passing through the guard ring layer 53.

[0051] Furthermore, in this embodiment, the distance D1 between the lower end of the trench insulating film 21 and the FP electrode 13 in the vertical direction is made longer than the distance D2 between the center of the guard ring layer 53 and the FP electrode 13. The center of the guard ring layer 53 in the vertical direction is the part of the guard ring layer 53 that is least likely to be depleted. Therefore, by making the distance D1 longer than the distance D2, the trench insulating film 21 penetrates the undepleted portion of the guard ring layer 53 and protrudes downward. As a result, the undepleted portion of the guard ring layer 53 is divided by the trench insulating film 21, and the resistance of the hole current 72 increases further.

[0052] Furthermore, according to this embodiment, in the process shown in Figure 4(a), the guard ring layer 53 is formed inside the drift layer 52 by ion implanting impurities using a high acceleration voltage. Then, in the process shown in Figure 4(b), the connecting layer 54 is formed on the guard ring layer 53, so that when the FP electrode 13 is formed in the process shown in Figure 4(c), the guard ring layer 53 is connected to the FP electrode 13. In this way, by forming the guard ring layer 53 and the connecting layer 54 in two separate steps, it is not necessary to perform high-temperature, long-duration heat treatment to diffuse impurities. This reduces the manufacturing cost of the semiconductor device 1.

[0053] Furthermore, according to this embodiment, the connecting layer 54 is formed in the process of forming the base layer 56. Also, the FP trench 61 is formed in the process of forming the gate trench 62, the trench insulating film 21 is formed in the process of forming the gate insulating film 22, and the trench electrode 14 is formed in the process of forming the gate electrode 15. Therefore, there is no need to provide separate processes for forming the connecting layer 54, the FP trench 61, the trench insulating film 21, and the trench electrode 14. This also reduces the manufacturing cost of the semiconductor device 1.

[0054] <Second Embodiment> Figure 6 is a cross-sectional view showing a semiconductor device according to this embodiment. As shown in Figure 6, the semiconductor device 2 according to this embodiment differs from the semiconductor device 1 according to the first embodiment in that trench electrodes 14 and trench insulating film 21 are not placed directly beneath some of the FP electrodes 13.

[0055] More specifically, two trench electrodes 14a and a trench insulating film 21 are located directly below the FP electrode 13a, which is positioned on the inner circumference of the semiconductor device 2. Two trench electrodes 14b and a trench insulating film 21 are located directly below the FP electrode 13b, which is positioned around the FP electrode 13a. However, no trench electrodes or trench insulating films are located directly below the FP electrode 13c, which is positioned around the FP electrode 13b. However, a guard ring layer 53 and a connecting layer 54 are located directly below the FP electrode 13c.

[0056] Since hole current 72 does not flow beyond the terminal side of the position 70 where avalanche breakdown occurs, the absence of trench electrodes 14 and trench insulating film 21 beyond the terminal side of position 70 does not affect the resistance of the hole current 72. For this reason, if the position 70 where avalanche breakdown occurs can be controlled with high precision, the trench electrodes 14 and trench insulating film 21 beyond that point can be omitted. The configuration, manufacturing method, operation, and effects of this embodiment other than those described above are the same as those of the first embodiment.

[0057] <Third Embodiment> Figure 7 is a cross-sectional view showing a semiconductor device according to this embodiment. As shown in Figure 7, the semiconductor device 3 according to this embodiment is an IGBT. In the semiconductor device 3, a buffer layer 60 with conductivity type n is provided instead of the drain layer 51 of the semiconductor device 1. In addition, a collector layer 58 is provided at the bottom of the semiconductor portion 50. The conductivity type of the collector layer 58 is p +This is the type. The collector layer 58 is positioned between the drain electrode 11 and the buffer layer 60, and is in contact with both the drain electrode 11 and the buffer layer 60.

[0058] In semiconductor device 3, the thinner the semiconductor portion 50, the less carriers enter the semiconductor portion 50 when it is ON, and therefore the smaller the switching loss when it is turned OFF. The configuration, manufacturing method, operation, and effects of this embodiment other than those described above are the same as those of the first embodiment.

[0059] <Reference example> Figure 8 is a cross-sectional view showing a semiconductor device according to this reference example. As shown in Figure 8, the semiconductor device 101 according to this reference example differs from the semiconductor device 1 according to the first embodiment in that trench electrodes 14 and trench insulating films 21 are not placed directly beneath all FP electrodes 13. However, guard ring layers 53 and connecting layers 54 are placed in the area directly beneath each FP electrode 13. Furthermore, in the horizontal direction, the distance L1 between adjacent connecting layers 54 is longer than the distance L2 between adjacent guard ring layers 53. The configuration and manufacturing method in this reference example other than those described above are the same as in the first embodiment.

[0060] <Comparative Example> Figure 9 is a cross-sectional view showing a semiconductor device according to this comparative example. As shown in Figure 9, the semiconductor device 201 according to this comparative example differs from the semiconductor device 1 according to the first embodiment in that the guard ring layer 253 reaches the upper surface of the semiconductor portion 250 and is in contact with the FP electrode 213, and that the trench electrode 14 and trench insulating film 21 are not located directly beneath the FP electrode 213.

[0061] Figures 10(a) to 10(d) are cross-sectional view images showing the process for manufacturing a semiconductor device according to this comparative example. First, as shown in Figures 9 and 10(a), n + n -A laminate 259 is prepared by stacking drift layers 252 of a specific type. Then, impurities that will act as acceptors are ion-implanted. Next, a heat treatment is performed at a temperature of 1100°C or higher for a time of 60 minutes or more to diffuse the ion-implanted impurities to a thickness of approximately 8 μm. This forms a guard ring layer 253. The guard ring layer 253 reaches the upper surface of the semiconductor portion 250.

[0062] Next, as shown in Figures 9 and 10(b), acceptor impurities are ion-implanted into the drift layer 252. This forms a p-type base layer 256 on the drift layer 252 in the cell region Rc. Note that the connecting layer 54 is not formed at this time.

[0063] Next, as shown in Figures 9 and 10(c), a gate trench 262 is formed in the cell region Rc. The gate trench 262 penetrates the base layer 256 and reaches the drift layer 252. At this time, no FP trench 61 is formed in the terminal region Rt. Next, a gate insulating film 222 is formed on the inner surface of the gate trench 262. Next, a gate electrode 215 is formed inside the gate trench 262.

[0064] Next, by ion implanting the donor impurities, n in the terminal region Rt + A terminal layer 255 of type 255 is formed, and in the cell region Rc, a portion of the base layer 256 is n + It forms a source layer of the type (not shown).

[0065] The subsequent steps are the same as in the first embodiment. That is, as shown in Figures 9 and 10(d), the termination insulating film 223, cell insulating film (not shown), drain electrode 211, source electrode 212, FP electrode 213, gate pad 216, and termination electrode 217 are formed. In this way, the semiconductor device 201 is manufactured.

[0066] As shown in Figure 9, in the semiconductor device 201 according to this comparative example, when avalanche breakdown occurs at position 270, an electron current 271 toward the drain electrode 211 and a hole current 272 toward the source electrode 212 are generated. The hole current 272 flows toward the source electrode 212 along the shortest path along the upper surface of the semiconductor portion 250. As a result, sufficient resistance cannot be provided to the hole current 272, and negative resistance is likely to occur in the hole current 272.

[0067] If negative resistance occurs, current can concentrate in that path, potentially destroying the semiconductor device 201. Furthermore, in this comparative example, high-temperature, long-duration heat treatment is required to form the guard ring layer 253. This increases the manufacturing cost of the semiconductor device.

[0068] <Example Test> In this test example, simulations were performed assuming the semiconductor device 1 according to the first embodiment described above and the semiconductor device 201 according to the comparative example, and their behavior when avalanche breakdown occurs was compared. Figure 11 is a graph showing the IV characteristics of the semiconductor device in this test example, with the voltage applied to the source and drain electrodes of the semiconductor device on the horizontal axis and the current flowing through the source and drain electrodes of the semiconductor device on the vertical axis.

[0069] As shown in Figure 11, in the comparative example semiconductor device 201, after avalanche breakdown occurred at voltage V1, the slope of the graph became negative, indicating the occurrence of negative resistance. In contrast, in the semiconductor device 1 according to the first embodiment, even after avalanche breakdown occurred at voltage V1, the slope of the graph remained positive, and the occurrence of negative resistance was suppressed.

[0070] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0071] The present invention includes the following embodiments.

[0072] (Note 1) First electrode and, A semiconductor portion disposed on the first electrode, A second electrode is disposed on the cell region of the semiconductor portion, A third electrode is disposed on the terminal region of the semiconductor portion, A fourth electrode is disposed between the first electrode and the third electrode within the semiconductor portion and is connected to the third electrode, A first insulating film disposed between the semiconductor portion and the fourth electrode, A semiconductor device equipped with the following features.

[0073] (Note 2) The semiconductor device described in Appendix 1, wherein, when viewed from above, the fourth electrode is an annular ring surrounding the second electrode.

[0074] (Note 3) The semiconductor device according to Appendix 1 or 2, wherein, when viewed from above, the third electrode is an annular ring surrounding the second electrode.

[0075] (Note 4) The aforementioned semiconductor portion is A first semiconductor layer of a first conductivity type connected to the first electrode, A second semiconductor layer of second conductivity type covering the lower part of the first insulating film, A third semiconductor layer of second conductivity type in contact with the second semiconductor layer and the third electrode, A semiconductor device having any one of the appendices 1 to 3.

[0076] (Note 5) The semiconductor device described in Appendix 4, wherein the carrier concentration of the third semiconductor layer is higher than the carrier concentration of the second semiconductor layer.

[0077] (Note 6) The semiconductor device according to Appendix 4 or 5, wherein, in the vertical direction, the distance between the lower end of the first insulating film and the upper end of the semiconductor portion is longer than the distance between the center of the second semiconductor layer and the upper end of the semiconductor portion.

[0078] (Note 7) A fifth electrode is disposed between the first electrode and the second electrode within the semiconductor portion, A second insulating film is disposed between the semiconductor portion and the fifth electrode, Furthermore, The aforementioned semiconductor portion is A fourth semiconductor layer is disposed on the first semiconductor layer, is in contact with the second insulating film, and has a second conductivity type. A fifth semiconductor layer, which is disposed on the fourth semiconductor layer, connected to the second electrode, and having a first conductivity type, It further possesses, The semiconductor device according to any one of the appendices 4 to 6, wherein the carrier concentration of the fourth semiconductor layer is higher than the carrier concentration of the second semiconductor layer.

[0079] (Note 8) The semiconductor device according to any one of appendices 4 to 7, wherein the semiconductor portion is disposed between the first electrode and the first semiconductor layer and further comprises a sixth semiconductor layer of second conductivity type.

[0080] (Note 9) Multiple third electrodes, second semiconductor layers, and third semiconductor layers are provided. A semiconductor device according to any one of appendices 4 to 8, wherein, when viewed from above, the plurality of second semiconductor layers and the plurality of third semiconductor layers are each annular in shape.

[0081] (Note 10) The semiconductor device according to Appendix 9, wherein the fourth electrode and the first insulating film are not disposed at a position in contact with the outermost of the plurality of second semiconductor layers.

[0082] (Note 11) A step of forming a second semiconductor layer of a second conductivity type within the terminal region of a first semiconductor layer by ion implanting impurities into a first semiconductor layer of a first conductivity type, A step of forming a third semiconductor layer on the second semiconductor layer within the first semiconductor layer by ion implanting impurities into the first semiconductor layer, the third semiconductor layer being exposed on the upper surface of the first semiconductor layer, having a second conductivity type, and having a carrier concentration higher than that of the second semiconductor layer, A step of forming a first trench that penetrates the third semiconductor layer and reaches the second semiconductor layer, The steps include forming a first insulating film on the inner surface of the first trench, A step of forming a fourth electrode in contact with the first insulating film within the first trench, A step of forming a first electrode connected to the first semiconductor layer, a second electrode disposed on the cell region of the first semiconductor layer, and a third electrode connected to the fourth electrode, A method for manufacturing a semiconductor device equipped with [the specified features].

[0083] (Note 12) In the process of forming the third semiconductor layer, a fourth semiconductor layer having a second conductivity type is also formed on the cell region of the first semiconductor layer. In the process of forming the first trench, a second trench is also formed that penetrates the fourth semiconductor layer and reaches the first semiconductor layer. In the step of forming the first insulating film, a second insulating film is also formed in the second trench. In the process of forming the fourth electrode, a fifth electrode in contact with the second insulating film is also formed in the second trench. The process further comprises a step of forming a fifth semiconductor layer which is disposed on a portion of the fourth semiconductor layer and has a first conductivity type, The method for manufacturing a semiconductor device as described in Appendix 11, wherein the second electrode is connected to the fifth semiconductor layer. [Explanation of Symbols]

[0084] 1, 2, 3 Semiconductor equipment 11 Drain electrode (first electrode) 12. Source electrode (second electrode) 13, 13a, 13b, 13c FP electrode (3rd electrode) 14, 14a, 14b, 14c Trench electrodes (fourth electrode) 15 Grid gate (5th electrode) 16 Gate Pads 17 Termination electrode 21, 21a, 21b, 21c Trench insulating film (first insulating film) 22 Gate insulating film (second insulating film) 23 Termination insulating film 24-cell insulating film 50 Semiconductor part 51 Drain layer 52 Drift Layers 53, 53a, 53b, 53c Guard ring layer (second semiconductor layer) 54, 54a, 54b, 54c Connecting layer (third semiconductor layer) 55 Termination layer 56 Base layer (fourth semiconductor layer) 57. Source layer (5th semiconductor layer) 58. Collector layer (6th semiconductor layer) 59 Laminate 60 buffer layers 61 FP Trench (Trench 1) 62 Gate Trench (Second Trench) 70 positions 71 Electron current 72 Hole current 80 Outer edge 101 Semiconductor Equipment 201 Semiconductor Equipment 211 Drain electrode 212 Source Electrodes 213 FP electrode 215 Grid control 216 Gate Pad 217 Termination electrode 222 Gate insulating film 223 Termination insulating film 250 Semiconductor part 251 Drain layer 252 drift layers 253 Guard Ring Layer 255 Termination layer 256 Base Layer 259 Laminate 262 Gate Trench 270 positions 271 Electron current 272 Hole current D1 Distance between the lower end of the trench insulating film 21 and the FP electrode 13 D2 Distance between the center of the guard ring layer 53 and the FP electrode 13 L1 Distance between adjacent connection layers 54 L2 Distance between adjacent guard ring layers 53 Rc cell area Rt termination region

Claims

1. First electrode and, A semiconductor portion disposed on the first electrode, A second electrode is disposed on the cell region of the semiconductor portion, A third electrode is disposed on the terminal region of the semiconductor portion, A fourth electrode is disposed between the first electrode and the third electrode within the semiconductor portion and connected to the third electrode, A first insulating film disposed between the semiconductor portion and the fourth electrode, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein, when viewed from above, the fourth electrode is an annular shape surrounding the second electrode.

3. The semiconductor device according to claim 1, wherein, when viewed from above, the third electrode is an annular shape surrounding the second electrode.

4. The aforementioned semiconductor portion is A first semiconductor layer of a first conductivity type connected to the first electrode, A second semiconductor layer of second conductivity type covering the lower part of the first insulating film, A third semiconductor layer of second conductivity type in contact with the second semiconductor layer and the third electrode, A semiconductor device according to any one of claims 1 to 3, having the following:

5. The semiconductor device according to claim 4, wherein the carrier concentration of the third semiconductor layer is higher than the carrier concentration of the second semiconductor layer.

6. The semiconductor device according to claim 4, wherein, in the vertical direction, the distance between the lower end of the first insulating film and the upper end of the semiconductor portion is longer than the distance between the center of the second semiconductor layer and the upper end of the semiconductor portion.

7. A fifth electrode is disposed between the first electrode and the second electrode within the semiconductor portion, A second insulating film is disposed between the semiconductor portion and the fifth electrode, Furthermore, The aforementioned semiconductor portion is A fourth semiconductor layer is disposed on the first semiconductor layer, is in contact with the second insulating film, and has a second conductivity type. A fifth semiconductor layer, which is disposed on the fourth semiconductor layer, connected to the second electrode, and having a first conductivity type, It further possesses, The semiconductor device according to claim 4, wherein the carrier concentration of the fourth semiconductor layer is higher than the carrier concentration of the second semiconductor layer.

8. The semiconductor device according to claim 4, wherein the semiconductor portion is disposed between the first electrode and the first semiconductor layer and further comprises a sixth semiconductor layer of second conductivity type.

9. Multiple third electrodes, second semiconductor layers, and third semiconductor layers are provided. The semiconductor device according to claim 4, wherein, when viewed from above, the plurality of second semiconductor layers and the plurality of third semiconductor layers are each annular.

10. The semiconductor device according to claim 9, wherein the fourth electrode and the first insulating film are not disposed at a position in contact with the outermost of the plurality of second semiconductor layers.

11. A step of forming a second semiconductor layer of a second conductivity type within the terminal region of a first semiconductor layer by ion implanting impurities into a first semiconductor layer of a first conductivity type, A step of forming a third semiconductor layer on the second semiconductor layer within the first semiconductor layer by ion implanting impurities into the first semiconductor layer, the third semiconductor layer being exposed on the upper surface of the first semiconductor layer, having a second conductivity type, and having a carrier concentration higher than that of the second semiconductor layer, A step of forming a first trench that penetrates the third semiconductor layer and reaches the second semiconductor layer, The steps include forming a first insulating film on the inner surface of the first trench, A step of forming a fourth electrode in contact with the first insulating film within the first trench, The process involves forming a first electrode connected to the first semiconductor layer, a second electrode disposed on the cell region of the first semiconductor layer, and a third electrode connected to the fourth electrode. A method for manufacturing a semiconductor device equipped with [the specified features].

12. In the process of forming the third semiconductor layer, a fourth semiconductor layer having a second conductivity type is also formed on the cell region of the first semiconductor layer. In the process of forming the first trench, a second trench is also formed that penetrates the fourth semiconductor layer and reaches the first semiconductor layer. In the step of forming the first insulating film, the second insulating film is also formed in the second trench. In the process of forming the fourth electrode, a fifth electrode in contact with the second insulating film is also formed in the second trench. The process further comprises the step of forming a fifth semiconductor layer which is disposed on a portion of the fourth semiconductor layer and has a first conductivity type, The method for manufacturing a semiconductor device according to claim 11, wherein the second electrode is connected to the fifth semiconductor layer.

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