Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device and a method for manufacturing the same that enable improved reliability. [Solution] The semiconductor device according to the embodiment includes a semiconductor layer and a protective film. The semiconductor layer has an upper surface, a lower surface, a first side surface, a second side surface, and a stepped surface. The lower surface is on the opposite side from the upper surface. The second side surface is located closer to the upper surface than the first side surface and has irregularities. The stepped surface connects the first side surface and the second side surface and faces upward. The protective film covers at least a portion of the upper surface, at least a portion of the second side surface, and at least a portion of the stepped surface.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] In a semiconductor device including a semiconductor device such as a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a protective film covering the surface of the semiconductor substrate may be provided. In such a semiconductor device, it is desired to improve reliability.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device and a method for manufacturing the same that can improve reliability.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a semiconductor layer and a protective film. The semiconductor layer has an upper surface, a lower surface, a first side surface, a second side surface, and a step surface. The lower surface is on the opposite side of the upper surface. The second side surface is located on the side of the upper surface rather than the first side surface and has irregularities. The step surface connects the first side surface and the second side surface and faces upward. The protective film covers at least a part of the upper surface, at least a part of the second side surface, and at least a part of the step surface.

Brief Description of the Drawings

[0006] [Figure 1]Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. [Figure 2] Figure 2(a) is a schematic plan view illustrating a semiconductor layer, and Figure 2(b) is a schematic side view illustrating a semiconductor layer. [Figure 3] Figures 3(a) and 3(b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] Figures 4(a) and 4(b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] Figures 5(a) and 5(b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] Figures 6(a) and 6(b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] Figure 7 is a schematic cross-sectional view illustrating a semiconductor device according to a reference example. [Figure 8] Figure 8 is a schematic cross-sectional view illustrating an example of a gate structure provided in a semiconductor layer. [Modes for carrying out the invention]

[0007] Each embodiment of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the following description and drawings, n + , n -The notation indicates the relative levels of each impurity concentration. That is, a "+" indicates a relatively higher impurity concentration than a notation without either a "+" or "-", and a "-" indicates a relatively lower impurity concentration than a notation without either a "+" or "-". When both p-type and n-type impurities are present in each region, these notations represent the relative levels of the net impurity concentration after the impurities have compensated for each other. In the following example, the first conductivity type is n-type, and the second conductivity type is p-type. However, for each embodiment described below, the p-type and n-type of each semiconductor region may be reversed when carrying out each embodiment.

[0008] Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. As shown in Figure 1, the semiconductor device 100 according to this embodiment includes a semiconductor layer 10, a protective film 20, a first electrode 30, and a second electrode 33. The semiconductor device 100 is, for example, a semiconductor chip including a vertical MOSFET.

[0009] The semiconductor layer 10 is a semiconductor substrate (e.g., a Si substrate) containing a semiconductor such as silicon (Si). The semiconductor layer 10 has a bottom surface 14 and an upper surface 15 opposite to the bottom surface 14. The upper surface 15 is a device surface on which elements such as transistors are provided. Specifically, for example, a gate structure is formed on the upper surface 15 side. The protective film 20 is provided on the upper surface side of the semiconductor layer 10.

[0010] In describing the embodiments, mutually orthogonal X, Y, and Z directions are used. The direction from the semiconductor layer 10 to the protective film 20 is along the Z direction. The upper surface 15 and the lower surface 14 extend along the XY plane. The planar shape of the semiconductor device 100 as viewed from above is, for example, a rectangle, and each side of the rectangle extends along either the X or Y direction. For convenience, the direction from the semiconductor layer 10 to the protective film 20 is referred to as "up," and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the semiconductor layer 10 and the protective film 20 and are independent of the direction of gravity.

[0011] The semiconductor layer 10 has a side surface that connects the upper surface 15 and the lower surface 14. A recess is formed on the side of this side surface that faces the upper surface 15. That is, the semiconductor layer 10 has a first side surface 11 and a second side surface 12. The first side surface 11 and the second side surface 12 are surfaces that face outward from the semiconductor device. The second side surface 12 is located closer to the upper surface 15 than the first side surface 11. The second side surface 12 extends downward from the outer edge of the upper surface 15. The second side surface 12 is a recessed area on the side surface of the semiconductor layer 10, relative to the first side surface 11. The second side surface 12 has irregularities. The first side surface 11 does not have irregularities like the second side surface 12. The first side surface 11 is flatter than the second side surface 12. The irregularities of the second side surface 12 are the shape excluding slight irregularities that occur as noise due to, for example, processing errors. For example, the surface irregularities of the second side surface 12 are a shape that excludes surface roughness caused by slight recesses or protrusions arranged at random intervals or directions. The irregularities of the second side surface 12 may also be a regular pattern, and may have recesses or protrusions arranged in a certain direction.

[0012] The semiconductor layer 10 has a surface (referred to as a stepped surface 13) that connects the first side surface 11 and the second side surface 12 and faces upward. The stepped surface 13 extends from the upper end of the first side surface 11 to the lower end of the second side surface 12. The stepped surface 13 extends along the XY plane. The second side surface 12 forms a step between the stepped surface 13 and the upper surface 15. The stepped surface 13 does not have the same irregularities as the second side surface 12. The stepped surface 13 is flatter than the second side surface 12.

[0013] The protective film 20 is, for example, a water-repellent insulating film. A resin such as polyimide can be used for the protective film 20. The protective film 20 covers at least a portion of the upper surface 15, at least a portion of the second side surface 12, and at least a portion of the stepped surface 13. The protective film 20 is a film formed as a single unit and is continuous with at least a portion of the upper surface 15, at least a portion of the second side surface 12, and at least a portion of the stepped surface 13.

[0014] More specifically, the protective film 20 contacts a region including at least the outer peripheral end portion 15e of the upper surface 15. The protective film 20 contacts the entire second side surface 12. Note that the surface (side surface) of the protective film 20 does not have to have a shape reflecting the unevenness of the second side surface 12. The surface (side surface) of the protective film 20 may be flatter than the second side surface 12. Further, the stepped surface 13 has an inner region 13a covered with the protective film 20 and contacting the protective film 20, and an outer region 13b not covered with the protective film 20 and exposed from the protective film 20. The inner region 13a extends outward from the lower end of the second side surface 12. The outer region 13b is located outside the inner region 13a and extends from the outer peripheral end of the inner region 13a to the upper end of the first side surface 11. The first side surface 11 is not covered with the protective film 20 and does not contact the protective film 20.

[0015] The second electrode 33 is provided below the lower surface 14. The first electrode 30 is provided above the upper surface 15. In this example, the first electrode 30 has a first conductive layer 31 and a second conductive layer 32 provided on the first conductive layer 31. The protective film 20 covers an end portion 31e of the first conductive layer 31 (an end portion of the first electrode 30). That is, the protective film 20 contacts the side surface and the upper surface of the end portion 31e. The protective film 20 contacts covering the side surface of the second conductive layer 32. The protective film 20 is not provided on the second conductive layer 32. That is, the upper surface of the second conductive layer 32 is exposed upward from an opening provided in the protective film 20.

[0016] For example, a metal material can be used for the first electrode 30 and the second electrode 33. For example, the first conductive layer 31 contains aluminum. The second conductive layer 32 contains at least one of nickel and gold, for example. The second electrode 33 contains at least one of nickel, gold, aluminum, and titanium, for example.

[0017] FIG. 2(a) is a schematic plan view illustrating a semiconductor layer, and FIG. 2(b) is a schematic side view illustrating the semiconductor layer. As shown in Figure 2(a), the second side surface 12 surrounds the outer periphery of the top surface 15. The stepped surface 13 surrounds the outer periphery of the second side surface 12. The first side surface 11 surrounds the outer periphery of the stepped surface 13. In other words, for example, the step on the side surface of the semiconductor layer 10 is provided along the entire circumference of the outer periphery of the semiconductor layer 10.

[0018] Furthermore, in Figure 2(a), the dashed line indicates the position of the outer periphery of the protective film 20. The outer region 13b of the stepped surface 13 that is not covered by the protective film 20 surrounds the outer periphery of the inner region 13a of the stepped surface 13 that is covered by the protective film 20.

[0019] The irregularities on the second side surface 12 are, for example, scallop-shaped. That is, as shown in Figure 2(b), the irregularities on the second side surface 12 have a plurality of recesses 12r and a plurality of protrusions 12p arranged in the vertical direction. The recesses 12r and protrusions 12p are arranged alternately in the vertical direction. The recesses 12r are groove-shaped and extend along the X or Y direction. The recesses 12r have curved surfaces that are recessed inward. The protrusions 12p have curved surfaces that are pointed outward.

[0020] For example, the number of recesses 12r arranged vertically on the second side surface 12 is 5 or more. The recesses 12r and protrusions 12p may be arranged periodically (for example, with a constant period) in the vertical direction. In other words, for example, recesses 12r with a constant vertical length and protrusions 12p with a constant vertical length may be arranged alternately. The height h12p of the recesses and protrusions (the length along the X direction from the bottom of the recess 12r to the top of the protrusion 12p) is, for example, about 1 μm to 3 μm.

[0021] Figures 3(a) to 6(b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. As shown in Figure 3(a), a patterned protective film 40 is formed on the upper surface 15 of the semiconductor layer 10. Using the protective film 40 as a mask, grooves 17 are formed on the upper surface 15 by etching. The Bosch process is used for etching.

[0022] The Bosch process involves repeatedly performing steps such as isotropically etching a semiconductor layer to form grooves, depositing a passivation film on the surface of the semiconductor layer containing the grooves, and removing the passivation film at the bottom of the grooves by anisotropic etching. For example, an F-type plasma using SF6 gas is used for etching, and a CF-type plasma using C4F8 gas is used for depositing the passivation film.

[0023] Furthermore, semiconductor elements such as transistors are provided in the semiconductor layer 10. Specifically, for example, a gate structure is provided on the upper surface 15, and grooves 17 are provided around the region where the gate structure is provided. Above the region where semiconductor elements such as the gate structure are formed, a first conductive layer 31 is provided.

[0024] After removing the protective film 40, a polyimide film is applied to the upper surface 15. This forms a protective film 20 that covers the upper surface 15 of the semiconductor layer 10 and the first conductive layer 31, as shown in Figure 3(b). A portion of the protective film 20 fills the groove 17.

[0025] Subsequently, as shown in Figure 4(a), a resist 41 is formed on the protective film 20. Then, as shown in Figure 4(b), the resist 41 is patterned by photolithography. A portion of the protective film 20 exposed by the patterning of the resist 41 is dissolved in the developer during the photolithography of the resist 41 and removed. As a result, the sides of the groove 17 remain covered with the protective film 20, while a portion of the bottom surface of the groove 17 is exposed from the protective film 20. A portion of the top surface of the first conductive layer 31 is exposed from the protective film 20.

[0026] As shown in Figure 5(a), the resist 41 is removed. Then, as shown in Figure 5(b), a second conductive layer 32 is formed on the first conductive layer 31, for example, by electroless plating.

[0027] Subsequently, the lower surface of the semiconductor layer 10 is ground to thin it. Then, as shown in Figure 6(a), a second electrode 33 is formed on the lower surface 14 of the semiconductor layer 10, for example, by sputtering.

[0028] Subsequently, as shown in Figure 6(b), the semiconductor layer 10 (and the second electrode 33) is cut at a point on the bottom surface of the groove 17 exposed from the protective film 20. A dicing blade is used for cutting. Through this blade dicing process, the semiconductor layer 10 is divided into individual chips. The cut surface of the semiconductor layer 10 becomes the first side surface 11. The side surface of the groove 17 becomes the second side surface 12. The bottom surface of the groove 17 becomes the stepped surface 13.

[0029] For example, when cutting a semiconductor layer 10 by blade dicing, chipping may occur near the cutting position (i.e., the surface edge of the semiconductor layer 10). For example, chipping may occur on the stepped surface 13. In this embodiment, there is a step (second side surface 12) between the stepped surface 13 and the top surface 15, and the stepped surface 13 and the top surface 15 are of different heights. Therefore, even if chipping occurs on the stepped surface 13, it is possible to suppress the chipping from extending to the top surface 15 in the center of the substrate. The range of chipping is limited, and the effects of chipping can be suppressed. For example, it is possible to suppress the deterioration of characteristics such as reliability due to chipping.

[0030] Figure 7 is a schematic cross-sectional view illustrating a semiconductor device according to a reference example. In the semiconductor device 190 according to this reference example, no step is provided on the outer periphery of the upper surface 15 of the semiconductor layer 10. In other words, in this reference example, the stepped surface 13 and the second side surface 12 are not provided.

[0031] For example, devices such as transistor gate structures are formed on the upper surface 15. In the manufacturing of the semiconductor device 190, the cutting position where the semiconductor layer 10 is cut by the dicing blade becomes the edge of the upper surface 15. In this case, as shown in Figure 7, chipping 10c may occur at the edge of the upper surface 15. The chipping 10c may reach the area on the upper surface 15 where the devices are formed, potentially degrading characteristics such as reliability. For example, when chipping 10c occurs, moisture may penetrate from the edge of the chipped semiconductor layer 10 along a path on the surface of the semiconductor layer 10 to the center of the upper surface 15, potentially reducing reliability. For example, degradation such as dielectric breakdown may be more likely to occur in high-humidity environments.

[0032] In contrast, in the semiconductor device 100 according to this embodiment, the presence of the second side surface 12 allows for a longer distance from the edge of the semiconductor layer 10 (the edge on the side of the first side surface 11 of the stepped surface 13) to the top surface 15. Furthermore, because the second side surface 12 has irregularities (recesses 12r and protrusions 12p), the moisture intrusion path along the surface of the semiconductor layer 10 from the edge of the semiconductor layer 10 to the top surface 15 is further lengthened. This makes it more difficult for moisture to penetrate to the top surface 15. Therefore, reliability can be improved.

[0033] Furthermore, the presence of irregularities on the second side surface 12 improves the adhesion between the protective film 20 and the semiconductor layer 10. Specifically, for example, the adhesion of the protective film 20 to the semiconductor layer 10 can be improved. This makes the protective film 20 less likely to peel off, improving its reliability. For example, it can suppress the intrusion of moisture.

[0034] For example, as shown in Figure 1, the height of the step, i.e., the length H12 along the vertical direction of the second side surface 12, may be longer than the thickness of the protective film 20 (the length H20a along the vertical direction of the portion located above the top surface 15). A longer second side surface 12 allows for a greater distance between the stepped surface 13 and the top surface 15. Also, for example, the length H12 of the second side surface 12 may be longer than the width W13 of the stepped surface 13. The width W13 corresponds to the shortest distance from the first side surface 11 to the second side surface 12. However, the length H12 of the second side surface 12 may be equal to or less than the width W13.

[0035] For example, the thickness (length H20a) of the protective film 20 is approximately 3 μm to 10 μm. The length H12 of the second side surface 12 is approximately 5 μm to 30 μm. The width W13 of the stepped surface 13 is approximately 5 μm to 30 μm. Since the stepped surface 13 is an area where no devices such as gate structures are provided, the width of the stepped surface 13 may be narrower than the width of the top surface 15. This allows for effective utilization of the chip area.

[0036] The second side surface 12 is formed from grooves 17 as described in Figure 3(a), etc. Here, as mentioned above, the grooves 17 are formed by the Bosch process. The Bosch process makes it easier to make the grooves 17 deeper, that is, it makes it easier to form a second side surface 12 that is long in the vertical direction. Furthermore, by using the Bosch process, the irregularities of the second side surface 12 can be formed at the same time as the formation of the grooves 17. In this case, the irregularities have a shape with groove-shaped recesses 12r arranged in the vertical direction, as described above with respect to Figure 2(b).

[0037] As explained with respect to Figure 3(b), etc., when forming the protective film 20 on the upper surface 15, the protective film 20 is embedded in the groove 17. This allows the protective film 20 to be formed as a continuous film that is formed as a single unit. In this case, in the semiconductor device 100 of Figure 1, the side surface of the protective film 20 becomes thicker. That is, the length H20b of the side surface of the protective film 20 (the length along the vertical direction of the side surface of the protective film 20 located on the stepped surface 13) is longer than the thickness of the protective film 20 on the upper surface 15 (length H20a).

[0038] For example, the length H12 along the vertical direction of the second side surface 12 may be less than or equal to half the thickness of the semiconductor layer 10. By ensuring that the length H12 is not too long, i.e., that the groove 17 is not too deep, the protective film 20 can be easily embedded. The thickness of the semiconductor layer 10 is, for example, approximately 40 μm to 150 μm.

[0039] As explained with respect to Figures 6(a) and 6(b), the exposed bottom surface of the groove 17 is cut by blade dicing. By using blade dicing, the semiconductor layer 10 and the back metal (second electrode 33) can be cut in the same process. By using blade dicing, the semiconductor layer can be made into individual pieces in a simple process while suppressing manufacturing costs. In addition, by using blade dicing, the first side surface 11 is easier to cut flat. The first side surface 11 is flatter than the second side surface 12. When the groove 17 is cut by blade dicing in this way, an inner region 13a covered by the protective film 20 and an outer region 13b not covered by the protective film 20 are formed on the stepped surface 13.

[0040] Furthermore, as shown in Figure 1, for example, the width W13a of the inner region 13a of the stepped surface 13 may be wider than the width W13b of the outer region 13b. A wider width W13a of the inner region 13a can further suppress the intrusion of moisture into the upper surface 15. Note that the width W13a of the inner region 13a corresponds to the shortest distance from the second side surface 12 to the outer region 13b. Also, the width W13b of the outer region 13b corresponds to the shortest distance from the first side surface 11 to the inner region 13a.

[0041] Figure 8 is a schematic cross-sectional view illustrating an example of a gate structure provided in a semiconductor layer. As shown in Figure 8, the semiconductor layer 10 has semiconductor regions 51, 52, 53, and 54. Semiconductor region 51 (drain region) has a first conductivity type (n + The semiconductor region 52 (drift region) is provided on top of the semiconductor region 51 and has a first conductivity shape (n -The semiconductor region 53 (base region) is provided on a part of the semiconductor region 52 and is of the second conductivity type. The semiconductor region 54 (source region) is provided on a part of the semiconductor region 53 and is of the first conductivity type (n + The semiconductor regions 53 and 54 form the upper surface 15 of the semiconductor layer 10.

[0042] The upper surface 15 is provided with a transistor gate structure. The gate structure includes a gate insulating film 61 and a gate conductive portion 62. The gate insulating film 61 is in contact with, for example, the upper surface 15 of the semiconductor layer 10. In this example, a trench Tr1 is formed on the upper surface 15, and the gate insulating film 61 and the gate conductive portion 62 are arranged within the trench Tr1. The gate insulating film 61 is provided so as to be in contact with the side surface of the trench Tr1. The gate conductive portion 62 faces the semiconductor regions 52, 53, and 54 via the gate insulating film 61.

[0043] The gate conductive portion 62 is electrically connected to the gate electrode G1 located above the upper surface 15. The semiconductor regions 53 and 54 are electrically connected to the source electrode S1 located above the upper surface 15. The semiconductor region 51 is electrically connected to the drain electrode D1 located below the lower surface 14. In Figure 1 and other documents, the first electrode 30 corresponds to the source electrode S1 (or gate electrode G1), and the second electrode 33 corresponds to the drain electrode D1.

[0044] The gate structure controls the current flowing between the drain electrode D1 and the source electrode S1 via the semiconductor layer 10. That is, for example, when a positive voltage is applied to the drain electrode D1 relative to the source electrode S1, the gate electrode G1 controls the voltage of the gate conductive part 62. When the voltage of the gate conductive part 62 exceeds a threshold, an on-current flows between the drain electrode D1 and the source electrode S1. When the voltage of the gate conductive part 62 falls below the threshold, no on-current flows.

[0045] Although Figure 8 illustrates a trench-type vertical MOSFET, the embodiment is not limited to this; for example, a planar type may also be used.

[0046] The embodiment may include the following configurations. (Composition 1) Top surface and, The lower surface opposite to the upper surface, The first aspect and, A second side surface located closer to the upper surface than the first side surface, and having irregularities, A stepped surface connecting the first side and the second side, facing upward, A semiconductor layer having, A protective film covering at least a portion of the upper surface, at least a portion of the second side surface, and at least a portion of the stepped surface, A semiconductor device equipped with the following features. (Configuration 2) The semiconductor device according to configuration 1, wherein the length of the side surface of the protective film located on the stepped surface, along the vertical direction, is longer than the thickness of the portion of the protective film located above the upper surface. (Composition 3) The irregularities on the second side surface have a plurality of recesses arranged in the vertical direction, The semiconductor device according to configuration 1 or 2, wherein the recess is groove-shaped and extends along a direction perpendicular to the vertical direction. (Composition 4) The aforementioned stepped surface is The inner region covered with the protective film, An outer region located outside the aforementioned inner region and not covered by the protective film, A semiconductor device according to any one of configurations 1 to 3. (Composition 5) The semiconductor device according to configuration 4, wherein the width of the inner region is wider than the width of the outer region. (Composition 6) The semiconductor device according to any one of configurations 1 to 5, wherein the length of the second side surface along the vertical direction is longer than the thickness of the portion of the protective film located above the upper surface. (Composition 7) A semiconductor device according to any one of configurations 1 to 6, wherein the length of the second side surface along the vertical direction is longer than the width of the stepped surface. (Composition 8) The system further comprises a first electrode provided above the aforementioned upper surface, The protective film covers the end of the first electrode, A semiconductor device according to any one of configurations 1 to 7, wherein a portion of the first electrode is not covered by the protective film. (Composition 9) A process of forming grooves on the upper surface of a semiconductor layer by etching using a Bosch process, A step of forming a protective film that covers the inside of the groove and the upper surface of the semiconductor layer, A step of removing a portion of the protective film inside the groove so that the sides of the groove remain covered by the protective film while a portion of the bottom surface of the groove is exposed from the protective film, A step of cutting the semiconductor layer by blade dicing at a position on a part of the bottom surface of the groove exposed from the protective film, A method for manufacturing a semiconductor device equipped with [the specified features].

[0047] According to the embodiment, a semiconductor device capable of improving reliability and a method for manufacturing the same can be provided.

[0048] In this specification, "electrically connected" includes not only cases where the connection is made by direct contact, but also cases where the connection is made via other conductive members or the like.

[0049] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of Symbols]

[0050] 10: Semiconductor layer 10c: Chipping 11:1st side 12:Second side 12p: Convex part 12r: recessed 13: Step surface 13a: Inner area 13b:Outer area 14: Bottom surface 15:Top surface 15e: Outer edge 17: Groove 20:Protective film 30: 1st electrode 31: First conductive layer 31e: End 32: Second conductive layer 33:Second electrode 40:Protective film 41: Resist 51-54: Semiconductor field 61: Gate Insulator 62: Gate Conductor 100, 190: Semiconductor devices D1: Drain electrode G1: Gate Shuttle S1: Source electrode Tr1: Trench

Claims

1. Top surface and, The lower surface opposite to the upper surface, The first aspect and, A second side surface located closer to the upper surface than the first side surface, and having irregularities, A stepped surface connecting the first side and the second side, facing upward, A semiconductor layer having, A protective film covering at least a portion of the upper surface, at least a portion of the second side surface, and at least a portion of the stepped surface, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the length of the side surface of the protective film located on the stepped surface, along the vertical direction, is longer than the thickness of the portion of the protective film located above the upper surface.

3. The irregularities on the second side surface have a plurality of recesses arranged in the vertical direction, The semiconductor device according to claim 1 or 2, wherein the recess is groove-shaped and extends along a direction perpendicular to the vertical direction.

4. The aforementioned stepped surface is The inner region covered by the protective film, An outer region located outside the aforementioned inner region and not covered by the protective film, A semiconductor device according to claim 1 or 2, having the following features.

5. The semiconductor device according to claim 4, wherein the width of the inner region is wider than the width of the outer region.

6. The semiconductor device according to claim 1 or 2, wherein the length of the second side surface in the vertical direction is longer than the thickness of the portion of the protective film located above the upper surface.

7. The semiconductor device according to claim 1 or 2, wherein the length of the second side surface along the vertical direction is longer than the width of the stepped surface.

8. The first electrode is further provided above the aforementioned upper surface, The protective film covers the end of the first electrode, The semiconductor device according to claim 1 or 2, wherein a portion of the first electrode is not covered by the protective film.

9. A process of forming grooves on the upper surface of a semiconductor layer by etching using a Bosch process, A step of forming a protective film that covers the inside of the groove and the upper surface of the semiconductor layer, A step of removing a portion of the protective film inside the groove so that the sides of the groove remain covered by the protective film while a portion of the bottom surface of the groove is exposed from the protective film, A step of cutting the semiconductor layer at a position on a part of the bottom surface of the groove exposed from the protective film, A method for manufacturing a semiconductor device equipped with [the specified features].

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