Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same, which have a high Early voltage while ensuring high current gain characteristics of a BJT (Bipolar Junction Transistor). [Solution] The semiconductor device includes a substrate 100 of a first conductivity type, a first region R1 of a second conductivity type disposed on the substrate, a second region R2 disposed on the first region R1 and containing a first impurity of the first conductivity type, a third region R3 disposed on the second region R2 and containing a second impurity of the second conductivity type, a fourth region R4 of the first conductivity type disposed on the third region R3, an emitter region 101 of the second conductivity type disposed on the fourth region R4, a base region 103 of the first conductivity type disposed on the fourth region R4 and separated from the emitter region, and a collector region 105 of the second conductivity type disposed on the substrate 100 and separated from the base region 103.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] The content described in this part only provides background information related to this embodiment and does not constitute the prior art.

[0003] Among semiconductor devices, in a BJT (Bipolar Junction Transistor), in order to ensure high DC current gain and small signal current gain characteristics, the width of the effective base is reduced or the doping level of the base region is lowered to implement a high-gain BJT structure. On the other hand, when the width of the effective base decreases, the gain increases when the collector voltage increases, which increases the collector current. However, when the collector current increases, the result is a decrease in the early voltage. In other words, the width of the effective base is in a trade-off relationship with the gain and the early voltage.

[0004] Thus, there has been a need for a BJT structure that has a high early voltage while ensuring high current gain characteristics of the BJT.

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to provide a semiconductor device having a high early voltage while ensuring high current gain characteristics of a BJT and a method for manufacturing the same. The object of the present invention is not limited to the object mentioned above, and other objects and advantages of the present invention not mentioned will be understood from the following description and will be more clearly understood by the embodiments of the present invention. Furthermore, it will be easily understood that the objects and advantages of the present invention can be realized by the means shown in the claims and combinations thereof. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment of the present invention includes a substrate of a first conductivity type, a first region of a second conductivity type disposed on the substrate, a second region disposed on the first region and containing a first impurity of the first conductivity type, a third region disposed on the second region and containing a second impurity of the second conductivity type, a fourth region of the first conductivity type disposed on the third region, an emitter region of the second conductivity type disposed on the fourth region, a base region of the first conductivity type disposed on the fourth region and spaced apart from the emitter region, and a collector region of the second conductivity type disposed on the substrate and spaced apart from the base region.

[0007] The substrate further includes a collector ring, which is arranged on the substrate so as to surround the second region, the third region, and the fourth region, and is positioned below the collector region.

[0008] Furthermore, the third region is connected to the collector ring.

[0009] Furthermore, the doping level in the second region is higher than the doping level in the fourth region.

[0010] Furthermore, the third region further includes a first connecting portion that connects a portion of the fourth region and a portion of the second region, and the first connecting portion is of the first conductivity type.

[0011] Furthermore, the third region further includes a second connecting portion that connects the other part of the fourth region to the other part of the second region, the second connecting portion being separated from the first connecting portion, and the second connecting portion being of the first conductivity type.

[0012] Furthermore, the third region includes a first connecting portion connecting the first portion of the fourth region and the first portion of the second region, a second connecting portion connecting the second portion of the fourth region and the second portion of the second region, a third connecting portion connecting the third portion of the fourth region and the third portion of the second region, a first portion of the third region between the first connecting portion and the second connecting portion, and a second portion of the third region between the second connecting portion and the third connecting portion. The first and second portions of the third region contain the second impurity of the second conductivity type, and the first, second, and third connecting portions are of the first conductivity type.

[0013] Furthermore, the first and second portions of the third region are each extended from the third region to the second region and connected to the first region.

[0014] Furthermore, the second portion of the second region located between the first portion of the extended third region and the second portion of the extended third region contains the first impurity of the first conductivity type.

[0015] A semiconductor device according to an embodiment of the present invention includes a substrate of a first conductivity type, a first depletion layer on the substrate, a second depletion layer on the first depletion layer, an emitter region on the substrate, and a third depletion layer disposed on the second depletion layer, which is a part of the emitter region.

[0016] Furthermore, the substrate includes a first region of a second conductivity type, a second region located on the first region and containing a first impurity of the first conductivity type, a third region located on the second region and containing a second impurity of the second conductivity type, and a fourth region located on the third region and containing a first conductivity type, wherein the first depletion layer includes the boundary between the first region and the second region, the second depletion layer includes the boundary between the second region and the third region, and the boundary between the third region and the fourth region, and the third depletion layer includes the boundary between the fourth region and the emitter region.

[0017] The device further includes a base region of a first conductivity type, which is disposed on the substrate and spaced apart from the emitter region, and a collector region of a second conductivity type, which is disposed on the substrate and spaced apart from the base region.

[0018] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of: providing a substrate of a first conductivity type; forming an emitter region of a second conductivity type within the substrate; forming a first region of the second conductivity type within the substrate; forming a second region containing a first impurity of the first conductivity type on the first region within the substrate; and forming a third region containing a second impurity of the second conductivity type and a fourth region of the first conductivity type on the second region within the substrate.

[0019] Furthermore, the steps of forming the third and fourth regions include the step of forming a pre-fourth region on the second region and the step of forming a portion of the third region within a portion of the pre-fourth region through the injection of the second impurity, thereby defining the third region which includes the fourth region and the portion of the third region.

[0020] Furthermore, the third region further includes a first connecting portion that connects a portion of the fourth region and a portion of the second region, and the first connecting portion is of the first conductivity type.

[0021] The process further includes the step of forming a collector ring within the substrate below the collector region, surrounding the second region, the third region, and the fourth region, and the collector ring is connected to the third region.

[0022] The method further includes the step of forming a first connecting portion within the third region that connects the third region and the fourth region.

[0023] Also, the step of forming the third region and the fourth region includes the step of forming a pre-fourth region on the second region, and the step of forming the first part of the third region and the second part of the third region respectively within the first part of the pre-fourth region and the second part of the pre-fourth region through the implantation process of the second impurity. A first connection part connecting the second region and the fourth region is formed between the first part of the third region and the second part of the third region, and the first connection part is of the first conductivity type.

[0024] Also, each of the first part and the second part of the third region extends from the third region to the second region and is formed to be connected to the first region.

[0025] Further, it further includes the step of forming a base region of the first conductivity type, which is disposed apart from the emitter region, within the substrate, and the step of forming a collector region of the second conductivity type, which is disposed apart from the base region, within the substrate.

Advantages of the Invention

[0026] The semiconductor device and its manufacturing method of the present invention can ensure a high Early voltage while ensuring high current gain characteristics of the BJT by sequentially arranging layers of opposite conductivity types under the emitter region and the base region. In addition to the above-described content, the specific effects of the present invention will be described together while explaining the specific matters for implementing the following invention.

Brief Description of the Drawings

[0027] [Figure 1] FIG. 1 is a layout diagram for explaining a semiconductor device according to some embodiments of the present invention. [Figure 2] FIG. 2 is a cross-sectional view taken along the line A - A of FIG. 1. [Figure 3] FIG. 3 is a drawing for explaining the effects of a semiconductor device according to some embodiments of the present invention. [Figure 4] Figure 4 is a layout diagram illustrating a semiconductor device according to several embodiments of the present invention. [Figure 5] Figure 5 is a cross-sectional view taken along the line B-B in Figure 4. [Figure 6] Figure 6 is a layout diagram illustrating a semiconductor device according to several embodiments of the present invention. [Figure 7] Figure 7 is a layout diagram illustrating a semiconductor device according to several embodiments of the present invention. [Figure 8] Figure 8 is a cross-sectional view taken along the line C-C in Figure 7. [Figure 9] Figure 9 is a layout diagram illustrating a semiconductor device according to several embodiments of the present invention. [Figure 10] Figure 10 is a cross-sectional view taken along the DD line in Figure 9. [Figure 11] Figure 11 is a cross-sectional view taken along the line D-D in Figure 8. [Figure 12] Figure 12 is a flowchart illustrating a method for manufacturing a semiconductor device according to several embodiments of the present invention. [Figure 13] Figure 13 is a cross-sectional view illustrating stages S100 and S200 of Figure 12. [Figure 14] Figure 14 is a diagram illustrating stages S300, S400, and S500 of Figure 12. [Figure 15] Figure 15 is a diagram illustrating stages S300, S400, and S500 of Figure 12. [Figure 16] Figure 16 is a diagram illustrating step S500 in Figure 12. [Figure 17] Figure 17 is a diagram illustrating step S510 in Figure 16. [Figure 18] Figure 18 is a diagram illustrating step S520 in Figure 16. [Figure 19] Figure 19 is a diagram illustrating step S520 in Figure 16. [Figure 20] Figure 20 is a diagram illustrating step S500 in Figure 12. [Figure 21] Figure 21 is a diagram illustrating step S500 in Figure 12. [Figure 22] Figure 22 is a diagram illustrating step S500 in Figure 12. [Figure 23] Figure 23 is a diagram illustrating step S500 in Figure 12. [Figure 24] Figure 24 is a diagram illustrating step S500 in Figure 12. [Figure 25] Figure 25 is a diagram illustrating step S500 in Figure 12. [Modes for carrying out the invention]

[0028] The terms or words used herein and in the claims shall not be construed to be limited to their general or dictionary meanings. In accordance with the principle that an inventor may define the concept of a term or word to best describe their invention, they should be interpreted as meanings and concepts consistent with the technical idea of ​​the present invention. Furthermore, it should be understood that the embodiments and configurations shown in the drawings herein represent only one embodiment of the present invention and do not represent the entire technical idea of ​​the present invention; therefore, various equivalents, variations, and applicable examples may exist that can replace them at the time of filing.

[0029] The terms first, second, A, B, etc., as used herein and in the claims, may be used to describe various components, but such components shall not be limited by such terms. The terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the rights of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The terms "and / or" include a combination of multiple related items or any of multiple related items.

[0030] The terms used herein and in the claims are used solely to describe specific embodiments and are not intended to limit the invention. A singular expression includes plural expressions unless the context clearly indicates otherwise. In this application, terms such as “includes” or “having” should be understood as not preemptively excluding the existence or possibility of additional features, figures, steps, actions, components, parts, or combinations thereof described in the specification.

[0031] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as they would be generally understood by a person with ordinary skill in the art to which this invention pertains.

[0032] Terms as defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and not as ideal or overly formal unless explicitly defined in this application. Furthermore, each configuration, process, step, or method included in each embodiment of the present invention may be shared to the extent that they are not technically contradictory to one another.

[0033] Hereinafter, a semiconductor device according to several embodiments of the present invention will be described with reference to Figures 1 to 3.

[0034] Figure 1 is a layout diagram illustrating a semiconductor device according to several embodiments of the present invention. Figure 2 is a cross-sectional view taken along the line A-A in Figure 1.

[0035] Referring to Figures 1 and 2, a semiconductor device (10) according to some embodiments of the present invention may include a substrate (100), first to fourth regions (R), an emitter region (101), a first element isolation film (111), a second element isolation film (112), a base region (103), and a collector region (105).

[0036] The substrate (100) may be of the first conductivity type. The emitter region (101) can be placed on the substrate (100). The emitter region (101) may be a second conductivity type different from the first conductivity type.

[0037] The first element isolation film (111) can be positioned to surround the emitter region (101). The first element isolation film (111) may contain an insulating material. The second element isolation film (112) can be positioned to surround the base region (103). The second element isolation film (112) may contain an insulating material. The first element isolation film (111) can insulate the emitter region (101) and the base region (103) from each other, and the second element isolation film (112) can insulate the base region (103) and the collector region (105) from each other.

[0038] In the following figures, the semiconductor device (10) is shown to include a first element isolation film (111) and a second element isolation film (112), but is not limited thereto. For example, in some embodiments, the semiconductor device (10) can isolate the emitter region (101), base region (103), and collector region (105) from each other using non-silicide regions instead of the first element isolation film (111) and the second element isolation film (112). For example, the first non-silicide region can be arranged to surround the emitter region (101), and the second non-silicide region can be arranged to surround the base region (103).

[0039] The base region (103) can be placed on the substrate (100). The base region (103) can be placed so as to surround the emitter region (101) and the first element isolation film (111). The base region (103) may be of the first conductivity type. The base region (103) can be placed at a distance from the emitter region (101). The base region (103) can be separated from the emitter region (101) by the first element isolation film (111).

[0040] The collector region (105) can be placed on the substrate (100). The collector region (105) can be placed so as to surround the emitter region (101), the base region (103), and the second element isolation film (112). The collector region (105) may be of the second conductivity type. The collector region (105) can be placed at a distance from the base region (103). The collector region (105) can be separated from the base region (103) by the second element isolation film (112). The base region (103) can be placed between the emitter region (101) and the collector region (105).

[0041] The collector ring (107) can be placed on the substrate (100) below the collector region (105). The collector ring (107) can be connected to the first region (R1), the third region (R3), and the collector region (105). The collector ring (107) can be placed between the substrate (100) and the collector region (105) so as to surround the first to fourth regions (R). The collector ring (107) can have the same conductivity type as the collector region (105). The collector ring (107) may have a second conductivity type. The doping level of the collector ring (107) and the doping level of the collector region (105) may be the same or different.

[0042] The first to fourth regions (R) may be regions located on the substrate (100). The first to fourth regions (R) may be regions located between the substrate (100) and the emitter region (101). The first to fourth regions (R) may be regions located between the substrate (100) and the base region (103). The first to fourth regions (R) may be arranged to overlap the emitter region (101) and the base region (103) in a perpendicular direction. The perpendicular direction may be from the emitter region (101) toward the bottom surface of the substrate (100). The first to fourth regions (R) may be surrounded by a collector ring (107).

[0043] The first region (R1) may be a region located on the substrate (100). The first region (R1) may be of the second conductivity type. The first region (R1) may be connected to the collector ring (107). For example, the first region (R1) may be in direct contact with the collector ring (107). The first region (R1) may be located between the substrate (100) and the collector region (105). The first region (R1) may be located between the substrate (100) and the base region (103). The first region (R1) may be located between the substrate (100) and the emitter region (101). The first region (R1) may be located between the substrate (100) and the collector ring (107).

[0044] The second region (R2) can be placed on the substrate (100) and on at least a portion of the first region (R1). The second region (R2) can be placed so as to be surrounded by the collector ring (107). The second region (R2) can contain a first impurity of a first conductivity type. The second region (R2) can be placed between the substrate (100) and the base region (103) and between the substrate (100) and the emitter region (101).

[0045] The third region (R3) can be placed on the substrate (100) or on the second region (R2). The third region (R3) can be placed so as to be surrounded by the collector ring (107). The third region (R3) can be placed between the substrate (100) and the base region (103) or between the substrate (100) and the emitter region (101).

[0046] The third region (R3) may contain a second impurity of the second conductivity type. In some embodiments, the third region (R3) of the second conductivity type can be connected to the collector ring (107). For example, the third region (R3) can be in direct contact with the collector ring (107).

[0047] The fourth region (R4) can be placed on the substrate (100) or on the third region (R3). The fourth region (R4) can be placed so as to be surrounded by the collector ring (107). The fourth region (R4) can be placed between the substrate (100) and the base region (103) or between the substrate (100) and the emitter region (101). The fourth region (R4) may be of the first conductivity type.

[0048] The emitter region (101) and the base region (103) can be placed on the fourth region (R4). The fourth region (R4) can be placed between the emitter region (101) and the third region (R3), and between the base region (103) and the third region (R3).

[0049] The emitter region (101), the fourth region (R4), the third region (R3), the second region (R2), and the first region (R1) can be arranged so as to overlap each other along the direction from the emitter region (101) toward the lower surface of the substrate (100). In the semiconductor device (10) according to an embodiment of the present invention, the second conductivity region and the first conductivity region can be arranged alternately along the direction from the emitter region (101) toward the lower surface of the substrate (100).

[0050] The first depletion layer (1DL) may include the boundary (1IF) (e.g., a junction) between the first region (R1) and the second region (R2). The first depletion layer (1DL) may also include a portion of the boundary between the second region (R2) and the collectoring (107). The first depletion layer (1DL) may be, for example, a region that includes a portion of the first region (R1) and a portion of the second region (R2).

[0051] The second depletion layer (2DL) includes the boundary (2IF) between the second region (R2) and the third region (R3), and may include the boundary (3IF) between the third region (R3) and the fourth region (R4). The second depletion layer (2DL) includes a portion of the boundary between the second region (R2) and the collectoring (107), and may include at least a portion of the boundary between the fourth region (R4) and the collectoring (107). The second depletion layer (2DL) may be, for example, a region including another portion of the second region (R2), the third region (R3), and a portion of the fourth region (R4).

[0052] In some embodiments, within a certain voltage range, the semiconductor device (10) may include a first partial depletion layer and a second partial depletion layer on a first depletion layer (1DL). The first and second partial depletion layers may be referred to as the second depletion layer (2DL) within a certain voltage range. The certain voltage range may be, for example, the voltage range of the operating voltage of the semiconductor device (10) up to a certain voltage. Within the certain voltage range, the third region (R3) may not be completely depleted, and thus the first and second partial depletion layers may be formed. The first partial depletion layer may include a portion of the second region (R2) and a portion of the third region (R3). The second partial depletion layer may include a portion of the fourth region (R4) and at least a portion of the remaining portion of the third region (R3).

[0053] The third depletion layer (3DL) may include the boundary (4IF) between the fourth region (R4) and the emitter region (101). The third depletion layer (3DL) may be, for example, a region that includes the rest of the fourth region (R4) and a portion of the emitter region (101).

[0054] In a semiconductor device (10) according to some embodiments of the present invention, the effective base (EB) may be the remaining region of the fourth region (R4) located between the third depletion layer (3DL) and the second depletion layer (2DL). The effective base (EB) may be the remaining region of the fourth region (R4), excluding the portion of the fourth region (R4) included in the second depletion layer (2DL) and the other portion of the fourth region (R4) included in the third depletion layer (3DL).

[0055] The doping level of the second region (R2) may be higher than the doping level of the fourth region (R4). If the doping level of the second region (R2) is lower than that of the fourth region (R4), and the voltage Vce applied between the collector region (105) and the emitter region (101) is within the operating voltage range, when the second region (R2) is depleted, Vce is applied to the junction between the third region (R3) and the fourth region (R4), reducing the width of the effective base (EB), and lowering the Early voltage and output resistance (Ro).

[0056] The third region (R3) of the semiconductor device (10) can be completely depleted under zero bias to form a second depletion layer (2DL). With the second depletion layer (2DL) formed, even if the voltage Vce applied between the collector region (105) and the emitter region (101) is increased, Vce may not be applied to the second depletion layer (2DL). In other words, the second depletion layer (2DL) formed at the junction between the third region (R3) and the fourth region (R4) may not change with the voltage of Vce. On the other hand, an increase in the Vce voltage can be applied to the second region (R2). This means that the width of the effective base (EB) is not affected by the change in Vce. Because the width of the effective base (EB) is not affected by the change in Vce, a stable gain and a high Early voltage can be ensured in response to the voltage. Here, the width of the effective base (EB) may be the distance between the third depletion layer (3DL) and the second depletion layer (2DL), measured along the direction from the emitter region (101) toward the bottom surface of the substrate (100).

[0057] Figure 3 is a diagram illustrating the effects of a semiconductor device according to several embodiments of the present invention. Referring to Figures 1, 2, and 3, the x-axis in Figure 3 represents Vce (in V), the voltage applied between the collector region (105) and the emitter region (101), and the y-axis represents Ic (in A), the current in the collector region (105). The first graph (G1) shows the Ic against Vce of a semiconductor device (10) according to several embodiments of the present invention shown in Figures 1 and 2, and the first Early voltage (Va1) and the first output resistance can be determined from the first graph (G1). The second graph (G2) shows the Ic against Vce of a semiconductor device that does not include at least one of the second region (R2) and the third region (R3), and the second Early voltage (Va2) and the second output resistance can be determined from the second graph (G2). The first and second output resistances can represent the resistance values ​​in the current saturation region (SR), i.e., the flat region where the increase in Ic is relatively small even when Vce increases. The output resistance (Ro) can be calculated using the following formula 1. Equation 1) Ro = ΔVce / ΔIce [Ω]

[0058] When comparing the first graph (G1) and the second graph (G2), it can be seen that the first Early voltage (Va1) in the first graph (G1) is greater than the second Early voltage (Va2) in the second graph (G2), and the first output resistance in the first graph (G1) is greater than the second output resistance in the second graph (G2).

[0059] A semiconductor device (10) according to some embodiments of the present invention can ensure an effective base (EB) regardless of Vce, and can increase the Early voltage and output resistance by including a third region (R3) of the first conductivity type, a second region (R2) of the second conductivity type, and a first region (R1) of the first conductivity type, which are sequentially arranged below the emitter region (101) of the second conductivity type and the fourth region (R4) of the first conductivity type.

[0060] Hereinafter, a semiconductor device according to several embodiments of the present invention will be described with reference to Figures 4 and 5. To clarify the explanation, parts that overlap with the above content will be made concise or omitted.

[0061] Figure 4 is a layout diagram illustrating a semiconductor device according to several embodiments of the present invention. Figure 5 is a cross-sectional view taken along the line B-B in Figure 4.

[0062] The cross-sectional view obtained by cutting along the line A-A in Figure 4 is the same as that in Figure 2. Referring to Figures 2, 4, and 5, a semiconductor device (10) according to some embodiments of the present invention may further include a first connection portion (CP1) and a second connection portion (CP2).

[0063] The size of the first to fourth regions (R) may differ from the size of a portion of the third region (R3) (R31).

[0064] The third region (R3) may include a first connection portion (CP1), a second connection portion (CP2), and a portion of the third region (R3) (R31). The first connection portion (CP1) may be a portion of the third region (R3) that connects a portion of the second region (R2) and a portion of the fourth region (R4). The second connection portion (CP2) may be another portion of the third region (R3) that connects another portion of the second region (R2) and another portion of the fourth region (R4).

[0065] The first connection portion (CP1) can be positioned, for example, between a portion (R31) of the third region (R3) and the collector ring (107). The second connection portion (CP2) can be positioned, for example, between a portion (R31) of the third region (R3) and the collector ring. Each of the first connection portion (CP1) and the second connection portion (CP2) can be in contact with the collector ring (107), for example.

[0066] The first connection portion (CP1) and the second connection portion (CP2) can each be formed on the substrate (100) spaced apart from each other.

[0067] However, in some embodiments, the first connection portion (CP1) and the second connection portion (CP2) are connected to each other and may enclose a portion (R31) of the third region (R3).

[0068] The fourth region (R4), the second region (R2), the first connection point (CP1), and the second connection point (CP2) can all be of the same first conductivity type. The doping levels of the fourth region (R4), the first connection point (CP1), and the second connection point (CP2) may be lower than the doping level of the second region (R2). A portion of the third region (R3) (R31) may be of the second conductivity type. Second impurities of the second conductivity type may be contained in a portion of the third region (R3) (R31).

[0069] The second depletion layer (2DL) may include the third region (R3). For example, the second depletion layer (2DL) may include the boundary between the first connection portion (CP1) and the collectoring (107), the boundary between the first connection portion (CP1) and a portion (R31) of the third region (R3), the boundary between the second connection portion (CP2) and the collectoring (107), and the boundary between the second connection portion (CP2) and a portion (R31) of the third region (R3).

[0070] Hereinafter, a semiconductor device according to several embodiments of the present invention will be described with reference to Figure 6. To clarify the explanation, parts that overlap with the above content will be made concise or omitted.

[0071] Figure 6 is a layout diagram illustrating a semiconductor device according to several embodiments of the present invention.

[0072] The cross-sectional view obtained by cutting along the line A-A in Figure 6 is the same as that in Figure 2.

[0073] Referring to Figures 2 and 6, the first connection portion (CP1) and the second connection portion (CP2) of the semiconductor device (10) according to some embodiments of the present invention can be arranged in the corner portions of the first to fourth regions (R).

[0074] The third region (R3) may include a first connection portion (CP1), a second connection portion (CP2), and a portion of the third region (R3) (R31). The first connection portion (CP1) may be a portion of the third region (R3) that connects a portion of the second region (R2) and a portion of the fourth region (R4). The second connection portion (CP2) may be another portion of the third region (R3) that connects another portion of the second region (R2) and another portion of the fourth region (R4).

[0075] The first connection portion (CP1) can be positioned, for example, between a portion (R31) of the third region (R3) and the collector ring (107). The second connection portion (CP2) can be positioned, for example, between a portion (R31) of the third region (R3) and the collector ring. Each of the first connection portion (CP1) and the second connection portion (CP2) can be in contact with the collector ring (107), for example.

[0076] The first connection portion (CP1) and the second connection portion (CP2) can each be formed on the substrate (100) spaced apart from each other.

[0077] The fourth region (R4), the second region (R2), the first connection point (CP1), and the second connection point (CP2) can all be of the same first conductivity type. The doping levels of the fourth region (R4), the first connection point (CP1), and the second connection point (CP2) may be lower than the doping level of the second region (R2). A portion of the third region (R3) (R31) may be of the second conductivity type. Second impurities of the second conductivity type may be contained in a portion of the third region (R3) (R31).

[0078] The second depletion layer (2DL) may include the boundary between the first connection portion (CP1) and the collectoring (107), the boundary between the first connection portion (CP1) and a portion (R31) of the third region (R3), the boundary between the second connection portion (CP2) and the collectoring (107), and the boundary between the second connection portion (CP2) and a portion (R31) of the third region (R3).

[0079] Hereinafter, a semiconductor device according to several embodiments of the present invention will be described with reference to Figures 7 and 8. To clarify the explanation, parts that overlap with the above will be made concise or omitted.

[0080] Figure 7 is a layout diagram illustrating a semiconductor device according to several embodiments of the present invention. Figure 8 is a cross-sectional view taken along the line C-C in Figure 7.

[0081] The cross-sectional view obtained by cutting along the line A-A in Figure 7 is the same as that in Figure 2. Referring to Figures 2, 7, and 8, semiconductor devices (10) according to some embodiments of the present invention may include a first connection portion (CP1).

[0082] The size of the first to fourth regions (R) may differ from the size of a portion of the third region (R3) (R31).

[0083] The third region (R3) may include the first connection portion (CP1) and a portion of the third region (R31). The first connection portion (CP1) may be a portion of the third region (R3) that connects a portion of the second region (R2) and a portion of the fourth region (R4). Unlike the embodiments described with reference to Figures 3 and 4, the semiconductor device (10) according to some embodiments may include only the first connection portion (CP1).

[0084] The first connection portion (CP1) can be placed, for example, between a portion (R31) of the third region (R3) and the collector ring (107).

[0085] The fourth region (R4), the second region (R2), and the first connection portion (CP1) may all be of the same first conductivity type. The doping levels of the fourth region (R4) and the first connection portion (CP1) may be lower than the doping level of the second region (R2). A portion of the third region (R3) (R31) may be of the second conductivity type. Second impurities of the second conductivity type may be contained in a portion of the third region (R3) (R31).

[0086] The second depletion layer (2DL) includes the boundary between the first connection portion (CP1) and the collectoring (107), and may also include the boundary between the first connection portion (CP1) and a portion (R31) of the third region (R3).

[0087] Hereinafter, a semiconductor device according to several embodiments of the present invention will be described with reference to Figures 9 and 10. To clarify the explanation, parts that overlap with the above will be made concise or omitted.

[0088] Figure 9 is a layout diagram illustrating a semiconductor device according to several embodiments of the present invention. Figure 10 is a cross-sectional view taken along the line D-D in Figure 9.

[0089] Referring to Figures 9 and 10, the third region (R3) of the semiconductor device (10) according to some embodiments of the present invention may include a plurality of alternately arranged connection portions (CP1, CP2, CP3, CP4) and a plurality of portions (P31, P32, P33) of the third region (R3).

[0090] The first connection part (CP1) can connect the first part (P41) of the fourth region (R4) and the first part (P21) of the second region (R2). The second connection part (CP2) can connect the second part (P42) of the fourth region (R4) and the second part (P22) of the second region (R2). The third connection part (CP3) can connect the third part (P43) of the fourth region (R4) and the third part (P23) of the second region (R2). The fourth connection part (CP4) can connect the fourth part (P44) of the fourth region (R4) and the fourth part (P24) of the second region (R2).

[0091] A portion (R31) of the third region (R3) may include the first portion (P31) of the third region (R3), the second portion (P32) of the third region (R3), and the third portion (P33) of the third region (R3).

[0092] The first part (P31) of the third region (R3) can be placed between the first connection part (CP1) and the second connection part (CP2). The second part (P32) of the third region (R3) can be placed between the third connection part (CP3) and the fourth connection part (CP4). The third part (P33) of the third region (R3) can be placed between the fourth connection part (CP4) and the second connection part (CP2).

[0093] Multiple connection points (CP1, CP2, CP3, CP4) may be of the first conductivity type. The doping levels of multiple connection points (CP1, CP2, CP3, CP4) may be lower than the doping levels of the second region (R2). Multiple portions of the third region (R3) (P31, P32, P33) may be of the second conductivity type. Second impurities of the second conductivity type may be present in multiple portions of the third region (R3) (P31, P32, P33).

[0094] Hereinafter, a semiconductor device according to several embodiments of the present invention will be described with reference to Figure 11. To clarify the explanation, parts that overlap with the above content will be made concise or omitted.

[0095] Figure 11 is a cross-sectional view taken along the line D-D in Figure 8. The plan view in Figure 11 may be the same as that in Figure 9.

[0096] Referring to Figures 9 and 11, multiple portions of the third region (R3) (P31, P32, P33) can be extended from the third region (R3) to the second region (R2) and connected to the first region (R1). The third region (R3) can include parts of multiple portions of the third region (R3) arranged alternately (P31, P32, P33) and multiple connecting portions (CP1, CP2, CP3, CP4). The second region (R2) can include the remaining parts of multiple portions of the third region (R3) arranged alternately (P31, P32, P33) and multiple portions of the second region (R2) (P21, P22, P23, P24).

[0097] A portion of the first part (P31) of the third region (R3) may be located in the third region (R3), and the remainder of the first part (P31) of the third region (R3) may be located in the second region (R2). A portion of the second part (P32) of the third region (R3) may be located in the third region (R3), and the remainder of the second part (P32) of the third region (R3) may be located in the second region (R2). A portion of the third part (P33) of the third region (R3) may be located in the third region (R3), and the remainder of the third part (P33) of the third region (R3) may be located in the second region (R2).

[0098] The third portion (P23) of the second region (R2) can be positioned between the first portion (P31) of the extended third region (R3) and the second portion (P32) of the extended third region (R3). The fourth portion (P24) of the second region (R2) can be positioned between the second portion (P32) of the extended third region (R3) and the third portion (P33) of the extended third region (R3).

[0099] The semiconductor device according to an embodiment of the present invention can ensure a high Early voltage and output resistance, and a high gain, by further including a third region (R3). The semiconductor device according to an embodiment of the present invention can ensure that changes in the voltage applied between the collector region (105) and the emitter region (101) do not affect the width of the effective base (EB).

[0100] The following describes a method for manufacturing a semiconductor device according to several embodiments of the present invention, with reference to Figures 12 to 15. To clarify the explanation, any parts that overlap with the previously mentioned content will be simplified or omitted.

[0101] Figure 12 is a flowchart illustrating a method for manufacturing a semiconductor device according to several embodiments of the present invention.

[0102] Referring to Figure 12, a method for manufacturing a semiconductor device according to some embodiments of the present invention may include the step of providing a substrate of a first conductivity type (S100).

[0103] A method for manufacturing a semiconductor device according to some embodiments of the present invention may include the step (S200) of forming at least one of a second conductivity type emitter region, base region, and collector region within a substrate. The first conductivity type base region may be formed within the substrate, separated from the emitter region. The second conductivity type collector region may be formed within the substrate, separated from the base region.

[0104] Figure 13 is a cross-sectional view illustrating stages S100 and S200 of Figure 12. Figure 13 may be a cross-sectional view taken along the line A-A in Figure 1.

[0105] Referring to Figures 12 and 14, a first-conductivity substrate (100) can be provided, having an emitter region (101), a base region (103), a collector region (105), and a collector ring (107) formed thereon.

[0106] In some embodiments, a substrate (100) can be provided before at least one of the emitter region (101), base region (103), collector region (105), and collector ring (107) is formed.

[0107] Referring again to Figure 12, a method for manufacturing a semiconductor device according to some embodiments of the present invention may include a step (S300) of forming a first region of a second conductivity type in a substrate. A method for manufacturing a semiconductor device according to some embodiments of the present invention may include a step (S400) of forming a second region containing a first impurity of a first conductivity type on the first region in the substrate. A method for manufacturing a semiconductor device according to some embodiments of the present invention may include a step (S500) of forming a third region containing a second impurity of a second conductivity type and a fourth region of a first conductivity type on the second region in the substrate.

[0108] Figures 14 and 15 are diagrams illustrating stages S300, S400, and S500 of Figure 12. Figure 14 is a plan view, and Figure 15 is a cross-sectional view taken along line A-A in Figure 14.

[0109] Referring to Figures 12, 14, and 15, a first mask pattern (PR1) can be formed on the substrate (100) to form the first region (R1), the second region (R2), the third region (R3), and the fourth region (R4). An impurity injection process can be performed to form the first region (R1), the second region (R2), the third region (R3), and the fourth region (R4) in the area exposed by the first mask pattern (PR1).

[0110] Although the steps in Figure 12 have been described as being executed sequentially, this is not the only way to do so, and the order of the steps in Figure 12 is not restricted. For example, step S200 in Figure 12 described above may be executed after steps S300 to S500 have been executed.

[0111] The following describes a method for manufacturing a semiconductor device according to several embodiments of the present invention, with reference to Figures 12, 14, 16, 17, 18, and 19. To clarify the explanation, any parts that overlap with the previously mentioned content will be simplified or omitted.

[0112] Figure 16 is a diagram illustrating stage S500 in Figure 12. Figure 17 is a diagram illustrating stage S510 in Figure 16. Figure 17 is a cross-sectional view taken along line A-A in Figure 14. Figures 18 and 19 are diagrams illustrating stage S520 in Figure 16. Figure 18 is a plan view, and Figure 19 is a cross-sectional view taken along line B-B in Figure 18.

[0113] Referring to Figures 12 and 16, the step of forming the third and fourth regions (S500) in a semiconductor device manufacturing method according to some embodiments of the present invention may include the step of first forming a pre-fourth region on the second region (S510). The step of forming the third and fourth regions (S500) in a semiconductor device manufacturing method according to some embodiments of the present invention may include the step of forming a portion of the third region within a portion of the pre-fourth region through an injection step of a second impurity (S520). By forming a portion of the third region in a portion of the pre-fourth region, a third region including a portion of the third region can be defined, and the remaining portion of the pre-fourth region can be defined as the fourth region. According to the manufacturing method of Figure 15, a first connection region and a second connection region can be formed in a semiconductor device.

[0114] Referring to Figures 12, 14, 16, and 17, the first mask pattern (PR1) can be used to form the first region (R1), the second region (R2), and the pre-fourth region (PRER4) on the substrate (100). After the first region (R1), the second region (R2), and the fourth region (PRER4) are formed, the first mask pattern (PR1) can be removed.

[0115] Referring to Figures 18 and 19, a second mask pattern (PR2) can be formed on the substrate (100). A portion (R31) of the third region (R3) can be formed in the region exposed by the second mask pattern (PR2). For example, an impurity implantation process can be performed to inject a second impurity into the region exposed by the second mask pattern (PR2). A portion (R31) of the third region (R3) can be formed by the impurity implantation process.

[0116] By forming a portion (R31) of the third region (R3), the third region (R3) can be defined to include the fourth region (R4) and a portion (R31).

[0117] The width (W2) of the region exposed by the second mask pattern (PR2) may be narrower than the width (W1) of the region exposed by the first mask pattern (PR1). This allows for the formation of a first connection portion (CP1) and a second connection portion (CP2) in the third region (R3). For example, the difference between the width (W1) of the first mask pattern (PR1) and the width (W2) of the second mask pattern (PR2) allows the remaining portion of the third region (R3), which is the first conductivity type portion, to be defined as the first connection portion (CP1) and the second connection portion (CP2), respectively.

[0118] A portion of the third region (R3) (R31) is formed within a portion of the pre-fourth region (PRER4), and a first connection portion (CP1) and a second connection portion (CP2) are defined. Thus, a third region (R3) can be defined that includes the portion of the third region (R31), the first connection portion (CP1), and the second connection portion (CP2). In order to form the third region (R3), the remaining portion of the pre-fourth region (PRER4) can be defined as the fourth region (R4).

[0119] The semiconductor device (10) after the second mask pattern (PR2) has been removed may be the same as the semiconductor device (10) shown in Figures 3 and 4.

[0120] The following describes a method for manufacturing a semiconductor device according to several embodiments of the present invention, with reference to Figures 12, 14, 15, 20, and 21. To clarify the explanation, any parts that overlap with the previously mentioned content will be simplified or omitted.

[0121] Figures 20 and 21 are diagrams illustrating step S500 in Figure 12. Figures 20 and 21 may be diagrams after the step described with reference to Figures 14 and 15 has been performed. Figure 20 is a plan view, and Figure 21 is a cross-sectional view taken along the line B-B in Figure 20.

[0122] Referring to Figures 12, 14, 15, 20, and 21, the first mask pattern (PR1) can be used to form the first region (R1), the second region (R2), the third region (R3), and the fourth region (R4) on the substrate (100). After the first mask pattern (PR1) is removed, the third mask pattern (PR3) can be formed on the substrate (100).

[0123] A first connection portion (CP1) and a second connection portion (CP2) can be formed in the region exposed by the third mask pattern (PR3). For example, the first connection portion (CP1) and the second connection portion (CP2) can be formed by performing an impurity injection process in which a first impurity is injected into the region exposed by the third mask pattern (PR3).

[0124] The semiconductor device (10) after the third mask pattern (PR3) has been removed may be similar to the semiconductor device (10) shown in Figures 4 and 5.

[0125] In some embodiments, if the third mask pattern (PR3) exposes only one region, only one of the first connection portion (CP1) and the second connection portion (CP2) can be formed. In this case, it may be similar to the semiconductor device (10) shown in Figures 7 and 8.

[0126] The following describes a method for manufacturing a semiconductor device according to several embodiments of the present invention, with reference to Figures 12, 14, 15, and 22. To clarify the explanation, any parts that overlap with the previously mentioned content will be simplified or omitted.

[0127] Figure 22 is a diagram illustrating stage S500 in Figure 12. Figure 22 is a plan view.

[0128] Referring to Figures 12, 14, 15, and 22, a fourth mask pattern (PR4) for forming the semiconductor device (10) shown in Figure 6 can be formed on the substrate (100). The area exposed by the fourth mask pattern (PR4) can form a first connection portion (CP1) and a second connection portion (CP2) in the same manner as in Figure 6.

[0129] The following describes a method for manufacturing a semiconductor device according to several embodiments of the present invention, with reference to Figures 12, 14, 17, 23, and 24. To clarify the explanation, any parts that overlap with the previously mentioned content will be simplified or omitted.

[0130] Figures 23 and 24 are diagrams illustrating step S500 of Figure 12. Figures 23 and 24 may be diagrams after the step described with reference to Figures 14 and 17 has been performed. Figure 23 is a plan view, and Figure 24 is a cross-sectional view taken along line D-D in Figure 23.

[0131] Referring to Figures 12, 14, 17, 23, and 24, a first mask pattern (PR1) can be used to form a first region (R1), a second region (R2), and a pre-fourth region (PRER4) on the substrate (100). After the first mask pattern (PR1) is removed, a fifth mask pattern (PR5) can be formed on the substrate (100).

[0132] The first portion (P31), the second portion (P32), and the third portion (P33) of the third region (R3) can be formed in the region exposed by the fifth mask pattern (PR5). For example, the first portion (P31), the second portion (P32), and the third portion (P33) of the third region (R3) can be formed by an impurity injection process in which a second impurity is injected into the region exposed by the fifth mask pattern (PR5).

[0133] By forming the first part (P31), the second part (P32), and the third part (P33) of the third region (R3), the first connection part (CP1), the second connection part (CP2), the third connection part (CP3), and the fourth connection part (CP4) can be defined. Alternatively, the third region (R3) can be defined including the first part (P31), the second part (P32), the third part (P33), the first connection part (CP1), the second connection part (CP2), the third connection part (CP3), and the fourth connection part (CP4). By defining a part of the pre-fourth region (PRER4) as the third region (R3), the remaining part of the pre-fourth region (PRER4) can be defined as the fourth region (R4).

[0134] The semiconductor device (10) after the fifth mask pattern (PR5) has been removed may be similar to the semiconductor device (10) shown in Figures 9 and 10.

[0135] In some embodiments, as described with reference to Figures 14 and 15, an impurity implantation step is performed in which a first impurity is implanted into a substrate (100) in which a third region (R3) is defined, thereby forming a first connection portion (CP1), a second connection portion (CP2), a third connection portion (CP3), and a fourth connection portion (CP4) in the third region (R3). By forming the first connection portion (CP1), the second connection portion (CP2), the third connection portion (CP3), and the fourth connection portion (CP4) in the third region (R3), a first portion (P31), a second portion (P32), and a third portion (P33) of the third region (R3) can be defined.

[0136] The following describes a method for manufacturing a semiconductor device according to several embodiments of the present invention, with reference to Figures 12, 14, 17, 23, and 25. To clarify the explanation, any parts that overlap with the previously mentioned content will be simplified or omitted.

[0137] Figure 25 is a diagram illustrating step S500 in Figure 12. Figure 25 may be a diagram after the steps described with reference to Figures 14 and 17 have been performed. Figure 25 is a cross-sectional view taken along the line D-D in Figure 23.

[0138] Referring to Figures 12, 14, 17, 23, and 25, when the first portion (P31), second portion (P32), and third portion (P33) of the third region (R3) are formed in the region exposed by the fifth mask pattern (PR5), each of the first portion (P31), second portion (P32), and third portion (P33) of the third region (R3) can be extended to the second region (R2) and connected to the first region (R1).

[0139] The semiconductor device (10) after the fifth mask pattern (PR5) has been removed may be similar to the semiconductor device (10) shown in Figures 9 and 11.

[0140] The above description is merely illustrative of the technical concept of this embodiment, and any person with ordinary skill in the art to which this embodiment belongs could make various modifications and variations without departing from the essential characteristics of this embodiment. Therefore, this embodiment is for illustrative purposes only, not to limit the technical concept of this embodiment, and the scope of the technical concept of this embodiment is not limited by such embodiment. The scope of protection of this embodiment should be interpreted in accordance with the following claims, and all technical concepts within an equivalent scope should be interpreted as being included in the scope of rights of this embodiment.

Claims

1. First-type conductive substrate; A first region of the second conductivity type, disposed on the substrate; A second region located on the first region and containing a first impurity of the first conductivity type; A third region located on the second region and containing the second impurity of the second conductivity type; A fourth region of the first conductivity type, located on the third region; The emitter region of the second conductivity type, which is located on the fourth region; A base region of the first conductivity type, located on the fourth region and separated from the emitter region; A collector region of the second conductivity type, disposed on the substrate and separated from the base region; and Including a collector ring connected to the first region, the third region, and the collector region, Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the collector ring is arranged between the substrate and the collector region so as to surround the second region, the third region, and the fourth region, and is positioned below the collector region.

3. The semiconductor device according to claim 2, wherein the third region is connected to the collector ring.

4. The semiconductor device according to claim 1, wherein the doping level of the second region is higher than the doping level of the fourth region.

5. The third region further includes a first connecting portion that connects a portion of the fourth region and a portion of the second region, The first connection portion is of the first conductivity type. The semiconductor device according to claim 1.

6. The third region further includes a second connecting portion that connects the other portion of the fourth region with the other portion of the second region. The second connection portion is separated from the first connection portion. The second connection portion is of the first conductivity type. The semiconductor device according to claim 5.

7. The aforementioned third region is, A first connecting portion that connects the first portion of the fourth region and the first portion of the second region; A second connecting portion that connects the second portion of the fourth region and the second portion of the second region; A third connecting portion that connects the third portion of the fourth region and the third portion of the second region; The first portion of the third region between the first connecting portion and the second connecting portion; and The second portion of the third region between the second connection portion and the third connection portion, The third region, the first portion and the second portion contain the second impurity of the second conductivity type, The first connection portion, the second connection portion, and the third connection portion are of the first conductivity type. The semiconductor device according to claim 1.

8. The semiconductor device according to claim 7, wherein each of the first and second portions of the third region extends from the third region to the second region and is connected to the first region.

9. The semiconductor device according to claim 8, wherein the second portion of the second region located between the first portion of the extended third region and the second portion of the extended third region contains the first impurity of the first conductivity type.

10. First-type conductive substrate; The first depletion layer on the substrate; The second depletion layer on the first depletion layer; The emitter region on the aforementioned substrate; A third depletion layer, which includes a portion of the emitter region and is located on the second depletion layer; The base region of the first conductivity type, which is disposed on the substrate and separated from the emitter region; and The substrate includes a second conductive type collector region, which is disposed on the substrate and separated from the base region. Semiconductor equipment.

11. A first region of the second conductivity type, disposed on the substrate; A second region located on the first region and containing a first impurity of the first conductivity type; A third region located on the second region and containing a second impurity of the second conductivity type; and Displaced on the third region and including the fourth region of the first conductivity type, The first depletion layer includes the boundary between the first region and the second region, The aforementioned second depletion layer includes the boundary between the aforementioned second region and the aforementioned third region, and the boundary between the aforementioned third region and the aforementioned fourth region. The third depletion layer includes the boundary between the fourth region and the emitter region. The semiconductor device according to claim 10.

12. The second depletion layer includes a first partial depletion layer and a second partial depletion layer within a certain voltage range included in the operating voltage range of the semiconductor device. The first partial depletion layer includes a portion of the second region and a portion of the third region, The second partial depletion layer includes at least a portion of the fourth region and the remaining portion of the third region. The semiconductor device according to claim 10.

13. Steps include providing a substrate of the first conductivity type; A step of forming a second-conductivity emitter region within the substrate; A step of forming the first region of the second conductivity type within the substrate; A step of forming a second region containing the first impurity of the first conductivity type on the first region within the substrate; and The step includes forming a third region containing a second impurity of the second conductivity type and a fourth region of the first conductivity type on the second region within the substrate. A method for manufacturing a semiconductor device.

14. The steps of forming the third and fourth regions are as follows: The step of forming a pre-fourth region on the second region; and The step includes forming a portion of the third region within a portion of the pre-fourth region through the injection of the second impurity, The portion of the third region is formed, and the third region is defined, including the fourth region and the portion of the third region. The method for manufacturing a semiconductor device according to claim 13.

15. The third region further includes a first connecting portion that connects a portion of the fourth region and a portion of the second region, The first connection portion is of the first conductivity type. The method for manufacturing a semiconductor device according to claim 14.

16. The step further includes forming a collector ring within the substrate below the collector region so as to surround the second region, the third region, and the fourth region. The collector is connected to the third region. The method for manufacturing a semiconductor device according to claim 13.

17. The method for manufacturing a semiconductor device according to claim 13, further comprising the step of forming a first connecting portion that connects the third region and the fourth region within the third region.

18. The steps of forming the third and fourth regions are as follows: The step of forming a pre-fourth region on the second region; and The step includes forming the first portion of the third region and the second portion of the third region, respectively, within the first portion of the pre-fourth region and the second portion of the fourth region through the injection of the second impurity, A first connecting portion is formed between the first portion of the third region and the second portion of the third region, connecting the second region and the fourth region. The first connection portion is of the first conductivity type. The method for manufacturing a semiconductor device according to claim 13.

19. The method for manufacturing a semiconductor device according to claim 18, wherein each of the first and second portions of the third region is formed to extend from the third region to the second region and connect to the first region.

20. A step of forming a base region of the first conductivity type, which is disposed within the substrate at a distance from the emitter region; and The step further includes forming the second conductive collector region, which is disposed within the substrate at a distance from the base region. The method for manufacturing a semiconductor device according to claim 13.

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