Display board and display panel

Abstract

A display substrate and a display panel. The display substrate includes a base substrate (10) and a plurality of sub-pixels (12) disposed on the base substrate (10), each of the plurality of sub-pixels (12) including a light-emitting element (121) and a pixel circuit (120) for driving the light-emitting element to emit light. The pixel circuit (120) includes a driving sub-circuit (200), a data writing sub-circuit (230), a threshold compensation sub-circuit (240), a leakage prevention sub-circuit (270), and a memory sub-circuit (280). The display substrate includes a display sub-circuit (280) including a storage capacitor (Cst1), the storage capacitor including a first electrode plate (CC1), a second electrode plate (CC2), and a third electrode plate (CC3), the first electrode plate (CC1) and the third electrode plate (CC3) being electrically connected to each other and located in different layers with respect to the base substrate, and the second electrode plate (CC2) at least partially overlapping the first electrode plate and the third electrode plate in a direction perpendicular to the base substrate. This display substrate can increase the size of the storage capacitor without increasing the occupied space.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display panel.

Background Art

[0002] With the rapid development of the organic light-emitting diode (OLED) in the display field, the requirements for the display effect are increasing. Due to advantages such as high display quality, the application range of high-resolution display devices is also expanding. An important technology in the display field is the design of pixel circuits.

Summary of the Invention

Means for Solving the Problems

[0003] At least one embodiment of the present disclosure provides a display board comprising a base board and a plurality of subpixels mounted on the base board, each of the plurality of subpixels comprising a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, the pixel circuit comprising a drive subcircuit, a data writing subcircuit, a threshold compensation subcircuit, a leakage protection subcircuit, and a storage subcircuit, the drive subcircuit comprising a control terminal, a first terminal, and a second terminal and configured to control the drive current flowing through the light-emitting element, the data writing subcircuit connected to the first terminal, a data line, and a scan signal line of the drive subcircuit and configured to write a data signal provided by the data line to the first terminal of the drive subcircuit in response to a gate scan signal provided by the scan signal line, and the threshold compensation subcircuit connected to the second terminal, the leakage protection subcircuit, and the scan signal line The drive subcircuit is configured to write a compensation signal based on the data signal to the control terminal of the drive subcircuit in response to a gate scan signal provided by the scan signal line, the leakage protection subcircuit is connected to the control terminal of the drive subcircuit, the threshold compensation subcircuit, the storage subcircuit and the leakage protection control signal line and is configured to suppress leakage at the control terminal of the drive subcircuit, the storage subcircuit is connected to the control terminal of the drive subcircuit and the first voltage line and is arranged to store the compensation signal and hold it at the control terminal of the drive subcircuit, the storage subcircuit includes a storage capacitor, the storage capacitor includes a first electrode plate, a second electrode plate and a third electrode plate, the first electrode plate and the third electrode plate are electrically connected to each other and are located in different layers relative to the base substrate, and the second electrode plate at least partially overlaps the first electrode plate and the third electrode plate in a direction perpendicular to the base substrate.

[0004] For example, in a display substrate according to at least one embodiment of the present disclosure, the second electrode plate is located between the first electrode plate and the third electrode plate in a direction perpendicular to the base substrate, the first electrode plate is connected to the control terminal of the drive subcircuit, the second electrode plate is connected to the first voltage line, and the third electrode plate is connected to the control terminal of the drive subcircuit.

[0005] For example, in a display board according to at least one embodiment of the present disclosure, the threshold compensation subcircuit includes a threshold compensation transistor, the data writing subcircuit includes a data writing transistor, the active layer of the threshold compensation transistor is formed integrally with the active layer of the data writing transistor, the orthogonal projections of the active layer of the threshold compensation transistor and the active layer of the data writing transistor onto the base substrate are located on either side of the orthogonal projection of the storage capacitance onto the base substrate, the gates of the threshold compensation transistor and the gates of the data writing transistor are parallel in a first direction, and the gates of the threshold compensation transistor and the gates of the data writing transistor are formed integrally with the scan signal line.

[0006] For example, in a display board according to at least one embodiment of the present disclosure, the leakage protection subcircuit includes a leakage protection transistor, the active layer of the leakage protection transistor, the active layer of the threshold compensation transistor, and the active layer of the data writing transistor all extend along a second direction and are arranged side by side along a first direction intersecting the second direction, the orthogonal projection of the active layer of the leakage protection transistor onto the base substrate is located on the side of the orthogonal projection of the active layer of the data writing transistor onto the base substrate that is away from the orthogonal projection of the active layer of the data writing transistor onto the base substrate.

[0007] For example, in a display board according to at least one embodiment of the present disclosure, the gate of the leakage protection transistor is formed integrally with the leakage protection control signal line, the leakage protection control signal line extends along the first direction, and the orthogonal projection of the leakage protection control signal line onto the base board is located between the orthogonal projection of the scan signal line onto the base board and the orthogonal projection of the storage capacitance onto the base board.

[0008] For example, in a display board according to at least one embodiment of the present disclosure, the leakage protection control signal line includes a first sub-control signal line and a second sub-control signal line, wherein the orthogonal projection of the first sub-control signal line onto the base board at least partially overlaps with the orthogonal projection of the second sub-control signal line onto the base board.

[0009] For example, in a display substrate according to at least one embodiment of the present disclosure, the gate of the leakage protection transistor includes a first gate and a second gate, the first gate being formed integrally with the first sub-control signal line, and the second gate being formed integrally with the second sub-control signal line, and in a direction perpendicular to the base substrate, the active layer of the leakage protection transistor is located between the first gate and the second gate.

[0010] For example, in a display substrate according to at least one embodiment of the present disclosure, the active layer of the leakage prevention transistor and the third electrode plate are located on the same layer, and the materials of the active layer of the leakage prevention transistor and the third electrode plate include an oxide semiconductor material.

[0011] For example, in a display board according to at least one embodiment of the present disclosure, the pixel circuit further includes a first reset subcircuit, the first reset subcircuit is connected to the threshold compensation subcircuit, the leakage prevention subcircuit, a first initial signal line, and a first reset control signal terminal, and is configured to apply an initial voltage provided by the first initial signal line to the control terminal of the drive subcircuit via the leakage prevention subcircuit in response to a reset control signal received at the first reset control signal terminal.

[0012] For example, in a display substrate according to at least one embodiment of the present disclosure, the first reset subcircuit includes a first reset transistor, the active layer of the first reset transistor is formed integrally with the active layer of the threshold compensation transistor, and the orthogonal projection of the active layer of the first reset transistor onto the base substrate is located on the side of the orthogonal projection of the storage capacitance onto the base substrate of the orthogonal projection of the active layer of the threshold compensation transistor onto the base substrate.

[0013] For example, a display substrate according to at least one embodiment of the present disclosure further includes a first connecting electrode, the first terminal of the first connecting electrode being integrally formed with the first pole of the first reset transistor and the first pole of the threshold compensation transistor and connected to the active layer of the threshold compensation transistor and the active layer of the first reset transistor, respectively, via vias penetrating an insulating layer; and the second terminal of the first connecting electrode being integrally formed with the first pole of the leakage prevention transistor and connected to the active layer of the leakage prevention transistor via vias penetrating an insulating layer.

[0014] For example, a display substrate according to at least one embodiment of the present disclosure further includes a second connecting electrode, the first terminal of the second connecting electrode being integrally formed with the second electrode of the leakage prevention transistor and connected to the active layer of the leakage prevention transistor via a via penetrating an insulating layer, the second terminal of the second connecting electrode being connected to the first electrode plate of the storage capacitor via a via penetrating an insulating layer, and the third terminal of the second connecting electrode being connected to the third electrode plate of the storage capacitor via a via penetrating an insulating layer.

[0015] For example, a display substrate according to at least one embodiment of the present disclosure further includes a parasitic capacitance connected to the second electrode of the leakage protection transistor and the scan signal line, wherein the first electrode plate of the parasitic capacitance is formed integrally with the scan signal line, the second electrode plate of the parasitic capacitance at least partially overlaps the first electrode plate of the parasitic capacitance in a direction perpendicular to the base substrate, the second electrode plate of the parasitic capacitance and the third electrode plate of the storage capacitance are located in the same layer, the orthogonal projection of the second electrode plate of the parasitic capacitance onto the base substrate is located between the orthogonal projection of the active layer of the threshold compensation transistor onto the base substrate and the orthogonal projection of the active layer of the data writing transistor onto the base substrate, and the second electrode plate of the parasitic capacitance is connected to the fourth terminal of the second connecting electrode via a via penetrating an insulating layer.

[0016] For example, in a display substrate according to at least one embodiment of the present disclosure, the drive subcircuit includes a drive transistor, the gate of the drive transistor is formed integrally with the first electrode plate of the storage capacitor, the active layer of the drive transistor and the active layer of the data writing transistor are formed integrally with the active layer of the threshold compensation transistor, and the orthogonal projection of the active layer of the drive transistor onto the base substrate lies between the orthogonal projection of the active layer of the data writing transistor onto the base substrate and the orthogonal projection of the active layer of the threshold compensation transistor onto the base substrate.

[0017] For example, in a display substrate according to at least one embodiment of the present disclosure, the pixel circuit further includes a first light emission control subcircuit and a second light emission control subcircuit, the first light emission control subcircuit being connected to a first voltage line, a first terminal of the drive subcircuit and a light emission control line, and configured to apply a first voltage provided by the first voltage line to the first terminal of the drive subcircuit in response to a light emission control signal provided by the light emission control line; the second light emission control subcircuit being connected to a second terminal of the drive subcircuit, a first terminal of the light-emitting element and the light emission control line, and configured to apply a drive current to the first terminal of the light-emitting element in response to a light emission control signal provided by the light emission control line, the light emission control line extending along the first direction, the orthogonal projection of the light emission control line onto the base substrate being located on the side of the orthogonal projection of the storage capacitance onto the base substrate that is away from the orthogonal projection of the scan signal line onto the base substrate.

[0018] For example, in a display substrate according to at least one embodiment of the present disclosure, the first light emission control subcircuit includes a first light emission control transistor, and the second light emission control subcircuit includes a second light emission control transistor, wherein the active layer of the first light emission control transistor, the active layer of the second light emission control transistor, the active layer of the data writing transistor, and the active layer of the threshold compensation transistor are formed integrally with the active layer of the drive transistor, and the orthogonal projection of the active layer of the drive transistor onto the base substrate lies between the orthogonal projection of the active layer of the data writing transistor and the active layer of the first light emission control transistor onto the base substrate and the orthogonal projection of the active layer of the second light emission control transistor and the active layer of the threshold compensation transistor onto the base substrate.

[0019] For example, in a display board according to at least one embodiment of the present disclosure, the leakage prevention control signal provided by the leakage prevention control signal line and the light emission control signal provided by the light emission control signal line are the same or different.

[0020] For example, in a display substrate according to at least one embodiment of the present disclosure, the first voltage line includes a first sub-voltage line extending along the second direction and a second sub-voltage line extending along the first direction, wherein the first sub-voltage line and the second sub-voltage line are located on different layers, the orthogonal projection of the first sub-voltage line onto the base substrate is located between the orthogonal projection of the active layer of the data writing transistor onto the base substrate and the orthogonal projection of the active layer of the threshold compensation transistor onto the base substrate, and at least partially overlaps with the orthogonal projection of the second electrode plate of the parasitic capacitance onto the base substrate, and the second sub-voltage line is formed integrally with the second electrode plate of the storage capacitance.

[0021] For example, a display substrate according to at least one embodiment of the present disclosure further includes a third connecting electrode, the first terminal of the third connecting electrode being integrally formed with the first pole of the first light-emitting control transistor and connected to the active layer of the first light-emitting control transistor via a via penetrating an insulating layer, the second terminal of the third connecting electrode being connected to the second electrode plate of the storage capacitor via a via penetrating an insulating layer, and the third terminal of the third connecting electrode being connected to the first projection of the first sub-voltage line via a via penetrating an insulating layer.

[0022] For example, in a display substrate according to at least one embodiment of the present disclosure, the first sub-voltage line further includes a second projection, the second projection being "revolving", and the orthogonal projection of the second projection onto the base substrate at least partially overlaps with the orthogonal projection of the active layer of the leakage protection transistor onto the base substrate.

[0023] At least one embodiment of the present disclosure further provides a display panel including a display substrate as described in any one of the above embodiments. [Brief explanation of the drawing]

[0024] To more clearly illustrate the technical concepts of the embodiments of this disclosure, the drawings of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description relate only to some embodiments of this disclosure and do not limit the disclosure. [Figure 1] Schematic block diagram of a display substrate according to some embodiments of the present disclosure. [Figure 2A] Schematic structural diagram of a pixel circuit according to some embodiments of the present disclosure. [Figure 2B] Circuit timing diagram of a pixel circuit according to some embodiments of the present disclosure. [Figure 2C] Circuit timing diagram of another pixel circuit according to some embodiments of the present disclosure. [Figure 3] Schematic layout diagram of a pixel circuit according to some embodiments of the present disclosure. [Figure 4A-4O] Schematic diagram of each structural layer of a pixel circuit according to some embodiments of the present disclosure. [Figure 5A] Schematic diagram obtained by splicing cross-sectional structures corresponding to three regions of the second light emission control transistor, leakage prevention transistor, and storage capacitor in FIG. 3. [Figure 5B] Another schematic cross-sectional view according to some embodiments of the present disclosure. [Figure 5C] Another schematic cross-sectional view according to some embodiments of the present disclosure. [Figure 6] Schematic diagram in which some structures are stacked according to some embodiments of the present disclosure. [Figure 7] Schematic diagram in which some structures are stacked according to some embodiments of the present disclosure. [Figure 8] Schematic diagram in which some structures are stacked according to some embodiments of the present disclosure. [Figure 9] Schematic diagram of a display panel according to at least one embodiment of the present disclosure.

Mode for Carrying Out the Invention

[0025] To further clarify the purpose, technical proposal and advantages of the embodiments of this disclosure, the technical proposal of the embodiments of this disclosure is described below clearly and completely, along with the drawings of the embodiments of this disclosure. Clearly, the embodiments described are partial embodiments of this disclosure, not all embodiments. All other embodiments obtained by a person skilled in the art without requiring any creative work based on the embodiments of this disclosure described are all within the scope of this disclosure.

[0026] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by a person with general skill in the art to which this disclosure belongs. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, number, or importance, but are used solely to distinguish different components. Similar terms such as “includes” or “contains” mean that the element or object preceding the word covers the elements or objects and their equivalents listed after the word without excluding other elements or objects. Similar terms such as “connected” or “linked” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as “up,” “down,” “left,” and “right” are used only to describe relative positions, and if the absolute position of the described object changes, its relative position may change accordingly.

[0027] In order to maintain clarity and brevity in the following descriptions of the embodiments of this disclosure, this disclosure omits detailed descriptions of some known functions and known components.

[0028] Because the stability of this gate voltage is related to the display uniformity and display quality such as flicker of the display panel, pixel circuits manufactured based on LTPS (Low Temperature Poly-silicon) require attention to the stability of the gate voltage of the drive transistor DTFT during operation. In conventional pixel circuits manufactured based on LTPS, the leakage current of the compensation transistor STFT cannot meet the demand for operation at low frequencies (1-30Hz), leading to display problems such as reduced compensation capability and increased flicker.

[0029] Oxide semiconductor thin-film transistors (Oxide TFTs) possess high hysteresis characteristics and low leakage current (less than 1e-14A), and their low mobility can compensate for these shortcomings. Therefore, by using oxide semiconductor thin-film transistors instead of compensation transistors (STFTs) manufactured based on LTPS, low leakage current performance can be achieved, and the gate voltage stability of the driving transistor (DTFT) can be ensured. However, based on conventional processes, the size of oxide semiconductor thin-film transistors is larger than that of transistors manufactured based on LTPS, and the location of the film layers is different. This leads to difficulties in pixel layout due to issues such as the addition of vias and insulating layers, and improvements are needed.

[0030] Furthermore, in the field of displays, the demand for resolution is increasing, and display panels are gradually showing a trend toward higher pixel density (Pixels Per Inch, abbreviated as PPI). For example, the resolution of mainstream displays has reached 460 PPI or higher. The demand for high pixel density reduces the pixel layout space and thus the pixel storage capacitance. However, a smaller storage capacitance is detrimental to the stability of the gate potential of the drive transistor, affecting the display uniformity of the display panel and causing flicker.

[0031] At least some embodiments of the present disclosure provide a display substrate and a display panel, the display substrate comprising a base substrate and a plurality of subpixels mounted on the base substrate, each of the plurality of subpixels comprising a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, the pixel circuit comprising a drive subcircuit, a data writing subcircuit, a threshold compensation subcircuit, a leakage protection subcircuit and a storage subcircuit, the drive subcircuit comprising a control terminal, a first terminal and a second terminal and configured to control the drive current flowing through the light-emitting element, the data writing subcircuit connected to the first terminal of the drive subcircuit, a data line and a scan signal line and configured to write a data signal provided by the data line to the first terminal of the drive subcircuit in response to a gate scan signal provided by the scan signal line, the threshold compensation subcircuit connected to the second terminal of the drive subcircuit, a leakage protection subcircuit and A drive subcircuit is connected to the scan signal line and configured to write a compensation signal based on a data signal to the control terminal of the drive subcircuit in response to a gate scan signal provided by the scan signal line; a leakage protection subcircuit is connected to the control terminal of the drive subcircuit, the threshold compensation subcircuit, the memory subcircuit and the leakage protection control signal line and configured to suppress leakage at the control terminal of the drive subcircuit; a memory subcircuit is connected to the control terminal of the drive subcircuit and the first voltage line and configured to store the compensation signal and hold it at the control terminal of the drive subcircuit; the memory subcircuit includes a storage capacitor, which includes a first electrode plate, a second electrode plate and a third electrode plate, the first electrode plate and the third electrode plate being electrically connected to each other and located in different layers relative to the base substrate, and the second electrode plate at least partially overlapping the first electrode plate and the third electrode plate in a direction perpendicular to the base substrate.

[0032] In the display substrate according to the embodiment of this disclosure, by employing a storage capacitor having at least three electrode plates in the pixel circuit, the size of the storage capacitor can be effectively increased without increasing the occupied space, the capacitance value of the storage capacitor can be increased, and the stability of the gate potential of the drive transistor can be improved, thereby mitigating the problem of insufficient pixel capacitance under the demand for high pixel density.

[0033] The following describes in detail some embodiments of this disclosure, accompanied by drawings, but this disclosure is not limited to these specific embodiments.

[0034] Figure 1 is a schematic block diagram of a display substrate according to some embodiments of the present disclosure, Figure 2A is a schematic diagram of the structure of a pixel circuit according to some embodiments of the present disclosure, and Figure 2B is a circuit timing diagram of a pixel circuit according to some embodiments of the present disclosure.

[0035] For example, as shown in Figure 1, the display board 100 according to an embodiment of the present disclosure includes a base board 10, a plurality of sub-pixels 12 installed on the base board 10, a first voltage line, data lines, scan signal lines, light emission control line, initial signal line, and leakage prevention control line. It should be noted that Figure 1 does not show the first voltage line, data lines, scan signal line, light emission control line, initial signal line, and leakage prevention control line.

[0036] For example, the display substrate 100 can be used in a display panel, such as an active-matrix organic light-emitting diode (AMOLED) display panel. The display substrate 100 may also be an array substrate.

[0037] For example, the base substrate 10 may be a flexible substrate or a rigid substrate. For example, the base substrate 10 may be made of glass, plastic, silver or other suitable material, and the embodiments of this disclosure are not limited thereto.

[0038] For example, each subpixel 12 includes a light-emitting element 121 and a pixel circuit 120, with the light-emitting element 121 located on the side of the pixel circuit 120 away from the base substrate 10. The subpixels 12 shown in Figure 1 are merely to illustrate that each subpixel 12 includes two components, the light-emitting element 121 and the pixel circuit 120, and are not intended to limit the positional relationship between the light-emitting element 121 and the pixel circuit 120. In some examples, the light-emitting element 121 and the pixel circuit 120 are installed overlapping in a direction perpendicular to the base substrate 10.

[0039] For example, the pixel circuit 120 is configured to drive the light-emitting element 121 to emit light. The pixel circuit and its operating principle will be explained below with reference to Figures 2A and 2B.

[0040] For example, as shown in Figure 2A, the pixel circuit 120 includes a drive subcircuit 200, a first reset subcircuit 210, a second reset subcircuit 220, a data writing subcircuit 230, a threshold compensation subcircuit 240, a first light emission control subcircuit 250, a second light emission control subcircuit 260, a leakage current prevention subcircuit 270, and a storage subcircuit 280.

[0041] For example, as shown in Figure 2A, the drive sub-circuit 200 includes a control terminal, a first terminal, and a second terminal, and is configured to control the drive current flowing through the light-emitting element 121. For example, the control terminal of the drive sub-circuit 200 is connected to the first node N1, the first terminal is connected to the second node N2, and the second terminal is connected to the third node N3.

[0042] The data writing subcircuit 230 is connected to the first terminal of the drive subcircuit 200, the data line Vda, and the scan signal line Ga, and is configured to write the data signal provided by the data line Vda to the first terminal of the drive subcircuit 200 in response to the gate scan signal provided by the scan signal line Ga.

[0043] The threshold compensation subcircuit 240 is connected to the second terminal of the drive subcircuit 200, the leakage prevention subcircuit 270, and the scan signal line Ga, and is configured to write a compensation signal based on the data signal to the control terminal of the drive subcircuit 200 in response to the gate scan signal provided by the scan signal line Ga.

[0044] The leakage current prevention sub-circuit 270 is connected to the control terminal of the drive sub-circuit 200, the threshold compensation sub-circuit 240, the memory sub-circuit 280, and the leakage current prevention control signal line EM2, and is configured to suppress leakage current at the control terminal of the drive sub-circuit 200.

[0045] The first light emission control subcircuit 250 is connected to the first voltage line VDD, the first terminal of the drive subcircuit 200, and the light emission control signal line EM1, and is configured to apply the first voltage provided by the first voltage line VDD to the first terminal of the drive subcircuit 200 in response to the light emission control signal provided by the light emission control signal line EM1.

[0046] The second light emission control subcircuit 260 is connected to the second terminal of the drive subcircuit 200, the first terminal of the light-emitting element 121, and the light emission control signal line EM1, and is configured to apply a drive current to the first terminal of the light-emitting element 121 in response to the light emission control signal provided by the light emission control signal line EM1.

[0047] The first reset subcircuit 210 is connected to the threshold compensation subcircuit 240, the leakage prevention subcircuit 270, the first initial signal line Vinit1, and the first reset control signal terminal Re1, and is configured to apply an initial voltage provided by the first initial signal line to the control terminal of the drive subcircuit 200 via the leakage prevention subcircuit 270 in response to the reset control signal received at the first reset control signal terminal Re1.

[0048] For example, when the first reset subcircuit 210 transmits the initial voltage output from the first initial signal line Vinit1 to the control terminal of the drive subcircuit 200 to initialize the control terminal of the drive subcircuit 200, the leakage prevention subcircuit 270 is configured to conduct under the control of the leakage prevention control signal, thereby transmitting the initial voltage to the control terminal of the drive subcircuit 200 (i.e., the first node N1) via the leakage prevention subcircuit 270 to initialize the control terminal of the drive subcircuit 200.

[0049] The second reset subcircuit 220 is connected to the second initial signal line Vinit2, the second reset control signal terminal Re2, and the first terminal of the light-emitting element 121, and is configured to apply an initial voltage provided by the second initial signal line Vinit2 to the first terminal of the light-emitting element 121 in response to the reset control signal received by the second reset control signal terminal Re2.

[0050] For example, the initial voltage provided by the first initial signal line Vinit1 and the initial voltage provided by the second initial signal line Vinit2 may be the same or different.

[0051] The memory sub-circuit 280 is connected to the control terminal and the first voltage line VDD of the drive sub-circuit 200 and is configured to store the compensation signal and hold it at the control terminal of the drive sub-circuit 200.

[0052] For example, the memory subcircuit 280 includes a storage capacity Cst1, which includes a first electrode plate, a second electrode plate, and a third electrode plate, the first and third electrode plates being electrically connected to each other and located in different layers relative to the base substrate, and the second electrode plate overlapping at least partially with the first and third electrode plates in a direction perpendicular to the base substrate. By setting up at least three stacked electrode plates and electrically connecting the first and third electrode plates to each other, i.e., having the same potential as the first and third electrode plates and different from the potential of the second electrode plate, a storage capacity with a three-layer structure is formed, and in this way the area of ​​the storage capacity can be increased without increasing the occupied space, and the capacity value of the storage capacity Cst1 can be increased. For example, the storage capacity value of the embodiments of this disclosure may increase by 60% to 80% from the capacity value of a conventional two-layer system. For example, a capacity value of 60 fF may increase to 96 fF-108 fF, or even to 100 fF, and the embodiments of this disclosure are not limited thereto.

[0053] In the embodiments of this disclosure, in a pixel circuit including a drive subcircuit 200, a first reset subcircuit 210, a second reset subcircuit 220, a data writing subcircuit 230, a threshold compensation subcircuit 240, a first light emission control subcircuit 250, a second light emission control subcircuit 260, a leakage prevention subcircuit 270, and a storage subcircuit 280, by using a storage capacitor having at least three electrode plates, the size of the storage capacitor can be effectively increased without increasing the occupied space, the capacitance value of the storage capacitor can be increased, the stability of the gate potential of the drive transistor can be improved, and the problem of insufficient storage capacitor under the demand for high pixel density can be mitigated.

[0054] For example, the pixel circuit 120 may further include a parasitic capacitance Cst2, which is connected to the control terminal of the drive sub-circuit 200 and the scan signal line Ga, and is configured to adjust the voltage at the control terminal of the drive sub-circuit 200 in response to the scan signal provided by the scan signal line Ga. For example, based on the principle of charge conservation, the parasitic capacitance can increase the voltage at the control terminal of the drive sub-circuit 200 when the scan signal provided by the scan signal line Ga changes from a low level to a high level. The drive current of the pixel circuit is related to the voltage at the control terminal of the drive sub-circuit 200, and the voltage at the control terminal of the drive sub-circuit 200 is related to the data signal provided by the data line Vda, which has an upper limit, for example, around 6V or 7V. In order to achieve a low drive current, the data line Vda needs to provide a high data signal voltage, and therefore, in actual use, this demand may exceed the upper limit of the data signal voltage, thereby preventing the ideal drive current from being achieved. However, by using the parasitic capacitance Cst2 to increase the voltage at the control terminal of the drive sub-circuit 200, the data line Vda can provide a slightly lower data signal voltage. This allows for the realization of a low drive current even under the influence of the parasitic capacitance Cst2, thus avoiding the situation where the voltage demand for the data signal exceeds its upper voltage limit, preventing the realization of a low drive current.

[0055] For example, as shown in Figure 2A, the second electrode of the light-emitting element 121 is electrically connected to the second voltage line VSS to receive the second voltage.

[0056] For example, the light-emitting element 121 may be a light-emitting diode. The light-emitting diode may be a micro light-emitting diode (micro LED), an organic light-emitting diode (OLED), or a quantum dot light-emitting diode (QLED). The light-emitting element 121 is configured to receive a light emission signal (for example, a drive current) when operating and to emit light of an intensity corresponding to this light emission signal. The light-emitting element 121 may include a first electrode, a second electrode, and a light-emitting layer placed between the first electrode and the second electrode. The first electrode of the light-emitting element 121 may be an anode, and the second electrode of the light-emitting diode may be a cathode. It should be noted that in embodiments of this disclosure, the light-emitting layer of the light-emitting element may include the electroluminescent layer itself and other common layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer. Typically, the light-emitting element 121 has a light emission threshold voltage, and emits light when the voltage between the first and second electrodes of the light-emitting element 121 is equal to or greater than the light emission threshold voltage. In actual applications, the specific structure of the light-emitting element 121 may be designed and determined according to the actual application environment, and is not limited thereto.

[0057] For example, as shown in Figure 2A, the drive subcircuit 200 includes a drive transistor T3, the first reset subcircuit 210 includes a first reset transistor T1, the second reset subcircuit 220 includes a second reset transistor T7, the data write subcircuit 230 includes a data write transistor T4, the threshold compensation subcircuit 240 includes a threshold compensation transistor T2, the first light emission control subcircuit 250 includes a first light emission control transistor T5, the second light emission control subcircuit 260 includes a second light emission control transistor T6, and the leakage prevention subcircuit 270 includes a leakage prevention transistor T8.

[0058] The control terminal of the drive subcircuit 200 includes the gate of the drive transistor T3, the first terminal of the drive subcircuit 200 includes the first pole of the drive transistor T3, and the second terminal of the drive subcircuit 20 includes the second pole of the drive transistor T3. The gate of the drive transistor T3 is electrically connected to the first node N1, the first pole of the drive transistor T3 is electrically connected to the second node N2, and the second pole of the drive transistor T3 is electrically connected to the third node N3.

[0059] The gate of the data writing transistor T4 is electrically connected to the scan signal line Ga, the first pole of the data writing transistor T4 is electrically connected to the data line Vda, and the second pole of the data writing transistor T4 is electrically connected to the second node N2, which is electrically connected to the first pole of the drive transistor T3.

[0060] The gate of threshold compensation transistor T2 is electrically connected to the scan signal line Ga, the first pole of threshold compensation transistor T2 is electrically connected to the first pole of leakage protection transistor T8, and the second pole of threshold compensation transistor T2 is electrically connected to the third node N3, i.e., the second pole of drive transistor T3.

[0061] The gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal line EM1 to receive the light-emitting control signal, the first pole of the first light-emitting control transistor T5 is electrically connected to the first voltage line VDD to receive the first voltage, and the second pole of the first light-emitting control transistor T5 is electrically connected to the second node N2, that is, electrically connected to the first pole of the drive transistor T3.

[0062] The gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line EM1 to receive the light-emitting control signal. The first pole of the second light-emitting control transistor T6 is electrically connected to the fourth node N4, i.e., electrically connected to the first electrode of the light-emitting element 121. The second pole of the second light-emitting control transistor T6 is electrically connected to the third node N3, i.e., electrically connected to the second pole of the drive transistor T3.

[0063] The gate of the first reset transistor T1 is electrically connected to the first reset control signal terminal Re1, the first pole of the first reset transistor T1 is electrically connected to the first pole of the threshold compensation transistor T2 and the first pole of the leakage prevention transistor T8, and the second pole of the first reset transistor T1 is electrically connected to the first initial signal line Vinit1.

[0064] The gate of the second reset transistor T7 is electrically connected to the second reset control signal terminal Re2, the first pole of the second reset transistor T7 is electrically connected to the second initial signal line Vinit2, and the second pole of the second reset transistor T7 is electrically connected to the fourth node N4, i.e., electrically connected to the first electrode of the light-emitting element 121.

[0065] The gate of the leakage protection transistor T8 is electrically connected to the leakage protection control signal line EM2, the first pole of the leakage protection transistor T8 is electrically connected to the first pole of the threshold compensation transistor T2 and the first pole of the first reset transistor T1, and the second pole of the leakage protection transistor T8 is electrically connected to the first node N1, i.e., electrically connected to the gate of the drive transistor T3.

[0066] For example, if a leakage protection transistor T8 is not installed in the pixel circuit, the leakage path of the gate of the drive transistor T3 is through transistors T1 and T2, and in some examples, the first reset transistor T1 and the threshold compensation transistor T2 may be installed as dual-gate transistors to suppress the leakage current. If a leakage protection transistor T8 is installed in the pixel circuit, the leakage path of the gate of the drive transistor T3 is through transistors T8-T1 and T8-T2, and the path leakage current is lower compared to the leakage path of transistors T1 and T2 in the original pixel circuit. Since the leakage current of the leakage protection transistor T8 is an important reference indicator, the first reset transistor T1 and the threshold compensation transistor T2 may be installed as single-gate transistors to save space. The leakage current prevention transistor T8 may be an oxide semiconductor thin-film transistor (Oxide TFT). Oxide semiconductor thin-film transistors have good hysteresis characteristics and low leakage current (1e-14A or less), and because they have low mobility, the voltage stability of the gate of the driving transistor can be ensured by using an oxide semiconductor thin-film transistor.

[0067] For example, the first electrode plate CC1 and the third electrode plate CC3 of the storage capacitor Cst1 are both electrically connected to the control terminals of the drive sub-circuit 200, and the second electrode plate CC2 of the storage capacitor Cst1 is electrically connected to the first voltage line VDD to receive the first voltage. In a direction perpendicular to the base substrate, the second electrode plate is located between the first electrode plate and the third electrode plate.

[0068] For example, one of the voltages output from the first voltage line VDD and the second voltage line VSS is a high voltage, and the other is a low voltage. For example, in the embodiment shown in Figure 2A, the voltage output from the first voltage line VDD is a constant first voltage which is a positive voltage, while the voltage output from the second voltage line VSS is a constant second voltage which is a negative voltage. For example, in some cases, the second voltage line VSS may be grounded.

[0069] It should be noted that the transistors adopted in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switch devices with the same characteristics. The thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, polysilicon thin film transistors, etc. For example, in the description of the embodiments of the present disclosure, the driving transistor T3, the data writing transistor T4, the threshold compensation transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, the first reset transistor T1, and the second reset transistor T7 may all be low temperature polysilicon (LTPS) thin film transistors, and the leakage prevention transistor T8 may be an oxide semiconductor thin film transistor. Since the source and drain of the transistor may be structurally symmetric, the source and drain may have no physical structural difference. In the embodiments of the present disclosure, in order to distinguish the transistors, except for the gate as the control pole, it is directly described that one pole is the first pole and the other pole is the second pole. Therefore, the first pole and the second pole of all or some of the transistors in the embodiments of the present disclosure can be exchanged as required.

[0070] For example, in a specific implementation, in the embodiments of the present disclosure, the initial voltage V output from the first initial signal line Vinit1 and the second initial signal line Vinit2 i and the voltage V output from the second voltage line VSS s are such that V i -V s can satisfy <VEL>. VEL represents the light emission threshold voltage of the light emitting element 121. In some embodiments, the initial voltage of the first initial signal line Vinit1 and the initial voltage of the second initial signal line Vinit2 may be different. For example, the initial voltage of the first initial signal line Vinit1 may be smaller than the initial voltage of the second initial signal line Vinit2. For example, the initial voltage of the first initial signal line Vinit1 is 0.5V to 1V smaller than the initial voltage of the second initial signal line Vinit2.

[0071] For example, the first reset control signal terminal Re1 of the pixel circuit in row y (where y is an integer greater than 1) and the second reset control signal terminal Re2 of the pixel circuit in row y-1 are connected to a first reset signal line (not shown), and the first reset control signal terminal Re1 of the pixel circuit in row y+1 and the second reset control signal terminal Re2 of the pixel circuit in row y are connected to a second reset signal line (not shown). That is, each subpixel in each row is connected to the first reset control signal terminal Re1 and the second reset control signal terminal Re2, respectively, by being connected to two reset signal lines (the first reset signal line and the second reset signal line). For example, one reset signal line (e.g., a first reset signal line) is electrically connected to the gate of a first reset transistor T1 in the subpixel of the current row (i.e., the first reset control signal terminal Re1) to provide a first reset control signal, and this first reset signal line is further electrically connected to the gate of a second reset transistor T7 in the subpixel of the previous row (i.e., the second reset control signal terminal Re2) to provide a second reset control signal to the subpixel of the previous row, and another reset signal line (e.g., a second reset signal line) is electrically connected to the gate of a first reset transistor T1 corresponding to the pixel circuit of the next row (i.e., the pixel circuit row where scan lines are located that are turned on sequentially after the scan signal lines of the current row according to the scan order of the scan signal lines) to provide a first reset control signal to the subpixel of the next row, and this second reset signal line is further electrically connected to the gate of a second reset transistor T7 in the pixel circuit of the current row (i.e., the second reset control signal terminal Re2). In other words, one reset signal line is shared by two adjacent rows of subpixels.

[0072] For example, the second pole of the first reset transistor T1 in the y-th row pixel circuit and the first pole of the second reset transistor T7 in the y-1 row pixel circuit are connected to the first initial signal line Vinit1, and the second pole of the first reset transistor T1 in the y+1 row pixel circuit and the first pole of the second reset transistor T7 in the y row pixel circuit are connected to the second initial signal line Vinit2. That is, each subpixel in each row is connected to two initial signal lines (the first initial signal line and the second initial signal line), and these are connected to the first reset transistor T1 and the second reset transistor T7, respectively. For example, one initial signal line (e.g., first initial signal line Vinit1) is electrically connected to a first reset transistor T1 in the subpixel of the current row to provide a first initial voltage, and this first initial signal line Vinit1 is further connected to a second reset transistor T7 in the subpixel of the previous row to provide a second initial signal to the subpixel of the previous row, and another initial signal line (e.g., second initial signal line Vinit2) is electrically connected to a first reset transistor T1 corresponding to the pixel circuit of the next row (i.e., the pixel circuit row where the scan lines that turn on sequentially after the scan signal lines of the current row, according to the scan order of the scan signal lines), to provide a first initial control signal to the subpixel of the next row, and this second initial signal line Vinit2 is further electrically connected to a second reset transistor T7 in the pixel circuit of the current row. In other words, one initial signal line is shared by two adjacent rows of subpixels.

[0073] The following describes the operation process of the pixel circuit shown in Figure 2A, along with Figure 2B.

[0074] For example, as shown in Figure 2B, Re1 represents a first reset control signal provided by a first reset control signal line, Re2 represents a second reset control signal provided by a second reset control signal line, Ga represents a gate scan signal output from a scan signal line Ga, EM1 represents a light emission control signal output from a light emission control signal line EM1, EM2 represents a ground fault prevention control signal output from a ground fault prevention control signal line EM2, and Vda represents a data signal output from a data line Vda. It should be noted that in the embodiments of this disclosure, the symbols Re1, Re2, Ga, EM1, EM2, Vda, and VDD represent signal lines as well as signals on those signal lines.

[0075] For example, in the operation process of one display frame of one pixel circuit, the operation process of the pixel driving circuit has three stages: initialization stage T10, data writing and compensation stage T20, and light emission stage T30.

[0076] In the initialization stage T10, the first reset control signal Re1 and the second reset control signal Re2 are at a low level, the light emission control signal EM1, the leakage prevention control signal EM2, and the gate scan signal Ga are at a high level, the first reset transistor T1 conducts under the low-level control of the first reset control signal Re1, and the leakage prevention transistor T8 conducts under the high-level control of the leakage prevention control signal EM2, thereby providing the initial voltage transmitted on the first initial signal line Vinit1 to the gate of the drive transistor T3, and initializing the gate of the drive transistor T3. At the same time, the second reset transistor T7 conducts under the control of the second reset control signal Re2, and provides the initial voltage output from the second initial signal line Vinit2 to the first electrode of the light-emitting element 121, initializing the first electrode of the light-emitting element 121. Also at this stage, the first light emission control transistor T5 and the second light emission control transistor T6 are shut off under the high-level control of the light emission control signal EM1, and the data writing transistor T4 is shut off under the high-level control of the scan signal Ga.

[0077] In the data writing and compensation stage T20, the first reset control signal Re1 and the second reset control signal Re2 are at a high level, the light emission control signal EM1 and the leakage protection control signal EM2 are at a high level, and the gate scan signal Ga is at a low level. The data writing transistor T4 and the threshold compensation transistor T2 both conduct in response to the low level of the gate scan signal Ga. The leakage protection transistor T8 also conducts in response to the high level of the leakage protection control signal EM2, thereby charging the gate of the drive transistor T3 with the data signal Vda transmitted on the data line until the gate voltage of the drive transistor T3 changes to Vda + Vth, and the gate voltage of the drive transistor T3 Vda + Vth is stored by the storage capacitor Cst1. In this case, Vth represents the threshold voltage of the drive transistor T3, and Vda represents the voltage of the data signal. Furthermore, at this stage, the first reset transistor T1 is shut off in response to a low level of the first reset control signal Re1, the second reset transistor T7 is shut off in response to a low level of the second reset control signal Re2, and both the first light emission control transistor T5 and the second light emission control transistor T6 are shut off in response to a high level of the light emission control signal EM1.

[0078] In the light emission stage T30, the first reset control signal Re1 and the second reset control signal Re2 are at a high level, the light emission control signal EM1 and the leakage prevention control signal EM2 are at a low level, and the gate scan signal Ga is at a high level. The first light emission control transistor T5 and the second light emission control transistor T6 both conduct in response to the low level of the light emission control signal EM1. The conducting first light emission control transistor T5 provides the voltage of the first voltage line VDD to the first pole of the drive transistor T3, setting the voltage of the first pole of the drive transistor T3 to VDD and the gate voltage of the drive transistor T3 to Vda + Vth. In this way, the drive transistor T3 can be brought to a saturated state, thereby supplying the drive current Ids to the drive transistor T3: Ids = K * ((Vda + Vth - VDD) - Vth) 2 =K*(Vda-VDD) 2This generates a current, where K is a structural constant related to the process and design. This drive current Ids is supplied to the light-emitting element 121 via the conducting second light-emitting control transistor T6, driving the light-emitting element 121 to emit light. Also at this stage, the first reset transistor T1 is shut off in response to a low level of the first reset control signal Re1, and controls the second reset transistor T7 to shut off in response to a low level of the second reset control signal Re2. The data write transistor T2 and the threshold compensation transistor T4 are both shut off in response to a high level of the gate scan signal Ga. The leakage protection transistor T8 is shut off in response to a low level of the leakage protection control signal EM2.

[0079] In another embodiment, if a parasitic capacitance Cst2 is installed in the pixel circuit, when the gate scan signal Ga rises from a low level to a high level during the light emission stage T30, based on the charge conservation principle of the capacitance, the voltage at the gate of the drive transistor T3 increases, for example, Vcs, by coupling to the gate of the drive transistor T3 via the parasitic capacitance Cst2, and Vcs is, for example, 0.4V to 0.5V. In the above formula for calculating Ids, since Vda + Vth is smaller than VDD, Vda + Vth - VDD is a negative value. If the voltage at the gate of the drive transistor T3 is higher than Vda + Vth, the absolute value of Vda + Vth + Vcs - VDD is smaller than the absolute value of Vda + Vth - VDD, and therefore the drive current Ids decreases.

[0080] The drive current Ids is related to the data signal Vda, and the upper voltage limit of the data signal provided by the data line Vda is, for example, around 6V or 7V. To achieve a low drive current, the data line Vda needs to provide a high data signal voltage, which may be exceeded in actual use. After adding the parasitic capacitance Cst2, in the light emission stage T30, the voltage of the gate of the drive transistor T3 is increased using the parasitic capacitance Cst2, allowing the data line Vda to provide a slightly lower data signal voltage. This reduces the demands on the data signal provided by the data line Vda, enabling a low drive current even under the action of the parasitic capacitance Cst2, and preventing the data signal Vda voltage from exceeding its upper voltage limit.

[0081] For example, in some cases, the leakage prevention control signal provided by the leakage prevention control signal line EM2 and the light emission control signal provided by the light emission control signal line EM1 may be the same. For example, the drive timing of the leakage prevention transistor T8 and the drive timing of the first light emission control transistor T5 and the second light emission control transistor T6 may be the same, so the same signal can be used to drive the leakage prevention transistor T8, the first light emission control transistor T5 and the second light emission control transistor T6 simultaneously.

[0082] For example, in another example, the leakage prevention control signal provided by the leakage prevention control signal line EM2 and the light emission control signal provided by the light emission control signal line EM1 may be different. The leakage prevention control signal EM2 is used to independently control the conduction and disconnection of the leakage prevention transistor T8, and the light emission control signal EM1 controls the conduction and disconnection of the first light emission control transistor T5 and the second light emission control transistor T6. In the light emission stage T30, the drive timing of the leakage prevention transistor T8 and the drive timing of the first light emission control transistor T5 and the second light emission control transistor T6 may be different. For example, the leakage prevention control signal of the leakage prevention transistor T8 may always be kept at a low level in the light emission stage T30, while the light emission control signals of the first light emission control transistor T5 and the second light emission control transistor T6 may be kept at a low level overall in the light emission stage T30 and can rise to a high level once at predetermined intervals (as shown in Figure 2C). This reduces the light emission time of the light-emitting element 121, reduces the light emission brightness of the light-emitting element 121 in a short time, and thereby reduces the power consumption of this pixel circuit. Due to the visual afterimage phenomenon, the user cannot perceive the change in brightness of the light-emitting element 121. Therefore, in the light emission stage T30, the drive timing of the leakage prevention transistor T8 and the drive timing of the first light emission control transistor T5 and the second light emission control transistor T6 do not need to be the same, so the leakage prevention control signal line EM2 is used to control the leakage prevention transistor T8 independently.

[0083] Figure 3 is a schematic diagram of the layout of a pixel circuit according to some embodiments of the present disclosure, and Figures 4A-4O are schematic diagrams of each layer of the pixel circuit according to some embodiments of the present disclosure. For example, as shown in Figures 3 and 4A-4O, a stacked structure of one pixel circuit 120 is introduced as an example.

[0084] Figure 3 is a schematic diagram of the pixel circuit layout shown in Figure 2A, and the display substrate may include a first active semiconductor layer, a first conductive layer, a second conductive layer, a second active semiconductor layer, a third conductive layer, a source-drain metal layer, a fourth conductive layer, and an anode layer. Figures 4A-4O are schematic diagrams of each structural layer of a pixel circuit according to some embodiments of the present disclosure, where Figure 4A is a schematic diagram of the first active semiconductor layer 310, Figure 4B is a schematic diagram of the first conductive layer 320, Figure 4C is a schematic diagram of the first active semiconductor layer 310 overlapping with the first conductive layer 320, Figure 4D is a schematic diagram of the second conductive layer 330, Figure 4E is a schematic diagram of the second conductive layer 330 overlapping with the stacked structure shown in Figure 4C, Figure 4F is a schematic diagram of the second active semiconductor layer 340, Figure 4G is a schematic diagram of the third conductive layer 350, and Figure 4H is a schematic diagram of the second active semiconductor layer 3 Figure 4E shows a schematic diagram of the laminated structure in which layer 40 and the third conductive layer 350 overlap, Figure 4I shows a schematic diagram of the source-drain metal layer 360, Figure 4J shows a schematic diagram of the insulating layer vias, Figure 4K shows a schematic diagram of the source-drain metal layer 360 overlapping with the insulating layer vias, Figure 4L shows a schematic diagram of the source-drain metal layer 360 overlapping with the laminated structure in Figure 4H, Figure 4M shows a schematic diagram of the insulating layer vias between the source-drain metal layer 360 and the fourth conductive layer 370, Figure 4N shows a schematic diagram of the fourth conductive layer 370, and Figure 4O shows a schematic diagram of the fourth conductive layer 370 overlapping with the laminated structure in Figure 4L.

[0085] For example, in a direction perpendicular to the base substrate 10, the first active semiconductor layer 310 is located between the base substrate 10 and the first conductive layer 320, the first conductive layer 320 is located between the first active semiconductor layer 310 and the second conductive layer 330, the second conductive layer 330 is located between the first conductive layer 320 and the second active semiconductor layer 340, the second active semiconductor layer 340 is located between the second conductive layer 330 and the third conductive layer 350, the third conductive layer 350 is located between the second active semiconductor layer 340 and the source-drain metal layer 360, the source-drain metal layer 360 is located between the third conductive layer 350 and the fourth conductive layer 370, and the fourth conductive layer 370 is located between the source-drain metal layer 360 and the anode layer (not shown).

[0086] For example, as shown in Figure 3, the first reset signal line Re1, the first initial signal line Vinit1, the scan signal line Ga, the leakage prevention control signal line EM2, the light emission control signal line EM1, the second reset signal line Re2, and the second initial signal line Vinit2 extend along the first direction X and are arranged in order from top to bottom along the second direction Y which intersects the first direction X.

[0087] For example, in some embodiments, the first direction X and the second direction Y are perpendicular to each other. The first direction X may be parallel to the horizontal direction, and the second direction Y may be parallel to the vertical direction.

[0088] For example, in the second direction Y, the storage capacitor Cst1 is located between the light emission control line EM1 and the scan signal line Ga or the leakage prevention control line EM2. For example, as shown in Figure 3, the orthogonal projection of the light emission control line EM1 onto the base substrate 10 is located on the side of the orthogonal projection of the storage capacitor Cst1 onto the base substrate 10 that is away from the orthogonal projection of the scan signal line Ga onto the base substrate 10. Also, in the second direction Y, the storage capacitor Cst1 is located between the first reset signal line Re1 and the second reset signal line Re2. For example, as shown in Figure 3, the orthogonal projection of the storage capacitor Cst1 onto the base substrate is located between the orthogonal projection of the first reset signal line Re1 onto the base substrate and the orthogonal projection of the second reset signal line Re2 onto the base substrate.

[0089] For example, in the second direction Y, the first initial signal line Vinit1 is located between the first reset signal line Re1 and the second reset signal line Re2. For example, as shown in Figure 3, the orthogonal projection of the first initial signal line Vinit1 onto the base board is located between the orthogonal projection of the first reset signal line Re1 onto the base board and the orthogonal projection of the second reset signal line Re2 onto the base board. For example, in the second direction Y, the second initial signal line Vinit2 is located on the side of the second reset signal line Re2 away from the first reset signal line Re1. For example, as shown in Figure 3, the orthogonal projection of the second initial signal line Vinit2 onto the base board is located on the side of the orthogonal projection of the second reset signal line Re2 onto the base board away from the orthogonal projection of the first reset signal line Re1 onto the base board.

[0090] For example, the leakage protection control signal line EM2 extends along the first direction X. In the second direction Y, the leakage protection control signal line EM2 is located between the scan signal line Ga and the storage capacitance Cst1. For example, as shown in Figure 3, the orthogonal projection of the leakage protection control signal line EM2 onto the base substrate 10 is located between the orthogonal projection of the scan signal line Ga onto the base substrate 10 and the orthogonal projection of the storage capacitance Cst1 onto the base substrate 10.

[0091] For example, as shown in Figure 3, the first voltage line VDD includes a first sub-voltage line VDD1 extending along the second direction Y and a second sub-voltage line VDD2 extending along the first direction X, where the first sub-voltage line VDD1 and the second sub-voltage line VDD2 are located in different layers, for example, the second sub-voltage line VDD2 is located in the second conductive layer 330 and the first sub-voltage line VDD1 is located in the fourth conductive layer 370, and the first sub-voltage line VDD1 and the second sub-voltage line VDD2, located in different layers, are connected via vias penetrating the insulating layer, so that the first voltage line VDD is wired in a grid pattern on the base substrate, that is, the first sub-voltage line VDD1 and the second sub-voltage line VDD2 are arranged in a grid pattern on the entire display substrate, thereby reducing the resistance of the first voltage line VDD, reducing the voltage drop, and further increasing the stability of the power supply voltage provided by the first voltage line VDD.

[0092] For example, data line Vda extends along the second direction Y, and data line Vda and first sub-voltage line VDD1 are aligned along the first direction X.

[0093] For example, as shown in Figure 3, in the first direction X, the data writing transistor T4 and the first light emission control transistor T5 are located on one side of the storage capacitor Cst1, for example, the left side as shown in Figure 3. The first reset transistor T1, the threshold compensation transistor T2, the second light emission control transistor T6, and the second reset transistor T7 are located on the other side of the storage capacitor Cst1, for example, the right side as shown in Figure 3. In the second direction Y, the data writing transistor T4, the first reset transistor T1, and the threshold compensation transistor are located on one side of the storage capacitor Cst1, for example, the upper side as shown in Figure 3. The first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7 are located on the other side of the storage capacitor Cst1, for example, the lower side as shown in Figure 3.

[0094] For example, as shown in Figure 3, in the first direction X, the leakage protection transistor T8 is located on the side of the threshold compensation transistor T2 away from the data writing transistor T4. For example, the orthogonal projection of the leakage protection transistor T8 onto the base substrate is located on the side of the orthogonal projection of the threshold compensation transistor T2 onto the base substrate away from the orthogonal projection of the data writing transistor T4 onto the base substrate. In the second direction Y, the leakage protection transistor T8 is located on the side of the storage capacitor Cst1 away from the light emission control line EM1. For example, the orthogonal projection of the leakage protection transistor T8 onto the base substrate is located on the side of the orthogonal projection of the storage capacitor Cst1 onto the base substrate away from the orthogonal projection of the light emission control line EM1 onto the base substrate. The threshold compensation transistor T2, the data writing transistor T4, and the leakage protection transistor T8 extend along the second direction Y and are aligned along the first direction X.

[0095] For example, as shown in Figure 3, in the first direction X, the parasitic capacitance Cst2 is located between the data writing transistor T4 and the threshold compensation transistor T2. For example, the orthogonal projection of the parasitic capacitance Cst2 onto the base substrate is located between the orthogonal projection of the data writing transistor T4 onto the base substrate and the orthogonal projection of the threshold compensation transistor T2 onto the base substrate. In the second direction Y, the parasitic capacitance Cst2 is located on the side of the storage capacitance Cst1 away from the light emission control line EM1. For example, the orthogonal projection of the parasitic capacitance Cst2 onto the base substrate is located on the side of the orthogonal projection of the storage capacitance Cst1 onto the base substrate away from the orthogonal projection of the light emission control line EM1 onto the base substrate. The orthogonal projection of the parasitic capacitance Cst2 onto the base substrate at least partially overlaps with the orthogonal projection of the scan signal line Ga onto the base substrate.

[0096] For example, Figure 4A shows a first active semiconductor layer 310, which may be formed by patterning a semiconductor material on a base substrate, as shown in Figure 4A. The first active semiconductor layer includes the active layers A1-A7 of transistors T1-T7, and the active layers of transistors T1-T7 are located on the same layer. The active layer A1 of the first reset transistor T1, the active layer A2 of the threshold compensation transistor T2, the active layer A6 of the second light emission control transistor T6, and the active layer A7 of the second reset transistor T7 are formed integrally, and may also be formed integrally with the active layer A3 of the drive transistor T3, the active layer A4 of the data writing transistor T4, and the active layer A5 of the first light emission control transistor T5. The active layer of each transistor may include a source region, a drain region, and a channel region located between the source region and the drain region.

[0097] For example, in the first direction X, the active layer A4 of the data writing transistor T4 and the active layer A5 of the first light emission control transistor T5 are located on the first side of the active layer A3 of the drive transistor T3, for example, on the left side as shown in Figure 4A. The active layer A1 of the first reset transistor T1, the active layer A2 of the threshold compensation transistor T2, the active layer A6 of the second light emission control transistor T6, and the active layer A7 of the second reset transistor T7 are located on the second side of the active layer A3 of the drive transistor T3, for example, on the right side as shown in Figure 4A.

[0098] For example, in the second direction Y, the active layer A1 of the first reset transistor T1, the active layer A2 of the threshold compensation transistor T2, and the active layer A4 of the data writing transistor T4 are located on the third side of the active layer A3 of the drive transistor T3, for example, on the upper side as shown in Figure 4A. The active layer A5 of the first light emission control transistor T5, the active layer A6 of the second light emission control transistor T6, and the active layer A7 of the second reset transistor T7 are located on the fourth side of the active layer A3 of the drive transistor T3, for example, on the lower side as shown in Figure 4A.

[0099] For example, the active semiconductor layer 310 may be made of amorphous silicon, polysilicon, oxide semiconductor material, etc. It should be noted that the source region and drain region described above may be regions doped with n-type impurities or p-type impurities. In the embodiments of this disclosure, the doped source region corresponds to the source of the transistor, and the doped drain region corresponds to the drain of the transistor.

[0100] For example, Figure 4B shows the first conductive layer 320, and as shown in Figure 4B, the first reset signal line Re1, the second reset signal line Re2, the light emission control line EM1, and the scan signal line Ga are all located on the first conductive layer 320. The first conductive layer 320 may further include the first electrode plate CC1 of the storage capacitance Cst1, the gate of the first reset transistor T1, the gate of the threshold compensation transistor T2, the gate of the data writing transistor T4, the gate of the first light emission control transistor T5, the gate of the second light emission control transistor T6, the gate of the second reset transistor T7, and the gate of the drive transistor T3. The first conductive layer 320 may further include the first electrode plate CCa of the parasitic capacitance Cst2.

[0101] For example, the scan signal line Ga is electrically connected to the gates of the threshold compensation transistor T2 and the data writing transistor T4 to control the threshold compensation transistor T2 and the data writing transistor T4 to conduct or disconnect, respectively; the light emission control line EM1 is electrically connected to the gates of the first light emission control transistor T5 and the second light emission control transistor T6 to control the first light emission control transistor T5 and the second light emission control transistor T6 to conduct or disconnect, respectively; the first reset signal line Re1 is electrically connected to the gate of the first reset transistor T1 to control the first reset transistor T1 to conduct or disconnect, respectively; and the second reset signal line Re2 is electrically connected to the gate of the second reset transistor T7 to control the second reset transistor T7 to conduct or disconnect, respectively.

[0102] For example, as shown in Figure 4B, the scan signal line Ga is connected to the first electrode plate CCa of the parasitic capacitance, and the first electrode plate CCa of the parasitic capacitance is formed integrally with the scan signal line Ga.

[0103] For example, Figure 4C shows a schematic diagram of the stacking positional relationship between the first conductive layer 320 and the first active semiconductor layer 310. As shown in Figure 4C, the scan signal line Ga overlaps with the active layer A2 of the threshold compensation transistor T2 and the active layer A4 of the data writing transistor T4. The light emission control signal line EM1 overlaps with the active layer A5 of the first light emission control transistor T5 and the active layer A6 of the second light emission control transistor T6. The first reset signal line Re1 overlaps with the active layer A1 of the first reset transistor T1, and the second reset signal line Re2 overlaps with the active layer A7 of the second reset transistor T7. The first electrode plate CC1 of the storage capacitor overlaps with the active layer A3 of the drive transistor T3.

[0104] For example, as shown in Figure 4C, the gate of the threshold compensation transistor T2 and the gate of the data writing transistor T4 are formed integrally with the scan signal line Ga, the gate of the threshold compensation transistor T2 and the gate of the data writing transistor T4 are parallel in the first direction, the gate of the threshold compensation transistor T2 may be the portion of the scan signal line Ga that overlaps with the active layer A2 of the threshold compensation transistor T2, and the gate of the data writing transistor T4 may be the portion of the scan signal line Ga that overlaps with the active layer A4 of the data writing transistor T4. The gate of the first light emission control transistor T5 and the gate of the second light emission control transistor T6 are formed integrally with the light emission control line EM1, the gate of the first light emission control transistor T5 may be the portion of the light emission control line EM1 that overlaps with the active layer A5 of the first light emission control transistor T5, and the gate of the second light emission control transistor T6 may be the portion of the light emission control line EM1 that overlaps with the active layer A6 of the second light emission control transistor T6. The gate of the first reset transistor T1 is formed integrally with the first reset signal line Re1, and the gate of the first reset transistor T1 may be the portion of the first reset signal line Re1 that overlaps with the active layer A1 of the first reset transistor T1. The gate of the second reset transistor T7 is formed integrally with the second reset signal line Re2, and the gate of the second reset transistor T7 may be the portion of the second reset signal line Re2 that overlaps with the active layer A2 of the second reset transistor T7. The gate of the drive transistor T3 may be the first electrode plate CC1 of the storage capacitor Cst1, that is, the gate of the drive transistor T3 is formed integrally with the first electrode plate CC1 of the storage capacitor.

[0105] For example, the first reset signal line Re1 is formed integrally with the gate of the first reset transistor T1 in the y-th row pixel circuit and the gate of the second reset transistor T7 in the y-1-th row pixel circuit; in other words, the first reset signal line Re1 is formed integrally with the gate of the first reset transistor T1 in the subpixel of the current row and the gate of the second reset transistor T7 in the subpixel of the previous row.

[0106] For example, the second reset signal line Re2 is formed integrally with the gate of the first reset transistor T1 of the pixel circuit in row y+1 and the gate of the second reset transistor T7 of the pixel circuit in row y. In other words, the second reset signal line Re2 is formed integrally with the gate of the second reset transistor T7 in the subpixel of the current row and the gate of the first reset transistor T1 in the subpixel of the next row.

[0107] For example, as shown in Figure 4C, in a direction perpendicular to the base substrate 10, the portion of the first active semiconductor layer 310 covered by the first electrode plate CC1 of the storage capacitance Cst1 is the active layer channel region of the drive transistor T3, and the active layer channel region of the drive transistor T3 may be of the "π" type. The portion of the first active semiconductor layer 310 covered by the light emission control signal line EM1 is the active layer channel region of the first light emission control transistor T5 and the active layer channel region of the second light emission control transistor T6. The portion of the first active semiconductor layer 310 covered by the scan signal line Ga is the active layer channel region of the threshold compensation transistor T2 and the active layer channel region of the data writing transistor T4. The portion of the first active semiconductor layer 310 covered by the first reset signal line Re1 is the active layer channel region of the first reset transistor T1. The portion of the first active semiconductor layer 310 covered by the second reset signal line Re2 is the active layer channel region of the second reset transistor T7.

[0108] For example, as shown in Figures 3 and 4C, in the first direction X, the orthogonal projections of the active layer A2 of the threshold compensation transistor T2 and the active layer A4 of the data writing transistor T4 onto the base substrate are located on either side of the orthogonal projection of the storage capacitor Cst1 onto the base substrate. The orthogonal projection of the active layer A3 of the drive transistor T3 onto the base substrate is located between the orthogonal projection of the active layer A4 of the data writing transistor T4 onto the base substrate and the orthogonal projection of the active layer A2 of the threshold compensation transistor T2 onto the base substrate. The orthogonal projection of the active layer A3 of the drive transistor T3 onto the base substrate is located between the orthogonal projections of the active layer A4 of the data writing transistor T4 and the active layer A5 of the first light emission control transistor T5 onto the base substrate and the orthogonal projections of the active layer A6 of the second light emission control transistor T6 and the active layer A2 of the threshold compensation transistor T2 onto the base substrate.

[0109] For example, in the second direction Y, the orthogonal projection of the active layer A1 of the first reset transistor T1 onto the base substrate is located on the side of the orthogonal projection of the storage capacitance Cst1 onto the base substrate in the orthogonal projection of the active layer A2 of the threshold compensation transistor T2 onto the base substrate. The orthogonal projection of the active layer A7 of the second reset transistor T7 onto the base substrate is located on the side of the orthogonal projection of the active layer A6 of the second light emission control transistor T6 onto the base substrate, away from the orthogonal projection of the active layer A1 of the first reset transistor T1 onto the base substrate.

[0110] For example, as shown in Figure 4C, in the second direction Y, the gates of the first reset transistor T1, the threshold compensation transistor T2, and the data writing transistor T4 are all located on the first side of the gate of the drive transistor T3, for example, on the upper side as shown in Figure 4C, while the gates of the second reset transistor T7, the first light emission control transistor T5, and the second light emission control transistor T6 are located on the second side of the gate of the drive transistor T3, for example, on the lower side as shown in Figure 4C.

[0111] For example, in some cases, the gate of the leakage protection transistor T8 is formed integrally with the leakage protection control signal line EM2. In the second direction Y, the gate of the leakage protection transistor T8 is located on the side of the gate of the drive transistor T3 that is away from the gate of the second light emission control transistor T6, for example, on the upper side as shown in Figure 3. The leakage protection control signal line EM2 includes a first sub-control signal line EM21 and a second sub-control signal line EM22.

[0112] Figure 4D shows a schematic diagram of the second conductive layer 330. As shown in Figure 4D, the second conductive layer 330 includes a second electrode plate CC2 of storage capacitance and a first sub-control line EM21. The second electrode plate CC2 of storage capacitance is formed integrally with the second sub-voltage line VDD2. The first sub-control line EM21 extends along the first direction X.

[0113] Figure 4E is a schematic diagram of the stacking positional relationship between the first active semiconductor layer 310, the first conductive layer 320, and the second conductive layer 330. As shown in Figures 4C and 4E, the orthogonal projection of the second electrode plate CC2 of the storage capacitance onto the base substrate overlaps at least partially with the orthogonal projection of the first electrode plate CC1 of the storage capacitance onto the base substrate. As shown in Figures 4C and 4E, in the second direction Y, the first sub-control signal line EM21 is located between the second electrode plate CC2 and the scan signal line Ga. For example, the orthogonal projection of the first sub-control signal line EM21 onto the base substrate is located between the orthogonal projection of the second electrode plate CC2 onto the base substrate and the orthogonal projection of the scan signal line Ga onto the base substrate.

[0114] Figure 4F shows a schematic diagram of the second active semiconductor layer 340. As shown in Figure 4F, the second active semiconductor layer 340 includes the active layer A8 of the leakage protection transistor T8, the third electrode plate CC3 for storage capacitance, and the second electrode plate CCb for parasitic capacitance. The material of the second active semiconductor layer 340 is, for example, an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), and the embodiments of this disclosure are not limited thereto. That is, the materials of the active layer A8, the third electrode plate CC3 for storage capacitance, and the second electrode plate CCb for parasitic capacitance of the leakage transistor include oxide semiconductor materials. For example, only the second active semiconductor layer 340 employs an oxide semiconductor material, that is, this oxide semiconductor material is present only in the leakage protection transistor T8 among the transistors T1 to T8.

[0115] For example, the leakage protection transistor T8 employs an oxide semiconductor thin-film transistor, while transistors T1 to T7 employ polysilicon thin-film transistors. The active layer A8 of the leakage protection transistor T8 and the active layers A1 to A7 of transistors T1 to T7 are located in different layers; that is, the film layer where the oxide semiconductor thin-film transistor is located and the film layer where the polysilicon thin-film transistor is located are different.

[0116] For example, as shown in Figures 3, 4C, and 4F, the active layer A8 of the leakage protection transistor T8, the active layer A2 of the threshold compensation transistor T2, and the active layer A4 of the data writing transistor T4 all extend along the second direction Y and are installed side by side along the first direction X. For example, a portion of the active layer A2 of the threshold compensation transistor T2 includes protruding and folded portions, but the entire structure extends along the second direction Y. The orthogonal projection of the active layer A8 of the leakage protection transistor onto the base substrate is located on the side away from the orthogonal projection of the active layer A4 of the data writing transistor onto the base substrate in the orthogonal projection of the active layer A2 of the threshold compensation transistor onto the base substrate. Based on the extending direction and relative position of the active layer A2 of the threshold compensation transistor T2 and the active layer A8 of the leakage protection transistor T8, the occupied area of ​​the pixel circuit can be saved, and both poles of the leakage protection transistor T8 can be easily connected to the threshold compensation transistor T2 and the storage capacitor, respectively, avoiding wiring winding and further reducing the occupied area.

[0117] Figure 4G shows a schematic diagram of the third conductive layer 350, which includes a second sub-control line EM22, and the second sub-control line EM22 extends along the first direction X.

[0118] For example, the leakage current prevention control signal line EM2 includes a first sub-control signal line EM21 and a second sub-control signal line EM22, where the first sub-control signal line EM21 is located on the second conductive layer 330 and the second sub-control signal line EM22 is located on the third conductive layer 350, and as shown in Figure 4H, the orthogonal projection of the first sub-control signal line EM21 onto the base substrate at least partially overlaps with the orthogonal projection of the second sub-control signal line EM22 onto the base substrate.

[0119] Figure 4H is a schematic diagram showing the stacking of the second active semiconductor layer 340 and the third conductive layer 350 based on Figure 4E. As shown in Figure 4H, in the direction perpendicular to the base substrate, the first sub-control line EM21 and the second sub-control line EM22 overlap at least partially with the active layer A8 of the leakage prevention transistor T8.

[0120] For example, the BB' portion of Figure 5A shows a schematic diagram of the cross-sectional structure corresponding to the leakage protection transistor T8 in Figure 3. As shown in Figure 4H and the BB' portion of Figure 5A, the gate of the leakage protection transistor T8 includes a first gate gc81 and a second gate gc82. The first gate gc81 is formed integrally with the first sub-control line EM21, and the first gate gc81 may be the portion of the first sub-control line EM21 that overlaps with the active layer A8 of the leakage protection transistor T8. The second gate gc82 is formed integrally with the second sub-control line EM22, and the second gate gc82 may be the portion of the second sub-control line EM22 that overlaps with the active layer A8 of the leakage protection transistor T8. In a direction perpendicular to the base substrate, the active layer A8 of the leakage protection transistor is located between the first gate gc81 and the second gate gc82. Based on this embodiment, by realizing the leakage prevention transistor T8 as a dual-gate transistor, the reliability of the leakage prevention transistor T8 can be improved, for example, its ability to withstand high temperatures and humidity can be enhanced, and the two gates of the leakage prevention transistor T8 and the active layer A8 can be arranged perpendicular to the base substrate, thereby saving occupied space.

[0121] For example, the CC' portion of Figure 5A shows a schematic diagram of the cross-sectional structure corresponding to the storage capacitance Cst1 in Figure 3. As shown in the CC' portions of Figures 4H and 5A, the first electrode plate CC1 of the storage capacitance is located in the first conductive layer 320. As shown in the CC' portions of Figures 4D and 5A, the second electrode plate CC2 of the storage capacitance is located in the second conductive layer 330. As shown in the CC' portions of Figures 4F and 5A, the third electrode plate CC3 is located in the second active semiconductor layer 340. In a direction perpendicular to the base substrate, the first electrode plate CC1, the second electrode plate CC2, and the third electrode plate CC3 overlap at least partially to form the storage capacitance Cst1.

[0122] For example, as shown in Figures 4F and 4H, the second parasitic capacitance electrode plate CCb is located in the second active semiconductor layer 340, on the same layer as the third storage capacitance electrode plate CC3. The first parasitic capacitance electrode plate CCa is formed integrally with the scan signal line Ga, and the second parasitic capacitance electrode plate CCb overlaps at least partially with the first parasitic capacitance electrode plate CCa in a direction perpendicular to the base substrate to form the parasitic capacitance Cst2. The orthogonal projection of the second parasitic capacitance electrode plate CCb onto the base substrate lies between the orthogonal projection of the active layer of the threshold compensation transistor T2 onto the base substrate and the orthogonal projection of the active layer of the data writing transistor T4 onto the base substrate.

[0123] For example, at least one insulating layer is placed between two adjacent layers among the first active semiconductor layer 310, the first conductive layer 320, the second conductive layer 330, the second active semiconductor layer 340, the third conductive layer 350, the source-drain metal layer 360, the fourth conductive layer 370, and the anode layer (not shown). For example, as shown in Figure 5A, there is a first insulating layer 510 between the first active semiconductor layer 310 and the first conductive layer 320, a second insulating layer 520 between the first conductive layer 320 and the second conductive layer 330, a third insulating layer 530 and a buffer layer 540 between the second conductive layer 330 and the second active semiconductor layer 340, a fourth insulating layer 550 between the second active semiconductor layer 340 and the third conductive layer 350, a fifth insulating layer 560 between the third conductive layer 350 and the source-drain metal layer 360, a sixth insulating layer 570 between the source-drain metal layer 360 and the fourth conductive layer 370, and a planarization layer 580 between the fourth conductive layer 370 and the anode layer.

[0124] For example, since the first insulating layer 510 to the sixth insulating layer 570, the buffer layer 540, and the planarization layer 580 are all manufactured from insulating materials, such as inorganic insulating materials like silicon nitride, silicon oxide, or silicon oxynitride, or other suitable materials, the buffer layer 540 and the planarization layer 580 can be used as insulating layers.

[0125] Figure 4I shows a schematic diagram of the source-drain metal layer 360, which includes a first connecting electrode Co1, a second connecting electrode Co2, a third connecting electrode Co3, a fourth connecting electrode Co4, a fifth connecting electrode Co5, a first initial signal line Vinit1, and a second initial signal line Vinit1.

[0126] Figure 4J shows a schematic diagram of insulating layer vias, where each of the multiple insulating layer vias V21-V28 and V31-V34 penetrates multiple insulating layers. Figure 4K shows a schematic diagram in which the source-drain metal layer 360 and insulating layer vias are stacked, and Figure 4L shows a schematic diagram in which the source-drain metal layer 360 is stacked based on Figure 4H.

[0127] As shown in Figures 4I to 4L, the first electrode sc1 of the first reset transistor T1 and the first electrode sc2 of the threshold compensation transistor T2 are the same electrode, and the first terminal of the first connecting electrode Co1 is formed integrally with the first electrode sc1 of the first reset transistor T1 and the first electrode sc2 of the threshold compensation transistor T2, and is connected to the active layer A2 of the threshold compensation transistor T2 and the active layer A1 of the first reset transistor T1 via V21 through a via that penetrates the insulating layer. The second terminal of the first connecting electrode Co1 is formed integrally with the first electrode fc8 of the leakage prevention transistor T8, and is connected to the active layer A8 of the leakage prevention transistor T8 via V31 that penetrates the insulating layer.

[0128] For example, via V21 penetrates the insulating layer between the source-drain metal layer 360 and the first active semiconductor layer 310, namely the first insulating layer 510 to the fifth insulating layer 560 and the buffer layer 540, so that the first terminal of the first connecting electrode Co1 is connected to the source or drain region of the first active semiconductor layer 310 corresponding to the threshold compensation transistor T2. Via V31 penetrates the insulating layer between the source-drain metal layer 360 and the second active semiconductor layer 340, namely the fourth insulating layer 550 and the fifth insulating layer 560, so that the second terminal of the first connecting electrode Co1 is connected to the source or drain region of the second active semiconductor layer 340 corresponding to the leakage prevention transistor T8.

[0129] For example, the first terminal of the second connecting electrode Co2 is formed integrally with the second electrode sc8 of the leakage prevention transistor T8 and is connected to the active layer A8 of the leakage prevention transistor T8 via a via V32 that penetrates the insulating layer. The second terminal of the second connecting electrode Co2 is connected to the first electrode plate CC1 of the storage capacitor via a via V24 that penetrates the insulating layer, and the third terminal of the second connecting electrode is connected to the third electrode plate CC3 of the storage capacitor via a via V33 that penetrates the insulating layer.

[0130] For example, via V32 penetrates the insulating layer between the source-drain metal layer 360 and the second active semiconductor layer 340, namely the fourth insulating layer 550 and the fifth insulating layer 560, so that the first terminal of the second connecting electrode Co2 is connected to the source or drain region corresponding to the leakage prevention transistor T8 in the second active semiconductor layer 340. Via V33 penetrates the insulating layer between the source-drain metal layer 360 and the second active semiconductor layer 340, namely the fourth insulating layer 550 and the fifth insulating layer 560, so that the third terminal of the second connecting electrode Co2 is connected to the third electrode plate CC3 in the second active semiconductor layer 340.

[0131] For example, via V24 penetrates the insulating layer between the source-drain metal layer 360 and the first conductive layer 320, i.e., the second insulating layer 520 to the fifth insulating layer 560 and the buffer layer 540. For example, as shown in Figure 4D, a first conductive layer via V11 is formed on the second electrode plate CC2 of the storage capacitance, and as shown in Figure 4F, a second conductive layer via V12 is formed on the third electrode plate CC3 of the storage capacitance. In a direction perpendicular to the base substrate, the first conductive layer via V11 and the second conductive layer via V12 overlap at least partially with the insulating layer via V24. As shown in Figure 5A, the second terminal of the second connecting electrode Co2 is connected to the first electrode plate CC1 of the storage capacitance in the first conductive layer 320 via V24 of the second insulating layer 520 to the fifth insulating layer 560 and the buffer layer 540, via V11 of the first conductive layer, and via V12 of the second conductive layer.

[0132] For example, Figure 5B is a schematic cross-sectional view of another embodiment of the present disclosure, and the distinction between Figure 5B and Figure 5A lies in the CC' portion, where, as shown in Figure 5B, vias are not required on the third electrode plate CC3, and the first electrode plate CC1 and the third electrode plate CC3 may be connected via vias. For example, insulating layer vias may be provided that penetrate the insulating layer (second insulating layer 520, third insulating layer 530, and buffer layer 540) between the third electrode plate CC3 and the first electrode plate CC1, and the third electrode plate CC3 may be connected to the first electrode plate CC1 in the first conductive layer 320 via these insulating layer vias and vias on the second electrode plate CC2. Since the third electrode plate CC3 is connected to the second connecting electrode Co2, the connection between the first electrode plate CC1 and the second connecting electrode Co2 can be achieved.

[0133] For example, Figure 5C is a schematic cross-sectional view of another embodiment of the present disclosure, and the distinction between Figure 5C and Figures 5A and 5B lies in the CC' portion. As shown in Figure 5C, a region may be provided on the second connecting electrode Co2 that overlaps with the first electrode plate CC1 but does not overlap with the third electrode plate CC3. An insulating layer via is provided that penetrates the insulating layer (second insulating layer 520 to fifth insulating layer 560 and buffer layer 540) corresponding to this region. The second connecting electrode Co2 is connected to the first electrode plate CC1 in the first conductive layer 320 via this insulating layer via without penetrating the third electrode plate CC3, and there is no need to provide a via on the third electrode plate CC3.

[0134] As shown in Figure 5C, in some embodiments, a region may be provided on the second connecting electrode Co2 that overlaps with the first electrode plate CC1 but does not overlap with either the third electrode plate CC3 or the second electrode plate CC2. An insulating layer via is provided that penetrates the insulating layer corresponding to this region (second insulating layer 520 to fifth insulating layer 560 and buffer layer 540). The second connecting electrode Co2 is directly connected to the first electrode plate CC1 in the first conductive layer 320 via this insulating layer via without penetrating the third electrode plate CC3 or the second electrode plate CC2, eliminating the need to provide vias in the third electrode plate CC3 or the second electrode plate CC2.

[0135] For example, the parasitic capacitance second electrode plate CCb is connected to the fourth terminal of the second connecting electrode Co2 via a via V34 that penetrates the insulating layer. The via V34 penetrates the insulating layer between the source-drain metal layer 360 and the second active semiconductor layer 340, namely the fourth insulating layer 550 and the fifth insulating layer 560, so that the fourth terminal of the second connecting electrode Co2 is connected to the parasitic capacitance second electrode plate CCb in the second active semiconductor layer 340.

[0136] For example, the first terminal of the third connecting electrode Co3 is formed integrally with the first electrode fc5 of the first light-emitting control transistor T5 and is connected to the active layer A5 of the first light-emitting control transistor T5 via a via V26 that penetrates the insulating layer, and the second terminal of the third connecting electrode Co3 is connected to the second electrode plate CC2 of the storage capacitor via a via V25 that penetrates the insulating layer.

[0137] For example, via V26 penetrates the insulating layer between the source-drain metal layer 360 and the first active semiconductor layer 310, i.e., the first insulating layer 510 to the fifth insulating layer 560 and the buffer layer 540, so that the first terminal of the third connecting electrode Co3 is connected to the source or drain region of the first active semiconductor layer 310 corresponding to the first light emission control transistor T5. Via V25 penetrates the insulating layer between the source-drain metal layer 360 and the second conductive layer 330, i.e., the third insulating layer 530 to the fifth insulating layer 560 and the buffer layer 540, so that the second terminal of the third connecting electrode Co3 is connected to the second electrode plate CC2 of the second conductive layer 330.

[0138] For example, the fourth connecting electrode Co4 is formed integrally with the first electrode sc4 of the data writing transistor T4 and is connected to the active layer A4 of the data writing transistor T4 via a via V22 that penetrates the insulating layer. For example, the via V22 penetrates the insulating layer between the source-drain metal layer 360 and the first active semiconductor layer 310, i.e., the first insulating layer 510 to the fifth insulating layer 560, so that the first terminal of the fourth connecting electrode Co4 is connected to the source region or drain region in the first active semiconductor layer 310 corresponding to the data writing transistor T4.

[0139] For example, the fifth connecting electrode Co5 is formed integrally with the first electrode sc6 of the second light-emitting control transistor T6 and is connected to the active layer A6 of the second light-emitting control transistor T6 via a via V27 that penetrates the insulating layer. The via V27 penetrates the insulating layer between the source-drain metal layer 360 and the first active semiconductor layer 310, i.e., the first insulating layer 510 to the fifth insulating layer 560, so that the first terminal of the fifth connecting electrode Co5 is connected to the source region or drain region in the first active semiconductor layer 310 corresponding to the second light-emitting control transistor T6.

[0140] For example, the first initial signal line Vinit1 is formed integrally with the second pole fc1 of the first reset transistor T1 and is connected to the active layer A1 of the first reset transistor T1 via a via V21 that penetrates the insulating layer. For example, the via V21 penetrates the insulating layer between the source-drain metal layer 360 and the first active semiconductor layer 310, i.e., the first insulating layer 510 to the fifth insulating layer 560 and the buffer layer 540, so that the first initial signal line Vinit1 is connected to the source region or drain region of the first active semiconductor layer 310 corresponding to the first reset transistor T1.

[0141] For example, the first initial signal line Vinit1 extends along the first direction X, and the orthogonal projection of the first initial signal line Vinit1 onto the base board lies between the orthogonal projection of the first reset signal line Re1 onto the base board and the orthogonal projection of the second reset signal line Re2 onto the base board.

[0142] For example, the first initial signal line Vinit1 is formed integrally with the second pole of the first reset transistor T1 in the y-th row pixel circuit and the first pole of the second reset transistor T7 in the y-1 row pixel circuit; that is, the first initial signal line Vinit1 is formed integrally with the second pole of the first reset transistor T1 in the subpixel of the current row and the first pole of the second reset transistor T7 in the subpixel of the previous row.

[0143] For example, the second initial signal line Vinit2 is formed integrally with the first pole fc7 of the second reset transistor T7 and is connected to the active layer A2 of the second reset transistor T7 via a via V28 that penetrates the insulating layer. For example, the via V28 penetrates the insulating layer between the source-drain metal layer 360 and the first active semiconductor layer 310, i.e., the first insulating layer 510 to the fifth insulating layer 560, so that the second initial signal line Vinit2 is connected to the source region or drain region of the first active semiconductor layer 310 corresponding to the second reset transistor T7.

[0144] For example, the second initial signal line Vinit2 extends along the first direction X, and the orthogonal projection of the second initial signal line Vinit2 onto the base board is located on the side of the orthogonal projection of the second reset signal line Re2 onto the base board that is away from the orthogonal projection of the first reset signal line Re1 onto the base board.

[0145] For example, the second initial signal line Vinit2 is formed integrally with the second pole of the first reset transistor T1 in the pixel circuit of row y+1 and the first pole of the second reset transistor T7 in the pixel circuit of row y, that is, the first initial signal line Vinit1 is formed integrally with the first pole of the second reset transistor T7 in the subpixel of the current row and the second pole of the first reset transistor T1 in the subpixel of the next row.

[0146] For example, the first initial signal line Vinit1 and the second initial signal line Vinit2 may be connected via a connecting wire extending along the second direction Y, the connecting wire may be located, for example, on a fourth conductive layer or another layer, and the connecting wire electrically connects the first sub-initial signal line Vinit1 and the second sub-initial signal line Vinit2 by connecting to the first initial signal line Vinit1 and the second initial signal line Vinit2 via vias penetrating the insulating layer. In the embodiments of this disclosure, by employing a jumper wire connection method to connect the vertically extending connecting wire located on different layers to the horizontally extending first sub-initial signal line Vinit1 and the second sub-initial signal line Vinit2, the initial signal line Vinit is wired in a grid pattern on the base substrate, resulting in a grid structure, which reduces the resistance of the initial signal line Vinit, lowers the voltage drop (IR drop), makes the distribution of the initial signal line Vinit on the base substrate more uniform, and further enhances the stability of the initial voltage provided by the initial signal line Vinit.

[0147] Figure 4M shows a schematic diagram of the insulating layer vias V41 to V43 between the source-drain metal layer 360 and the fourth conductive layer 370, Figure 4N shows a schematic diagram of the portion where the fourth conductive layer 370 is laminated with the insulating layer vias shown in Figure 4M, and Figure 4O shows a schematic diagram of the fourth conductive layer 370 being laminated based on Figure 4L.

[0148] As shown in Figures 4M to 4O, the fourth conductive layer 370 includes a data line Vda, a first sub-voltage line VDD1, and a sixth connecting electrode Co6. The data line Vda and the first sub-voltage line VDD1 are located in the same layer, both extending along the second direction Y, and aligned along the first direction X. The sixth connecting electrode Co6 and the first sub-voltage line VDD1 are located in the same layer, and in the first direction X, the sixth connecting electrode Co6 is located on the side of the first sub-voltage line VDD1 away from the data line Vda.

[0149] For example, as shown in Figures 3 and 4N, the orthogonal projection of the first sub-voltage line VDD1 onto the base substrate lies between the orthogonal projection of the active layer of the data writing transistor T4 onto the base substrate and the orthogonal projection of the active layer of the threshold compensation transistor T2 onto the base substrate, and at least partially overlaps with the orthogonal projection of the second electrode plate of the parasitic capacitance Cst2 onto the base substrate, and the first sub-voltage line VDD1 further at least partially overlaps with the orthogonal projection of the storage capacitance Cst1 onto the base substrate.

[0150] For example, as shown in Figures 4K and 4N, the first sub-voltage line VDD1 has a first protrusion P1, and the third terminal of the third connecting electrode Co3 is connected to the first protrusion P1 of the first sub-voltage line VDD1 via a via V42 that penetrates the insulating layer, and the via V42 penetrates the sixth insulating layer 570. The first sub-voltage line VDD1 is connected to the third connecting electrode Co3 of the source-drain metal layer 360, and the third connecting electrode Co3 is connected to the first electrode fc5 of the first light-emitting control transistor T5 and the second electrode plate CC2 of the storage capacitor, thereby electrically connecting the first sub-voltage line VDD1 to the first electrode fc5 of the first light-emitting control transistor T5 and the second electrode plate CC2 of the storage capacitor.

[0151] For example, as shown in Figures 4K, 4N, and 4O, the first sub-voltage line VDD1 further has a second protrusion P2, which is "curved" in shape, and in order to shield the leakage protection transistor T8 from light, the orthogonal projection of the second protrusion P2 onto the base substrate at least partially overlaps with the orthogonal projection of the active layer A8 of the leakage protection transistor T8 onto the base substrate. The leakage protection transistor T8 is an oxide semiconductor thin-film transistor, and oxide semiconductor thin-film transistors are sensitive to light irradiation, and the second protrusion P2 can shield the leakage protection transistor T8 from light by covering it, thereby reducing the effect of light irradiation on the leakage protection transistor T8.

[0152] For example, as shown in Figures 4K, 4N, and 4O, the orthogonal projection of the data line Vda onto the base substrate at least partially overlaps with the orthogonal projection of the active layer of the data writing transistor T4 onto the base substrate and the orthogonal projection of the active layer of the first light emission control transistor T5 onto the base substrate. For example, the data line Vda is close to the active layer A4 of the data writing transistor T4 and the active layer A5 of the first light emission control transistor T5, thereby providing a more favorable connection between the data line Vda and the data writing transistor T4, avoiding wiring winding and reducing the size of the display panel.

[0153] For example, as shown in Figures 4K, 4N, and 4O, the fourth connection electrode Co4 is connected to the data line Vda via a via V41 that penetrates the insulating layer, and the via V41 penetrates the sixth insulating layer 570. The fourth connection electrode Co4 has a third projection P3, and in a direction perpendicular to the base substrate, the third projection P3 at least partially overlaps with the via V41 of the insulating layer, and the third projection of the data line Vda is connected to the first pole sc4 of the data writing transistor on the fourth connection electrode Co4 via the P3 via V41, thereby electrically connecting the data line Vda and the first pole sc4 of the data writing transistor T4. The orthogonal projection of via V41 onto the base substrate may at least partially overlap with via V22 in a direction perpendicular to the base substrate, and of course, the embodiments of this disclosure are not limited thereto.

[0154] For example, as shown in Figures 4K, 4N, and 4O, the fifth connecting electrode Co5 and the sixth connecting electrode Co6 overlap at least partially in a direction perpendicular to the base substrate, and the fifth connecting electrode Co5 is connected to the sixth connecting electrode Co6 via a via V43 that penetrates the insulating layer, and the via V43 penetrates the sixth insulating layer 570. The orthogonal projection of via V43 onto the base substrate may at least partially overlap with via V21 in a direction perpendicular to the base substrate, and of course, the embodiments of this disclosure are not limited thereto.

[0155] The AA' portion of Figure 5A shows a schematic diagram of the cross-sectional structure corresponding to the second light-emitting control transistor T6 in Figure 3. As shown in Figure 4O and the AA' portion of Figure 5A, the sixth connecting electrode Co6 is connected to the first terminal (e.g., the first electrode) of the light-emitting element 121 via a via V51 that penetrates the insulating layer. For example, since the via V51 penetrates the flat layer 580, the first electrode sc6 of the second light-emitting control transistor T6 is connected to the first electrode of the light-emitting element 121 via the sixth connecting electrode Co6.

[0156] For example, as shown in Figure 4K, in the second direction Y, the orthogonal projection of via V51 onto the base substrate at least partially overlaps with the orthogonal projection of the light emission control line EM1 onto the base substrate, and of course, the embodiments of this disclosure are not limited thereto. The position of via V51 may be flexibly provided, and the pixel arrangement can be adapted to various pixel circuits. Furthermore, the position of via V51 may be flexibly adjusted based on the installation position of the first electrode of the light-emitting element, thereby bringing via V51 closer to the first electrode of the light-emitting element, reducing the wiring of the first electrode of the light-emitting element, and making the connection between the first electrode of the light-emitting element and the first electrode of the second light emission control transistor T6 more flexible.

[0157] For example, the anode layer may include the first electrode (i.e., anode) of the light-emitting element 121.

[0158] For example, the display panel may include multiple subpixels: a red subpixel R, a blue subpixel B, and a green subpixel G. For example, the light-emitting element 121 in the red subpixel R emits red light, the light-emitting element 121 in the blue subpixel B emits blue light, and the light-emitting element 121 in the green subpixel G emits green light. For example, the area of ​​the first electrode of one blue subpixel B is larger than the area of ​​the first electrode of one green subpixel G, and larger than the area of ​​the first electrode of one red subpixel R.

[0159] Figure 5A includes three parts: AA', BB', and CC'. Part AA' is a schematic diagram of the cross-sectional structure corresponding to the second light-emitting control transistor T6 in Figure 3 (i.e., location AA' in the cross-sectional diagram of Figure 4O). Part BB' is a schematic diagram of the cross-sectional structure corresponding to the leakage current prevention transistor T8 in Figure 3 (i.e., location BB' in the cross-sectional diagram of Figure 4O). Part CC' is a schematic diagram of the cross-sectional structure corresponding to the storage capacitor Cst1 in Figure 3 (i.e., location CC' in the cross-sectional diagram of Figure 4O). Figure 5A is a schematic diagram of the interface structures of these three parts joined together.

[0160] For example, as shown in Figure 5A, the base substrate 10 includes a multilayer structure, each made of a flexible material.

[0161] For example, an active semiconductor layer 310 is formed on the base substrate 10, and Figure 5A shows the active layer A6 of the second light emission control transistor T6 in the active semiconductor layer 310.

[0162] For example, a first insulating layer 510 is formed on one side of the base substrate 10 of the active semiconductor layer 310, and a first conductive layer 320 is formed on the side of the first insulating layer 510 away from the active semiconductor layer 310. Figure 5A shows the light emission control signal line EM1 and the first electrode plate CC1 of the storage capacitance in the first conductive layer 320.

[0163] For example, a second insulating layer 520 is formed on the side of the first conductive layer 320 away from the first insulating layer 510, and a second conductive layer 330 is formed on the side of the second insulating layer 520 away from the first conductive layer 320. Figure 5A shows the first gate gc81 (first sub-control signal line EM21) of the leakage prevention transistor T8 and the second electrode plate CC2 of the storage capacitance in the second conductive layer 330.

[0164] For example, a third insulating layer 530 is formed on the side of the second conductive layer 330 away from the second insulating layer 520, a buffer layer 540 is formed on the side of the third insulating layer 530 away from the second conductive layer 330, and a second active semiconductor layer 340 is formed on the side of the buffer layer 540 away from the third insulating layer 530. Figure 5A shows the active layer A8 and the third electrode plate CC3 of the storage capacitance of the leakage prevention transistor T8 in the second active semiconductor layer 340.

[0165] For example, a fourth insulating layer 550 is formed on the side of the second active semiconductor layer 340 away from the buffer layer 540, and a third conductive layer 350 is formed on the side of the fourth insulating layer 550 away from the second active semiconductor layer 340. Figure 5A shows the second gate gc82 (second sub-control signal line EM22) of the leakage prevention transistor in the third conductive layer 350.

[0166] For example, a fifth insulating layer 560 is formed on the side of the third conductive layer 350 away from the fourth insulating layer 550, and a source-drain metal layer 360 is formed on the side of the fifth insulating layer 560 away from the third conductive layer 350. Figure 5A shows the source drain sc6 (formed integrally with the fifth connecting electrode Co5) connected to the active layer of the second light-emitting control transistor T6 in the source-drain metal layer 360, the source drain fc8 (formed integrally with the first connecting electrode Co1) connected to the active layer of the leakage prevention transistor T8, the third connecting electrode Co3 connected to the second electrode plate CC2 of the storage capacitor, and the source drain sc8 (formed integrally with the second connecting electrode Co2) connected to the first electrode plate CC1 and the third electrode plate CC3 of the storage capacitor and the active layer of the leakage prevention transistor T8.

[0167] For example, a sixth insulating layer 570 is formed on the side of the source-drain metal layer 360 away from the fifth insulating layer 560, and a fourth conductive layer 370 is formed on the side of the sixth insulating layer 570 away from the source-drain metal layer 360. Figure 5A shows the sixth connecting electrode Co6 connected to the fifth connecting electrode Co5 in the fourth conductive layer 370, and the first sub-voltage line VDD1 connected to the third connecting electrode Co3.

[0168] For example, a planarization layer 580 is formed on the side of the fourth conductive layer 370 that is away from the sixth insulating layer 570, and the first electrode of the light-emitting element 121 is formed on the side of the planarization layer 580 that is away from the fourth conductive layer 370.

[0169] Figures 5B and 5C are schematic cross-sectional views of several embodiments of the present disclosure, respectively. The distinction between Figures 5B and 5C and Figure 5A lies in the CC' section, and specifically, refer to the descriptions of Figures 5B and 5C above.

[0170] For example, the parameters of the storage capacitance Cst1 in different subpixels on the display board 100 may be different.

[0171] For example, in some embodiments, the parameters of the storage capacitance Cst1 for subpixels of different colors (red subpixel R, blue subpixel B, and green subpixel G) may differ, and the storage capacitance Cst1 for the three types of subpixels may be set differently because the luminance demand or charging speed demand for the three RGB subpixels are different. For example, the parameters of the storage capacitance Cst1 for blue subpixel B may be different from the parameters of the storage capacitance Cst1 for red subpixel R. The drive current required for the light-emitting element of blue subpixel B may be greater than the drive current required for the light-emitting element of red subpixel R. Since the drive current can be increased by decreasing the gate voltage of the drive transistor during the light-emitting stage, the gate voltage of the drive transistor for blue subpixel B can be made smaller than the gate voltage of the drive transistor for red subpixel R. In other words, the capacitance value required for the storage capacitance Cst1 of blue subpixel B is smaller than the capacitance value required for the storage capacitance Cst1 of red subpixel R. Therefore, the area of ​​the electrode plate for the storage capacity Cst1 of the blue subpixel B can be made smaller than the area of ​​the electrode plate for the storage capacity Cst1 of the red subpixel R. For example, the area of ​​the third electrode plate CC3 located in the second active semiconductor layer 340 of the blue subpixel B can be made smaller than the area of ​​the third electrode plate CC3 located in the second active semiconductor layer 340 of the red subpixel R. Furthermore, the capacitance value of the storage capacity Cst1 of the blue subpixel B can be made smaller than the capacitance value of the storage capacity Cst1 of the red subpixel R. By making the blue subpixel B have a lower charge rate than the red subpixel R, a high drive current and high brightness can be obtained. In some embodiments, the parameters of the storage capacity Cst1 of the red subpixel R may be the same as the parameters of the storage capacity Cst1 of the green subpixel G.

[0172] For example, in a single pixel array, the arrangement of the corresponding pixel drive circuits for the red subpixel R, green subpixel G, and blue subpixel B is such that the drive circuit corresponding to the green subpixel G is in one row, and the corresponding drive circuits for the red subpixel R and blue subpixel B are in one row.

[0173] Figure 6 is a schematic diagram showing the stacking of some structures according to several embodiments of the present disclosure. For example, Figure 6 is a schematic diagram showing the stacking of a second electrode plate CC2 and a third electrode plate CC3 of a plurality of subpixels, or a schematic diagram showing the stacking of a second electrode plate CC2 and a first electrode plate CC1. As shown in Figure 6, the pixel circuits of the plurality of subpixels may be arranged with spacing such that one row 601 is the pixel circuit of a green subpixel G, and another adjacent row 602 is the pixel circuit corresponding to a red subpixel R and a blue subpixel B. For example, in some embodiments, the area of ​​the third electrode plate CC3 in the pixel circuit of the G subpixel (green subpixel) may be made larger than the area of ​​the third electrode plate CC3 in the pixel circuit of the R / B subpixel (red subpixel or blue subpixel). For example, the area of ​​the third electrode plate CC3 in the pixel circuit of the R / B subpixel may be reduced from the original size S to size S'. In this way, the storage capacitance value of the pixel circuit of the G subpixel can be made larger than the storage capacitance value of the pixel circuit shared by the RB subpixel. As a result, the G subpixel has a higher charge rate than the RB subpixel, which allows for lower drive current and lower brightness, and further balances the display difference caused by the G subpixel being too bright.

[0174] In some examples, for instance, the area of ​​the first electrode plate CC1 in the pixel circuit of the G subpixel (green subpixel) may be made larger than the area of ​​the first electrode plate CC1 in the pixel circuit of the R / B subpixel (red subpixel or blue subpixel). For example, the area of ​​the first electrode plate CC1 in the pixel circuit of the R / B subpixel may be reduced from its original size S to size S'. In this way, the storage capacitance value of the pixel circuit of the G subpixel can be made larger than the storage capacitance value of the pixel circuit corresponding to the R / B subpixel. As a result, the G subpixel has a higher charge rate than the RB subpixel, which allows for lower drive current and lower brightness, and further balances the display differences caused by the G subpixel being too bright.

[0175] In some examples, for instance, referring again to Figure 6, the areas of the first electrode plate CC1 and the third electrode plate CC3 (only one is shown in Figure 6) in the G subpixel (green subpixel) pixel circuit may both be larger than the areas of the first electrode plate CC1 and the third electrode plate CC3 in the R / B subpixel (red subpixel or blue subpixel) pixel circuit. For example, display differences can be mitigated by continuously reducing the area of ​​the first electrode plate CC1 in the R / B subpixel pixel circuit from S', or by continuously reducing the area of ​​the third electrode plate CC3 in the R / B subpixel pixel circuit from S'.

[0176] In some examples, the area of ​​the first electrode plate CC1 in the pixel circuit of the G subpixel may be made larger than the area of ​​the first electrode plate CC1 in the pixel circuit of the R / B subpixel, for example, the area of ​​the first electrode plate CC1 in the pixel circuit corresponding to the RB subpixel may be reduced.

[0177] In some examples, the areas of the first electrode plate CC1 and the third electrode plate CC3 in the pixel circuit of the G subpixel may be larger than the areas of the first electrode plate CC1 and the third electrode plate CC3 in the pixel circuit of the R / B subpixel, for example, the areas of both the first electrode plate CC1 and the third electrode plate CC3 in the pixel circuit of the R / B subpixel may be reduced.

[0178] For example, in some embodiments, referring to Figure 7, the storage capacity of the G subpixel may be appropriately reduced to take into consideration that the G subpixel brightness is higher than that of the R / B pixels, which makes it easier for the G subpixel to turn off and is also advantageous for improving the display effect. For example, the area of ​​the first electrode plate CC1 and / or the area of ​​the third electrode plate CC3 of the G subpixel may be made smaller than the area of ​​the first electrode plate CC1 and / or the area of ​​the third electrode plate CC3 of the R / B subpixel, which is the same as in the embodiments described above and will not be explained further.

[0179] For example, in some embodiments, referring to Figure 8, when the display board is used in an electronic device having a camera below the screen, the storage capacity Cst1 of the subpixels corresponding to the camera area B on the display board may differ from the parameters of the storage capacity Cst1 of the subpixels in other areas A, such as the normal display area. For example, since the requirements for the material and length of the lead of the pixel circuit in the driving camera area differ from those of the lead of the pixel circuit in other areas, the storage capacity Cst1 of the subpixels in camera area B and the storage capacity Cst1 of the subpixels in other areas A can be set differently. For example, subpixels in camera region B require longer lead wires than other regions A, resulting in higher resistance and a greater drive current. This allows the area of ​​the electrode plate for the storage capacitance Cst1 of the subpixels in camera region B to be smaller than in other regions. For instance, the area of ​​the third electrode plate for the storage capacitance Cst1 of the subpixels in camera region can be made smaller than in other regions. Furthermore, the capacitance value of the storage capacitance Cst1 of the subpixels in camera region can be made smaller than in other regions. As a result, the subpixels in camera region B have a lower charge level compared to other regions A, which allows for a higher drive current.

[0180] For example, in some embodiments, when the display board is used in an electronic device having a camera below the screen, a differentiated design of the storage capacity Cst1 between the G pixels and the R and B pixels may be adopted simultaneously. For example, the subpixels in camera region B may adopt the differentiated design of the storage capacity Cst1 between the G pixels and the R and B pixels as described in the above embodiment, or the subpixels in other region A may adopt the differentiated design of the storage capacity Cst1 between the G pixels and the R and B pixels as described in the above embodiment, and this will not be explained further here.

[0181] For example, to satisfy the different performance requirements of different subpixels for the storage capacity Cst1, the performance of the storage capacity Cst1 of different subpixels may be adjusted by adjusting the area of ​​the electrode plate of the storage capacity Cst1, or by adjusting parameters such as the thickness of the electrode plate of the storage capacity Cst1 of different subpixels, the distance between adjacent electrode plates (e.g., the distance between the first electrode plate and the second electrode plate and / or the distance between the second electrode plate and the third electrode plate), and the shape of the electrode plate.

[0182] At least one embodiment of the present disclosure further provides a display panel. Figure 9 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. As shown in Figure 9, this display panel 700 includes a display substrate 100 according to any one embodiment of the present disclosure, for example, the display substrate 100 shown in Figure 1.

[0183] For example, the display panel 700 may be a liquid crystal display panel or an organic light-emitting diode (OLED) display panel. For example, if the display panel 700 is a liquid crystal display panel, the display substrate 100 may be an array substrate or a color film substrate. If the display panel 700 is an organic light-emitting diode display panel, the display substrate 100 may be an array substrate.

[0184] For example, the display panel 700 may be a rectangular panel, a circular panel, an elliptical panel, or a polygonal panel. Furthermore, the display panel 700 may be a flat panel, a curved panel, or even a spherical panel.

[0185] For example, the display panel 700 may have a touch function; that is, the display panel 700 may be a touch display panel.

[0186] For example, the display panel 700 can be used in any product or component with a display function, such as a mobile phone, tablet computer, television, display, laptop computer, digital photo frame, or car navigation system.

[0187] For example, this display panel 700 may be a flexible display panel, thereby meeting various practical needs. For instance, this display panel 700 can be applied to curved screens and the like.

[0188] It should be noted that the display panel 700 may further include other components, such as data drive circuits and timing controllers, and the embodiments of this disclosure are not limited thereto. For clarity and brevity, the embodiments of this disclosure do not provide all the components of the display panel 700. To realize the basic functions of the display panel 700, those skilled in the art may provide and install other structures not shown as specific needs, and the embodiments of this disclosure are not limited thereto.

[0189] For the technical effects of the display panel 700 according to the above embodiment, refer to the technical effects of the display substrate 100 according to the embodiment of this disclosure. No further explanation is provided here.

[0190] The following points need to be explained regarding this disclosure:

[0191] (1) The drawings of the embodiments of this disclosure relate only to the configurations relating to the embodiments of this disclosure; other configurations should be referred to by the usual design.

[0192] (2) For clarity, in the drawings illustrating embodiments of the present invention, the thickness and dimensions of layers or structures are enlarged. When an element such as a layer, film, region, or substrate is referred to as being located "above" or "below" another element, it will be understood that the element may be located "directly" above or below another element, or an intermediate element may be present.

[0193] (3) If there is no conflict, new embodiments can be obtained by combining the embodiments and features of the embodiments of this disclosure with each other.

[0194] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto, and the scope of protection of the present disclosure shall be based on the scope of protection of the claims described above. [Explanation of Symbols]

[0195] 10 base boards 12 subpixels 100 display board 120-pixel circuit 121 Light-emitting element 210 First Reset Sub-Circuit 220 Second Reset Sub-Circuit 230 Data writing sub-circuit 240 Threshold compensation subcircuit 250 First light emission control sub-circuit 260 Second light emission control sub-circuit 270 Leakage current prevention sub-circuit 280 Memory Subcircuit 310 First Active Semiconductor Layer 320 First conductive layer 330 Second conductive layer 340 Second Active Semiconductor Layer 350 Third conductive layer 360 Source Drain Metal Layer 370 Fourth conductive layer 510 First insulating layer 520 Second insulating layer 530 Third insulating layer 540 buffer layers 550 Fourth insulating layer 560 Fifth insulating layer 570 Sixth insulating layer 580 Planarization layer

Claims

1. A display board, It includes a base substrate and a plurality of subpixels installed on the base substrate, Each of the plurality of subpixels includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light, and the pixel circuit includes a drive subcircuit, a data writing subcircuit, a threshold compensation subcircuit, a leakage current prevention subcircuit, and a storage subcircuit. The aforementioned drive subcircuit includes a control terminal, a first terminal, and a second terminal, and is configured to control the drive current flowing through the light-emitting element. The data writing subcircuit is connected to the first terminal, data line, and scan signal line of the drive subcircuit, and is configured to write the data signal provided by the data line to the first terminal of the drive subcircuit in response to the gate scan signal provided by the scan signal line. The threshold compensation subcircuit is connected to the second terminal of the drive subcircuit, the leakage prevention subcircuit, and the scan signal line, and is configured to write a compensation signal based on the data signal to the control terminal of the drive subcircuit in response to the gate scan signal provided by the scan signal line. The leakage prevention subcircuit is connected to the control terminal of the drive subcircuit, the threshold compensation subcircuit, the storage subcircuit, and the leakage prevention control signal line, and is configured to suppress leakage current at the control terminal of the drive subcircuit. The memory subcircuit is connected to the control terminal and first voltage line of the drive subcircuit, and is arranged to store the compensation signal and hold it at the control terminal of the drive subcircuit. The memory subcircuit includes a storage capacitor, the storage capacitor includes a first electrode plate, a second electrode plate, and a third electrode plate, the first electrode plate and the third electrode plate are electrically connected to each other and located in different layers relative to the base substrate, and the second electrode plate at least partially overlaps the first electrode plate and the third electrode plate in a direction perpendicular to the base substrate. In a direction perpendicular to the base substrate, the second electrode plate is located between the first electrode plate and the third electrode plate. The first electrode plate is connected to the control terminal of the drive sub-circuit, the second electrode plate is connected to the first voltage line, and the third electrode plate is connected to the control terminal of the drive sub-circuit. The aforementioned drive subcircuit includes a drive transistor, the gate of which is formed integrally with the first electrode plate of the storage capacitor. The aforementioned leakage prevention subcircuit includes a leakage prevention transistor, and the active layer of the leakage prevention transistor and the third electrode plate are located on the same layer as the display substrate.

2. The threshold compensation subcircuit includes a threshold compensation transistor, and the data writing subcircuit includes a data writing transistor. The active layer of the threshold compensation transistor is formed integrally with the active layer of the data writing transistor, and the orthogonal projections of the active layer of the threshold compensation transistor and the active layer of the data writing transistor onto the base substrate are located on both sides of the orthogonal projection of the storage capacitance onto the base substrate, respectively. The display board according to claim 1, wherein the gate of the threshold compensation transistor and the gate of the data writing transistor are parallel in a first direction, and the gate of the threshold compensation transistor and the gate of the data writing transistor are formed integrally with the scan signal line.

3. The active layer of the leakage current prevention transistor, the active layer of the threshold compensation transistor, and the active layer of the data writing transistor all extend along the second direction and are arranged side by side along the first direction intersecting the second direction. The display substrate according to claim 2, wherein the active layer of the leakage current prevention transistor has an orthogonal projection onto the base substrate that is located on the side of the orthogonal projection onto the base substrate of the active layer of the data writing transistor that is away from the orthogonal projection onto the base substrate of the active layer of the threshold compensation transistor.

4. The display board according to claim 3, wherein the gate of the leakage prevention transistor is formed integrally with the leakage prevention control signal line, the leakage prevention control signal line extends along the first direction, and the orthogonal projection of the leakage prevention control signal line onto the base substrate is located between the orthogonal projection of the scan signal line onto the base substrate and the orthogonal projection of the storage capacitance onto the base substrate.

5. The display board according to claim 3 or 4, wherein the leakage prevention control signal line includes a first sub-control signal line and a second sub-control signal line, and the orthogonal projection of the first sub-control signal line onto the base substrate at least partially overlaps with the orthogonal projection of the second sub-control signal line onto the base substrate.

6. The gate of the leakage prevention transistor includes a first gate and a second gate. The first gate is formed integrally with the first sub-control signal line, and the second gate is formed integrally with the second sub-control signal line. The display substrate according to claim 5, wherein, in a direction perpendicular to the base substrate, the active layer of the leakage prevention transistor is located between the first gate and the second gate.

7. The display substrate according to any one of claims 3 to 6, wherein the material of the active layer of the leakage prevention transistor and the material of the third electrode plate include an oxide semiconductor material.

8. The pixel circuit further includes a first reset subcircuit, The display board according to any one of claims 3 to 7, wherein the first reset subcircuit is connected to the threshold compensation subcircuit, the leakage prevention subcircuit, the first initial signal line, and the first reset control signal terminal, and is configured to apply an initial voltage provided by the first initial signal line to the control terminal of the drive subcircuit via the leakage prevention subcircuit in response to a reset control signal received by the first reset control signal terminal.

9. The first reset subcircuit includes a first reset transistor, The active layer of the first reset transistor is formed integrally with the active layer of the threshold compensation transistor. The display substrate according to claim 8, wherein the active layer of the first reset transistor has an orthogonal projection onto the base substrate that is located on the side away from the orthogonal projection of the storage capacitance onto the base substrate in the orthogonal projection of the active layer of the threshold compensation transistor onto the base substrate.

10. Further including a first connecting electrode, The first terminal of the first connecting electrode is formed integrally with the first pole of the first reset transistor and the first pole of the threshold compensation transistor, and is connected to the active layer of the threshold compensation transistor and the active layer of the first reset transistor, respectively, via vias penetrating the insulating layer. The display substrate according to claim 9, wherein the second terminal of the first connecting electrode is formed integrally with the first pole of the leakage prevention transistor and is connected to the active layer of the leakage prevention transistor via a via penetrating the insulating layer.

11. Further including a second connecting electrode, The first terminal of the second connecting electrode is formed integrally with the second pole of the leakage prevention transistor and is connected to the active layer of the leakage prevention transistor via a via that penetrates the insulating layer. The second terminal of the second connecting electrode is connected to the first electrode plate of the storage capacitance via a via that penetrates the insulating layer. The display substrate according to claim 10, wherein the third terminal of the second connecting electrode is connected to the third electrode plate of the storage capacitance via a via penetrating the insulating layer.

12. The invention further includes a parasitic capacitance connected to the second pole of the leakage prevention transistor and the scan signal line, The first electrode plate of the parasitic capacitance is formed integrally with the scan signal line. The second electrode plate of the parasitic capacitance at least partially overlaps the first electrode plate of the parasitic capacitance in a direction perpendicular to the base substrate, the second electrode plate of the parasitic capacitance and the third electrode plate of the storage capacitance are located in the same layer, and the orthogonal projection of the second electrode plate of the parasitic capacitance onto the base substrate is located between the orthogonal projection of the active layer of the threshold compensation transistor onto the base substrate and the orthogonal projection of the active layer of the data writing transistor onto the base substrate. The display substrate according to claim 11, wherein the second electrode plate of the parasitic capacitance is connected to the fourth terminal of the second connecting electrode via a via penetrating the insulating layer.

13. The display substrate according to claim 12, wherein the active layer of the drive transistor and the active layer of the data writing transistor are formed integrally with the active layer of the threshold compensation transistor, and the orthogonal projection of the active layer of the drive transistor onto the base substrate is located between the orthogonal projection of the active layer of the data writing transistor onto the base substrate and the orthogonal projection of the active layer of the threshold compensation transistor onto the base substrate.

14. The pixel circuit further includes a first light emission control subcircuit and a second light emission control subcircuit, the first light emission control subcircuit includes a first light emission control transistor, The first light emission control subcircuit is connected to the first voltage line, the first terminal of the drive subcircuit, and the light emission control signal line, and is configured to apply a first voltage provided by the first voltage line to the first terminal of the drive subcircuit in response to a light emission control signal provided by the light emission control signal line. The second light emission control subcircuit is connected to the second terminal of the drive subcircuit, the first terminal of the light-emitting element, and the light emission control signal line, and is configured to apply the drive current to the first terminal of the light-emitting element in response to the light emission control signal provided by the light emission control signal line. The display substrate according to claim 13, wherein the light emission control line extends along the first direction, and the orthogonal projection of the light emission control line onto the base substrate is located on the side of the orthogonal projection of the storage capacitance onto the base substrate that is away from the orthogonal projection of the scan signal line onto the base substrate.

15. The second light emission control subcircuit includes a second light emission control transistor. The display substrate according to claim 14, wherein the active layer of the first light-emitting control transistor, the active layer of the second light-emitting control transistor, the active layer of the data writing transistor, and the active layer of the threshold compensation transistor are formed integrally with the active layer of the drive transistor, and the orthogonal projection of the drive transistor onto the base substrate is located between the orthogonal projection of the active layer of the data writing transistor and the active layer of the first light-emitting control transistor onto the base substrate and the orthogonal projection of the active layer of the second light-emitting control transistor and the active layer of the threshold compensation transistor onto the base substrate.

16. The display board according to claim 14 or 15, wherein the leakage prevention control signal provided by the leakage prevention control signal line and the light emission control signal provided by the light emission control signal line are the same or different.

17. The first voltage line includes a first sub-voltage line extending along the second direction and a second sub-voltage line extending along the first direction. The first sub-voltage line and the second sub-voltage line are located in different layers. The first sub-voltage line has an orthogonal projection onto the base substrate that lies between the orthogonal projection onto the base substrate of the active layer of the data writing transistor and the orthogonal projection onto the base substrate of the active layer of the threshold compensation transistor, and at least partially overlaps with the orthogonal projection onto the base substrate of the second electrode plate of the parasitic capacitance. The display substrate according to claim 15 or 16, wherein the second sub-voltage line is formed integrally with the second electrode plate of the storage capacitance.

18. Further including a third connecting electrode, The first terminal of the third connecting electrode is formed integrally with the first pole of the first light-emitting control transistor and is connected to the active layer of the first light-emitting control transistor via a via that penetrates the insulating layer. The second terminal of the third connecting electrode is connected to the second electrode plate of the storage capacitance via a via that penetrates the insulating layer. The display board according to claim 17, wherein the third terminal of the third connecting electrode is connected to the first protrusion of the first sub-voltage line via a via penetrating the insulating layer.

19. The display substrate according to claim 18, wherein the first sub-voltage line further includes a second protrusion, the second protrusion being "revolving", and the orthogonal projection of the second protrusion onto the base substrate at least partially overlaps with the orthogonal projection of the active layer of the leakage prevention transistor onto the base substrate.

20. A display panel including a display board according to any one of claims 1 to 19.

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