Semiconductor memory

Abstract

The memory cell selection mechanism should be configured appropriately. [Solution] According to one embodiment, a semiconductor memory device is provided having a plurality of first memory cells and a first selection mechanism. The plurality of first memory cells are stacked on a substrate. The plurality of first memory cells are connected in parallel between a first vertical bit line and a first vertical source line. The first vertical bit line extends in the stacking direction. The first vertical source line extends in the stacking direction. The first selection mechanism is disposed between the substrate and the plurality of first memory cells in the stacking direction. The first selection mechanism selectively connects the first vertical bit line to a first local bit line. The first selection mechanism selectively connects the first vertical source line to a first local source line.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device.

Background Art

[0002] In a semiconductor memory device having a plurality of memory cells connected in parallel between bit lines and source lines, the selection potentials of the bit lines and source lines can be supplied to the memory cells via a selection mechanism. In a semiconductor memory device, it is desirable that the selection mechanism of the memory cells be appropriately configured.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment aims to provide a semiconductor memory device capable of appropriately configuring a selection mechanism of memory cells.

Means for Solving the Problems

[0006] According to one embodiment, a semiconductor memory device is provided having a plurality of first memory cells and a first selection mechanism. The plurality of first memory cells are stacked on a substrate. The plurality of first memory cells are connected in parallel between a first vertical bit line and a first vertical source line. The first vertical bit line extends in the stacking direction. The first vertical source line extends in the stacking direction. The first selection mechanism is disposed between the substrate and the plurality of first memory cells in the stacking direction. The first selection mechanism selectively connects the first vertical bit line to a first local bit line. The first selection mechanism selectively connects the first vertical source line to a first local source line. [Brief explanation of the drawing]

[0007] [Figure 1] A perspective view showing the configuration of a semiconductor memory device according to an embodiment. [Figure 2] A block diagram showing the configuration of a semiconductor memory device according to an embodiment. [Figure 3] A circuit diagram showing the configuration of a memory cell array in an embodiment. [Figure 4] A circuit diagram showing the configuration of the memory cell and selection mechanism in the embodiment. [Figure 5] A plan view showing the configuration of the array layer in the embodiment. [Figure 6] A cross-sectional view showing the configuration of the array layer and the selection gate layer in the embodiment. [Figure 7] A plan view showing the configuration of the selection gate layer in the embodiment. [Figure 8] A cross-sectional view showing the configuration of the array layer and the selection gate layer in the embodiment. [Figure 9] A plan view showing the configuration of the selection gate layer in the embodiment. [Figure 10] A cross-sectional view showing the configuration of the array layer and the selection gate layer in a first modified example of the embodiment. [Figure 11] A plan view showing the configuration of the selection gate layer in a first modified example of the embodiment. [Figure 12] A cross-sectional view showing the configuration of the array layer and the selection gate layer in a second modified example of the embodiment. [Figure 13] Plan view showing the configuration of the selection gate layer in the second modification of the embodiment. [Figure 14] Cross-sectional view showing the configuration of the array layer and the selection gate layer in the third modification of the embodiment. [Figure 15] Plan view showing the configuration of the selection gate layer and the operation of the selection gate layer during "1" writing in the fourth modification of the embodiment. [Figure 16] Enlarged plan view showing the operation of the selected memory cell during "1" writing in the fourth modification of the embodiment. [Figure 17] Enlarged plan view showing the operation of the non-selected memory cell during "1" writing in the fourth modification of the embodiment. [Figure 18] Plan view showing the operation of the selection gate layer during "0" writing in the fourth modification of the embodiment. [Figure 19] Enlarged plan view showing the operation of the selected memory cell during "0" writing in the fourth modification of the embodiment. [Figure 20] Enlarged plan view showing the operation of the non-selected memory cell during "0" writing in the fourth modification of the embodiment. [Figure 21] Plan view showing the operation of the selection gate layer during reading in the fourth modification of the embodiment. [Figure 22] Enlarged plan view showing the operation of the selected memory cell during reading in the fourth modification of the embodiment. [Figure 23] Enlarged plan view showing the operation of the non-selected memory cell during reading in the fourth modification of the embodiment.

Embodiments for Carrying Out the Invention

[0008] The semiconductor memory device according to the embodiment will be described in detail below with reference to the accompanying drawings. Note that the present invention is not limited by this embodiment.

[0009] (Embodiment)

[0010] The semiconductor memory device according to this embodiment has a plurality of memory cells connected in parallel between a bit line and a source line, and can supply the selection potentials of the bit line and the source line to the memory cells via a selection mechanism, and measures are taken to appropriately configure the selection mechanism.

[0011] The semiconductor memory device 1 may be configured as shown in Figure 1. Figure 1 is a perspective view showing the configuration of the semiconductor memory device 1. Hereinafter, the direction perpendicular to the surface of the substrate SB will be defined as the Z direction, and the two mutually orthogonal directions in the plane perpendicular to the Z direction will be defined as the X direction and the Y direction.

[0012] The semiconductor memory device 1 is a three-dimensional memory, for example, a ferroelectric memory. The semiconductor memory device 1 has a substrate SB, a selective gate layer L1, a connection layer CL, a selective gate layer L2, and an array layer L3. The selective gate layer L1, the connection layer CL, the selective gate layer L2, and the array layer L3 are stacked sequentially on the substrate SB.

[0013] The array layer L3 includes a memory cell array 2, a word line WL, a columnar body PL3, and a columnar body PL13.

[0014] The substrate SB extends in a plate-like shape in the XY direction. The substrate SB may be formed from a material mainly composed of a semiconductor (e.g., silicon). Above the substrate SB (+Z side), multiple word lines WL are stacked spaced apart in the Z direction. Multiple layers of insulating layer IF2 and word lines WL may be alternately provided on the substrate SB. At the same Z position, multiple word lines WL are arranged spaced apart in the X direction. Each word line WL extends mainly in the Y direction. Each word line WL may be plate-like with a main surface along the XY direction. Each word line WL may be formed from a material mainly composed of a metal such as tungsten. The insulating layer IF2 may be formed from a material mainly composed of a semiconductor oxide (e.g., silicon oxide).

[0015] The memory cell array 2 has multiple channel regions CH and multiple insulating films FE.

[0016] Multiple channel regions CH are stacked on the +Z side of the substrate SB, spaced apart in the Z direction. Multiple layers of insulating layer IF2 and channel regions CH may be arranged alternately. Multiple channel regions CH are arranged in the XYZ direction.

[0017] Multiple channel regions CH adjacent in the XY direction between multiple word lines WL are electrically isolated by an insulating film IF1. Multiple channel regions CH adjacent in the X direction across multiple word lines WL are electrically isolated by a slit IF3. The slit IF3 may be formed from a material mainly composed of a semiconductor oxide (e.g., silicon oxide). Multiple channel regions CH adjacent in the Z direction are electrically isolated by an insulating layer IF2.

[0018] Each channel region CH extends in a plate-like manner in the XY direction. Each channel region CH can be formed from a semiconductor film whose main component is a semiconductor (e.g., silicon).

[0019] Multiple insulating films FE are stacked on the +Z side of the substrate SB, spaced apart in the Z direction. Multiple layers of insulating layers IF2 and insulating films FE may be arranged alternately. Multiple insulating films FE are arranged in the X direction. In the X direction, each insulating film FE is positioned between the word line WL and the channel region CH. Each insulating film FE extends linearly in the Y direction. Each insulating film FE may be formed of an insulator. Each insulating film FE may contain a ferroelectric material.

[0020] Each insulating film FE may be formed from a material primarily composed of hafnium oxide (HfO). Each insulating film FE may further be formed from a material containing at least one element selected from the group including silicon (Si), scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), zirconium (Zr), aluminum (Al), strontium (Sr), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0021] Multiple columnar bodies PL3 are arranged in the XY direction on the +Z side of the substrate SB. The XY arrangement of the multiple columnar bodies PL3 corresponds to the XY arrangement of multiple channel regions CH. Each columnar body PL3 corresponds to multiple channel regions CH aligned in the Z direction. Each columnar body PL3 extends in the Z direction, which is the stacking direction of the multiple channel regions CH aligned in the Z direction, and reaches the channel region CH on the -Z side (see Figure 6). Each columnar body PL3 extends in the Z direction within the channel region CH. Each columnar body PL3 may be formed from a material mainly composed of metal, such as tungsten. The columnar bodies PL3 function as part of the vertical bit line vBL (see Figure 4). The vertical bit line vBL can be connected to the global bit line GBL via the local bit line LBL.

[0022] Multiple columnar bodies PL13 are arranged in the XY direction on the +Z side of the substrate SB. The XY arrangement of the multiple columnar bodies PL13 corresponds to the XY arrangement of multiple channel regions CH, and corresponds to the XY arrangement of multiple columnar bodies PL3. Each columnar body PL13 corresponds to multiple channel regions CH aligned in the Z direction. Each columnar body PL13 penetrates the corresponding multiple channel regions CH at a position spaced apart from the columnar body PL3 in the Y direction, extends in the Z direction which is the stacking direction of those regions, and reaches the channel region CH on the -Z side (see Figure 6). Each columnar body PL13 extends in the Z direction within the channel region CH. Each columnar body PL13 may be formed from a material mainly composed of metal, such as tungsten. The columnar bodies PL13 function as part of the vertical source line vSL (see Figure 4). The vertical source line vSL can be connected to the global source line GSL via the local source line LSL.

[0023] In the array layer L3, a stacked structure SST is formed in which word lines WL, insulating films FE, and channel regions CH are alternately stacked with insulating layers IF2. In the stacked structure SST, multiple channel regions CH are arranged in the XYZ directions, and in the X direction, the insulating film FE and word lines WL are adjacent to each other in sequence, forming a three-dimensional arrangement of memory cells MT (memory cell array).

[0024] In other words, in the semiconductor memory device 1, the portion of the channel region CH facing the word line WL via an insulating film FE functions as a memory cell MT, and a memory cell array 2 is formed in which multiple memory cells MT are arranged three-dimensionally. In the semiconductor memory device 1, the storage capacity can be increased by increasing the number of stacked word lines WL in the stacked structure SST, without using finer patterning techniques.

[0025] In the selection gate layer L2, a selection mechanism SM2 (see Figure 4) is provided. The selection mechanism SM2 includes selection transistors BT2 and ST2. Selection transistors BT2 and ST2 are driven via selection gate lines SG2 connected to their respective gates.

[0026] In the connecting layer CL, conductive films CN1 and CN2 (see Figures 6 and 8) are arranged. Conductive films CN1 and CN2 can each be formed from materials primarily composed of metals, such as aluminum and copper. Conductive film CN1 functions as part of the local bit line LBL (see Figure 4). Conductive film CN2 functions as part of the local source line LSL (see Figure 4).

[0027] In the selection gate layer L1, a selection mechanism SM1 (see Figure 4) is provided. The selection mechanism SM1 includes selection transistors BT1 and ST1. Selection transistors BT1 and ST1 are driven via selection gate lines SG1 connected to their respective gates.

[0028] An interlayer insulating film 81 may be interposed between the substrate SB and the selected gate layer L1 in the Z direction. The interlayer insulating film 81 can be formed from a material mainly composed of a semiconductor oxide (for example, silicon oxide).

[0029] The selection potential of the global bit line GBL can be supplied to the memory cell MT via selection mechanism SM1, local bit line LBL, selection mechanism SM2, and vertical bit line vBL. The selection potential of the global source line GSL can be supplied to the memory cell MT via selection mechanism SM1, local source line LSL, selection mechanism SM2, and vertical bit line vBL.

[0030] For example, when manufacturing a semiconductor memory device 1, the structure of the selection gate layer L1, the structure of the connection layer CL, the structure of the selection gate layer L2, and the structure of the array layer L3 are formed on the +Z side of the substrate SB in roughly this order. When forming the structure of the selection gate layer L1 (selection mechanism SM1) and the structure of the selection gate layer L2 (selection mechanism SM2), a relatively high temperature (for example, 1000°C or higher) heat treatment is performed. If each insulating film FE contains a ferroelectric material, when this heat treatment is applied to each insulating film FE, the ferroelectricity of each insulating film FE is lost (it becomes paraelectric), and it becomes difficult to maintain a "1" or "0" in the direction of its polarization.

[0031] On the other hand, in the semiconductor memory device 1, as shown in Figure 1, the memory cell selection mechanisms SM1 and SM2 are arranged between the substrate SB and the memory cell array 2 in the Z direction. As a result, in the manufacturing process of the semiconductor memory device 1, the structure of the array layer L3 is formed after the completion of relatively high-temperature heat treatment. Therefore, the structure of the semiconductor memory device 1 is suitable for avoiding this heat treatment being applied to each insulating film FE if each insulating film FE contains a ferroelectric material.

[0032] Figure 2 is a block diagram showing the schematic configuration of the semiconductor memory device 1. As shown in Figure 2, the semiconductor memory device 1 has a memory cell array 2, peripheral circuits 100, and an interface 200. The peripheral circuits 100 include a WL drive circuit 110, an SG1 drive circuit 120, an SG2 drive circuit 130, an SL drive circuit 140, and a sense amplifier circuit 150.

[0033] The WL drive circuit 110 controls the voltage applied to the word line WL, and the SG1 drive circuit 120 controls the voltage applied to the selected gate line SG1. The SG2 drive circuit 130 controls the voltage applied to the selected gate line SG2, and the SL drive circuit 140 controls the voltage applied to the global source line GSL. The sense amplifier circuit 150 controls the voltage applied to the global bit line GBL and also determines the data read out according to the signal from the selected memory cell.

[0034] The peripheral circuit 100 controls the operation of the semiconductor memory device 1 based on instructions input from an external source (for example, the memory controller of the memory system to which the semiconductor memory device 1 is applied) via the interface 200.

[0035] Next, the circuit configuration of memory cell array 2 will be explained using Figure 3. Figure 3 is a three-dimensional diagram showing the circuit configuration of memory cell array 2.

[0036] In Figure 3, the memory cell array 2 is provided with, for example, 4n word lines WL_1 to WL_4n (where n is an integer greater than or equal to 2). The memory cell array 2 is also provided with m vertical bit lines vBL_1 to vBL_m (where m is a multiple of 2 greater than or equal to 2) and m vertical source lines vSL_1 to vSL_m.

[0037] In memory cell array 2, multiple memory cells MT are arranged in a NOR-type circuit.

[0038] The memory cell array 2 can be divided into m drive units DU_1 to DU_m. The m drive units DU_1 to DU_m are arranged in the XY direction. In Figure 3, a 2x2 / m array is exemplified as the arrangement of drive units DU. Each drive unit DU contains n memory cells MT that share a vertical bit line vBL and a vertical source line vSL. The n memory cells MT are aligned in the Z direction.

[0039] In the drive unit DU, n memory cells MT are connected in parallel between the vertical bit line vBL and the vertical source line vSL to form a NOR-type memory cell group MG.

[0040] The word line WL is connected across the drive units DU, which are aligned in the Y direction. The word line WL is connected to the gates of multiple memory cells MT, which are aligned in the Y direction.

[0041] As shown in Figure 4, selection mechanisms SM1 and SM2 are provided on the -Z side of the vertical bit line vBL and the vertical source line vSL. Figure 4 is a circuit diagram showing the configuration of the memory cell MT and the selection mechanisms SM1 and SM2. In Figure 4, for simplification, one memory cell MT in the memory cell group MG of the drive units DU_1 and DU_2 is shown, and the other memory cells MT in the memory cell group MG are not shown.

[0042] The selection mechanism SM1 includes selection transistors BT1 and ST1. The selection mechanism SM2 includes selection transistors BT2 and ST2.

[0043] The selection transistor BT1 is connected between the local bit line LBL and the global bit line GBL. The drain of the selection transistor BT1 is connected to the local bit line LBL, the source is connected to the global bit line GBL, and the gate is connected to the selection gate line SG1. The selection transistor BT1 is driven via the selection gate line SG1, which is connected to its gate.

[0044] The selection transistor BT2 is connected between the vertical bit line vBL and the local bit line LBL. The drain of the selection transistor BT2 is connected to the vertical bit line vBL, the source is connected to the local bit line LBL, and the gate is connected to the selection gate line SG2. The selection transistor BT2 is driven via the selection gate line SG2, which is connected to its gate.

[0045] The selection transistor ST1 is connected between the local source line LSL and the global source line GSL. The drain of the selection transistor ST1 is connected to the local source line LSL, the source is connected to the global source line GSL, and the gate is connected to the selection gate line SG1. The selection transistor ST1 is driven via the selection gate line SG1, which is connected to its gate.

[0046] The selection transistor ST2 is connected between the vertical source line vSL and the local source line LSL. The drain of the selection transistor ST2 is connected to the vertical source line vSL, the source is connected to the local source line LSL, and the gate is connected to the selection gate line SG2. The selection transistor ST2 is driven via the selection gate line SG2, which is connected to its gate.

[0047] The memory cell group MG is selected and connected in two stages by the global bit line GBL using selection transistors BT1 and BT2. The global source line GSL is selected and connected in two stages by selection transistors ST1 and ST2. The selection of memory cells MT within the selected memory cell group MG is performed by the word line WL.

[0048] Next, the detailed configurations of array layer L3, selection gate layer L2, and selection gate layer L1 will be explained using Figures 5 to 9. Figure 5 is an XY plan view showing the configuration of array layer L3, and is an enlarged XY plan view corresponding to part A of Figure 1. Figure 6 is an XZ cross-sectional view showing the configuration of array layer L3, selection gate layer L2, and selection gate layer L1, and shows the cross-section obtained by cutting Figure 5 along the BB line. Figure 7 is an XY plan view showing the configuration of selection gate layer L2, and corresponds to the cross-section obtained by cutting Figure 6 along the EE line. Figure 8 is a YZ cross-sectional view showing the configuration of array layer L3, selection gate layer L2, and selection gate layer L1, and shows the cross-section obtained by cutting Figure 5 along the CC line. Figure 9 is an XY plan view showing the configuration of selection gate layer L1, and corresponds to the cross-section obtained by cutting Figure 8 along the FF line.

[0049] As shown in Figures 5, 6, and 8, in the array layer L3, the portion of the channel region CH facing the word line WL via the insulating film FE functions as a memory cell MT, and a memory cell array 2 is formed in which multiple memory cells MT are arranged three-dimensionally. In the memory cell array 2, the multiple memory cells MT are grouped into multiple memory cell groups, each corresponding to a drive unit DU (see Figure 3). Each memory cell group contains multiple memory cells MT arranged in the Z direction. The multiple memory cell groups are arranged in the XY direction.

[0050] Multiple memory cell groups correspond to multiple columnar bodies PL3 and multiple columnar bodies PL13. In the channel region CH of each memory cell group, the corresponding columnar body PL3 extends in the Z direction, and the corresponding columnar body PL13 extends in the Z direction. Each columnar body PL3 may be formed from a material mainly composed of metal, such as tungsten. The columnar body PL3 functions as part of the vertical bit line vBL (see Figure 4). Each columnar body PL13 may be formed from a material mainly composed of metal, such as tungsten. The columnar body PL13 functions as part of the vertical source line vSL (see Figure 4).

[0051] In the selective gate layer L2, as shown in Figures 6 and 7, multiple columnar bodies PL2, multiple columnar bodies PL12, multiple selective gate lines SG2_1 to SG2_3, and multiple insulating films IF4 are arranged. Selective gate line SG2_1 has multiple conductive films SG2_1a and SG2_1b. Selective gate line SG2_2 has multiple conductive films SG2_2a and SG2_2b. Selective gate line SG2_3 has multiple conductive films SG2_3a and SG2_3b.

[0052] Multiple columnar bodies PL2 correspond to multiple columnar bodies PL3, and to multiple conductive films CN1. Each columnar body PL2 extends in the Z direction. The +Z end of each columnar body PL2 is connected to the corresponding columnar body PL3. The -Z end of each columnar body PL2 is connected to the corresponding conductive film CN1 (local bit line LBL).

[0053] Multiple columnar bodies PL12 correspond to multiple columnar bodies PL13, and to multiple conductive films CN2. Each columnar body PL12 extends in the Z direction. The +Z end of each columnar body PL12 is connected to the corresponding columnar body PL13. The -Z end of each columnar body PL12 is connected to the corresponding conductive film CN2 (local source line LSL).

[0054] Multiple conductive films SG2_1a to SG2_3b correspond to multiple columnar bodies PL2 and PL12 aligned in the Y direction. Each conductive film SG2 extends in the Y direction. Each conductive film SG2 can be formed from a material primarily composed of metal, such as tungsten.

[0055] As shown in Figure 7, the conductive film SG2_1a approaches the -X side of columnar body PL2 and the -X side of columnar body PL12 alternately multiple times as it progresses from the -Y side to the +Y side. At each point of approach, an insulating film IF4 is interposed between the conductive film SG2_1a and the columnar bodies PL2 and PL12. The insulating film IF4 can be formed from a material mainly composed of semiconductor oxide (e.g., silicon oxide). As the conductive film SG2_1b progresses from the -Y side to the +Y side, it approaches the +X side of columnar body PL2 and the +X side of columnar body PL12 alternately multiple times. At each point of approach, an insulating film IF4 is interposed between the conductive film SG2_1b and the columnar bodies PL2 and PL12.

[0056] The conductive films SG2_1a and SG2_1b form a pair and work together to function as a selection gate line SG2_1 (see Figure 4). The portions of the columnar body PL2 facing the conductive films SG2_1a and SG2_1b via the insulating film IF4 function as a selection transistor BT2. The selection transistor BT2 has a vertical thin-film transistor (TFT) structure in which the channel region extends in the Z direction and has gates on both sides in the X direction.

[0057] The portions of the columnar body PL12 facing the conductive films SG2_1a and SG2_1b via the insulating film IF4 function as selection transistors ST2. Selection transistors ST2 have a vertical thin-film transistor (TFT) structure in which the channel region extends in the Z direction and gates are located on both sides in the X direction.

[0058] Furthermore, the pairs of conductive films SG2_2a and SG2_2b, and the pairs of conductive films SG2_3a and SG2_3b, are the same as the pairs of conductive films SG2_1a and SG2_1b, respectively.

[0059] As shown in Figures 6 to 9, the connecting layer CL contains multiple conductive films CN1 and multiple conductive films CN2. Each conductive film CN1 functions as part of the local bit line LBL shown in Figures 7 and 9, for example, as the portion from the +X end of the local bit line LBL to just before the +X side of the selection transistor BT1. The multiple conductive films CN1 are arranged in the Y direction, and each extends in the X direction. Each conductive film CN2 functions as part of the local source line LSL shown in Figures 7 and 9, for example, as the portion from the -X end of the local source line LSL to just before the -X side of the selection transistor ST1. The multiple conductive films CN2 are arranged in the X direction, and each extends in the Y direction.

[0060] In the selective gate layer L1, as shown in Figures 8 and 9, multiple columnar bodies PL1, multiple columnar bodies PL11, multiple selective gate lines SG1_1 to SG1_8, and multiple insulating films IF5 are arranged. Selective gate line SG1_1 has multiple conductive films SG1_1a and SG1_1b. Selective gate line SG1_2 has multiple conductive films SG1_2a and SG1_2b. Selective gate line SG1_3 has multiple conductive films SG1_3a and SG1_3b. Selective gate line SG1_4 has multiple conductive films SG1_4a and SG1_4b. Selective gate line SG1_5 has multiple conductive films SG1_5a and SG1_5b. Selective gate line SG1_6 has multiple conductive films SG1_6a and SG1_6b. Selective gate line SG1_7 has multiple conductive films SG1_7a and SG1_7b. The selected gate line SG1_8 has multiple conductive films SG1_8a and SG1_8b.

[0061] Multiple columnar bodies PL1 correspond to multiple conductive films CN1. Each columnar body PL1 extends in the Z direction. The +Z end of each columnar body PL1 is connected to the corresponding conductive film CN1 (local bit line LBL). The -Z end of each columnar body PL1 is connected to the global bit line GBL.

[0062] Multiple columnar bodies PL11 correspond to multiple conductive films CN2. Each columnar body PL11 extends in the Z direction. The +Z end of each columnar body PL11 is connected to the corresponding conductive film CN2. The -Z end of each columnar body PL12 is connected to the global source line GSL.

[0063] Multiple conductive films SG1_1a to SG1_8b correspond to multiple columnar bodies PL1 and PL11 aligned in the Y direction. Each conductive film SG1 extends in the X direction. Each conductive film SG1 can be formed from a material primarily composed of metal, such as tungsten.

[0064] As shown in Figure 9, the conductive film SG1_1a approaches the -Y side of columnar body PL1 and the -Y side of columnar body PL11 multiple times alternately as it moves from the -X side to the +X side. At each point of approach, an insulating film IF5 is interposed between the conductive film SG1_1a and the columnar bodies PL1 and PL11. The insulating film IF5 can be formed from a material mainly composed of semiconductor oxide (e.g., silicon oxide). As the conductive film SG1_1b moves from the -X side to the +X side, it approaches the +Y side of columnar body PL1 and the +Y side of columnar body PL11 multiple times alternately. At each point of approach, an insulating film IF5 is interposed between the conductive film SG1_1b and the columnar bodies PL1 and PL11.

[0065] The portions of the columnar body PL1 facing the conductive films SG1_1a and SG1_1b via the insulating film IF5 function as selection transistors BT1. Selection transistors BT1 have a vertical thin-film transistor (TFT) structure in which the channel region extends in the Z direction and gates are located on both sides in the Y direction.

[0066] The portions of the columnar body PL11 facing the conductive films SG1_1a and SG1_1b via the insulating film IF5 function as selection transistors ST1. Selection transistors ST1 have a vertical thin-film transistor (TFT) structure in which the channel region extends in the Z direction and gates are located on both sides in the Y direction.

[0067] Furthermore, the same applies to the pairs of conductive films SG2_2a and SG2_2b, SG2_3a and SG2_3b, SG2_4a and SG2_4b, SG2_5a and SG2_5b, SG2_6a and SG2_6b, SG2_7a and SG2_7b, and SG2_8a and SG2_8b, respectively, as to the pairs of conductive films SG2_1a and SG2_1b. For example, the pairs of conductive films SG2_2a and SG2_2b, SG2_3a and SG2_3b, SG2_4a and SG2_4b, SG2_5a and SG2_5b, SG2_6a and SG2_6b, SG2_7a and SG2_7b, and SG2_8a and SG2_8b work together to function as select gate lines SG1_2, SG1_3, SG1_4, SG1_5, SG1_6, SG1_7, and SG1_8, respectively.

[0068] Figures 7 and 9 illustrate the arrangement of selection mechanisms SM2 and SM1, respectively, when multiple drive units DU_1 to DU_12 are arranged in a 4x3 grid.

[0069] In Figure 7, the selection mechanism SM2 is exemplified by selection transistors BT2_1 to BT2_12 and selection transistors ST2_1 to ST2_12. The selection transistors BT2_1 to BT2_12 correspond to the drive unit DU and are arranged in a 4x3 grid. The selection transistors ST2_1 to ST2_12 correspond to the drive unit DU and are arranged in a 4x3 grid.

[0070] In Figure 9, the selection mechanism SM1 is exemplified by selection transistors BT1_1 to BT1_4 and selection transistors ST1_1 to ST1_4. Selection transistors BT1_1 to BT1_12 correspond to the local bit line LBL and are arranged in a 4x1 grid on the -X side of the array of multiple drive units DU_1 to DU_12. Selection transistors ST1_1 to ST1_4 correspond to the local source line LSL and are arranged in a 4x1 grid on the +X side of the array of multiple drive units DU_1 to DU_12.

[0071] The local bit line LBL and local source line LSL are arranged alternately multiple times in the Y direction. The global bit line GBL is positioned on the -X side of the arrangement of multiple drive units DU_1 to DU_12 and extends in the Y direction. The global source line GSL is positioned on the +X side of the arrangement of multiple drive units DU_1 to DU_12 and extends in the Y direction.

[0072] For example, suppose that memory cell MT_n (see Figure 3) of drive unit DU_7 shown in Figures 7 and 9 is selected, and all memory cells MT_1 to MT_n-1 of drive unit DU_7 and all memory cells MT of other drive units DU_1 to DU_6, DU_8 to DU_12 are deselected.

[0073] When a write operation of "1" is performed to the selected memory cell MT_n by the drive unit DU_7, a select potential of "1" (e.g., -2.5V) is applied to the word line WL_n of the selected memory cell MT_n, and a deselect potential (e.g., 0V) is applied to the word lines WL_1 to WL_n-1 of the non-selected memory cells MT_1 to MT_n-1. The global bit line GBL and global source line GSL are each controlled to a select potential of "1" (e.g., 2.5V).

[0074] In Figures 7 and 9, the selected gate lines SG1_5a, SG1_5b, SG1_6a, SG1_6b and SG2_2a, SG2_2b, indicated by hatched lines, correspond to the selected memory cells MT_n. The selected gate lines SG1_5a, SG1_5b, SG1_6a, SG1_6b and SG2_2a, SG2_2b are controlled to a selection potential (e.g., 1.5V), while the other selected gate lines SG1_1a~SG1_4b, SG1_7a~SG1_8b and the other selected gate lines SG2_1a, SG2_1b, SG2_3a, SG2_3b are controlled to a non-selection potential (e.g., 0V).

[0075] As a result, the select transistors BT1 and BT2 of the drive unit DU_7 are selectively turned on, and the select potential of the global bit line GBL is supplied to the select memory cell MT_n of the drive unit DU_7 via the select transistors BT1 and BT2. The select transistors ST1 and ST2 of the drive unit DU_7 are selectively turned on, and the select potential of the global source line GSL is supplied to the select memory cell MT_n of the drive unit DU_7 via the select transistors ST1 and ST2.

[0076] In response, the channel region CH of the selected memory cell MT_n of the drive unit DU_7 becomes the selection potential (e.g., 2.5V), and in the selected memory cell MT_n of the drive unit DU_7, an electric field (e.g., 5V) exceeding the threshold for the word line WL_n to be positive relative to the channel region CH is applied to the insulating film FE, causing a write operation to the memory cell MT that shifts Vth in the negative direction. A "1" can be written to the memory cell MT_n of the drive unit DU_7. The memory cell MT_n can retain a "1" unless its polarization state changes due to an external electric field or the like.

[0077] In this case, in the non-selected memory cells MT_1 to MT_n-1 of the selection drive unit DU_7, the selection potentials of the global bit line GBL and global source line GSL are supplied, but an electric field below the positive threshold (e.g., 2.5V) is applied to the insulating film FE, and no writing occurs to the memory cell MT.

[0078] Alternatively, when a write operation of "0" is performed to the selected memory cell MT_n of the drive unit DU_7, a select potential of "0" (e.g., 2.5V) is applied to the word line WL_n of the selected memory cell MT_n, and a deselect potential (e.g., 0V) is applied to the word lines WL_1 to WL_n-1 of the unselected memory cells MT_1 to MT_n-1. The global bit line GBL and global source line GSL are controlled to a select potential of "0" (e.g., -2.5V).

[0079] In Figures 7 and 9, the selected gate lines SG1_5a, SG1_5b, SG1_6a, SG1_6b and SG2_2a, SG2_2b, indicated by hatched lines, correspond to the selected memory cells MT_n. The selected gate lines SG1_5a, SG1_5b, SG1_6a, SG1_6b and SG2_2a, SG2_2b are controlled to a selection potential (e.g., 1.5V), while the other selected gate lines SG1_1a~SG1_4b, SG1_7a~SG1_8b and the other selected gate lines SG2_1a, SG2_1b, SG2_3a, SG2_3b are controlled to a non-selection potential (e.g., 0V).

[0080] As a result, the select transistors BT1_3 and BT2_7 of the drive unit DU_7 are selectively turned on, and the select potential of the global bit line GBL is supplied to the select memory cell MT_n of the drive unit DU_7 via the select transistors BT1_3 and BT2_7. The select transistors ST1_3 and ST2_7 of the drive unit DU_7 are selectively turned on, and the select potential of the global source line GSL is supplied to the select memory cell MT_n of the drive unit DU_7 via the select transistors ST1_3 and ST2_7.

[0081] In response, the channel region CH of the selected memory cell MT_n of the drive unit DU_7 becomes the selection potential (e.g., -2.5V), and in the selected memory cell MT_n, an electric field (e.g., -5V) exceeding the threshold for the word line WL_n to become negative relative to the channel region CH is applied to the insulating film FE, causing a write operation to the memory cell MT_n that shifts Vth in the positive direction. A "0" can be written to the memory cell MT_n of the drive unit DU_7. The memory cell MT_n of the drive unit DU_7 can retain a "0" unless its polarization state changes due to an external electric field or the like.

[0082] In this case, in the non-selected memory cells MT_1 to MT_n-1 of the drive unit DU_7, the selection potentials of the global bit line GBL and global source line GSL are supplied, but an electric field below the positive threshold (e.g., 2.5V) is applied to the insulating film FE, and no writing occurs to the memory cell MT.

[0083] Alternatively, when a read operation is performed on the selected memory cell MT_n of the drive unit DU_7, the read selection potential (e.g., 1.5V) is applied to the word line WL_n of the selected memory cell MT_n, and the deselection potential (e.g., 0V) is applied to the word lines WL_1 to WL_n-1 of the non-selected memory cells MT_1 to MT_n-1. The global bit line GBL is controlled to the read selection potential (e.g., 0.5V), and the global source line GSL is controlled to the read selection potential (e.g., 0V).

[0084] In Figures 7 and 9, the selected gate lines SG1_5a, SG1_5b, SG1_6a, SG1_6b and SG2_2a, SG2_2b, indicated by hatched lines, correspond to the selected memory cells MT_n. The selected gate lines SG1_5a, SG1_5b, SG1_6a, SG1_6b and SG2_2a, SG2_2b are controlled to a selection potential (e.g., 1.5V), while the other selected gate lines SG1_1a~SG1_4b, SG1_7a~SG1_8b and the other selected gate lines SG2_1a, SG2_1b, SG2_3a, SG2_3b are controlled to a non-selection potential (e.g., 0V).

[0085] As a result, the select transistors BT1_3 and BT2_7 of the drive unit DU_7 are selectively turned on, and the select potential of the global bit line GBL is supplied to the select memory cell MT_n of the drive unit DU_7 via the select transistors BT1_3 and BT2_7. The select transistors ST1_3 and ST2_7 of the drive unit DU_7 are selectively turned on, and the select potential of the global source line GSL is supplied to the select memory cell MT_n of the drive unit DU_7 via the select transistors ST1_3 and ST2_7.

[0086] If "1" is written to the selected memory cell MT_n of the drive unit DU_7, cell current flows from the conductive film BL to the conductive film SL in the channel region CH of the selected memory cell MT_n, causing the potential of the conductive film BL to decrease. The sense amplifier circuit 150 detects "1" in response to the decrease in the potential of the conductive film BL. As a result, "1" is read from the selected memory cell MT_n of the drive unit DU_7. Alternatively, if "0" is written to the selected memory cell MT_n of the drive unit DU_7, almost no cell current flows from the conductive film BL to the conductive film SL in the channel region CH of the selected memory cell MT_1, and the potential of the conductive film BL is maintained. The sense amplifier circuit 150 detects "0" in response to the maintenance of the potential of the conductive film BL. As a result, "0" is read from the selected memory cell MT_n of the drive unit DU_7.

[0087] In this case, in the non-selected memory cells MT_1 to MT_n-1 of the selection drive unit DU_7, the selection potential is supplied to the global bit line GBL and the global source line GSL, but the non-selected potential is supplied to the word lines WL_1 to WL_n-1. Therefore, no reads occur from the memory cells MT in the non-selected memory cells MT_1 to MT_n-1 of the selection drive unit DU_7.

[0088] As described above, in this embodiment, the memory cell selection mechanisms SM1 and SM2 of the semiconductor memory device 1 are arranged between the substrate SB and the memory cell array 2 in the Z direction. As a result, in the manufacturing process of the semiconductor memory device 1, the structure of the array layer L3 is formed after a relatively high-temperature heat treatment is completed. Therefore, a semiconductor memory device 1 structure is provided that is suitable for avoiding this heat treatment being applied to each insulating film FE when each insulating film FE contains a ferroelectric material.

[0089] As a first modification of the embodiment, in the selection mechanism SM101, the conductive film functioning as the selection gate line SG1 may be arranged on one side in the Y direction of the columnar bodies PL1 and PL11, as shown in Figures 10 and 11. Figure 10 is a YZ cross-sectional view showing the configuration of the array layer L3, selection gate layer L2, and selection gate layer L1 in the first modification of the embodiment, and corresponds to the cross-section obtained when Figure 5 is cut along the CC line. Figure 11 is an XY plan view showing the configuration of the selection gate layer L1, and corresponds to the cross-section obtained when Figure 10 is cut along the GG line.

[0090] In the selective gate layer L1, each selective gate line SG1 omits one of the two conductive films located on both sides of the columnar bodies PL1 and PL11 in the Y direction. Figures 10 and 11 illustrate a configuration in which the conductive film located on the -Y side of the two conductive films located on both sides of the columnar bodies PL1 and PL11 in the Y direction is omitted.

[0091] As shown in Figures 10 and 11, the select gate wire SG1_1 has a conductive film SG1_1b. The select gate wire SG1_2 has a conductive film SG1_2b. The select gate wire SG1_3 has a conductive film SG1_3b. The select gate wire SG1_4 has a conductive film SG1_4b. The select gate wire SG1_5 has a conductive film SG1_5b. The select gate wire SG1_6 has a conductive film SG1_6b. The select gate wire SG1_7 has a conductive film SG1_7b. The select gate wire SG1_8 has a conductive film SG1_8b.

[0092] As shown in Figure 11, the conductive film SG1_1b approaches the +Y side of columnar body PL1 and the +Y side of columnar body PL11 alternately multiple times as it moves from the -X side to the +X side. At each point of approach, the insulating film IF5 is interposed between the conductive film SG1_1b and the columnar bodies PL1 and PL11.

[0093] The portion of the columnar body PL1 facing the conductive film SG1_1b via the insulating film IF5 functions as the selection transistor BT1 in the selection mechanism SM101. The selection transistor BT1 has a vertical thin-film transistor (TFT) structure in which the channel region extends in the Z direction and the gate is on one side in the Y direction.

[0094] The portion of the columnar body PL11 facing the conductive film SG1_1b via the insulating film IF5 functions as the selection transistor ST1 in the selection mechanism SM101. The selection transistor ST1 has a vertical thin-film transistor (TFT) structure in which the channel region extends in the Z direction and the gate is on one side in the Y direction.

[0095] Furthermore, conductive films SG2_2b, SG2_3b, SG2_4b, SG2_5b, SG2_6b, SG2_7b, and SG2_8b are the same as conductive film SG2_1b.

[0096] Thus, in the selection mechanism SM101, a conductive film that functions as the selection gate line SG1 is arranged on one side in the Y direction of the columnar bodies PL1 and PL11. This allows the distance between the columnar bodies PL1 and PL11 in the Y direction to be brought closer to each other, and consequently, the distance between the local bit line LBL and the local source line LSL in the Y direction can be brought closer to each other. As a result, the arrangement density of the selection transistor BT1 and the arrangement density of the selection transistor ST1 in the Y direction can be improved.

[0097] Alternatively, as a second modification of the embodiment, in the selection mechanism SM202, the conductive film functioning as the selection gate line SG2 may be arranged on one side in the X direction of the columnar bodies PL2 and PL12, as shown in Figures 12 and 13. Figure 12 is a YZ cross-sectional view showing the configuration of the array layer L3, selection gate layer L2, and selection gate layer L1 in the second modification of the embodiment, and corresponds to the cross-section obtained when Figure 5 is cut along the BB line. Figure 13 is an XY plan view showing the configuration of the selection gate layer L1, and corresponds to the cross-section obtained when Figure 12 is cut along the HH line.

[0098] In the selective gate layer L2, for each selective gate line SG2, one of the two conductive films located on both sides of the columnar bodies PL2 and PL12 in the X direction is omitted. Figures 12 and 13 illustrate a configuration in which the conductive film located on the -Y side of the two conductive films located on both sides of the columnar bodies PL2 and PL12 in the X direction is omitted.

[0099] The select gate wire SG2_1 shown in Figures 12 and 13 has a conductive film SG2_1a. The select gate wire SG2_2 has a conductive film SG2_2a. The select gate wire SG2_3 has a conductive film SG2_3a.

[0100] As shown in Figure 13, the conductive film SG2_1a approaches the +Y side of columnar body PL2 and the +Y side of columnar body PL12 alternately multiple times as it moves from the -Y side to the +Y side. At each point of approach, the insulating film IF4 is interposed between the conductive film SG2_1a and the columnar bodies PL2 and PL12.

[0101] The portion of the columnar body PL2 facing the conductive film SG2_1a via the insulating film IF4 functions as the selection transistor BT2 in the selection mechanism SM202. The selection transistor BT2 has a vertical thin-film transistor (TFT) structure in which the channel region extends in the Z direction and the gate is on one side in the X direction.

[0102] The portion of the columnar body PL12 facing the conductive film SG2_1a via the insulating film IF4 functions as the selection transistor ST2 in the selection mechanism SM202. The selection transistor ST2 has a vertical thin-film transistor (TFT) structure in which the channel region extends in the Z direction and the gate is on one side in the X direction.

[0103] Furthermore, conductive films SG2_2a and SG2_3a are the same as conductive film SG2_1a, respectively.

[0104] Thus, in the selection mechanism SM202, a conductive film that functions as the selection gate line SG2 is arranged on one side in the X direction of the columnar bodies PL2 and PL12. This allows the distance between the columnar bodies PL2 and PL12 in the X direction to be brought closer to each other. As a result, the arrangement density of the selection transistor BT2 and the arrangement density of the selection transistor ST2 in the X direction can be improved.

[0105] Alternatively, as a third modification of the embodiment, the conductive film functioning as the selection gate line SG1 in the selection mechanism SM301 may be divided into two layers.

[0106] The semiconductor memory device 301 has a selection gate layer L301u and a selection gate layer L301d instead of a selection gate layer L1 (see Figure 8), as shown in Figure 14. Figure 14 is a YZ cross-sectional view showing the configuration of the array layer L3, selection gate layer L2, selection gate layer L301u, and selection gate layer L301d in a third modified example of the embodiment, and corresponds to the cross-section obtained when Figure 5 is cut along the CC line.

[0107] The selective gate layer L301d is positioned between the substrate SB and the selective gate layer L301u in the Z direction. The selective gate layer L301u is positioned between the selective gate layer L301d and the connecting layer CL in the Z direction.

[0108] The selection mechanism SM301 is divided into a selection gate layer L301u and a selection gate layer L301d. The selection mechanism SM301 includes a selection transistor BT1 and a selection transistor ST1. One of the selection transistors BT1 and ST1 is located in the selection gate layer L301u, and the other is located in the selection gate layer L301d. Figure 14 illustrates a configuration in which the selection transistor BT1 is located in the selection gate layer L301u and the selection transistor ST1 is located in the selection gate layer L301d.

[0109] In the selection gate layer L301u, multiple columnar bodies PL1, odd-numbered selection gate lines SG1_1, SG1_3, SG1_5, SG1_7, and multiple insulating films IF5u are arranged.

[0110] Select gate line SG1_1 has multiple conductive films SG1_1a and SG1_1b. Select gate line SG1_3 has multiple conductive films SG1_3a and SG1_3b. Select gate line SG1_5 has multiple conductive films SG1_5a and SG1_5b. Select gate line SG1_7 has multiple conductive films SG1_7a and SG1_7b.

[0111] In the selection gate layer L301d, multiple columnar bodies PL11, even-numbered selection gate lines SG1_2, SG1_4, SG1_6, SG1_8, and multiple insulating films IF5d are arranged.

[0112] Select gate line SG1_2 has multiple conductive films SG1_2a and SG1_2b. Select gate line SG1_4 has multiple conductive films SG1_4a and SG1_4b. Select gate line SG1_6 has multiple conductive films SG1_6a and SG1_6b. Select gate line SG1_8 has multiple conductive films SG1_8a and SG1_8b.

[0113] The conductive films SG1_2a and SG1_2b are spaced apart in the Y direction from the conductive films SG1_1a and SG1_1b, as well as in the Z direction. This suppresses electric field interference between the conductive films SG1_2a and SG1_2b and the conductive films SG1_1a and SG1_1b.

[0114] The conductive films SG1_4a and SG1_4b are spaced apart in the Y direction from the conductive films SG1_3a and SG1_3b, as well as in the Z direction. This suppresses electric field interference between the conductive films SG1_4a and SG1_4b and the conductive films SG1_3a and SG1_3b.

[0115] The conductive films SG1_8a and SG1_8b are spaced apart in the Y direction from the conductive films SG1_7a and SG1_7b, as well as in the Z direction. This suppresses electric field interference between the conductive films SG1_8a and SG1_8b and the conductive films SG1_7a and SG1_7b.

[0116] Thus, in the selection mechanism SM301, multiple conductive films that function as the selection gate line SG1 are arranged to be spaced apart not only in the Y direction but also in the Z direction. This suppresses electric field interference between the multiple conductive films and allows the distance between the columnar bodies PL1 and PL11 in the Y direction to be brought closer together. Consequently, the distance between the local bit line LBL and the local source line LSL in the Y direction can be brought closer together. As a result, the arrangement density of the selection transistor BT1 and the selection transistor ST1 in the Y direction can be improved.

[0117] Alternatively, as a fourth modification of the embodiment, the selection mechanism SM401 for the selection gate layer L401 may be configured as shown in Figure 15. Figure 15 is a plan view showing the configuration of the selection gate layer L401 and the operation of the selection gate layer L401 when "1" is written in the fourth modification of the embodiment.

[0118] In the selection gate layer L401, in addition to the selection transistors BT1_1 to BT1_4 and ST1_1 to ST1_4 (see Figure 9), the selection mechanism SM401 is provided with selection transistors BT401_1 to BT401_4 and ST401_1 to ST401_4.

[0119] The selection transistor BT401 is connected between the local source line LSL and the global bit line GBL. The drain of the selection transistor BT401 is connected to the local source line LSL, the source is connected to the global bit line GBL, and the gate is connected to the selection gate line SG1. The selection transistor BT401 is driven via the selection gate line SG1, which is connected to its gate.

[0120] The selection gate line SG401R, which is connected to the gate of selection transistor BT401, and the selection gate line SG1L, which is connected to selection transistor ST1 located on the +X side, are separate. This allows selection transistors BT401 and ST1 to be controlled on and off individually.

[0121] The selection transistor ST401 is connected between the local bit line LBL and the global source line GSL. The drain of the selection transistor ST401 is connected to the local bit line LBL, the source is connected to the global source line GSL, and the gate is connected to the selection gate line SG1. The selection transistor ST401 is driven via the selection gate line SG401, which is connected to its gate.

[0122] The selection gate line SG401L, which is connected to the gate of selection transistor ST401, and the selection gate line SG1R, which is connected to selection transistor BT1 located on its -X side, are separate. This allows selection transistors ST401 and BT1 to be controlled on and off individually.

[0123] The memory cell group MG is selected and connected in two stages by the global bit line GBL, either by selection transistors BT1 and BT2, or by selection transistors BT401 and ST2. The memory cell group MG is also selected and connected in two stages by the global source line GSL, either by selection transistors ST1 and ST2, or by selection transistors ST401 and BT2. The selection of memory cells MT within the selected memory cell group MG is performed by the word line WL.

[0124] When a write operation of "1" is performed by the drive unit DU_7 to the selected memory cell MT_7n, the global bit line GBL is controlled to a select potential of "1" (e.g., -2.5V) and the global source line GSL is controlled to a non-select potential (e.g., 0.0V), as shown in Figure 15. As shown in Figures 16 and 17, a select potential of "1" (e.g., +2.5V) is applied to the word line WL_7n of the selected memory cell MT_7n, and a non-select potential (e.g., 0V) is applied to the word lines WL_7n-1, WL_3n, WL_3n-1 of the non-selected memory cells MT_7n-1, MT_3n, MT_3n-1.

[0125] The selected gate lines SG1L_3 and SG401L_3 correspond to the selected memory cells MT_7n of the drive unit DU7. The selected gate lines SG1L_3 and SG401L_3 are controlled to a selected potential (e.g., +2.5V), while the other selected gate lines are controlled to a non-selected potential (e.g., 0V).

[0126] In Figure 15, the selected gate line SG2_2a, indicated by the hatched area, is controlled to a selected potential (e.g., +2.5V), while the other selected gate lines SG1_1a and SG1_3a are controlled to non-selected potentials (e.g., 0.0V).

[0127] As a result, on the -X side, the selection transistors BT1_3 and BT2_7 of the drive unit DU_7 are selectively turned on, and the selection potential of the global bit line GBL is supplied to one end of the selection memory cell MT_7n of the drive unit DU_7 via the selection transistors BT1_3 and BT2_7. The selection transistors BT401_3 and ST2_7 of the drive unit DU_7 are selectively turned on, and the selection potential of the global bit line GBL is supplied to the other end of the selection memory cell MT_7n of the drive unit DU_7 via the selection transistors BT401_3 and ST2_7.

[0128] In response, the channel region CH of the selected memory cell MT_7n of the drive unit DU_7 becomes the selection potential (e.g., +2.5V), and in the selected memory cell MT_7n of the drive unit DU_7, an electric field (e.g., -5V) exceeding the threshold for the word line WL_7n to become negative relative to the channel region CH is applied to the insulating film FE, causing a write operation to the memory cell MT that shifts Vth in the negative direction. A "1" can be written to the memory cell MT_7n of the drive unit DU_7. The memory cell MT_7n can retain a "1" unless its polarization state changes due to an external electric field or the like.

[0129] In this case, the global bit line GBL is supplied to the non-selected memory cell MT_7n-1 in the selected drive unit DU_7 and to MT_3n,MT_3n-1 in the non-selected drive unit DU_3, but an electric field below the threshold (e.g., -2.5V) is applied to the insulating film FE, and no write occurs to the memory cell MT.

[0130] Furthermore, on the +X side, the selection transistors ST1_1, ST401_1, ST1_2, ST1_402, ST1_4, and ST401_4 are selectively turned on, and the unselected potential of the global source line GSL is supplied to the unselected memory cell MT via the selection transistors ST1_1, ST401_1, ST1_2, ST1_402, ST1_4, and ST401_4. Because it is an unselected potential, no write occurs to the memory cell MT.

[0131] Alternatively, when a write operation of "0" is performed to the selected memory cell MT_7n by the drive unit DU_7, the global bit line GBL is controlled to a select potential of "0" (e.g., +2.5V) and the global source line GSL is controlled to a deselect potential (e.g., 0.0V), as shown in Figure 18. As shown in Figures 19 and 20, a select potential of "1" (e.g., +2.5V) is applied to the word line WL_7n of the selected memory cell MT_7n, and a deselect potential (e.g., 0V) is applied to the word lines WL_7n-1, WL_3n, WL_3n-1 of the non-selected memory cells MT_7n-1, MT_3n, MT_3n-1.

[0132] The selected gate lines SG1L_3 and SG401L_3 correspond to the selected memory cells MT_7n of the drive unit DU7. The selected gate lines SG1L_3 and SG401L_3 are controlled to a selected potential (e.g., +2.5V), while the other selected gate lines are controlled to a non-selected potential (e.g., 0V).

[0133] In Figure 18, the selected gate line SG2_2a, indicated by the hatched area, is controlled to a selected potential (e.g., -2.5V), while the other selected gate lines SG1_1a and SG1_3a are controlled to non-selected potentials (e.g., 0.0V).

[0134] As a result, on the -X side, the selection transistors BT1_3 and BT2_7 of the drive unit DU_7 are selectively turned on, and the selection potential of the global bit line GBL is supplied to one end of the selection memory cell MT_7n of the drive unit DU_7 via the selection transistors BT1_3 and BT2_7. The selection transistors BT401_3 and ST2_7 of the drive unit DU_7 are selectively turned on, and the selection potential of the global bit line GBL is supplied to the other end of the selection memory cell MT_7n of the drive unit DU_7 via the selection transistors BT401_3 and ST2_7.

[0135] In response, the channel region CH of the selected memory cell MT_7n of the drive unit DU_7 becomes the selection potential (e.g., -2.5V), and in the selected memory cell MT_7n of the drive unit DU_7, an electric field (e.g., +5V) exceeding the threshold for the word line WL_7n to be positive relative to the channel region CH is applied to the insulating film FE, causing a write operation to the memory cell MT that shifts Vth in the positive direction. A "0" can be written to the memory cell MT_7n of the drive unit DU_7. The memory cell MT_7n can retain a "0" unless its polarization state changes due to an external electric field or the like.

[0136] In this case, the global bit line GBL is supplied to the non-selected memory cell MT_7n-1 in the selected drive unit DU_7 and to MT_3n,MT_3n-1 in the non-selected drive unit DU_3, but an electric field below the positive threshold (e.g., +2.5V) is applied to the insulating film FE, and no write occurs to the memory cell MT.

[0137] Furthermore, on the +X side, the selection transistors ST1_1, ST401_1, ST1_2, ST1_402, ST1_4, and ST401_4 are selectively turned on, and the unselected potential of the global source line GSL is supplied to the unselected memory cell MT via the selection transistors ST1_1, ST401_1, ST1_2, ST1_402, ST1_4, and ST401_4. Because it is an unselected potential, no write occurs to the memory cell MT.

[0138] Alternatively, when a read operation is performed on the selected memory cell MT_7n of the drive unit DU_7, the global bit line GBL is controlled to the read selection potential (e.g., +0.5V) and the global source line GSL is controlled to the deselection potential (e.g., 0.0V), as shown in Figure 21. As shown in Figures 22 and 23, the read selection potential (e.g., +1.5V) is applied to the word line WL_7n of the selected memory cell MT_7n, and the deselection potential (e.g., 0V) is applied to the word lines WL_7n-1, WL_3n, WL_3n-1 of the non-selected memory cells MT_7n-1, MT_3n, MT_3n-1.

[0139] The selected gate lines SG1L_3 and SG401R_3 correspond to the selected memory cells MT_7n of the drive unit DU7. The selected gate lines SG1L_3 and SG401R_3 are controlled to a selected potential (e.g., +2.5V), while the other selected gate lines are controlled to a non-selected potential (e.g., 0V).

[0140] In Figure 21, the selected gate line SG2_2a, indicated by the hatched area, is controlled to a selected potential (e.g., +1.5V), while the other selected gate lines SG1_1a and SG1_3a are controlled to non-selected potentials (e.g., 0.0V).

[0141] As a result, on the -X side, the selection transistors BT1_3 and BT2_7 of the drive unit DU_7 are selectively turned on, respectively, and on the +X side, the selection transistors ST401_3 and ST2_7 of the drive unit DU_7 are selectively turned on, respectively. The selection potential of the global bit line GBL is supplied to one end of the selection memory cell MT_7n of the drive unit DU_7 via the selection transistors BT1_3 and BT2_7, and the non-selection potential of the global source line GSL is supplied to the other end of the selection memory cell MT_7n of the drive unit DU_7 via the selection transistors ST401_3 and ST2_7.

[0142] If "1" is written to the select memory cell MT_7n of the drive unit DU_7, cell current flows from the conductive film BL to the conductive film SL in the channel region CH of the select memory cell MT_7n, causing the potential of the conductive film BL to decrease. The sense amplifier circuit 150 detects "1" in response to the decrease in the potential of the conductive film BL. As a result, "1" is read from the select memory cell MT_7n of the drive unit DU_7. Alternatively, if "0" is written to the select memory cell MT_7n of the drive unit DU_7, almost no cell current flows from the conductive film BL to the conductive film SL in the channel region CH of the select memory cell MT_7n, and the potential of the conductive film BL is maintained. The sense amplifier circuit 150 detects "0" in response to the maintenance of the potential of the conductive film BL. As a result, "0" is read from the select memory cell MT_7n of the drive unit DU_7.

[0143] In this case, in the non-selected memory cell MT_7n-1 in the selected drive unit DU_7 and MT_3n,MT_3n-1 in the non-selected drive unit DU_3, the selected potential of the global bit line GBL and the non-selected potential of the global source line GSL are supplied to both ends, but the non-selected potential is supplied to the word lines WL_7n-1,WL_3n,WL_3n-1. Therefore, no reads occur from the memory cell MT in the non-selected memory cell MT_7n-1 in the selected drive unit DU_7 and MT_3n,MT_3n-1 in the non-selected drive unit DU_3.

[0144] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0145] 1. Semiconductor memory device; 2. Memory cell array; BT1, BT2, ST1, ST2 selection transistors; MT memory cell; SM1, SM2 selection mechanism.

Claims

1. A plurality of first memory cells are stacked on top of the substrate and connected in parallel between a first vertical bit line extending in the stacking direction and a first vertical source line extending in the stacking direction, A first selection mechanism is disposed between the substrate and the plurality of first memory cells in the stacking direction, and selectively connects the first vertical bit line to the first local bit line and the first vertical source line to the first local source line, A semiconductor memory device equipped with the following features.

2. The system further comprises a second selection mechanism disposed between the substrate and the first selection mechanism in the stacking direction, which selectively connects the first local bit line to the global bit line and the first local source line to the global source line. The semiconductor memory device according to claim 1.

3. The first selection mechanism described above is: A first selection transistor, the drain of which is connected to the first vertical bit line and the source of which is connected to the first local bit line, A second selection transistor, the drain of which is connected to the first vertical source line and the source of which is connected to the first local source line, has The semiconductor memory device according to claim 1.

4. The first selection mechanism described above is: A first selection transistor, the drain of which is connected to the first vertical bit line and the source of which is connected to the first local bit line, A second selection transistor, the drain of which is connected to the first vertical source line and the source of which is connected to the first local source line, It has, The second selection mechanism described above is: A third selection transistor, the drain of which is connected to the first local bit line and the source of which is connected to the global bit line, A fourth selection transistor, the drain of which is connected to the first local source line and the source of which is connected to the global source line, has The semiconductor memory device according to claim 2.

5. The gates of the first selection transistor and the second selection transistor are connected in common to the first selection gate line. The semiconductor memory device according to claim 3.

6. The gates of the first selection transistor and the second selection transistor are connected in common to the first selection gate line. The gate of the third selection transistor is connected to the second selection gate line. The gate of the fourth selection transistor is connected to the third selection gate line. The semiconductor memory device according to claim 4.

7. The first selection transistor includes a semiconductor and has a first columnar body extending in the stacking direction, The second selection transistor includes a semiconductor and has a second columnar body extending in the stacking direction, The first selection transistor and the second selection transistor are adjacent to each other in a first direction perpendicular to the stacking direction, The first selected gate line is, It has a first conductive film that extends in the first direction and covers the side surface of the first columnar body and the side surface of the second columnar body, respectively, with an insulating film in between. The semiconductor memory device according to claim 5.

8. The first selection transistor includes a semiconductor and has a first columnar body extending in the stacking direction, The second selection transistor includes a semiconductor and has a second columnar body extending in the stacking direction, The first selection transistor and the second selection transistor are adjacent to each other in a first direction perpendicular to the stacking direction, The first selected gate line is, A first conductive film extending in the first direction and covering the first side surface of the first columnar body and the second side surface of the second columnar body via an insulating film, A second conductive film extends in the first direction on the opposite side of the first and second selection transistors, and covers the first second side surface of the first columnar body and the second second side surface of the second columnar body via an insulating film, has The semiconductor memory device according to claim 5.

9. The first selection transistor includes a semiconductor and has a first columnar body extending in the stacking direction, The second selection transistor includes a semiconductor and has a second columnar body extending in the stacking direction, The first selection transistor and the second selection transistor are adjacent to each other in a first direction perpendicular to the stacking direction, The first selected gate line is, It has a first conductive film that extends in the first direction and covers the side surface of the first columnar body and the side surface of the second columnar body via an insulating film, The third selected transistor comprises a semiconductor and has a third columnar body extending in the stacking direction. The fourth selection transistor includes a semiconductor and has a fourth columnar body extending in the stacking direction, The third selected gate line is, It has a third conductive film that extends in a second direction perpendicular to the stacking direction and the first direction, and covers the side surface of the third columnar body via an insulating film, The fourth selected gate line is, The present invention has a fourth conductive film that extends in the second direction and covers the side surface of the third columnar body via an insulating film. The semiconductor memory device according to claim 6.

10. The first selection transistor includes a semiconductor and has a first columnar body extending in the stacking direction, The second selection transistor includes a semiconductor and has a second columnar body extending in the stacking direction, The first selection transistor and the second selection transistor are adjacent to each other in a first direction perpendicular to the stacking direction, The first selected gate line is, A first conductive film extending in the first direction and covering the first side surface of the first columnar body and the second side surface of the second columnar body via an insulating film, A second conductive film extends in the first direction on the opposite side of the first and second selection transistors, and covers the first second side surface of the first columnar body and the second second side surface of the second columnar body via an insulating film, It has, The third selected gate line is, A third conductive film extending in the second direction and covering the side surface of the third columnar body via an insulating film, A fifth conductive film extends in the second direction on the opposite side of the third selection transistor and covers the second side surface of the third columnar body via an insulating film, It has, The fourth selected gate line is, A fourth conductive film extending in the second direction and covering the side surface of the fourth columnar body via an insulating film, A sixth conductive film extends in the second direction on the opposite side of the fourth selection transistor and covers the second side of the fourth columnar body via an insulating film, has The semiconductor memory device according to claim 6.

11. The substrate further comprises a plurality of second memory cells stacked above the plurality of first memory cells, adjacent to the plurality of first memory cells in a first direction perpendicular to the stacking direction, and connected in parallel between a second vertical bit line extending in the stacking direction and a second vertical source line extending in the stacking direction. The first selection mechanism is disposed between the substrate and the plurality of second memory cells in the stacking direction, and selectively connects the second vertical bit line to the first local bit line and the second vertical source line to the first local source line. The semiconductor memory device according to claim 1.

12. The substrate further comprises a plurality of second memory cells stacked above the plurality of first memory cells, adjacent to the plurality of first memory cells in a first direction perpendicular to the stacking direction, and connected in parallel between a second vertical bit line extending in the stacking direction and a second vertical source line extending in the stacking direction. The first selection mechanism is arranged between the substrate and the plurality of second memory cells in the stacking direction, and selectively connects the second vertical bit line to the second local bit line, and selectively connects the second vertical source line to the second local source line, The second selection mechanism selectively connects the second local bit line to the global bit line and selectively connects the second local source line to the global source line. The semiconductor memory device according to claim 2.

13. The first vertical bit line and the second vertical bit line are adjacent in the first direction, The first vertical source line and the second vertical source line are adjacent in the first direction. The semiconductor memory device according to claim 11.

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