Semiconductor memory

Abstract

To provide a semiconductor memory device that enables high integration. [Solution] In the memory die, chip C M The base layer L SB Below that is the memory cell array layer L MCA Below that, a via contact electrode layer CH is provided, and below that, a plurality of wiring layers M0, M1, and below that, a chip bonding electrode layer MB is also provided. The substrate layer is provided with a conductive layer 100 on the upper surface of the memory cell array layer, an insulating layer 101 on the upper surface of the conductive layer, a back wiring layer MA on the upper surface of the back wiring layer MA, and an insulating layer 102 on the upper surface of the back wiring layer MA. The back wiring layer includes a plurality of wirings MA, some of which function as part of the source lines and are electrically connected to the conductive layer, and some which are external pad electrodes P X It functions as a peripheral region and is located in the surrounding area. The wiring ma is connected to the via contact electrode CC in the memory cell array layer in region VZ which does not contain the conductive layer, and a portion of it is exposed to the outside of the memory die through an aperture TV provided in the insulating layer.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that has a semiconductor substrate and a memory cell array layer disposed opposite to the semiconductor substrate, wherein the memory cell array layer has a stacked structure comprising alternately stacked conductive layers and insulating layers, and a semiconductor layer extending in the stacking direction of these conductive and insulating layers and facing the conductive layers. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2023 / 0036595 [Patent Document 2] U.S. Patent Application Publication No. 2023 / 0056261 [Overview of the project] [Problems that the invention aims to solve]

[0004] To provide a semiconductor memory device that enables high integration. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment comprises a semiconductor substrate and a memory cell array layer provided at a distance from the semiconductor substrate in a first direction intersecting the surface of the semiconductor substrate, wherein the memory cell array layer comprises a first stacked structure and a second stacked structure arranged in a second direction intersecting the first direction, and a third stacked structure provided between the first stacked structure and the second stacked structure. Each of the first stacked structure, the second stacked structure and the third stacked structure comprises a plurality of first layers and a plurality of first insulating layers alternately stacked in the first direction and extending in a third direction intersecting the first and second directions. Each of the first stacked structure and the second stacked structure comprises a plurality of blocks arranged in the second direction. Each of the plurality of blocks comprises a first semiconductor layer extending in the first direction and facing the plurality of first layers. Of the plurality of blocks, a plurality of blocks excluding the first block closest to the third stacked structure include a first conductive layer in the first layer. In the third stacked structure and the first block, the first layer is a second insulating layer. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. [Figure 2] This is a schematic circuit diagram showing a part of the configuration of the memory die MD. [Figure 3] This is a schematic exploded perspective view showing an example configuration of a memory die MD. [Figure 4] This is a schematic bottom view showing an example of the configuration of a chip CM. [Figure 5] This is a schematic plan view showing an example of the configuration of a chip CP. [Figure 6] This is a schematic cross-sectional view showing a portion of the configuration of a memory die (MD). [Figure 7] This is a schematic cross-sectional view showing a portion of the configuration of a memory die (MD). [Figure 8] This is a schematic cross-sectional view showing a portion of the configuration of a memory die (MD). [Figure 9]Figure 6 is a magnified rear view of a portion of the memory block BLK as seen from the Z direction. [Figure 10] This is a cross-sectional view, enlarged from a portion of Figure 6. [Figure 11] Figure 4 is an enlarged plan view of the portion indicated by D in the chip CM. [Figure 12] This is a cross-sectional view of a portion of the substrate layer LSB and the memory cell array layer LMCA of the chip CM, taken along the EE' line in Figure 11 and viewed in the direction of the arrow. [Figure 13] This is a schematic plan view of the portion indicated by F in Figure 4, enlarged. [Figure 14] This is a cross-sectional view illustrating the manufacturing method of the memory die MD according to this embodiment. [Figure 15] This is a cross-sectional view illustrating the manufacturing method of the memory die MD according to this embodiment. [Figure 16] This is a cross-sectional view illustrating the manufacturing method of the memory die MD according to this embodiment. [Figure 17] This is a cross-sectional view illustrating the manufacturing method of the memory die MD according to this embodiment. [Figure 18] This is a cross-sectional view illustrating the manufacturing method of the memory die MD according to this embodiment. [Figure 19] This is a cross-sectional view illustrating the manufacturing method of the memory die MD according to this embodiment. [Figure 20] This is a cross-sectional view illustrating the manufacturing method of the memory die MD according to this embodiment. [Figure 21] This is a cross-sectional view illustrating the manufacturing method of the memory die MD according to this embodiment. [Figure 22] This is a cross-sectional view illustrating the manufacturing method of the memory die MD according to this embodiment. [Figure 23] This is a cross-sectional view illustrating the manufacturing method of the memory die MD according to this embodiment. [Figure 24] This is a cross-sectional view illustrating the manufacturing method of the memory die MD according to this embodiment. [Figure 25]This is a cross-sectional view illustrating the manufacturing method of the memory die MD according to this embodiment. [Figure 26] This is a cross-sectional view illustrating the manufacturing method of the memory die MD according to this embodiment. [Figure 27] This is an enlarged plan view of the portion indicated by D of the chip CM of the memory die MD according to the second embodiment. [Figure 28] This is a cross-sectional view of a portion of the substrate layer LSB and the memory cell array layer LMCA of the chip CM, cut along the HH' line in Figure 27 and viewed in the direction of the arrow. [Figure 29] This is a cross-sectional view corresponding to Figure 28, illustrating the manufacturing method of the chip CM. [Figure 30] This is a plan view corresponding to Figure 27, illustrating the manufacturing method of the chip CM. [Figure 31] This is a cross-sectional view corresponding to Figure 28, illustrating the manufacturing method of the chip CM. [Figure 32] This is an enlarged plan view of the portion indicated by D of the chip CM of the memory die MD according to the third embodiment. [Figure 33] This is a cross-sectional view of a portion of the substrate layer LSB and the memory cell array layer LMCA of the chip CM, cut along line II' in Figure 32 and viewed in the direction of the arrow. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is said that the first configuration is "connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0013] Furthermore, in this specification, the direction intersecting a predetermined surface may be referred to as the first direction, the direction intersecting the first direction along this predetermined surface may be referred to as the second direction, and the direction intersecting both the first and second directions may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the Z, Y, and X directions.

[0014] Furthermore, in this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "top," and the direction approaching the substrate along the Z direction is called "bottom." Also, when referring to the bottom surface or bottom end of a configuration, it means the surface or end of that configuration that is on the substrate side, and when referring to the top surface or top end, it means the surface or end of that configuration that is on the opposite side from the substrate. In addition, surfaces that intersect with the X direction or Y direction are called sides, etc.

[0015] Furthermore, in this specification, when we refer to the "width," "length," or "thickness" of a component, member, etc., in a predetermined direction, it may mean the width, length, or thickness of a cross-section observed by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy), etc.

[0016] Furthermore, in this specification, the term "wiring" may include wiring, via contact electrodes, connectors for connecting wiring and via contact electrodes, bonded electrodes, etc.

[0017] [First Embodiment] [Circuit configuration of the memory die MD] Figure 1 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. Figure 2 is a schematic circuit diagram showing a part of the configuration of the memory die MD.

[0018] As shown in Figure 1, the memory die MD comprises multiple memory planes MP0, MP1, ... and peripheral circuit PC. Although Figure 1 shows two memory planes MP10 and MP1, more memory planes MPn may be provided. The peripheral circuit PC comprises a voltage generation circuit VG and a sequencer SQC. The peripheral circuit PC also comprises a cache memory CM, an address register ADR, a command register CMR, and a status register STR. Furthermore, the peripheral circuit PC comprises an input / output control circuit I / O and a logic circuit CTR.

[0019] [Circuit configuration of memory plane MP0] As shown in Figure 2, memory plane MP0 comprises a memory cell array MCA, a row decoder RD, and a sense amplifier module SAM. Memory plane MP1 is configured similarly. The memory cell array MCA comprises multiple memory blocks BLK. Each of these memory blocks BLK comprises multiple string units SU. Each of these string units SU comprises multiple memory strings MS. One end of each of these memory strings MS is connected to the sense amplifier module SAM via a bit line BL. The other end of each of these memory strings MS is connected to the sense amplifier module SAM via a common source line SL.

[0020] A memory string MS comprises a drain-side selection transistor STD, multiple memory cells MC (memory transistors), and a source-side selection transistor STS. The drain-side selection transistor STD, the multiple memory cells MC, and the source-side selection transistor STS are connected in series between the bit line BL and the source line SL. Hereinafter, the drain-side selection transistor STD and the source-side selection transistor STS may simply be referred to as selection transistors (STD, STS).

[0021] A memory cell MC is a field-effect transistor. A memory cell MC comprises a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage film. A memory cell MC stores one or more bits of data. Word lines WL are connected to the gate electrodes of multiple memory cell MCs corresponding to one memory string MS. These word lines WL are commonly connected to all memory string MS in one memory block BLK.

[0022] A selection transistor (STD, STS) is a field-effect transistor. A selection transistor (STD, STS) comprises a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film may include a charge storage layer. A selection gate line (SGD, SGS) is connected to the gate electrode of each selection transistor (STD, STS). One drain-side selection gate line SGD is commonly connected to all memory strings MS in one string unit SU. One source-side selection gate line SGS is commonly connected to all memory strings MS in one memory block BLK. Note that the drain-side selection gate line SGD and the source-side selection gate line SGS are sometimes referred to as selection gate lines SG, respectively.

[0023] The word line WL and the selection gate line SG are connected to the row decoder RD. The row decoder RD supplies predetermined control voltages to the word line WL and the selection gate line SG.

[0024] While this explanation focuses on the circuit configuration of memory plane MP0, the other memory planes MP1, ... are configured similarly. [Memory die MD structure] Figure 3 is a schematic exploded perspective view showing an example configuration of a semiconductor memory device according to the first embodiment. As shown in Figure 3, the memory die MD is located on the chip C on the memory cell array MCA side. Mand a peripheral circuit PC, a sense amplifier module SAM, and a chip C on the low decoder side P and equipped with them.

[0025] Chip C M On the upper surface of the chip C, a plurality of external pad electrodes P that can be connected to bonding wires (not shown) are provided. X In addition, on the lower surface of the chip C, a plurality of bonding electrodes P are provided. M In addition, on the upper surface of the chip C, a plurality of bonding electrodes P are provided. I1 In addition, on the upper surface of the chip C, a plurality of bonding electrodes P are provided. P In the following, for the chip C, the surface on which the plurality of bonding electrodes P are provided is called the front surface, and the surface on which the plurality of external pad electrodes P are provided is called the back surface. Also, for the chip C, the surface on which the plurality of bonding electrodes P are provided is called the front surface, and the surface on the opposite side of the front surface is called the back surface. In the illustrated example, the front surface of the chip C is provided above the back surface of the chip C, and the back surface of the chip C is provided above the front surface of the chip C. I2 In the following, for the chip C, the surface on which the plurality of bonding electrodes P are provided is called the front surface, and the surface on which the plurality of external pad electrodes P are provided is called the back surface. Also, for the chip C, the surface on which the plurality of bonding electrodes P are provided is called the front surface, and the surface on the opposite side of the front surface is called the back surface. In the illustrated example, the front surface of the chip C is provided above the back surface of the chip C, and the back surface of the chip C is provided above the front surface of the chip C. M For the chip C, the surface on which the plurality of bonding electrodes P are provided is called the front surface, and the surface on which the plurality of external pad electrodes P are provided is called the back surface. I1 For the chip C, the surface on which the plurality of bonding electrodes P are provided is called the front surface, and the surface on which the plurality of external pad electrodes P are provided is called the back surface. X In addition, for the chip C, the surface on which the plurality of bonding electrodes P are provided is called the front surface, and the surface on the opposite side of the front surface is called the back surface. P For the chip C, the surface on which the plurality of bonding electrodes P are provided is called the front surface, and the surface on the opposite side of the front surface is called the back surface. I2 In the illustrated example, the front surface of the chip C is provided above the back surface of the chip C, and the back surface of the chip C is provided above the front surface of the chip C. P The front surface of the chip C is provided above the back surface of the chip C. P The front surface of the chip C is provided above the back surface of the chip C. M The back surface of the chip C is provided above the front surface of the chip C. M The back surface of the chip C is provided above the front surface of the chip C.

[0026] Chip C M and chip C P are arranged such that the front surface of the chip C M and the front surface of the chip C P face each other. The plurality of bonding electrodes P I1 are provided corresponding to the plurality of bonding electrodes P I2 respectively, and are arranged at positions where they can be bonded to the plurality of bonding electrodes P I2 The bonding electrode P I1 and the bonding electrode P I2 function as bonding electrodes for bonding the chip C M and the chip C P and electrically connecting them.

[0027] In addition, in the example of FIG. 3, the corner portions a1, a2, a3, a4 of the chip C M are respectively the chip CP These correspond to corners b1, b2, b3, and b4.

[0028] Figure 4 shows chip C M This is a schematic bottom view showing an example of the configuration. Figure 4 shows the bonded electrode P I1 Some components, such as those mentioned above, have been omitted. Figure 5 shows chip C. P This is a schematic plan view showing an example of the configuration. In Figure 5, the bonded electrode P I2 Some of the components have been omitted.

[0029] [Chip C M Planar structure] In the example in Figure 4, chip C M It has a total of six memory planes MP0 to MP5, arranged in pairs in the X direction and three in the Y direction. Note that these six memory planes MP0 to MP5 are sometimes simply referred to as memory plane MP.

[0030] Interplane structures IPS are provided between adjacent memory planes MP0 and MP1 in the Y direction, between memory plane MP1 and MP2, between memory plane MP3 and MP4, and between memory plane MP4 and MP5. The interplane structures IPS isolate adjacent memory planes MP in the Y direction. In this example, memory plane MP0, memory plane MP1, and the interplane structures IPS between them correspond to the first stacked structure, the second stacked structure, and the third stacked structure, respectively.

[0031] Furthermore, each of these six memory planes MP0 to MP5 comprises multiple memory blocks BLK aligned in the Y direction. Also, in the example in Figure 4, each of these six memory planes MP0 to MP5 has memory hole regions R provided on both sides in the X direction. MH (Memory area) and hookup area R provided between them HU It also includes the memory hole region R in the example shown in Figure 4. MH Both sides in the X direction and on the chip C in the memory planes MP0, MP2, MP3, MP5. MDummy stair region R on the end side near both ends in the Y direction DS A chip C is provided. M This is a peripheral region R located on one end in the Y direction, beyond the six memory planes MP0 to MP5. P It is equipped with.

[0032] Note that in the illustrated example, the hookup region R HU This is located in the center of the memory plane MP in the X direction. However, this configuration is merely illustrative, and the specific configuration can be adjusted as needed. For example, the hookup region R HU It may be located at one end or both ends of the memory plane MP in the X direction, rather than in the center of the X direction.

[0033] [Chip C P Planar structure] Chip C P For example, as shown in Figure 5, chip C M Corresponding to this, it has a total of six memory planes MP0 to MP5, arranged in pairs in the X direction and three in the Y direction, and overlapping regions MP0' to MP5'. In the center of these six regions MP0' to MP5' in the X direction is the low control circuit region R RC A low control circuit region R is provided. RC On both sides in the X direction are two block decoder regions R BD A block decoder region R is provided. BD Outside the X direction, there are peripheral circuit regions R. PC A peripheral circuit region R is provided. PC Each of these has two column control circuit regions R aligned in the Y direction CC A is provided. Also, although not shown in the diagram, the peripheral circuit region R PC Circuits are also located in other areas inside. M The surrounding region R P (Figure 4) Opposite chip C P The region is the circuit region R C A system is in place.

[0034] [Chip CM , C P [Cross-sectional structure] Figures 6, 7, and 8 are schematic cross-sectional views showing a portion of the memory die MD. Figure 6 is a schematic cross-sectional view of the memory die MD cut along line AA' in Figures 4 and 5, viewed from the direction of the arrow. Figure 7 is a schematic cross-sectional view of the memory die MD cut along line BB' in Figures 4 and 5, viewed from the direction of the arrow. Figure 8 is a schematic cross-sectional view of the memory die MD cut along line CC' in Figures 4 and 5, viewed from the direction of the arrow.

[0035] [Chip C M [Cross-sectional structure] Chip C M For example, as shown in Figures 6 to 8, the substrate layer L SB and the base layer L SB Memory cell array layer L located below MCA and memory cell array layer L MCA It comprises a via contact electrode layer CH provided below, a plurality of wiring layers M0, M1 provided below the via contact electrode layer CH, and a chip bonding electrode layer MB provided below the wiring layers M0, M1.

[0036] [Chip C M The base layer L SB [Cross-sectional structure] For example, as shown in Figures 6 to 8, the substrate layer L SB The memory cell array layer L MCA It comprises a conductive layer 100 provided on the upper surface, an insulating layer 101 provided on the upper surface of the conductive layer 100, a back wiring layer MA provided on the upper surface of the insulating layer 101, and an insulating layer 102 provided on the upper surface of the back wiring layer MA.

[0037] The conductive layer 100 may contain, for example, a semiconductor layer such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or it may contain a metal such as tungsten (W), or it may contain a silicide such as tungsten silicide (WSi).

[0038] The conductive layer 100 functions as part of the source line SL (Figure 2). Four conductive layers 100 are provided, corresponding to the four memory planes MP0 to MP3 (Figure 4). Regions VZ, which do not include the conductive layer 100, are provided at the X and Y ends of the memory plane MP.

[0039] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0040] The back wiring layer MA includes multiple wirings ma. These multiple wirings ma may include, for example, aluminum (Al).

[0041] Some of the multiple wirings ma function as part of the source line SL (Figure 2). There are, for example, four of these wirings ma, corresponding to four memory planes. Each of these wirings ma is electrically connected to the conductive layer 100.

[0042] Furthermore, some of the multiple wirings ma are external pad electrodes P X This function is achieved by this wiring ma in the surrounding region R. P It is provided in the region VZ that does not include the conductive layer 100, and the memory cell array layer L MCA It is connected to the via contact electrode CC inside. In addition, a portion of the wiring ma is exposed to the outside of the memory die MD through an opening TV provided in the insulating layer 102.

[0043] The insulating layer 102 is a passivation layer made of an insulating material such as polyimide.

[0044] [Chip C M Memory cell array layer L MCA [Structure in the memory plane MP0] As shown in Figure 6, the memory cell array layer L MCAMultiple memory blocks BLK are provided, arranged in the Y direction. Between two adjacent memory blocks BLK in the Y direction, an inter-block insulating layer ST made of silicon oxide (SiO2) or the like is provided. The inter-block insulating layer ST may also include a conductive layer containing an insulating film such as silicon oxide (SiO2), a barrier conductive film such as titanium nitride (TiN), and a metal film such as tungsten (W).

[0045] The memory block BLK comprises a plurality of conductive layers 110 and interlayer insulating layers 111 arranged alternately in the Z direction, and a plurality of semiconductor layers 120 extending in the Z direction.

[0046] The conductive layer 110 has a substantially plate-like shape that is stretched in the X direction. The conductive layer 110 may also contain a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or molybdenum (Mo). The conductive layer 110 may also contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The interlayer insulating layer 111, which is arranged between a plurality of conductive layers 110 aligned in the Z direction, may contain, for example, silicon oxide (SiO2).

[0047] Of the multiple conductive layers 110, one or more of the uppermost conductive layers 110 function as the gate electrode and source-side selection gate line SGS of the source-side selection transistor STS (Figure 2). These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0048] Furthermore, the multiple conductive layers 110 located below this function as the gate electrodes and word lines WL of the memory cell MC (Figure 2). Each of these multiple conductive layers 110 is electrically independent for each memory block BLK.

[0049] Furthermore, one or more conductive layers 110 located below this function as the gate electrode and drain-side select gate line SGD of the drain-side select transistor STD. The width Y in the Y direction of these multiple conductive layers 110 SGD The width Y in the Y direction of the conductive layer 110, which functions as a word line WL.WL It is smaller than (also shown in Figure 9). In addition, an inter-string unit insulating layer SHE made of silicon oxide (SiO2) or the like is provided between two adjacent conductive layers 110 in the Y direction.

[0050] Figure 9 is a magnified rear view of a portion of the memory block BLK in Figure 6, viewed from the Z direction. The memory cell array layer L is on the right side of Figure 9. MCA The layer closest to the semiconductor substrate 200, on the left, is the memory cell array layer L. MCA This shows the intermediate layer.

[0051] As shown in Figure 9, the semiconductor layers 120 are arranged in a predetermined pattern in the X and Y directions. Each semiconductor layer 120 functions as a channel region for multiple memory cells MC and selection transistors (STD, STS) contained in one memory string MS (Figure 2). The semiconductor layer 120 includes, for example, polycrystalline silicon (Si). The semiconductor layer 120 has a substantially cylindrical shape, and an insulating layer 125 made of silicon oxide or the like is provided in the central portion. The outer circumferential surface of the semiconductor layer 120 is surrounded by multiple conductive layers 110 and faces these multiple conductive layers 110.

[0052] Furthermore, an impurity region (not shown) is provided at the upper end of the semiconductor layer 120. This impurity region is connected to the conductive layer 100 (see Figure 7). This impurity region contains, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B).

[0053] Furthermore, an impurity region (not shown) is provided at the lower end of the semiconductor layer 120. This impurity region is connected to the bit line BL via via contact electrodes ch and Vy. This impurity region contains, for example, N-type impurities such as phosphorus (P).

[0054] Figure 10 is an enlarged cross-sectional view of a portion of Figure 6. The gate insulating film 130 has a substantially cylindrical shape that covers the outer circumferential surface of the semiconductor layer 120. The gate insulating film 130 comprises a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the block insulating film 133 include, for example, silicon oxide (SiO2), silicon nitride (SiON), etc. The charge storage film 132 includes, for example, a charge-storing film such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer circumferential surface of the semiconductor layer 120, excluding the contact portion between the semiconductor layer 120 and the conductive layer 100.

[0055] Figure 10 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0056] [Chip C M Memory cell array layer L MCA [Interplane structure IPS and surrounding structure] In addition to Figure 7, please refer to Figures 11 and 12. Figure 11 shows the chip C shown in Figure 4. M This is a magnified plan view of the part indicated by D. Figure 12 shows chip C M The base layer L SB A portion of the memory cell array layer L MCA This is a cross-sectional view taken by cutting along the EE' line in Figure 11, as seen in the direction of the arrow. As shown in FIG. 7, an inter-plane structure IPS (third stacked structure) is provided between a memory plane MP0 (first stacked structure) and a memory plane MP1 (second stacked structure). The first memory block BLK1 (first block) closest to the inter-plane structure IPS of each memory plane MP0, MP1 and the second memory block BLK2 (second block) second closest to the inter-plane structure IPS are dummy blocks not used as memory. The third memory block BLK3 third closest to the inter-plane structure IPS may be used as a normal memory block BLK or as a dummy block.

[0057] The first memory block BLK1 includes a plurality of insulating layers 110A (second insulating layer) and an interlayer insulating layer 111 arranged alternately in the Z direction, and a plurality of semiconductor layers 120 extending in the Z direction.

[0058] The second memory block BLK2 includes, on the side closer to the inter-plane structure IPS, a plurality of insulating layers 110A and an interlayer insulating layer 111 arranged alternately in the Z direction, and a plurality of semiconductor layers 120 extending in the Z direction, and on the side farther from the inter-plane structure IPS, a plurality of conductive layers 110 (first conductive layer) and an interlayer insulating layer 111 arranged alternately in the Z direction, and a plurality of semiconductor layers 120 extending in the Z direction.

[0059] The inter-plane structure IPS includes a plurality of insulating layers 110A and an interlayer insulating layer 111 arranged alternately in the Z direction, and a plurality of via contact electrodes CC extending in the Z direction. One end of the via contact electrode CC penetrates the insulating layer 101 and is connected to an external pad electrode P X through the wiring ma. The other end of the via contact electrode CC is connected to a bonding electrode P i1 through the wirings m0 and m1. The conductive layer 100 of the memory plane MP0 and the conductive layer 100 of the memory plane MP1 are insulated and separated in the Y direction by the insulating layer 101 at the position of the inter-plane structure IPS.

[0060] In these configurations, the insulating layer 110A includes, for example, silicon nitride (SiN). Furthermore, the insulating layer 110A and the conductive layer 110 are connected to the memory cell array layer L MCA In this configuration, multiple first layers are arranged on the same layer. As shown in Figures 11 and 12, the first layer includes an insulating layer 110A formed on the interplane structure IPS, the first memory block BLK1, and a portion of the second memory block BLK2 that is close to the interplane structure IPS, and a conductive layer 110 formed on a portion of the second memory block BLK2 that is farther from the interplane structure IPS, the third memory block BLK3, and other memory block BLKs.

[0061] An interblock insulating layer ST1 (fourth insulating layer) is provided between the first memory block BLK1 and the second memory block BLK2. The interblock insulating layer ST1 is stretched in the X and Z directions and divides the space between the first memory block BLK1 and the second memory block BLK2 in the Y direction. The interblock insulating layer ST1 may contain, for example, silicon dioxide (SiO2). The interblock insulating layer ST1 may be made of the same material as the other interblock insulating layers ST (third insulating layer) or a different material, as long as it has resistance to liquid or gaseous etchants that etch the insulating layer 110A.

[0062] [Chip C M Memory cell array layer L MCA Hookup region R HU [Structure in] As shown in Figure 8, the hookup region R HU Then, the length of the conductive layer 110 (WL, SGD, SGS) in the X direction differs, forming a stepped section STP for the drain-side selected gate line SGD, the word line WL, and the source-side selected gate line SGS. Hook-up region R HU Multiple via contact electrodes CC are provided in this section. Each of these multiple via contact electrodes CC extends in the Z direction and is connected at its upper end to the conductive layer 110 (WL, SGD, SGS) of the stepped section STP.

[0063] FIG. 13 is a schematic plan view showing an enlarged portion indicated by F in FIG. 4. Hook-up region R HU has a first hook-up region R where terraces T(110(SGD)) connected to the drain-side selection gate line SGD are arranged on both sides in the X direction HU1 . Also, the hook-up region R HU has a second hook-up region R where a terrace T(110(WL)) connected to the word line WL and a terrace T(110(SGS)) connected to the source-side selection gate line SGS are arranged in the central portion in the X direction HU2 . Via contact electrodes CC connected to the drain-side selection gate line SGD are provided for each string unit SU. Via contact electrodes CC connected to the word line WL and the source-side selection gate line SGS are provided for each memory block BLK

[0064] [Structure in the peripheral region R of the memory cell array layer L of chip C M MCA In the peripheral region R P of the memory cell array layer L of chip C a plurality of via contact electrodes CC are provided corresponding to the external pad electrode P P . These plurality of via contact electrodes CC are connected to the external pad electrode P X at their upper ends X .

[0065] [Structure of the via contact electrode layer CH] The plurality of via contact electrodes ch included in the via contact electrode layer CH are electrically connected to at least one of the configuration in the memory cell array layer L MCA and the configuration in the chip C P .

[0066] The via contact electrode layer CH includes multiple via contact electrodes ch as multiple wirings. These multiple via contact electrodes ch may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The via contact electrodes ch are provided corresponding to multiple semiconductor layers 120 and are connected to the lower ends of the multiple semiconductor layers 120.

[0067] [Chip C M [Structure of wiring layers M0, M1] Multiple wirings included in wiring layers M0 and M1 are, for example, in the memory cell array layer L MCA Internal components and chip C P It is electrically connected to at least one of the internal components.

[0068] The wiring layer M0 includes multiple wirings m0. These multiple wirings m0 may include, for example, barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), a laminate of tantalum nitride (TaN) and tantalum (Ta), and a laminate of metal films such as copper (Cu). Some of the multiple wirings m0 function as bit lines BL. The bit lines BL are, for example, aligned in the X direction and extended in the Y direction.

[0069] The wiring layer M1 includes a plurality of wirings m1, as shown in Figure 6, for example. These plurality of wirings m1 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0070] [Structure of the chip-bonded electrode layer MB] Multiple wirings included in the chip bonding electrode layer MB are, for example, in the memory cell array layer L MCA Internal components and chip C P It is electrically connected to at least one of the internal components.

[0071] The chip-bonded electrode layer MB consists of multiple bonded electrodes P I1 (Includes adhesive pads). These multiple adhesive electrodes P I1Examples include barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), and multilayer films of tantalum nitride (TaN) and tantalum (Ta). I1B and metal films such as copper (Cu) p I1M It may also contain a multilayer film, etc.

[0072] [Chip C P [Cross-sectional structure] Chip C P As shown in Figure 6, for example, the device comprises a semiconductor substrate 200, an electrode layer GC provided above the semiconductor substrate 200, wiring layers D0, D1, D2, D3, D4 provided above the electrode layer GC, and a chip-bonded electrode layer DB provided above the wiring layers D0, D1, D2, D3, D4.

[0073] [Chip C P [Structure of semiconductor substrate 200] The semiconductor substrate 200 contains, for example, p-type silicon (Si) containing p-type impurities such as boron (B). The semiconductor substrate 200 has a main surface S on the electrode layer GC and wiring layers D0, D1, D2, D3, D4 side. M It has the main surface S of the semiconductor substrate 200. M The side surface is provided with, for example, an N-type diffusion layer 200N containing N-type impurities such as phosphorus (P), a P-type diffusion layer 200P containing P-type impurities such as boron (B), a semiconductor substrate region 200S where the N-type diffusion layer 200N and the P-type diffusion layer 200P are not provided, and an insulating layer STI. A portion of the P-type diffusion layer 200P is provided in the semiconductor substrate region 200S, and a portion of the P-type diffusion layer 200P is provided in the N-type diffusion layer 200N. The N-type diffusion layer 200N, the P-type diffusion layer 200P provided in the N-type diffusion layer 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S each function as part of a plurality of transistors Tr and a plurality of capacitors etc. that constitute the peripheral circuit PC. A portion of the plurality of transistors Tr functions as a word line switch WLSW and a selection gate line switch SGSW.

[0074] [Chip C P [Structure of the electrode layer GC] An electrode layer GC is provided on the upper surface of the semiconductor substrate 200 via an insulating layer 200G. The electrode layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 200. Furthermore, each region of the semiconductor substrate 200 and the plurality of electrodes gc included in the electrode layer GC are each connected to a via contact electrode CS.

[0075] The N-type diffusion layer 200N of the semiconductor substrate 200, the P-type diffusion layer 200P provided in the N-type diffusion layer 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S each function as the channel region of multiple transistors Tr constituting the peripheral circuit PC, and as one electrode of multiple capacitors, respectively.

[0076] The multiple electrodes gc contained in the electrode layer GC each function as the gate electrode of multiple transistors Tr that constitute the peripheral circuit PC, the other electrode of multiple capacitors, and so on.

[0077] The via contact electrode CS is extended in the Z direction and connected at its lower end to the semiconductor substrate 200 or the upper surface of electrode gc. The via contact electrode CS may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0078] [Chip C P [Structure of wiring layers D0, D1, D2, D3, D4] For example, as shown in Figure 6, the multiple connections and multiple wirings included in D0, D1, D2, D3, and D4 are, for example, in the memory cell array layer L MCA Internal components and chip C P It is electrically connected to at least one of the internal components.

[0079] Each wiring layer D0, D1, and D2 includes multiple connection points d0, d1, and d2, and multiple wirings. These multiple connection points d0, d1, and d2, and the multiple wirings may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0080] Each wiring layer D3 and D4 includes multiple connection parts d3 and d4 and multiple wirings. These multiple connection parts d3 and d4 and multiple wirings may include, for example, barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), a laminated film of tantalum nitride (TaN) and tantalum (Ta), and a laminated film of metal films such as copper (Cu).

[0081] [Structure of the chip-bonded electrode layer DB] Multiple wirings included in the chip bonding electrode layer DB are, for example, in the memory cell array layer L MCA Internal components and chip C P It is electrically connected to at least one of the internal components.

[0082] The chip-bonded electrode layer DB consists of multiple bonded electrodes P I2 This includes multiple bonded electrodes P. I2 Examples include barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), and multilayer films of tantalum nitride (TaN) and tantalum (Ta). I2B and metal films such as copper (Cu) p I2M It may also contain a multilayer film, etc.

[0083] In addition, the bonded electrode P I1 and bonded electrode P I2 and a metal film such as copper (Cu) p I1M ,p I2M Using this method, the metal film p I1M and metal film p I2M The two become integrated, making it difficult to confirm their boundaries. However, the bonded electrode P may be misaligned during bonding. I1 and bonded electrode P I2 Distortion of the shape when the two are bonded together, barrier conductive film p I1B ,p I2B The bonded structure can be confirmed by the misalignment (occurrence of discontinuities on the side). Also, bonded electrode P I1 and bonded electrode P I2 When formed by the damascene method, each side has a tapered shape. Therefore, the bonded electrode P I1 and bonded electrode P I2The cross-sectional shape along the Z-direction at the point where the two are bonded together is not a straight line, but rather a non-rectangular shape. Furthermore, the bonded electrode P I1 and bonded electrode P I2 When these are bonded together, the barrier metal covers the bottom, sides, and top surfaces of each Cu component forming them. In contrast, in a typical Cu wiring layer, an insulating layer (such as SiN or SiCN) with an oxidation prevention function for Cu is provided on the top surface of the Cu, and no barrier metal is provided. Therefore, even if there is no misalignment in the bonding, it is possible to distinguish it from a typical wiring layer.

[0084] [Memory die MD manufacturing method] Next, the manufacturing method of the memory die MD will be described with reference to Figures 14 to 26. Figures 14 to 26 are schematic cross-sectional views illustrating the manufacturing method. Figures 14 to 26 show cross-sections corresponding to the cross-section shown in Figure 12.

[0085] In manufacturing the memory die MD according to this embodiment, for example, as shown in Figure 14, chip C M An insulating layer 101 made of silicon oxide (SiO2) or the like is formed on the semiconductor substrate 100A. In this process, the insulating layer 101 is formed by a method such as CVD (Chemical Vapor Deposition).

[0086] Next, a conductive layer 100 and an insulating layer 112 are formed on the upper surface of the insulating layer 101. The conductive layer 100 may contain, for example, polycrystalline silicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). The conductive layer 100 may also contain metals such as tungsten (W) or silicides such as tungsten silicide (WSi). The insulating layer 112 may contain, for example, silicon nitride (SiN). This process is carried out by, for example, a method such as CVD.

[0087] Next, on the upper surface of the insulating layer 112, the memory cell array layer L MCAMultiple insulating layers 110A and interlayer insulating layers 111, each corresponding to half of the total area, are alternately laminated. The insulating layer 110A may contain, for example, silicon nitride (SiN). The interlayer insulating layer 111 is made of a different material from the insulating layer 110A and may contain, for example, silicon dioxide (SiO2). This process is carried out by, for example, a method such as CVD.

[0088] Next, although not shown in the diagram, there are multiple hook-up regions R of the insulating layers 110A and interlayer insulating layer 111. HU A portion corresponding to this is removed to form the stepped STP structure for half of the total number of layers. In this step, for example, a resist is formed to cover the three memory planes MP0 to MP2 and memory planes MP3 to MP5, which are aligned in the Y direction, as shown in G in Figure 4. Next, a portion of the insulating layer 110A is selectively removed by a method such as RIE or wet etching using this resist as a mask. Next, a portion of the interlayer insulating layer 111 is selectively removed by a method such as RIE or wet etching using this resist as a mask. Next, a portion of the resist isotropically removed by a method such as wet etching. Similarly, a portion of the insulating layer 110A, a portion of the interlayer insulating layer 111, and a portion of the resist are sequentially removed. Next, an insulating layer (not shown) such as silicon oxide (SiO2) is formed in the removed portion. This step is performed by a method such as CVD.

[0089] Next, as shown in Figure 15, for example, multiple through-holes 120A are formed at positions corresponding to the semiconductor layer 120. The through-holes 120A extend in the Z direction, penetrate the interlayer insulating layer 111 and the insulating layer 110A, and expose the upper surface of the insulating layer 112. This step is performed, for example, by a method such as RIE.

[0090] Next, as shown in Figure 16, for example, the gate insulating film 130, semiconductor layer 120, and insulating layer 125 shown in Figure 10 are formed on the inner circumferential surface of the through hole 120A. Note that only the semiconductor layer 120, which will be the channel of the memory column, is shown here. This process is carried out by a method such as CVD. Next, an interlayer insulating layer 111A is formed on the semiconductor layer 120. This process is carried out by a method such as CVD.

[0091] Next, as shown in Figure 17, the upper surface of the interlayer insulating layer 111A is scraped using methods such as CMP until the upper surface of the semiconductor layer 120 is exposed, and then the memory cell array layer L is placed on top of it. MCA Multiple insulating layers 110A and interlayer insulating layers 111, corresponding to the remaining half, are alternately laminated. This process is carried out, for example, by a method such as CVD.

[0092] Next, the memory cell array layer L is constructed in the same manner as described with reference to Figures 15 and 16. MCA The structure corresponding to the remaining half is formed, and multiple semiconductor layers 120 are formed.

[0093] Next, as shown in Figure 18, for example, a groove ST1A is formed at the boundary between the first memory block BLK1 and the second memory block BLK2. The groove ST1A extends in the Z and X directions, dividing the interlayer insulating layer 111, insulating layer 110A, and insulating layer 112 in the Y direction, and exposing the upper surface of the conductive layer 100. This step is carried out by a method such as RIE.

[0094] Next, as shown in Figure 19, for example, an interblock insulating layer ST1 is embedded in the groove ST1A. The interblock insulating layer ST1 contains, for example, silicon dioxide (SiO2). This step is carried out by methods such as CVD and CMP.

[0095] Next, as shown in Figure 20, for example, grooves STA are formed between each of the memory blocks BLK, excluding the first memory block BLK1. The grooves STA extend in the Z and X directions, dividing the interlayer insulating layer 111 and insulating layer 110A in the Y direction and exposing the upper surface of the insulating layer 112. This process is carried out by methods such as RIE.

[0096] Next, as shown in Figure 20, for example, a protective film 103 is formed on the inner wall of the groove STA, exposing the tip of the groove STA to the insulating layer 112. This step is performed by methods such as CVD or RIE.

[0097] Next, as shown in Figure 20, for example, a portion of the insulating layer 112 is removed through the groove STA, exposing a portion of the conductive layer 100. This step is performed, for example, by a method such as wet etching.

[0098] Next, as shown in Figure 20, for example, a semiconductor layer is formed in the area where a portion of the insulating layer 112 has been removed, thereby forming a new conductive layer 100. This connects the source-side tip of the semiconductor layer 120 to the conductive layer 100. This process is carried out by methods such as epitaxial growth and RIE. Alternatively, methods such as wet etching and CVD may also be used.

[0099] Next, as shown in Figure 21, for example, after removing the protective film 103 of the groove STA, the insulating layer 110A is removed through the groove STA. This step is carried out by methods such as wet etching or dry etching. At this time, as shown in Figure 21, since the interblock insulating layer ST1 is provided between the first memory block BLK1 and the second memory block BLK2, the liquid or gaseous etchant only reaches partway along the Y direction of the second memory block BLK2. For this reason, the insulating layer 110A remains unetched from partway along the second memory block BLK2 to the interplane structure IPS side.

[0100] Next, as shown in Figure 22, for example, a conductive layer 110 is formed in the space where the insulating layer 110A was removed through groove STA. The conductive layer 110 extends in the X and Y directions and stops at the location where the insulating layer 110A of the second memory block BLK2 exists. This process is carried out by a method such as CVD.

[0101] Next, as shown in Figure 23, for example, the conductive layer 110 in the groove STA is removed to form the interblock insulating layer ST. This step is performed by methods such as RIE or CVD.

[0102] Next, as shown in Figure 24, for example, a via contact electrode CC is formed that penetrates the inter-plane structure IPS in the Z direction. Then, an insulating layer SHE is formed between string units, and subsequently, wiring m0, m1, bit wire BL, and the first bonding electrode P are placed in the wiring layers M0, M1 and the chip bonding electrode layer MB. I1 These are formed. This process is carried out by methods such as CVD, photolithography, and etching.

[0103] Next, as shown in Figure 25, for example, chip C M and chip C P The two are bonded together. In this bonding process, for example, chip C M The wafer is chip C P By pressing it toward the wafer, chip C M The wafer is chip C P The first bonding electrode P is then attached to the wafer and subjected to heat treatment, etc. I1 and second laminated electrode P I2 via chip C M is chip C P It is bonded to it.

[0104] Next, as shown in Figure 26, for example, chip C M The semiconductor substrate 100A on the side is removed up to the insulating layer 101, and an insulating layer 104 is formed that divides the conductive layer 100 in the Y direction at the interplane structure IPS portion. This process is carried out by processes such as CMP, etching, and CVD.

[0105] After that, chip C M On top of the insulating layer 101, wiring ma and external pad electrode P X A memory die (MD) is formed by dicing a structure created by forming various elements and bonding wafers together.

[0106] [Effects of the first implementation method] As a method for isolating adjacent memory planes MP in the Y direction, the hookup region R HU When forming the stepped section (STP), a method is known in which dummy steps are formed between adjacent memory planes MP in the Y direction to physically separate the memory planes MP. However, this method requires space in the Y direction for each adjacent memory plane MP to form the dummy steps. Therefore, it is not possible to reduce the size of the memory chip in the Y direction.

[0107] In this respect, the memory die MD according to this embodiment does not have dummy stairs between adjacent memory planes MP in the Y direction, but instead has an interplane structure IPS. The interplane structure IPS is a laminated structure of an insulating layer 110A before it is replaced by a conductive layer 110 in adjacent memory blocks BLK, and an interlayer insulating layer 111. Therefore, adjacent memory planes MP are isolated, and the space for dummy stairs is unnecessary. As a result, the Y direction can be reduced. This makes it possible to reduce the size of the entire chip.

[0108] [Second Embodiment] Figures 27 and 28 show the configuration of the memory die MD according to the second embodiment. Figure 27 shows the chip C shown in Figure 4. M This is a magnified plan view of the part indicated by D. Figure 28 shows chip C M The base layer L SB A portion of the memory cell array layer L MCA This is a cross-sectional view taken by cutting along the line HH' in Figure 27, as seen in the direction of the arrow.

[0109] In this embodiment, an interblock insulating layer STB and an interblock insulating layer STC are provided between the first memory block BLK1 and the second memory block BLK2. The interblock insulating layer STB is stretched in the X direction. The interblock insulating layer STC is stretched in both the X and Z directions. The interblock insulating layer STB and the interblock insulating layer STC are stacked in the Z direction, with the interblock insulating layer STC on the side facing the conductive layer 100 and the interblock insulating layer STB on the opposite side from the conductive layer 100. The interblock insulating layer STB may contain, for example, silicon dioxide (SiO2). The interblock insulating layer STC may contain, for example, amorphous silicon (a-Si). The other configurations are the same as in the first embodiment.

[0110] [Memory die MD manufacturing method] Next, the manufacturing method of the memory die MD of the second embodiment will be described with reference to Figures 29 to 31. Figure 29 shows chip C M Figure 30 is a cross-sectional view corresponding to Figure 28, illustrating the manufacturing method of chip C. M This is a plan view corresponding to Figure 27, illustrating the manufacturing method. Figure 31 shows chip C M This is a cross-sectional view corresponding to Figure 28, illustrating the manufacturing method.

[0111] The manufacturing process up to the point shown in Figure 17 is the same as in the first embodiment. With the structure in the state shown in Figure 17, interblock insulating layers STB and STC are formed between the memory blocks BLK, as shown in Figure 29. This process is carried out by methods such as RIE and CVD.

[0112] Next, as shown in Figure 30, the interblock insulating layer STB, excluding the interblock insulating layer STB between the first memory block BLK1 and the second memory block BLK2, is selectively etched in the X direction to expose the interblock insulating layer STC beneath it. This step is performed, for example, by a method such as RIE.

[0113] Next, as shown in Figure 31, the interblock insulating layer STC exposed from between the interblock insulating layers STB is removed, and then the insulating layer 110A is removed. This step is carried out by a method such as wet etching. At this time, as shown in Figure 31, the interblock insulating layer STB functions as a bridge to prevent distortion of the laminate.

[0114] However, between the first memory block BLK1 and the second memory block BLK2, the interblock insulating layer STB is not divided in the X direction, so the interblock insulating layer STC remains. Therefore, the liquid or gaseous etchant only reaches partway through the second memory block BLK2 in the Y direction. Consequently, the insulating layer 110A remains on the interplane structure IPS side from partway through the second memory block BLK2.

[0115] The subsequent steps are almost identical to those shown in Figure 22 and later, so a detailed explanation will be omitted. Note that the interblock insulating layer STB separated in the X direction, other than the interblock insulating layer STB between the first memory block BLK1 and the second memory block BLK2, may be removed in subsequent steps or may remain.

[0116] [Effects of the second embodiment] In this embodiment, in addition to the same effects as in the first embodiment, the following effects are achieved. Specifically, when replacing the insulating layer 110A with the conductive layer 110, only the interblock insulating layer STB at the boundary portion of the memory plane MP is not divided in the X direction, among the interblock insulating layers STB that function as bridges to prevent distortion of the laminated structure. Therefore, the same effects as in the first embodiment can be obtained without significantly changing the manufacturing process that utilizes crosslinking.

[0117] [Third Embodiment] Figures 32 and 33 show the configuration of the memory die MD according to the third embodiment. Figure 32 shows the chip C shown in Figure 4. M This is a magnified plan view of the part indicated by D. Figure 33 shows chip C M The base layer L SB A portion of the memory cell array layer L MCAThis is a cross-sectional view taken by cutting along the line HH' in Figure 27, as seen in the direction of the arrow.

[0118] In this embodiment, no inter-block insulating layer is provided between the first memory block BLK1 and the second memory block BLK2. The other configurations are the same as in the first embodiment.

[0119] In this embodiment as well, it is considered that the liquid or gaseous etchant from the interblock insulating layer ST between the second memory block BLK2 and the third memory block BLK3 does not reach the position between the first memory block BLK1 and the second memory block BLK2. Therefore, in the interplane structure IPS, a laminated structure of insulating layer 110A and interlayer insulating layer 111 is formed. For this reason, the same effects as in the first embodiment can be achieved. According to this embodiment, since only the interblock insulating layer ST that should be formed at the furthest edge in the Y direction of the memory plane MP is not formed, there is almost no need to change the existing manufacturing process.

[0120] [Other embodiments] The semiconductor memory devices according to the first to third embodiments have been described above. However, the configurations described above are merely examples, and the specific configurations can be adjusted as appropriate.

[0121] For example, in each of the above embodiments, the hookup region R HU It was placed in the center of the memory plane. However, the hookup region R HU These may be provided at one or both ends of the memory plane MP in the X direction.

[0122] Furthermore, the embodiments described above have described examples of application to NAND flash memory. However, the technologies described herein can also be applied to configurations other than NAND flash memory, such as three-dimensional NOR flash memory. In addition, the technologies described herein can also be applied to semiconductor memory devices other than flash memory, such as three-dimensional DRAM.

[0123] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0124] 110...conductive layer, 110A...insulating layer, 120...semiconductor layer (semiconductor column), 200...semiconductor substrate, C M ...Chip, C P ...chip, BL...bit line, WL...word line, SG...selection gate line, CC...via contact electrode, MC...memory cell, ST, ST1, STB, STC...interblock insulating layer.

Claims

1. Semiconductor substrate and A memory cell array layer is provided on the semiconductor substrate, spaced apart in a first direction intersecting the surface of the semiconductor substrate, In a semiconductor memory device, The memory cell array layer is A first laminated structure and a second laminated structure arranged in a second direction intersecting the first direction, A third laminated structure provided between the first laminated structure and the second laminated structure, Equipped with, Each of the first, second, and third laminated structures comprises a plurality of first layers and a plurality of first insulating layers that are alternately stacked in the first direction and extend in a third direction intersecting the first and second directions. Each of the first and second laminated structures comprises a plurality of blocks arranged in the second direction, Each of the plurality of blocks comprises a first semiconductor layer extending in the first direction and facing the plurality of first layers, Of the plurality of blocks, all blocks except the first block closest to the third stacked structure include a first conductive layer in the first layer. The third laminated structure and the first block are such that the first layer is the second insulating layer. Semiconductor memory device.

2. Of the plurality of blocks, the second block closest to the third laminated structure includes the first conductive layer on the side of the first layer furthest from the third laminated structure and the second insulating layer on the side of the first layer closer to the third laminated structure. The semiconductor memory device according to claim 1.

3. Each of the first and second laminated structures is, Among the plurality of blocks, a plurality of third insulating layers extending in the first direction and the third direction are provided between the plurality of blocks excluding the first block. The semiconductor memory device according to claim 1.

4. Each of the first and second laminated structures is, A fourth insulating layer extending in the first and third directions is provided between the first block and the second block, which is the second closest to the third laminated structure. The semiconductor memory device according to claim 3.

5. Each of the first and second laminated structures is, Between the first block and the second block that is second closest to the third laminated structure, among the plurality of blocks, a fifth insulating layer extending in the first direction and the third direction is provided. A sixth insulating layer extending in the third direction and provided at one end of the fifth insulating layer in the first direction, Equipped with The semiconductor memory device according to claim 3.

6. Each of the first and second laminated structures is, The central part in the third direction has a hook-up region in which a stepped portion made of the plurality of first conductive layers is formed. The semiconductor memory device according to claim 1.

7. The third layered structure has via contact electrodes extending in the first direction. The semiconductor memory device according to claim 1.

8. The first insulating layer contains silicon dioxide, The second insulating layer contains silicon nitride. The semiconductor memory device according to claim 1.

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