Semiconductor memory

Abstract

To provide a semiconductor memory device with good data retention characteristics and reliability. [Solution] The semiconductor memory device comprises a memory block including first and second sub-memory blocks, bit lines and source lines, and a control circuit. The first and second sub-memory blocks each comprise first and second memory cells and first and second word lines. In erasing the memory block, the control circuit performs a first determination operation to determine the write state of the second memory cell, a first erasing operation performed when the second memory cell is in the write state, and a second erasing operation performed when the second memory cell is in the erase state. In the first erasing operation, an erase voltage is applied to the bit lines and source lines, and a selective erase voltage lower than the erase voltage is applied to the first and second word lines. In the second erasing operation, an erase voltage is applied to the bit lines and source lines, a selective erase voltage is applied to the first word line, and a non-selective erase voltage lower than the erase voltage and higher than the selective erase voltage is applied to the second word line.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that comprises a substrate, memory blocks aligned with the substrate in a first direction intersecting the surface of the substrate, and a control circuit for controlling the memory blocks. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-9511 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] To provide a semiconductor memory device with good data retention characteristics and reliability. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a substrate, a memory block including a first sub-memory block and a second sub-memory block arranged in a first direction intersecting the surface of the substrate, a bit line provided on one side of the memory block in the first direction, a source line provided on the other side of the memory block in the first direction, and a control circuit for controlling the memory block. The first sub-memory block includes a first memory cell electrically connected to the bit line and the source line, and a first word line electrically connected to the first memory cell. The second sub-memory block includes a second memory cell electrically connected to the bit line and the source line, and a second word line electrically connected to the second memory cell. The control circuit is configured to perform a first determination operation to determine whether the second memory cell is in a write state, a first erase operation to be performed when the second memory cell is in a write state, and a second erase operation to be performed when the second memory cell is in an erase state during an erase operation on the memory block. In the first erase operation, an erase voltage is applied to one or both of the bit line and the source line, and a selective erase voltage lower than the erase voltage is applied to the first word line and the second word line. In the second erase operation, an erase voltage is applied to one or both of the bit line and / or source line, a selective erase voltage is applied to the first word line, and a non-selective erase voltage, lower than the erase voltage but higher than the selective erase voltage, is applied to the second word line. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic block diagram illustrating a semiconductor memory device according to the first embodiment. [Figure 2] This is a schematic side view illustrating the semiconductor memory device. [Figure 3] This is a schematic plan view illustrating the semiconductor memory device. [Figure 4] This is a schematic block diagram illustrating the semiconductor memory device. [Figure 5] This is a schematic circuit diagram illustrating the semiconductor memory device. [Figure 6]This is a schematic perspective view illustrating the semiconductor memory device. [Figure 7] This is a schematic plan view illustrating the semiconductor memory device. [Figure 8] This is a schematic cross-sectional view illustrating the semiconductor memory device. [Figure 9] This is a schematic cross-sectional view illustrating the semiconductor memory device. [Figure 10] This is a schematic histogram illustrating the threshold voltage of a memory cell (MC) that records 3 bits of data. [Figure 11] This is a timing chart used to explain the operation method of the semiconductor memory device. [Figure 12] This is a schematic cross-sectional view illustrating the operation method of the semiconductor memory device. [Figure 13] This is a flowchart explaining how the semiconductor memory device operates. [Figure 14] This is a timing chart used to explain the operation method of the semiconductor memory device. [Figure 15] This is a schematic cross-sectional view illustrating the operation method of the semiconductor memory device. [Figure 16] This is a flowchart explaining how the semiconductor memory device operates. [Figure 17] This is a timing chart used to explain the operation method of the semiconductor memory device. [Figure 18] This is a schematic cross-sectional view illustrating the operation method of the semiconductor memory device. [Figure 19] This is a schematic cross-sectional view illustrating the operation method of the semiconductor memory device. [Figure 20] This is a flowchart explaining how the semiconductor memory device operates. [Figure 21] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 22]This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 23] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 24] This is a timing chart used to explain the operation method of the semiconductor memory device. [Figure 25] This is a schematic cross-sectional view illustrating the operation method of the semiconductor memory device. [Figure 26] This graph illustrates the semiconductor memory device. [Figure 27] This graph illustrates the semiconductor memory device related to the comparative example. [Figure 28] This is a graph illustrating the semiconductor memory device according to the first embodiment. [Figure 29] This is a histogram illustrating the semiconductor memory device related to the comparative example. [Figure 30] This is a flowchart illustrating the operation method of the semiconductor memory device according to the second embodiment. [Figure 31] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 32] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 33] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 34] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 35] This is a schematic cross-sectional view illustrating the operation method of the semiconductor memory device. [Figure 36] This is a schematic cross-sectional view illustrating the operation method of the semiconductor memory device. [Figure 37] This graph illustrates the semiconductor memory device. [Figure 38] This graph illustrates the semiconductor memory device. [Figure 39] This is a schematic perspective view illustrating a semiconductor memory device according to the third embodiment. [Figure 40] This is a flowchart explaining how the semiconductor memory device operates. [Figure 41] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 42] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 43] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 44] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 45] This is a flowchart illustrating the operation method of the semiconductor memory device according to the fourth embodiment. [Figure 46] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 47] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 48] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 49] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 50] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 51] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 52] This is a schematic histogram illustrating the threshold voltage of a memory cell (MC) on which 1 bit of data is recorded. [Figure 53] This is a flowchart illustrating the operation method of the semiconductor memory device according to the fifth embodiment. [Figure 54] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 55] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 56] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Figure 57] This is a schematic diagram illustrating an example of the writing status of a subblock in the semiconductor memory device. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. It should be noted that the following embodiments are merely examples and are not intended to limit the scope of the present invention.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die (memory chip), or to a memory system including a controller die, such as a memory card or SSD. It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is said that the first configuration is "connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0012] [First Embodiment] [Memory System 10] Figure 1 is a schematic block diagram showing the configuration of the memory system 10 according to the first embodiment.

[0013] The memory system 10 reads, writes, erases, etc., user data in response to signals transmitted from the host computer 20. The memory system 10 is, for example, a memory card, SSD, or other system capable of storing user data. The memory system 10 comprises a plurality of memory dies MD that store user data, and a controller die CD connected to these plurality of memory dies MD and the host computer 20. The controller die CD includes, for example, a processor, RAM, etc., and performs processing such as logical address-to-physical address conversion, bit error detection / correction, garbage collection (compaction), and wear leveling. The controller die CD may also include, for example, a register RG. The register RG may be capable of holding information related to the state of the memory dies MD, for example, information about the erase state and write state of subblock units, which will be described later.

[0014] Figure 2 is a schematic side view showing an example configuration of the memory system 10 according to this embodiment. Figure 3 is a schematic top view showing the same configuration example. For the sake of explanation, some components are omitted in Figures 2 and 3.

[0015] As shown in Figure 2, the memory system 10 according to this embodiment comprises a mounting substrate MSB, a plurality of memory dies MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory dies MD. Pad electrodes P are provided on the upper surface of the mounting substrate MSB at the Y-direction end region, and some other regions are bonded to the lower surface of the memory dies MD via adhesive or the like. Pad electrodes P are provided on the upper surface of the memory dies MD at the Y-direction end region, and other regions are bonded to the lower surface of other memory dies MD or controller die CD via adhesive or the like. Pad electrodes P are provided on the upper surface of the controller die CD at the Y-direction end region.

[0016] As shown in Figure 3, the mounting substrate MSB, the multiple memory dies MD, and the controller die CD each have multiple pad electrodes P arranged in the X direction. The multiple pad electrodes P on the mounting substrate MSB, the multiple memory dies MD, and the controller die CD are each connected to one another via bonding wires B.

[0017] Note that the configurations shown in Figures 2 and 3 are merely examples, and the specific configuration can be adjusted as appropriate. For example, in the examples shown in Figures 2 and 3, controller dies CD are stacked on multiple memory dies MD, and these components are connected by bonding wires B. In such a configuration, multiple memory dies MD and controller dies CD are contained within a single package. However, the controller die CD may be contained in a separate package from the memory dies MD. Also, multiple memory dies MD and controller dies CD may be connected to each other via through-electrodes or the like, instead of bonding wires B.

[0018] [Memory die MD configuration] Figure 4 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. Figure 5 is a schematic circuit diagram showing a part of the configuration of the memory die MD. For the sake of explanation, some configurations are omitted in Figures 4 and 5.

[0019] Figure 4 illustrates multiple control terminals. These control terminals may be represented as terminals corresponding to high-active signals (positive logic signals), as terminals corresponding to low-active signals (negative logic signals), or as terminals corresponding to both high-active and low-active signals. In Figure 4, the symbols for control terminals corresponding to low-active signals include an overline. In this specification, the symbols for control terminals corresponding to low-active signals include a slash (" / "). Note that the description in Figure 4 is illustrative, and the specific configuration can be adjusted as appropriate. For example, some or all high-active signals may be treated as low-active signals, or some or all low-active signals may be treated as high-active signals.

[0020] As shown in Figure 4, the memory die MD comprises memory cell arrays MCA0 and MCA1 for storing user data, and peripheral circuit PC connected to memory cell arrays MCA0 and MCA1. In the following description, memory cell arrays MCA0 and MCA1 may be referred to as memory cell array MCA.

[0021] [Circuit configuration of memory cell array MCA] As shown in Figure 5, the memory cell array MCA comprises multiple memory blocks BLK. Each of these memory blocks BLK comprises multiple string units SU. Each of these string units SU comprises multiple memory strings MS. One end of each of these memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other end of each of these memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0022] A memory string MS comprises a drain-side selection transistor STD, multiple memory cells MC (memory cell transistors), and a source-side selection transistor STS, all connected in series between the bit line BL and the source line SL. Hereinafter, the drain-side selection transistor STD and the source-side selection transistor STS may simply be referred to as selection transistors (STD, STS).

[0023] A memory cell MC is a field-effect transistor comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage film. The memory cell MC stores one or more bits of user data. Word lines WL are connected to the gate electrodes of multiple memory cell MCs corresponding to one memory string MS. These word lines WL are each commonly connected to all memory string MS in one memory block BLK.

[0024] A selection transistor (STD, STS) is a field-effect transistor comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrodes of the selection transistors (STD, STS) are connected to a drain-side selection gate line SGD and a source-side selection gate line SGS, respectively. The drain-side selection gate line SGD is provided corresponding to a string unit SU and is commonly connected to all memory strings MS in one string unit SU. The source-side selection gate line SGS is commonly connected to all memory strings MS in a memory block BLK. Hereinafter, the drain-side selection gate line SGD and the source-side selection gate line SGS may simply be referred to as selection gate lines (SGD, SGS).

[0025] [Circuit configuration of peripheral PC] The peripheral circuit PC includes, for example, row decoders RD0 and RD1 connected to memory cell arrays MCA0 and MCA1, respectively, and sense amplifiers SA0 and SA1, as shown in Figure 4. The peripheral circuit PC also includes a voltage generation circuit VG and a sequencer SQC. Furthermore, the peripheral circuit PC includes an input / output control circuit I / O, a logic circuit CTR, an address register ADR, a command register CMR, and a status register STR. In the following description, row decoders RD0 and RD1 may be referred to as row decoder RD, and sense amplifiers SA0 and SA1 may be referred to as sense amplifier SA.

[0026] The row decoder RD (Figure 4) includes an address decoder 22 that decodes address data Add (Figure 4), as shown in Figure 5, for example. The row decoder RD (Figure 4) also includes a block selection circuit 23 and a voltage selection circuit 24 that transfer the operating voltage to the memory cell array MCA according to the output signal of the address decoder 22.

[0027] The address decoder 22 is connected to multiple block selection lines BLKSEL and multiple voltage selection lines 33. The address decoder 22 sequentially references the row address RA of the address register ADR (Figure 4) according to a control signal from the sequencer SQC, for example.

[0028] The block selection circuit 23 comprises a plurality of block selection units 34 corresponding to memory block BLK. Each block selection unit 34 comprises a plurality of block selection transistors 35 corresponding to word lines WL and selection gate lines (SGD, SGS). The block selection transistors 35 are, for example, field-effect type breakdown transistors. The drain electrodes of the block selection transistors 35 are electrically connected to the corresponding word line WL or selection gate lines (SGD, SGS). The source electrodes of the block selection transistors 35 are electrically connected to the voltage supply line 31 via wiring CG and the voltage selection circuit 24. The gate electrodes of the block selection transistors 35 are commonly connected to the corresponding block selection line BLKSEL.

[0029] The voltage selection circuit 24 comprises a plurality of voltage selection units 36 corresponding to the word line WL and the selection gate lines (SGD, SGS). Each of these plurality of voltage selection units 36 comprises a plurality of voltage selection transistors 37. The voltage selection transistors 37 are, for example, field-effect type breakdown transistors. The drain terminals of the voltage selection transistors 37 are electrically connected to the corresponding word line WL or selection gate line (SGD, SGS) via the wiring CG and the block selection circuit 23, respectively. The source terminals are electrically connected to the corresponding voltage supply lines 31, respectively. The gate electrodes are connected to the corresponding voltage selection lines 33, respectively.

[0030] The sense amplifiers SA0 and SA1 (Figure 4) each comprise a sense amplifier module SAM0 and SAM1, and cache memories CM0 and CM1 (data registers), respectively. The cache memories CM0 and CM1 each comprise latch circuits XDL0 and XDL1. In the following description, the sense amplifier modules SAM0 and SAM1 may be referred to as sense amplifier module SAM, the cache memories CM0 and CM1 as cache memory CM, and the latch circuits XDL0 and XDL1 as latch circuits XDL.

[0031] The sense amplifier module SAM comprises, for example, a sense circuit corresponding to each of several bit lines BL, and several latch circuits connected to the sense circuits.

[0032] The cache memory CM comprises multiple latch circuits XDL. Each of the multiple latch circuits XDL is connected to a latch circuit in the sense amplifier module SAM. The latch circuits XDL store, for example, user data written to or read from the memory cell MC.

[0033] For example, a column decoder is connected to the cache memory CM. The column decoder decodes the column address CA stored in the address register ADR (Figure 4) and selects the latch circuit XDL corresponding to column address CA.

[0034] Furthermore, the user data Dat contained in these multiple latch circuits XDL is sequentially transferred to the latch circuits within the sense amplifier module SAM during a write operation. Similarly, the user data Dat contained in the latch circuits within the sense amplifier module SAM is sequentially transferred to the latch circuits XDL during a read operation. Finally, the user data Dat contained in the latch circuits XDL is sequentially transferred to the input / output control circuit I / O during a data output operation.

[0035] The voltage generation circuit VG (Figure 4) is connected to multiple voltage supply lines 31, as shown in Figure 5, for example. The voltage generation circuit VG includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. These step-down and step-up circuits each supply the power supply voltage V CC and ground voltage V SS (Figure 4) is connected to the voltage supply lines. These voltage supply lines are connected to the pad electrodes P, as explained with reference to Figures 2 and 3. The voltage generation circuit VG generates multiple operating voltages to be applied to the bit line BL, source line SL, word line WL and selection gate lines (SGD, SGS) during read, write, and erase operations on the memory cell array MCA, for example, according to a control signal from the sequencer SQC, and outputs them simultaneously to multiple voltage supply lines 31. The operating voltages output from the voltage supply lines 31 are adjusted as appropriate according to the control signal from the sequencer SQC.

[0036] The SQC sequencer (Figure 4) outputs internal control signals to the row decoders RD0 and RD1, the sense amplifier modules SAM0 and SAM1, and the voltage generation circuit VG, according to the command data Cmd stored in the command register CMR. The SQC sequencer also outputs status data Stt, which indicates the state of the memory die MD, to the status register STR as needed.

[0037] Furthermore, the SQC sequencer generates a ready / busy signal and outputs it to terminal RY / ( / BY). During the period when terminal RY / ( / BY) is in the "L" state (busy period), access to the memory die MD is basically prohibited. Conversely, during the period when terminal RY / ( / BY) is in the "H" state (ready period), access to the memory die MD is permitted. Terminal RY / ( / BY) is implemented, for example, by the pad electrode P as explained with reference to Figures 2 and 3.

[0038] As shown in Figure 4, the address register ADR is connected to the input / output control circuit I / O and stores the address data Add input from the input / output control circuit I / O. The address register ADR comprises, for example, multiple 8-bit register sequences. When an internal operation such as a read operation, write operation, or erase operation is performed, the register sequence holds the address data Add corresponding to the internal operation being performed.

[0039] The address data Add includes, for example, the column address CA (Figure 4) and the row address RA (Figure 4). The row address RA includes, for example, the block address that identifies the memory block BLK (Figure 5), the page address that identifies the string unit SU and the word line WL, the plane address that identifies the memory cell array MCA (plane), and the chip address that identifies the memory die MD.

[0040] The command register CMR is connected to the input / output control circuit I / O and stores the command data Cmd input from the I / O. The command register CMR comprises, for example, at least one set of 8-bit register sequences. When the command data Cmd is stored in the command register CMR, a control signal is sent to the sequencer SQC.

[0041] The status register STR is connected to the input / output control circuit (I / O) and stores status data Stt that is output to the I / O control circuit. The status register STR comprises, for example, multiple 8-bit register sequences. When internal operations such as read, write, or erase operations are performed, the register sequences hold status data Stt related to the internal operation being performed. The register sequences also hold, for example, ready / busy information for memory cell arrays MCA0 and MCA1.

[0042] The input / output control circuit I / O (Figure 4) includes data signal input / output terminals DQ0 to DQ7, data strobe signal input / output terminals DQS, / DQS, a shift register, and a buffer circuit.

[0043] Each of the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS, / DQS are implemented by a pad electrode P, as described with reference to Figures 2 and 3. Data input via the data signal input / output terminals DQ0 to DQ7 is input from the buffer circuit to the cache memory CM, address register ADR, or command register CMR, in accordance with an internal control signal from the logic circuit CTR. Similarly, data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or status register STR to the buffer circuit, in accordance with an internal control signal from the logic circuit CTR.

[0044] Signals input via the data strobe signal input / output terminals DQS and / DQS (e.g., data strobe signals and their complementary signals) are used when inputting data via the data signal input / output terminals DQ0 to DQ7. Data input via the data signal input / output terminals DQ0 to DQ7 is captured into the shift register in the input / output control circuit I / O at the timing of the rising edge of the voltage of the data strobe signal input / output terminal DQS (input signal switching) and the falling edge of the voltage of the data strobe signal input / output terminal / DQS (input signal switching), as well as at the timing of the falling edge of the voltage of the data strobe signal input / output terminal DQS (input signal switching) and the rising edge of the voltage of the data strobe signal input / output terminal / DQS (input signal switching).

[0045] The logic circuit CTR (Figure 4) comprises multiple external control terminals / CE, CLE, ALE, / WE, / RE, RE, and logic circuits connected to these multiple external control terminals / CE, CLE, ALE, / WE, / RE, RE. The logic circuit CTR receives external control signals from the controller die CD via the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and outputs internal control signals to the input / output control circuit I / O accordingly.

[0046] Furthermore, each of the external control terminals / CE, CLE, ALE, / WE, / RE, and RE is implemented by the pad electrode P, as explained with reference to Figures 2 and 3.

[0047] [Memory die MD structure] Figure 6 is a schematic perspective view showing a portion of the memory die MD's configuration. Figure 7 is a schematic plan view showing a portion of the memory die MD's configuration. Figures 8 and 9 are schematic cross-sectional views showing a portion of the memory die MD's configuration. Figure 8 is a schematic cross-sectional view taken by cutting the structure shown in Figure 7 along line AA' and viewing it in the direction of the arrow. Figure 9 is a schematic cross-sectional view of region D shown in Figure 8, enlarged. For the sake of explanation, some components are omitted in Figures 6 to 9.

[0048] The semiconductor memory device according to this embodiment, as shown in Figure 6, for example, has a transistor layer L provided on a semiconductor substrate 100. TR And the transistor layer L TR Memory cell array layer L located above MCA It is equipped with the following.

[0049] A wiring layer GC is provided on the upper surface of the semiconductor substrate 100, with an insulating layer in between. The wiring layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 100. Furthermore, each region of the semiconductor substrate 100 and the plurality of electrodes gc included in the wiring layer GC are connected to contact CS.

[0050] Each of the multiple electrodes gc faces the surface of the semiconductor substrate 100 and functions as the gate electrodes of multiple transistors Tr that constitute the peripheral circuit PC, and as electrodes of multiple capacitors, etc.

[0051] Multiple contacts CS extend in the Z direction and are connected at their lower ends to the upper surface of the semiconductor substrate 100 or electrode gc. An impurity region containing N-type or P-type impurities is provided at the connection portion between the contacts CS and the semiconductor substrate 100. The contacts CS may include a multilayer film containing, for example, a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0052] Each wiring layer D0, D1, and D2 contains multiple wirings, which are electrically connected to at least one of the components in the memory cell array MCA and the components in the peripheral circuit PC. These multiple wirings may include a laminated film containing, for example, a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0053] For example, as shown in Figure 6, the memory cell array layer L MCA A memory block BLK is provided there.

[0054] In the example of FIG. 7, the memory block BLK includes five string units SUa to SUe provided from one side in the Y direction (the positive Y direction in FIG. 4) to the other side in the Y direction (the negative Y direction in FIG. 4). These plurality of string units SUa to SUe respectively correspond to the string unit SU described with reference to FIG. 5. A string unit isolation layer SHE such as silicon oxide (SiO2) is provided between two adjacent string units SU in the Y direction. A between-block structure ST is provided between two adjacent memory blocks BLK in the Y direction.

[0055] As shown in FIGS. 6 and 8, in the memory cell array layer L MCA the memory block BLK includes the memory cell array layer L MCA1 and the memory cell array layer L MCA1 provided above the memory cell array layer L MCA2 . An insulating layer 151 such as silicon oxide (SiO2) is provided between the memory cell array layer L MCA1 and the memory cell array layer L MCA2 . The memory cell array layer L MCA1 and the memory cell array layer L MCA2 include a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0056] The conductive layer 110 is a substantially plate-shaped conductive layer stretched in the X direction. The conductive layer 110 may include a laminated film containing a barrier conductive film 116 such as titanium nitride (TiN) and a metal film 115 such as tungsten (W), as shown in Figure 9. An insulating metal oxide film 134 such as alumina (AlO) may be provided on the upper and lower surfaces of the conductive layer 110 and on the surface facing the semiconductor layer 120. The conductive layer 110 may also contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Contact CCs (Figure 6) are provided at the X-direction ends of each of the multiple conductive layers 110. An insulating layer 101 such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z direction.

[0057] As shown in Figure 8, semiconductor layers 111, 113, and 112 are provided below the multiple conductive layers 110, via an insulating layer 101. A portion of the gate insulating film 130 is provided between semiconductor layers 111 and 112 and semiconductor layer 120. Semiconductor layer 113 is connected to the lower end of semiconductor layer 120.

[0058] The upper surface of semiconductor layer 113 is connected to semiconductor layer 111, and its lower surface is connected to semiconductor layer 112. A conductive layer 114 may be provided on the lower surface of semiconductor layer 112. Semiconductor layers 111, 113, 112, and 114 function as a source line SL (Figure 1). The source line SL is provided in common for, for example, multiple memory blocks BLK. Semiconductor layers 111, 113, and 112 include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 114 may include, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers.

[0059] Memory cell array layer L MCA1Of the multiple conductive layers 110 provided, one or more conductive layers 110 located at the bottom layer function as gate electrodes for the source-side selection gate line SGS (Figure 5) and the multiple source-side selection transistors STS (Figure 5) connected thereto. These conductive layers 110 are electrically independent for each memory block BLK.

[0060] Also, the memory cell array layer L MCA1 Of the multiple conductive layers 110 provided, one or more conductive layers 110 located above this point are provided as dummies. Hereinafter, such conductive layers 110 will be referred to as dummy conductive layers 110DM. Dummy conductive layers 110DM do not function as selection gate lines (SGD, SGS) or word lines WL. No memory cells MC for recording data are provided between the dummy conductive layers 110DM and the semiconductor layer 120. Hereinafter, such dummy conductive layers 110DM may be referred to as dummy word lines DWL.

[0061] Also, the memory cell array layer L MCA1 Of the multiple conductive layers 110 provided, the multiple conductive layers 110 located above this point function as gate electrodes for the word line WL (Figure 5) and the multiple memory cells MC (Figure 5) connected thereto. Between these conductive layers 110 and the semiconductor layer 120, memory cells MC used for recording data are provided. Each of these multiple conductive layers 110 is electrically independent for each memory block BLK.

[0062] Also, the memory cell array layer L MCA1 Of the multiple conductive layers 110 provided, one or more conductive layers 110 located in the uppermost layer are dummy conductive layers 110DM.

[0063] Also, the memory cell array layer L MCA2 Of the multiple conductive layers 110 provided, one or more conductive layers 110 located at the bottom are dummy conductive layers 110DM.

[0064] Also, the memory cell array layer L MCA2Of the multiple conductive layers 110 provided, the multiple conductive layers 110 located above this point function as gate electrodes for the word line WL (Figure 5) and the multiple memory cells MC (Figure 5) connected thereto. Between these conductive layers 110 and the semiconductor layer 120, memory cells MC used for recording data are provided. Each of these multiple conductive layers 110 is electrically independent for each memory block BLK.

[0065] Furthermore, one or more conductive layers 110 located above this function as gate electrodes for the drain-side selection gate wire SGD (Figure 5) and the multiple drain-side selection transistors STD (Figure 5) connected thereto. These multiple conductive layers 110 have a smaller width in the Y direction than the other conductive layers 110. In addition, an inter-string unit insulating layer SHE is provided between two adjacent conductive layers 110 in the Y direction. Each of these multiple conductive layers 110 is electrically independent for each string unit SU.

[0066] The semiconductor layer 120 is arranged in a predetermined pattern in the X and Y directions, as shown in Figures 6 and 7, for example. The semiconductor layer 120 functions as the channel region of multiple memory cells MC and selection transistors (STD, STS) included in one memory string MS (Figure 5). The semiconductor layer 120 is, for example, a semiconductor layer made of polycrystalline silicon (Si). The semiconductor layer 120 has a substantially bottomed cylindrical shape, as shown in Figure 8, for example, and an insulating layer 125 made of silicon oxide (SiO2) or the like is provided in the central part.

[0067] As shown in Figure 8, the semiconductor layer 120 is the memory cell array layer L MCA1 Semiconductor region 120 included L and memory cell array layer L MCA2 Semiconductor region 120 included U It also includes the semiconductor layer 120, and the semiconductor region 120 L Upper end and semiconductor region 120 U Semiconductor region 120 connected to the lower end J And, semiconductor area 120 LAn impurity region 122 connected to the lower end and a semiconductor region 120 U It comprises an impurity region 121 connected to the upper end of the

[0068] Semiconductor field 120 L This is a roughly cylindrical region extending in the Z direction. Semiconductor region 120 L The outer surfaces are each the memory cell array layer L MCA1 It is surrounded by multiple conductive layers 110 and faces these multiple conductive layers 110.

[0069] Semiconductor field 120 U This is a roughly cylindrical region extending in the Z direction. Semiconductor region 120 U The outer surfaces are each the memory cell array layer L MCA2 It is surrounded by multiple conductive layers 110 and faces these multiple conductive layers 110.

[0070] Semiconductor field 120 J The memory cell array layer L MCA1 The memory cell array layer L is provided above the multiple conductive layers 110 included in it. MCA2 It is located below the multiple conductive layers 110 contained within it.

[0071] The impurity region 122 is connected to the semiconductor layer 113. The impurity region 122 contains, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). The portion of the semiconductor layer 120 located directly above the impurity region 122 functions as the channel region of the source-side selection transistor (STS).

[0072] The impurity region 121 contains, for example, N-type impurities such as phosphorus (P). The impurity region 121 is connected to the bit line BL via contacts Ch and Cb (Figure 6).

[0073] The gate insulating film 130 has a substantially bottomed cylindrical shape that covers the outer circumferential surface of the semiconductor layer 120. The gate insulating film 130 comprises, for example, a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110, as shown in Figure 9. The tunnel insulating film 131 and the block insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is, for example, silicon nitride (SiN) and is a film capable of storing charge. The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and are stretched in the Z direction along the outer circumferential surface of the semiconductor layer 120.

[0074] Furthermore, the gate insulating film 130 may include a floating gate made of, for example, polycrystalline silicon containing N-type or P-type impurities.

[0075] The interblock structure ST is a structure that extends in the Z and X directions, dividing multiple insulating layers 101, multiple conductive layers 110, semiconductor layer 111, and semiconductor layer 113 in the Y direction, and reaching semiconductor layer 112. The interblock structure ST is, for example, an insulating layer made of silicon oxide (SiO2). The interblock structure ST may also include a conductive layer made of tungsten or the like that extends in the X and Z directions in the center of the Y direction, and the lower end of this conductive layer may be connected to semiconductor layer 112.

[0076] [Semiconductor area 120] L of, 120 U ,120 J [Radial width] Next, semiconductor area 120 L ,120 U ,120 J The radial width of the semiconductor region 120 will be described below. L ,120 U The width of the semiconductor layer in the XY cross-section intersecting the Z direction, which is the extension direction, is called the radial width. For the sake of explanation, in Figure 8 and other figures, the width in the Y direction is shown as the radial width.

[0077] Semiconductor field 120L The lower end (for example, memory cell array layer L) MCA1 The radial width W of the portion located below the multiple conductive layers 110 included in the structure. 120LL Semiconductor area 120 L The upper end (for example, the memory cell array layer L) MCA1 The radial width W of the portion located above the multiple conductive layers 110 included in 120LU It is smaller than that. That is, semiconductor region 120 L The structure is designed so that its radial width decreases towards the bottom, closer to the substrate.

[0078] Semiconductor field 120 U The lower end (for example, memory cell array layer L) MCA2 The radial width W of the portion located below the multiple conductive layers 110 included in the structure. 120UL Semiconductor area 120 U The upper end (for example, the memory cell array layer L) MCA2 The radial width W of the portion located above the multiple conductive layers 110 included in 120UU It is smaller than that. That is, semiconductor region 120 U This is the substrate and semiconductor area 120 J The lower and closer to the semiconductor region 120, the smaller the radial width becomes. J It is positioned so that the radial width is smallest in the vicinity directly above it. 120UL is width W 120LU It is smaller than that.

[0079] Semiconductor field 120 J Radial width W 120J Semiconductor area 120 L ,120 U The radial width W of any of the 120LL ,W 120LU ,W 120UL ,W 120UU It is designed to be larger than that.

[0080] [Threshold voltage of memory cell MC that records multiple bits] Next, with reference to Figure 10, we will explain the threshold voltage of a memory cell MC that records multiple bits of data. Figure 10 shows, as an example, the threshold voltage of a memory cell MC that records 3 bits of data.

[0081] Figure 10(a) is a schematic histogram illustrating the threshold voltage of a memory cell MC that records 3 bits of data. The horizontal axis shows the voltage of the word line WL, and the vertical axis shows the number of memory cell MCs. Figure 10(b) is a table showing an example of the relationship between the threshold voltage of a memory cell MC that records 3 bits of data and the data recorded. Figure 10(c) is a table showing another example of the relationship between the threshold voltage of a memory cell MC that records 3 bits of data and the data recorded.

[0082] In the example shown in Figure 10(a), the threshold voltage of the memory cell MC is controlled to eight different states. The threshold voltage of the memory cell MC controlled to the Er state is the erase verify voltage V VFYEr It is smaller. Also, for example, the threshold voltage of a memory cell MC controlled to state A is the verify voltage V VFYA Larger verify voltage V VFYB It is smaller. Also, for example, the threshold voltage of a memory cell MC controlled to the B state is the verify voltage V VFYB Larger verify voltage V VFYC Smaller. Similarly, the threshold voltages of memory cells MC controlled to C state ~ F state are, respectively, the verify voltage V VFYC ~Verify voltage V VFYF Larger verify voltage V VFYD ~Verify voltage V VFYG It is smaller. Also, for example, the threshold voltage of a G-state controlled memory cell MC is the verify voltage V VFYG Larger read path voltage V READ Smaller. Read path voltage V READ This is a voltage of, for example, about 9V.

[0083] Also, in the example of FIG. 10(a), a read voltage V is set between the threshold distribution corresponding to the Er state and the threshold distribution corresponding to the A state. Also, a read voltage V is set between the threshold distribution corresponding to the A state and the threshold distribution corresponding to the B state. Similarly hereinafter, between the threshold distribution corresponding to the B state and the threshold distribution corresponding to the C state ~ between the threshold distribution corresponding to the F state and the threshold distribution corresponding to the G state, read voltages V~read voltages V are set respectively. CGAR is set. Also, a read voltage V is set between the threshold distribution corresponding to the A state and the threshold distribution corresponding to the B state. CGBR is set. Similarly hereinafter, between the threshold distribution corresponding to the B state and the threshold distribution corresponding to the C state ~ between the threshold distribution corresponding to the F state and the threshold distribution corresponding to the G state, read voltages V CGCR ~read voltages V CGGR are set.

[0084] For example, the Er state corresponds to the lowest threshold voltage. The memory cell MC of the Er state is, for example, a memory cell MC in the erased state. For example, the data "111" is assigned to the memory cell MC of the Er state.

[0085] Also, the A state corresponds to a threshold voltage higher than the threshold voltage corresponding to the above Er state. For example, the data "101" is assigned to the memory cell MC of the A state.

[0086] Also, the B state corresponds to a threshold voltage higher than the threshold voltage corresponding to the above A state. For example, the data "001" is assigned to the memory cell MC of the B state.

[0087] Similarly hereinafter, the C state ~ G state in the figure correspond to threshold voltages higher than the threshold voltages corresponding to the B state ~ F state. For example, the data "011", "010", "110", "100", "000" are assigned to the memory cells MC of these states.

[0088] In addition, in the case of the assignment as illustrated in FIG. 10(b), the data of the lower bit can be discriminated by one read voltage V CGDR , and the data of the middle bit can be discriminated by three read voltages V CGAR , V CGCR , V CGFRcan be discriminated by, and the data of the upper bits are three read voltages V CGBR , V CGER , V CGGR can be discriminated by. Such an assignment of data may be called a 1-3-3 code.

[0089] In addition, the number of bits of data recorded in the memory cell MC, the number of states, the assignment of data to each state, etc. can be changed as appropriate.

[0090] For example, in the case of the assignment illustrated in FIG. 10(c), the data of the lower bits can be discriminated by one read voltage V CGDR , the data of the middle bits can be discriminated by two read voltages V CGBR , V CGFR , and the data of the upper bits can be discriminated by four read voltages V CGAR , V CGCR , V CGER , V CGGR can be discriminated by. Such an assignment of data may be called a 1-2-4 code.

[0091] [Operation] Next, the operation of the semiconductor memory device according to this embodiment will be described.

[0092] [Read Operation] The read operation of the memory die MD according to this embodiment will be described. FIG. 11 is a timing chart for explaining the read operation. FIG. 12 is a schematic cross-sectional view for explaining the read operation. FIG. 12 shows each voltage supplied at timings t103 to t105 in FIG. 11.

[0093] In addition, in the following description, the drain-side selection gate line SGD corresponding to the string unit SU that is the target of the operation is referred to as the drain-side selection gate line SGD S , and the drain-side selection gate line SGD corresponding to other string units SU may be referred to as the drain-side selection gate line SGD U .

[0094] Also, select the word line WL that is the target of the operation. S This is called a non-selected word line WL, and other word lines WL are called non-selected word lines WL. U It is sometimes called that.

[0095] Furthermore, in the following explanation, among the multiple memory cells MC included in the string unit SU (Figure 12) that is the target of the operation, the selected word line WL S This section describes an example of performing a read operation on a connected memory cell (hereinafter sometimes referred to as a "selected memory cell MC"). In the following description, a configuration containing multiple such selected memory cell MCs may be referred to as a selected page PGs. A memory block BLK containing selected page PGs will also be referred to as a selected memory block BLK. tb It is sometimes called that.

[0096] In the following explanation, we will describe an example where each memory cell MC stores multiple bits of data, and multiple read voltages are used during the read operation.

[0097] At the timing t100 of the read operation, the controller die CD sequentially inputs command data Cmd (Figure 4) and address data Add (Figure 4) to the memory die MD, instructing it to perform a read operation. As a result, the terminal RY / ( / BY) enters a "L" state (busy period).

[0098] At timing t101, for example, as shown in Figure 11, the drain-side selected gate line SGD S Drain side selected gate line SGD U , and a voltage V is applied to the source-side selected gate line SGS. SG Supply the current to turn on all selection transistors (STD, STS). Also, the selection word line WL S Read path voltage V READ It supplies and the unselected word line WL U Read path voltage V READ This supplies power to turn on all memory cells (MCs).

[0099] At timing t102, for example, as shown in Figure 11, the unselected word line WL U Read path voltage V READ By supplying all unselected word lines WL U The connected memory cell MC is turned ON. Meanwhile, the selected word line WL S Ground voltage V SS By supplying, select word line WL S The memory cell MC connected to it is turned OFF. Also, the drain-side selected gate line SGD of the string unit SUa, which includes the selected pages PGs. S And voltage V is applied to the source-side selected gate line SGS. SG This supplies the necessary power and turns on the selection transistors STD and STS connected to them. Additionally, it includes the drain-side selection gate wire SGD of string units SUb~SUe that do not include the selection pages PGs. U Ground voltage V SS This supplies power and turns off the select transistor STD connected to it.

[0100] At timing t103, the selected word line WL S The predetermined read voltage V CGR It supplies the read voltage V. CGR For example, the seven readout voltages V explained with reference to Figure 10(a) CGAR ~V CGGR It may be either of the above. As a result, the selected memory cells MCs included in the selected page PGs will be in the ON or OFF state depending on their respective threshold voltages. That is, some of the selected memory cells MCs in the selected page PGs will be in the ON state, and the remaining selected memory cells MCs will be in the OFF state.

[0101] Furthermore, during the read operation timings t103 to t104, for example, charging of the bit line BL is performed. Also, for example, a voltage V is applied to the source line SL (semiconductor layer 112). SRC Supply voltage V to begin charging. SRC For example, the ground voltage V SSIt is of a similar size. Subsequently, the sense amplifier module SAM (Figure 4) performs a sense operation to detect the ON / OFF state of the memory cell MC, and acquires data indicating the state of this memory cell MC.

[0102] At the timing t104 of the read operation, the selected word line WL S In addition, other read voltages V CGR This supplies a supply of memory cells (MCs) to some of the selected memory cells (MCs) in the selected page PGs, while the remaining selected memory cells (MCs) remain in the OFF state.

[0103] During the read operation timings t104 to t105, a sense operation is performed by the sense amplifier module SAM, similar to timings t103 to t104, to acquire data indicating the state of the memory cell MC.

[0104] At the timing t105 of the read operation, the selected word line WL S , all unselected word lines WL U , and ground voltage V on the selected gate lines (SGD, SGS) SS To supply.

[0105] At timing t106, the read operation on the memory die MD is completed. Also, the terminal RY / ( / BY) changes from the "L" state to the "H" state, allowing access to the memory die MD.

[0106] During the read operation, AND, OR, and other arithmetic operations are performed on the data indicating the state of the memory cell MC, thereby calculating the data that was recorded in the memory cell MC. This data is then transferred to the cache memory CM (Figure 4).

[0107] [Write operation] Next, the write operation of the memory die MD according to this embodiment will be described. Figure 13 is a flowchart illustrating the write operation.

[0108] The following explanation describes an example of performing a write operation on multiple selected memory cells (MCs) corresponding to selected page PGs.

[0109] In step S101, the number of loop iterations is n. W This is set to 1. Loop count n W This is a variable that indicates the number of write loop iterations.

[0110] In step S102, a program operation is executed. The program operation is the selection of the word line WL. S Program voltage V PGM This operation involves supplying (Figure 15) to increase the threshold voltage of the memory cell MC.

[0111] In step S103, a verification operation is performed. The verification operation is basically performed in the same way as the read operation described with reference to Figures 11 and 12. However, in the verification operation, a predetermined read voltage V CGR Instead, for example, the verification voltage V explained with reference to Figure 10 VFYA ~Verify voltage V VFYG Select word line WL S It supplies power to the memory cell MC, detects the ON / OFF state of the memory cell MC, and detects whether the threshold voltage of the memory cell MC has reached the target value.

[0112] In step S104, the result of the verification operation is determined. For example, the number of memory cells (MCs) whose threshold voltage has not reached the target value is counted by referring to a counter circuit (not shown). If the number of memory cells (MCs) whose threshold voltage has not reached the target value is greater than or equal to a certain number, the verification is determined to be FAIL and the process proceeds to step S105. On the other hand, if the number of memory cells (MCs) whose threshold voltage has not reached the target value is less than a certain number, the verification is determined to be PASS and the process proceeds to step S107.

[0113] In step S105, the number of loop iterations is n. W a predetermined number of times N WDetermine whether the condition has been met. If it has not been met, proceed to step S106. If it has been met, proceed to step S108.

[0114] In step S106, the number of loop iterations is n. W Add 1 to the value and proceed to step S102. Also, in step S106, for example, the selected word line WL in the program operation... S The program voltage V supplied to it PGM (Figure 15) is increased by a predetermined voltage ΔV. Therefore, the program voltage V PGM The number of loop iterations is n. W It increases along with the increase of [something].

[0115] In step S107, the status data Stt, indicating that the write operation was completed successfully, is stored in the status register STR (Figure 4), and the write operation is terminated. The status data Stt is output to the controller die CD (Figure 1) by a status read operation.

[0116] In step S108, the status data Stt, indicating that the write operation did not complete successfully, is stored in the status register STR (Figure 4), and the write operation is terminated.

[0117] Figure 14 is a timing chart illustrating the write operation. Figure 15 is a schematic cross-sectional view illustrating the write operation. Figure 15 shows the voltages supplied at timings t113 to t114 in Figure 14.

[0118] Hereinafter, among the multiple selectable memory cells (MCs), those that adjust the threshold voltage will be referred to as "write memory cells (MCs)," and those that do not adjust the threshold voltage will be referred to as "prohibited memory cells (MCs)."

[0119] At the write operation timing t110, for example, as shown in Figure 14, the controller die CD sequentially inputs the command data Cmd (Figure 4) and address data Add (Figure 4) to the memory die MD, instructing it to perform a write operation. As a result, the terminal RY / ( / BY) enters a "L" state (busy period).

[0120] At timings t110~t111, for example, the bit line BL connected to the write memory cell MC. W (Figure 15) Voltage V SRC A voltage V is supplied to the bit line BL connected to the prohibited memory cell MC. DD It supplies voltage V to the source line SL (semiconductor layer 112). SRC To supply.

[0121] At timing t111, the drain-side selected gate line SGD S and drain-side selected gate line SGD U Voltage V SG This supplies power to turn on all drain-side selection transistors STD.

[0122] At timing t112, the drain-side selected gate line SGD S voltage V SGD It supplies voltage V. SGD The voltage is V SG It is smaller than the bit line BL and has a size such that the drain-side selection transistor STD is ON or OFF depending on the voltage of the bit line BL. Also, the drain-side selection gate line SGD U And ground voltage V to source-side selected gate line SGS SS This supplies power and turns off the selection transistors (STD, STS) connected to them. Also, the selection word line WL is used. S and non-selected word line WL U Write path voltage V PASS It supplies the write path voltage V. PASS The read path voltage V is explained with reference to Figure 12. READ It may have a size of about the same magnitude as the read path voltage V. READ It can be even bigger.

[0123] At timing t113, the selected word line WL S Program voltage V PGM It supplies the program voltage V. PGM The write path voltage V PASS It is larger than that.

[0124] Here, for example, as shown in Figure 15, bit line BL W The channel of the semiconductor layer 120 connected to it receives a voltage V from the bit line BL. SRC Such a semiconductor layer 120 and a selected word line WL are supplied. S A relatively large electric field is generated between the two. As a result, electrons in the channel of the semiconductor layer 120 tunnel through the tunnel insulating film 131 (Figure 9) into the charge storage film 132 (Figure 9). This increases the threshold voltage of the write memory cell MC.

[0125] Also, bit line BL W The channels of semiconductor layer 120 connected to bit lines BL other than the one mentioned above are electrically floating, and the potential of these channels is the non-selected word line WL. U Capacitive coupling with the write path voltage V PASS It has risen to this extent. Such a semiconductor layer 120 and selected word line WL S Only a smaller electric field than the one described above is generated between them. Therefore, electrons in the channel of the semiconductor layer 120 do not tunnel into the charge storage film 132 (Figure 9). Consequently, the threshold voltage of the disabled memory cell MC does not increase.

[0126] At timing t114, the selected word line WL S , non-selected word line WL U Drain side selected gate line SGD S Drain side selected gate line SGD U , and ground voltage V to source-side selected gate line SGS SS To supply.

[0127] At timing t115, the write operation on the memory die MD is completed. Also, the terminal RY / ( / BY) changes from the "L" state to the "H" state, allowing access to the memory die MD.

[0128] [Memory block erasure operation] Next, the memory block erasure operation of the memory die MD according to this embodiment will be described. Figure 16 is a flowchart illustrating the erasure operation.

[0129] In the following explanation, the selected memory block BLK is the target of the operation. tb This section describes an example of performing an erase operation on a file.

[0130] In step S111, for example, as shown in Figure 16, the number of loops n E This is set to 1. Loop count n E This variable indicates the number of iterations of the erase loop.

[0131] In step S112, the erase voltage supply operation is performed. The erase voltage supply operation supplies the ground voltage V to the word line WL. SS A voltage V is supplied to at least one of the source line SL and the bit line BL. ERA This operation reduces the threshold voltage of the memory cell MC by supplying (Figure 18, sometimes called the erase voltage).

[0132] In step S113, an erase-verify operation is performed. The erase-verify operation applies an erase-verify voltage V to the word line WL. VFYEr This operation involves supplying a voltage to detect the ON / OFF state of the memory cell MC and determining whether the threshold voltage of the memory cell MC has reached a target value.

[0133] In step S114, the result of the erase verification operation is determined. For example, the number of memory cells (MCs) whose threshold voltage has not reached the target value is counted by referring to the counter circuit described above. If the number of memory cells (MCs) whose threshold voltage has not reached the target value is greater than or equal to a certain number, the verification is determined to be FAIL and the process proceeds to step S115. On the other hand, if the number of memory cells (MCs) whose threshold voltage has not reached the target value is less than a certain number, the verification is determined to be PASS and the process proceeds to step S117.

[0134] In step S115, the number of loop iterations is n. E a predetermined number of times N E Determine whether the condition has been met. If it has not been met, proceed to step S116. If it has been met, proceed to step S118.

[0135] In step S116, the number of loop iterations is n. E Add 1 to this and proceed to step S112. Also, in step S116, for example, the voltage V supplied to at least one of the source line SL and the bit line BL in the erase voltage supply operation ERA (Figure 18) Add the predetermined voltage ΔV. Therefore, the voltage V ERA (Figure 18) shows the number of loop iterations n E It increases along with the increase of [something].

[0136] In step S117, the status data Stt, indicating that the erase operation has been successfully completed, is stored in the status register STR (Figure 4), and the erase operation is terminated. The status data Stt is output to the controller die CD (Figure 1) via a status read operation.

[0137] In step S118, the status data Stt, indicating that the erase operation did not complete successfully, is stored in the status register STR (Figure 4), and the erase operation is terminated.

[0138] Figure 17 is a timing chart illustrating the erase operation. Figure 18 is a schematic cross-sectional view illustrating the erase operation. Figure 18 shows the voltages supplied at timings t122 ​​to t123 in Figure 17.

[0139] At the erase operation timing t120, the controller die CD sequentially inputs the command data Cmd, which instructs the erase operation, and the address data Add to the memory die MD. As a result, the terminal RY / ( / BY) enters a "L" state (busy period).

[0140] At the timing t121 of the erase operation, voltage V is applied to the selected gate lines (SGD, SGS) respectively. ERA -V1 is supplied, and the ground voltage V is applied to the word line WL. SS It supplies the voltage V supplied to the selected gate lines (SGD, SGS). ERA -V1 is the ground voltage V supplied to the word line WL. SS It is larger. Also, a voltage V is applied to the bit line BL and source line SL (semiconductor layer 112). ERA The following is supplied. At the timing t121 of the erase operation, the voltage V is supplied to only one of either the drain-side selected gate line SGD or the source-side selected gate line SGS. ERA -V1 may be supplied. Voltage V is applied to the drain-side selected gate line SGD. ERA -When V1 is supplied, voltage V is applied to the bit line BL. ERA You may supply a voltage V to the source-side selected gate line SGS. ERA -When V1 is supplied, a voltage V is applied to the source line SL. ERA It is acceptable to supply it.

[0141] Between timings t122 ​​and t123, the data written to the memory cell MC is erased by GIDL (Gate Induced Drain Leakage), which will be described later.

[0142] At timing t123, the ground voltage V is applied to the bit line BL, the selection gate lines (SGD, SGS), and the word line WL. SSTo supply.

[0143] At timing t124, the erase operation on the memory die MD is completed. Also, the terminal RY / ( / BY) changes from the "L" state to the "H" state, allowing access to the memory die MD.

[0144] [Erase operation via GIDL] In timing t122 ​​to t123 in Figure 17, as shown in Figure 18, a voltage V is applied to the gate electrode of the selection transistor (STD, STS) via the selection gate wire (SGD, SGS). ERA -V1 is supplied. Also, voltage V is supplied to the channel region of the selection transistors (STD, STS) via the bit line BL and source line SL. ERA A voltage V1 is supplied. Therefore, a voltage V1 is applied between the gate electrode and channel region of the selected transistors (STD, STS).

[0145] The voltage V1 is, for example, a voltage of sufficient magnitude to generate GIDL near the channels of the selection transistors (STD, STS) (on the surface of the semiconductor layer 120). Due to GIDL, electron-hole pairs are generated near the channels of each selection transistor (STD, STS), as shown in Figure 18, for example.

[0146] Electrons generated in the drain-side selection transistor STD are supplied to the bit line BL, and holes are supplied to the memory cell MC. Electrons generated in the source-side selection transistor STS are supplied to the source line SL, and holes are supplied to the memory cell MC. Consequently, holes accumulate in the channel region of the memory cell MC, and the voltage in the channel region of the memory cell MC rises.

[0147] Furthermore, in timing t122 ​​to timing t123 in Figure 17, the ground voltage V is applied to the word line WL. SS A voltage V is supplied. Therefore, a voltage V is supplied between the gate electrode and channel region of the memory cell MC. ERAA voltage of a certain magnitude is applied. This voltage is large enough to allow holes supplied by GIDL to tunnel through the tunnel insulating film 131 and reach the charge storage film 132.

[0148] In this way, holes generated by GIDL are selected in memory block BLK tb By accumulating charge on the charge storage film 132 (Figure 9) of all memory cells MC contained within, the threshold voltage of the memory cells MC is reduced, thereby erasing the data of the memory cells MC.

[0149] [Erase and Verify Operation] Figure 19 is a schematic cross-sectional view illustrating the erase-verify operation. In the erase-verify operation, for example, as shown in Figure 19, the drain-side selected gate line SGD of the string unit SUa S And voltage V is applied to the source-side selected gate line SGS. SG This supplies power and turns ON the selection transistors STD and STS connected to them. Additionally, it selects the drain side gate wire SGD of the other string units SUb~SUe. U Ground voltage V SS A voltage is supplied, and the selection transistor STD connected to them is turned OFF. Also, the erase verify voltage V is applied to the word line WL. VFYEr It supplies a voltage and detects whether the threshold voltage of the memory cell MC included in the string unit SUa has reached the target value.

[0150] [Subblock Deletion Mode] With the increasing integration of semiconductor memory devices, the number of bits per memory block (BLK) is increasing. Consequently, the number of erasure units is increasing, and the number of write operations during garbage collection is also increasing. Therefore, the semiconductor memory device according to the first embodiment is configured to operate in sub-block erasure mode. In sub-block erasure mode, one memory block (BLK) can be divided into two sub-blocks, and the sub-blocks can be used as erasure units. In sub-block erasure mode, for example, among the configurations in the memory block (BLK), the memory cell array layer L described with reference to Figure 8 is erased. MCA1What is included in is taken as one sub-block SB1, and the memory cell array layer L MCA2 What is included in is taken as another sub-block SB0.

[0151] [Selective Erase Operation (1)] The semiconductor memory device according to this embodiment is configured to be able to execute the selective erase operation (1). FIG. 20 is a flowchart for explaining the selective erase operation (1).

[0152] In the example shown below, in the memory block BLK, a write operation is first performed on the sub-block SB0, and then a write operation is performed on the sub-block SB1.

[0153] Also, in the following description, when it is said that the sub-block SB is in a full erase state, it means that all the pages PG included in the sub-block SB and all the memory cells MC included in the page PG are in an erase state.

[0154] In step S121, it is determined whether the sub-block SB1 is in a full erase state. If the sub-block SB1 is in a full erase state, the process proceeds to step S122. If the sub-block SB1 is not in a full erase state, the process proceeds to step S123. Note that the operation of determining whether the sub-block SB1 is in a full erase state will be described later.

[0155] In step S122, a sub-block SB0 erase operation, which will be described later, is executed.

[0156] In step S123, the memory block erase operation (FIG. 16) described above is executed.

[0157] [Operation of Determining Whether the Sub-block SB1 is in a Full Erase State] FIGS. 21 to 23 are schematic diagrams showing examples of the write status of the sub-blocks.

[0158] Still, FIGS. 21 to 23, FIGS. 31 to 34, FIGS. 41 to 44, and FIGS. 46 to 51 show the writing status of a page PG corresponding to a plurality of word lines WL provided in a memory block BLK and four string units SU0, SU1, SU2, and SU3. The writing status of the page PG is shown as either a writing state Pg or an erasing state Er.

[0159] Still, in the examples shown in FIGS. 21 to 23, FIGS. 31 to 34, and FIGS. 54 to 57, a total of 96 layers of word lines WL are provided, and the nth (n is an integer from 1 to 96) word line WL counted from one side is shown as word line WL(n - 1). In the examples of FIGS. 21 and 22, sub-block SB0 includes word lines WL0 to WL47, and sub-block SB1 includes word lines WL48 to WL95.

[0160] In the examples shown in FIGS. 21 to 23, FIGS. 31 to 34, and FIGS. 54 to 57, the writing operation is performed in ascending order of n of word line WL(n - 1) from word line WL0 to word line WL95, and within each word line WL, the writing operation is performed in the order of string units SU0, SU1, SU2, and SU3.

[0161] This determination operation is one of the operations performed inside the memory die MD when, for example, a command instructing an erasing operation for the selected memory block BLK is sent to the memory die MD.

[0162] In this operation, for example, as shown in FIGS. 21 and 22, a reading operation is performed on the page PG_UF(1) where the writing operation is first performed among the pages PG in sub-block SB1. In the examples shown in FIGS. 21 and 22, the page PG_UF(1) is the page PG corresponding to word line WL48 of sub-block SB1 and string unit SU0.

[0163] Figure 21 shows a case where subblock SB1 is in a fully erased state, but subblock SB0 is not. In such a case, if the read operation yields a result that page PG_UF(1) is in an erased state Er, then it can be determined that subblock SB1 is in a fully erased state.

[0164] Figure 22 shows a case where subblock SB1 is not in a fully erased state. If the read operation results in page PG_UF(1) being in a written state Pg, it can be determined that subblock SB1 is not in a fully erased state.

[0165] [Subblock SB0 erase operation] The subblock SB0 erase operation erases the data from all memory cells MC in subblock SB0. The subblock SB0 erase operation is basically performed in the same way as the memory block erase operation (Figure 16). However, the erase voltage supply operation performed in the subblock SB0 erase operation is different from the erase voltage supply operation performed in the memory block erase operation (Figure 16).

[0166] Figure 24 is a timing chart illustrating the subblock SB0 erase operation. Figure 25 is a schematic cross-sectional view illustrating the subblock SB0 erase operation.

[0167] At the timing t131 of the subblock SB0 erase operation, as shown in Figures 24 and 25, voltage V is applied to the selected gate lines (SGD, SGS) respectively. ERA -V1 is supplied, and voltage V is applied to the bit line BL and source line SL (semiconductor layer 112). ERA To supply.

[0168] Furthermore, the word line WL of subblock SB0 has a ground voltage V. SS This supplies a voltage V between the gate electrode and channel region of the memory cell MC in subblock SB0. ERA A certain voltage is applied.

[0169] Furthermore, the word line WL of subblock SB1 has a ground voltage V. SS A non-selective cancellation voltage V greater than X This supplies a voltage V between the gate electrode and channel region of the memory cell MC in subblock SB1. ERA A voltage smaller than V ERA -V X A voltage V is applied. ERA -V X This voltage is such that even when the memory cell MC in subblock SB1 is in the Er state, i.e., when no electrons are stored in the charge storage film 132, holes do not tunnel through the tunnel insulating film 131. ERA -V X It has a size that causes the memory cell MC to be in the ON state when the memory cell MC is operated as a PMOS transistor.

[0170] Between timings t132 and t133, in the memory cell MC of subblock SB0, holes that tunnel through the tunnel insulating film 131 are accumulated in the charge storage film 132 (Figure 9), thereby erasing the data in the memory cell MC. On the other hand, in the memory cell MC of subblock SB1, holes do not tunnel through the tunnel insulating film 131, so the threshold value of the memory cell MC does not drop further (over-erasure).

[0171] Furthermore, in the erase voltage supply operation performed during the erase operation of subblock SB0, as shown in Figure 25, holes generated near the channel of the selection transistor STS may be used to erase the memory cell MC. Alternatively, holes generated near the channel of the selection transistor STD may be transferred to subblock SB0 via the channel region corresponding to subblock SB1 and used to erase the memory cell MC.

[0172] At timing t133, the ground voltage V is applied to the bit line BL, the selected gate lines (SGD, SGS), the word lines WL of subblocks SB0 and SB1, and the source line SL. SS To supply.

[0173] [Example of operation of selection and deletion operation (1)] The operation when subblock SB1 is in a completely erased state (Figure 21) is called operation example EX10. In operation example EX10, a read operation is performed on PG_UF(1) in step S121. Also, the subblock SB0 erase operation is performed in step S122, and all pages PG contained in memory block BLK are set to the erased state Er (Figure 23).

[0174] The operation when subblock SB1 is not in a fully erased state (Figure 22) is called operation example EX11. In operation example EX11, a read operation is performed on PG_UF(1) in step S121. Also in operation example EX11, the memory block erase operation is performed in step S123, and all pages PG contained in memory block BLK are set to the erased state Er (Figure 23).

[0175] [Threshold voltage distribution of memory cell MC during erase operation] Figures 26 and 28 are graphs illustrating the semiconductor memory device according to this embodiment. Figures 26 to 28 show the median threshold voltages of multiple memory cells MC within the page PG corresponding to each word line WL, with word lines WL0 to WL95 on the horizontal axis.

[0176] Figure 26 shows the case where subblock SB0 is partially written and subblock SB1 is fully erased (Figure 21). Page PG, which corresponds to the multiple word lines WL located on one side of subblock SB0, is in the written state Pg, so the median value of the threshold voltage is, for example, voltage V Pi This is the extent of the situation (group Db_01p in Figure 26). Page PG, corresponding to multiple word lines WL located on the other side of subblock SB0, is in the erased state Er, so the median of the threshold voltage is, for example, voltage V E0 This is the extent of the situation (group Db_02e in Figure 26). Since page PG corresponding to all word lines WL in subblock SB1 is in the erased state Er, the median threshold voltage is, for example, voltage V E0 This is the extent of the problem (group Db_10e in Figure 26).

[0177] [Comparative Example] Next, a semiconductor memory device according to a comparative example will be described. FIG. 27 is a graph for explaining the semiconductor memory device according to the comparative example. In the semiconductor memory device according to the comparative example, a memory block erasure operation is performed regardless of the writing status of the sub-blocks.

[0178] FIG. 27 is a diagram when a memory block erasure operation (FIG. 16) is performed on the memory block BLK in a state corresponding to FIGS. 21 and 26. By the memory block erasure operation, the pages PG corresponding to the plurality of word lines WL located on one side of the sub-block SB0 change from the written state Pg to the erased state Er, and the median value of the threshold voltage becomes, for example, voltage V E0 or the like (group Db_01e in FIG. 27). On the other hand, for the pages PG corresponding to the plurality of word lines WL located on the other side of the sub-block SB0, from the erased state Er, further, a voltage of about voltage V ERA is applied between the gate electrode and the channel region of the memory cell MC, so that holes are excessively injected into the charge storage film 132 (FIG. 9), and the median value of the threshold voltage becomes, for example, voltage V E0 lower than voltage V EX and becomes voltage V EX or the like (group Db_02ex in FIG. 27). Also, for the pages PG including all the word lines WL of the sub-block SB1, similarly, the median value of the threshold voltage becomes, for example, voltage V

[0179] As in the groups Db_02ex and Db_10ex, the situation where the threshold voltage after the erasure operation becomes a voltage V E0 lower than the normal voltage V EX is hereinafter referred to as an over-erased state. When a high voltage is applied to the gate electrode of the memory cell MC until it reaches the over-erased state, excessive stress is applied to the gate insulating film of the memory cell MC. In such a case, the data retention characteristics of the memory cell MC may deteriorate.

[0180] Figure 29 is a histogram illustrating the semiconductor memory device related to the comparative example. In Figure 29, the horizontal axis represents the threshold voltage of the word line WL, and the vertical axis represents the number of memory cells MC.

[0181] Figure 29(a) shows the threshold voltage distribution of multiple memory cells MC in the original Er state (solid line, median value is voltage V). E0 ) and the threshold voltage distribution of multiple memory cells MC in the Er state (dashed line, median is voltage V) EX This indicates that...

[0182] Figure 29(b) shows the threshold voltage distribution (solid line) when writing from the original Er state to states A through G, and the threshold voltage distribution (dashed line) when writing from an over-erased Er state to states A through G. As shown above, when states A through G written from different Er states are mixed, the threshold voltage distribution of each state widens, which can lead to malfunctions in read operations and other operations, thus reducing reliability.

[0183] [effect] In the semiconductor memory device according to this embodiment, the erase voltage is not supplied to the memory cell MC, which is included in the subblock SB1 in the fully erased state, by the selective erase operation (1).

[0184] Figure 28 shows the result of performing a selective erase operation (1) on memory block BLK in the state corresponding to Figures 21 and 26. By not supplying erase voltage to subblock SB1 in the fully erased state, the median value of the threshold voltage is, for example, voltage V E0 This condition is maintained (group Db_10e in Figure 28). Therefore, excessive stress on the memory cell MC included in subblock SB1 and the memory cell MC entering an over-erased state are prevented, making it possible to provide a semiconductor memory device with good data retention characteristics and reliability.

[0185] [Modified version of the first embodiment] The semiconductor memory device according to this modified example includes a controller die CD equipped with registers RG and the like that can record the erase state and write state of subblock units.

[0186] In step S121 of this modified example (Figure 20), the controller refers to register RG, etc., to determine whether or not subblock SB1 is in a completely erased state.

[0187] In step S122 of this modified example (Figure 20), the controller sends a command to the memory die MD instructing it to erase subblock SB0, and the memory die MD executes the subblock SB0 erase operation.

[0188] In step S123 of this modified example (Figure 20), the controller sends a command to the memory die MD instructing it to perform a memory block erase operation, and the memory die MD executes the memory block erase operation (Figure 16).

[0189] [Second Embodiment] Next, a semiconductor memory device according to the second embodiment will be described. Note that in the following description, configurations and operations similar to those of the first embodiment may be omitted from the explanation.

[0190] The semiconductor memory device according to this embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to this embodiment is configured to perform a selective erase operation (2).

[0191] [Selection and Deletion Operation (2)] Figure 30 is a flowchart illustrating the selection and elimination operation (2).

[0192] In the following example, in memory block BLK, the write operation is performed first on subblock SB0, and then on subblock SB1.

[0193] In the following explanation, when subblock SB is described as being in a partially written state, it means that some pages PG contained within subblock SB are in a written state (Pg), and the other pages PG are in an erased state (Er). Conversely, when subblock SB is not partially written, or when subblock SB is in a fully written state, it means that all pages PG contained within subblock SB are in a written state (Pg).

[0194] In step S201, it is determined whether or not subblock SB1 is in a fully erased state. If subblock SB1 is in a fully erased state, the process proceeds to step S202; otherwise, the process proceeds to step S205. Step S201 is performed in the same manner as, for example, step S121 (Figure 20).

[0195] In step S202, it is determined whether subblock SB0 is in a partially written state. If subblock SB0 is in a partially written state, the process proceeds to step S203; if subblock SB0 is in a fully written state, the process proceeds to step S204. The operation for determining whether subblock SB0 is in a partially written state will be described later.

[0196] In step S203, the preprogram for subblock SB0, described later, is executed, and the process proceeds to step S204.

[0197] In step S204, the subblock SB0 erase operation is performed. Step S204 is performed, for example, in the same way as step S122 (Figure 20).

[0198] In step S205, it is determined whether subblock SB1 is in a partially written state. If subblock SB1 is in a partially written state, the process proceeds to step S206; if subblock SB1 is in a fully written state, the process proceeds to step S207. The operation for determining whether subblock SB1 is in a partially written state will be described later.

[0199] In step S206, the preprogram for subblock SB1, described later, is executed, and the process proceeds to step S207.

[0200] In step S207, the memory block erase operation (Figure 16) is performed.

[0201] [An operation to determine whether subblock SB0 is in a partially written state.] Figures 31 to 34 are schematic diagrams illustrating examples of subblock writing status.

[0202] This operation is one of the operations performed internally by the memory die MD, for example, when a command instructing an erase operation on the selected memory block BLK is sent to the memory die MD.

[0203] Prior to this operation, a read operation is performed on page PG_UF(1), for example (step S201). This operation is performed when page PG_UF(1) is in the erased state Er.

[0204] In this operation, for example as shown in Figure 31, a read operation is performed on page PG_LE(2), which is the last page PG to be written to within the subblock SB0. In the example shown in Figure 31, page PG_LE(2) is the page PG corresponding to the word line WL47 and the string unit SU3 in the subblock SB0.

[0205] Figure 31 shows the case where subblock SB1 is in a fully erased state and subblock SB0 is in a partially written state. In such a case, if the read operation yields a result that page PG_LE(2) is in an erased state Er, then it can be determined that subblock SB0 is in a partially written state, as shown in Figure 31.

[0206] [An operation to determine whether subblock SB1 is in a partially written state or not] This operation is one of the operations performed internally by the memory die MD, for example, when a command instructing an erase operation on the selected memory block BLK is sent to the memory die MD.

[0207] Prior to this operation, a read operation is performed on page PG_UF(1), for example (step S201). This operation is performed when page PG_UF(1) is in the write state Pg.

[0208] In this operation, for example as shown in Figure 32, a read operation is performed on page PG_UE(2), which is the last page PG to be written to within subblock SB1. In the example shown in Figure 32, page PG_UE(2) is the page PG corresponding to the word line WL95 and string unit SU3 in subblock SB1.

[0209] Figure 32 shows the case where subblock SB1 is in a partially written state. If the read operation results in page PG_UE(2) being in an erased state Er, then it can be determined that subblock SB1 is in a partially written state, as shown in Figure 32.

[0210] [Pre-programming for subblocks SB0 and SB1] Figures 35 and 36 are schematic cross-sectional views illustrating the preprogramming of subblocks SB0 and SB1.

[0211] The pre-programming of subblocks SB0 and SB1 is basically performed in the same way as the writing operation (Figures 13 to 15).

[0212] However, the preprogramming of subblock SB0, in the program operation in step S102 (Figure 13), selects all word lines WL of subblock SB0, as shown in Figure 35, for example, the selected word lines WL S And all word lines WL in subblock SB1 are changed to unselected word lines WL U This will result in the programmed voltage V being applied to the word line WL of subblock SB0. PGMWhen this is supplied (Figure 35), the threshold voltage of the write memory cell MC included in subblock SB0 increases.

[0213] Furthermore, the preprogramming of subblock SB1, in the program operation in step S102 (Figure 13), selects all word lines WL of subblock SB1, as shown in Figure 36, for example, by selecting all word lines WL. S And all word lines WL in subblock SB0 are deselected word lines WL U This will result in the programmed voltage V being applied to the word line WL of subblock SB1. PGM When this is supplied (Figure 36), the threshold voltage of the write memory cell MC included in subblock SB1 increases.

[0214] These preprograms may be performed for each string unit SU (Figures 35 and 36), or they may be performed simultaneously for multiple string units SU.

[0215] By pre-programming subblock SB0 as shown in Figure 31, subblock SB0 will enter a fully written state as shown in Figure 33. By pre-programming subblock SB1 as shown in Figure 32, subblock SB1 will enter a fully written state as shown in Figure 34.

[0216] Furthermore, in the pre-programming of subblocks SB0 and SB1, steps S103 to S108 (Figure 13) related to the verification operation do not need to be performed.

[0217] Furthermore, in the preprogramming of subblocks SB0 and SB1, the selected word line WL S Program voltage V PGM The time for supplying the material (timing t113~t114) can be longer than the example shown in Figure 14.

[0218] [Example of operation of selection and deletion operation (2)] The operation when subblock SB1 is in a fully erased state and subblock SB0 is in a partially written state (Figure 31) is called operation example EX20. In operation example EX20, the preprogram in step S203 (Figure 30) puts subblock SB0 into a fully written state (Figure 33), and then the subblock SB0 erase operation in step S204 is performed, resulting in all pages PG being in the erased state Er (Figure 23).

[0219] The operation when subblock SB1 is in a fully erased state and subblock SB0 is in a fully written state is called operation example EX21. In operation example EX21, step S203 (Figure 30) is skipped, and the subblock SB0 erase operation in step S204 is performed, and all pages PG become in the erased state Er (Figure 23).

[0220] The operation when subblock SB1 is partially written (Figure 32) is referred to as operation example EX22. In operation example EX22, the preprogram in step S206 (Figure 30) sets subblock SB1 to a fully written state (Figure 34), and then the memory block erase operation in step S207 is performed, resulting in all pages PG being in the erased state Er (Figure 23).

[0221] The operation when subblock SB1 is in a fully written state is called operation example EX23. In operation example EX23, step S206 (Figure 30) is skipped, and the memory block erase operation in step S207 is performed, and all pages PG are in the erased state Er (Figure 23).

[0222] [effect] Figures 37 and 38 are graphs illustrating the semiconductor memory device according to this embodiment. Figures 37 and 38 show the median threshold voltages of multiple memory cells MC within a page PG corresponding to each word line WL, with word lines WL0 to WL95 on the horizontal axis.

[0223] Figure 37 shows the result of pre-programming the subblock SB0 corresponding to Figure 31. Pre-programming causes the page PG corresponding to multiple word lines WL located on the other side of subblock SB0 to change from the erase state Er to the write state Pg, and the median threshold voltage is, for example, V Pi It increases to a certain extent (group Db_02p in Figure 37).

[0224] Figure 38 shows the case when subblock SB0 is erased after preprogramming (Figure 37). Because preprogramming removes page PG in erase state Er from subblock SB0, as shown in Figure 38, the memory cell MC within subblock SB0 does not enter an over-erased state as a result of the subblock SB0 erase operation.

[0225] In operation examples EX20 and EX21, the erase operation is performed only on subblock SB0 in step S204, which prevents the memory cell MC in subblock SB1 from entering an over-erased state.

[0226] In operation examples EX20 and EX22, the pre-programming in steps S203 and S206 prevents some pages PG in erase state Er, which are included in subblocks SB0 and SB1, from entering an over-erased state.

[0227] In operation examples EX21 and EX23, the pre-program steps S203 and S206 are skipped, preventing unnecessary stress on the memory cell MC due to pre-programming.

[0228] [Modified version of the second embodiment] The semiconductor memory device according to this modified example includes a controller die CD equipped with registers RG and the like that can record the erase state and write state of subblock units.

[0229] In step S201 of this modified example (Figure 30), the controller refers to register RG, etc., to determine whether or not subblock SB1 is in a completely erased state.

[0230] In steps S202 and S205 of this modified example (Figure 30), the controller refers to register RG, etc., to determine whether or not subblocks SB0 and SB1 are in a partially written state.

[0231] In steps S203 and S206 of this modified example (Figure 30), the controller sends commands to the memory die MD to instruct the pre-programming of sub-blocks SB0 and SB1, respectively, and the memory die MD executes the pre-programming of sub-blocks SB0 and SB1, respectively.

[0232] In step S204 of this modified example (Figure 30), the controller sends a command to the memory die MD instructing it to erase subblock SB0, and the memory die MD executes the subblock SB0 erase operation.

[0233] In step S207 of this modified example (Figure 30), the controller sends a command to the memory die MD instructing it to perform a memory block erase operation, and the memory die MD executes the memory block erase operation (Figure 16).

[0234] [Third Embodiment] Next, a semiconductor memory device according to the third embodiment will be described. Figure 39 is a schematic perspective view showing a part of the configuration of the semiconductor memory device according to the third embodiment. In the following description, configurations and operations similar to those of the first embodiment may be omitted from the explanation.

[0235] The semiconductor memory device according to this embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, in the semiconductor memory device according to this embodiment, as shown in Figure 39, for example, the memory block BLK is a memory cell array layer L MCA2 Memory cell array layer L located above MCA3 To further enhance this.

[0236] Memory cell array layer L MCA3 Basically, the memory cell array layer LMCA1 and memory cell array layer L MCA2 It is provided in the same manner as the memory cell array layer L. MCA3 For example, it comprises a plurality of conductive layers 110 aligned in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120, respectively. Memory cell array layer L MCA3 and memory cell array layer L MCA2 An insulating layer 151 made of silicon oxide (SiO2) or the like is provided between them.

[0237] Furthermore, the semiconductor memory device according to this embodiment is configured to perform a selective erase operation (3).

[0238] [Selection and Deletion Operation (3)] Figure 40 is a flowchart illustrating the selection and elimination operation (3).

[0239] In the following example, in memory block BLK, the write operation is performed first on subblock SB0, then on subblock SB1, then subblock SB2, and so on.

[0240] In step S301, it is determined whether or not subblock SB2 is in a fully erased state. If subblock SB2 is in a fully erased state, the process proceeds to step S302; otherwise, the process proceeds to step S305. The operation for determining whether or not subblock SB2 is in a fully erased state will be described later.

[0241] In step S302, it is determined whether or not subblock SB1 is in a fully erased state. If subblock SB1 is in a fully erased state, the process proceeds to step S303; otherwise, the process proceeds to step S304. Step S302 is performed in the same manner as, for example, step S121 (Figure 20).

[0242] In step S303, the subblock SB0 erase operation is performed. Step S303 basically performs the same operation as step S122 (Figure 20). However, in this operation, the word line WL of subblock SB2 is also subjected to the same non-selective erase voltage V as subblock SB1. X To supply.

[0243] In step S304, the subblocks SB0 and SB1 are erased. Step S304 basically performs the same operation as step S122 (Figure 20). However, at the timing t132 of this operation (Figure 24), a ground voltage V is applied to the word line WL of the subblocks SB0 and SB1. SS The word line WL of subblock SB2 is supplied with a non-selective erase voltage V X This supplies the necessary components. As a result, the memory cells MC contained in subblock SB2 are not erased.

[0244] In step S305, the operation is basically the same as the memory block erase operation (Figure 16). However, at the timing t122 ​​of this operation (Figure 17), the same ground voltage V as the word line WL of subblock SB2 is applied to the word line WL of subblocks SB0 and SB1. SS To supply.

[0245] [An operation to determine whether subblocks SB1 and SB2 are in a completely erased state.] Figures 41 to 44 are schematic diagrams illustrating examples of subblock writing status.

[0246] This operation is one of the operations performed internally by the memory die MD, for example, when a command instructing an erase operation on the selected memory block BLK is sent to the memory die MD.

[0247] In the examples shown in Figures 41-44 and 46-51 below, a total of 144 word lines WL are provided, and the m-th word line WL (where m is an integer from 1 to 144) from the bottom layer is shown as word line WL(m-1). In the examples in Figures 41-44, subblock SB0 contains word lines WL0-WL47, subblock SB1 contains word lines WL48-95, and subblock SB2 contains word lines WL96-WL143.

[0248] Furthermore, in the examples shown in Figures 41-44 and 46-51 below, the writing operation is performed from word line WL0 to word line WL143, in order of increasing m in word line WL(m-1), and within each word line WL, the writing operation is performed in the order of string units SU0, SU1, SU2, and SU3.

[0249] In this operation, for example, as shown in Figures 41 to 43, a read operation is performed on page PG_TF(1), which is the first page PG in subblock SB2 to be written to. In the example shown in Figures 41 to 43, page PG_TF(1) is the page PG corresponding to the word line WL96 and the string unit SU0 in subblock SB2.

[0250] Figures 41 and 42 show the case where subblock SB2 is in a fully erased state. Figure 43 shows the case where subblock SB2 is not in a fully erased state. If page PG_TF(1) is in the erased state Er, it can be determined that subblock SB2 is in a fully erased state (Figures 41 and 42), and if page PG_TF(1) is in the written state Pg, it can be determined that subblock SB2 is not in a fully erased state (Figure 43).

[0251] If page PG_TF(1) is in the erase state Er, in step S302 (Figure 40), a read operation is performed on page PG_UF(2), which is the first page PG in subblock SB1 to be written to. In the example shown in Figures 41 and 42, page PG_UF(2) is the page PG corresponding to the word line WL48 and the string unit SU0 in subblock SB1.

[0252] Figure 41 shows the case where subblock SB1 is in a fully erased state. Figure 42 shows the case where subblock SB1 is not in a fully erased state. If page PG_UF(2) is in the erased state Er, it can be determined that subblock SB1 is in a fully erased state (Figure 41), and if page PG_UF(2) is in the written state Pg, it can be determined that subblock SB1 is not in a fully erased state (Figure 42).

[0253] [Example of operation of selection and deletion operation (3)] The operation when subblocks SB1 and SB2 are in a completely erased state (Figure 41) is referred to as operation example EX30. In operation example EX30, the subblock SB0 erase operation in step S303 is performed, and as shown in Figure 44, all pages PG contained in memory block BLK are in the erased state Er.

[0254] The operation when only subblock SB2 is in a completely erased state (Figure 42) is referred to as operation example EX31. In operation example EX31, the erase operation for subblocks SB0 and SB1 in step S304 is performed, and as shown in Figure 44, all pages PG contained in memory block BLK enter the erased state Er.

[0255] The operation when none of the subblocks SB0, SB1, and SB2 are in a completely erased state (Figure 43) is called operation example EX32. In operation example EX32, the memory block erase operation in step S305 is performed, and as shown in Figure 44, all pages PG contained in the memory block BLK are in the erased state Er.

[0256] [effect] In the example operation EX30, the erase operation is performed only on subblock SB0 in step S303, which prevents the memory cells MC in subblocks SB1 and SB2 from entering an over-erased state.

[0257] In the example operation EX31, by performing the erase operation only on subblocks SB0 and SB1 in step S304, it is possible to prevent the memory cell MC contained in subblock SB2 from entering an over-erased state.

[0258] [Modified version of the third embodiment] The semiconductor memory device according to this modified example includes a controller die CD equipped with registers RG and the like that can record the erase state and write state of subblock units.

[0259] In steps S301 and S302 of this modified example, the controller refers to register RG, etc., to determine whether or not subblocks SB2 and SB1 are in a completely erased state.

[0260] In step S303 of this modified example, the controller sends a command to the memory die MD instructing it to perform the subblock SB0 erase operation, and the memory die MD performs the subblock SB0 erase operation.

[0261] In step S304 of this modified example, the controller sends a command to the memory die MD instructing it to erase subblocks SB0 and SB1, and the memory die MD executes the erase operation for subblocks SB0 and SB1.

[0262] In step S305 of this modified example, the controller sends a command to the memory die MD instructing it to perform a memory block erase operation, and the memory die MD executes the memory block erase operation (Figure 16).

[0263] [Fourth Embodiment] Next, a semiconductor memory device according to the fourth embodiment will be described. Note that in the following description, configurations and operations similar to those in the first to third embodiments may be omitted.

[0264] The semiconductor memory device according to this embodiment is basically configured the same as the semiconductor memory device according to the third embodiment. However, the semiconductor memory device according to this embodiment is configured to perform a selective erase operation (4).

[0265] [Selection and Deletion Operation (4)] Figure 45 is a flowchart illustrating the selective erase operation (4). Figures 46 to 51 are schematic diagrams showing examples of the writing status of subblocks.

[0266] In the following example, in memory block BLK, the write operation is performed first on subblock SB0, then on subblock SB1, then subblock SB2, and so on.

[0267] In step S401, it is determined whether or not subblock SB2 is in a fully erased state. If subblock SB2 is in a fully erased state, the process proceeds to step S402; otherwise, the process proceeds to step S409. Step S401 is performed in the same manner as, for example, step S301 (Figure 40).

[0268] In step S402, it is determined whether or not subblock SB1 is in a fully erased state. If subblock SB1 is in a fully erased state, the process proceeds to step S403; otherwise, the process proceeds to step S406. Step S402 is performed, for example, in the same way as step S302 (Figure 40).

[0269] In step S403, it is determined whether subblock SB0 is in a partially written state. If subblock SB0 is in a partially written state, the process proceeds to step S404; if subblock SB0 is in a fully written state, the process proceeds to step S405. In step S403, a read operation is performed on page PG_LE(3) (Figure 46), which is the last page PG in subblock SB0 to be written, and the process is determined.

[0270] In step S404, the preprogram for subblock SB0 is executed, and the process proceeds to step S405. Step S404 is basically performed in the same way as step S203 (Figure 30). However, in step S404, in the program operation in step S102 (Figure 13), the word line WL of subblock SB0 is selected. SThe word lines WL of subblocks SB1 and SB2 are then selected as unselected word lines WL. U It will be done as follows.

[0271] In step S405, the subblock SB0 erase operation is performed. Step S405 is performed in the same manner as step S303 (Figure 40).

[0272] In step S406, it is determined whether subblock SB1 is in a partially written state. If subblock SB1 is in a partially written state, the process proceeds to step S407; if subblock SB1 is in a fully written state, the process proceeds to step S408. In step S406, a read operation is performed on page PG_UE(3) (Figure 48), which is the last page PG in subblock SB1 to be written, and the process is determined.

[0273] In step S407, the preprogram for subblock SB1 is executed, and the process proceeds to step S408. Step S407 is basically the same as step S206 (Figure 30). However, in step S407, the word line WL of subblock SB1 is selected. S The word lines WL of subblocks SB0 and SB2 are then selected as unselected word lines WL. U It will be done as follows.

[0274] In step S408, the subblocks SB0 and SB1 are erased. Step S408 is performed in the same manner as, for example, step S304 (Figure 40).

[0275] In step S409, it is determined whether subblock SB2 is in a partially written state. If subblock SB2 is in a partially written state, the process proceeds to step S410; if subblock SB1 is in a fully written state, the process proceeds to step S411. In step S409, a read operation is performed on page PG_TE(2) (Figure 50) within subblock SB2, which is the last page to be written, and a determination is made.

[0276] In step S410, the preprogram for subblock SB2 is executed, and the process proceeds to step S411. Step S410 is basically the same as step S407 (Figure 45). However, in step S410, the word line WL of subblock SB2 is selected. S The word lines WL of subblocks SB0 and SB1 are then selected as unselected word lines WL. U It will be done as follows.

[0277] In step S411, the memory block erase operation (Figure 16) is performed.

[0278] [Example of operation of selection and deletion operation (4)] The operation when subblocks SB1 and SB2 are in a fully erased state and subblock SB0 is in a partially written state (Figure 46) is called operation example EX40. In operation example EX40, read operations are performed on pages PG_TF(1), PG_UF(2), and PG_LE(3) in steps S401, S402, and S403, respectively. In operation example EX40, after subblock SB0 is put into a fully written state (Figure 47) in step S404 (Figure 45), the subblock SB0 erase operation is performed in step S405, and all pages PG are put into the erased state Er (Figure 44).

[0279] The operation when subblocks SB1 and SB2 are in a fully erased state and subblock SB0 is in a fully written state is called operation example EX41. Operation example EX41 is basically the same as operation example EX40, but in operation example EX41, step S404 (Figure 45) is skipped.

[0280] The operation when subblock SB2 is in a fully erased state and subblock SB1 is in a partially written state (Figure 48) is called operation example EX42. In operation example EX42, read operations are performed on pages PG_TF(1), PG_UF(2), and PG_UE(3) in steps S401, S402, and S406, respectively. In operation example EX42, after subblock SB1 is put into a fully written state (Figure 49) in step S407 (Figure 45), the erase operation of subblocks SB0 and SB1 is performed in step S408, and all pages PG are put into an erased state Er (Figure 44).

[0281] The operation when subblock SB2 is in a fully erased state and subblock SB1 is in a fully written state is called operation example EX43. Operation example EX43 is basically the same as operation example EX42, but in operation example EX43, step S407 (Figure 45) is skipped.

[0282] The operation when subblock SB2 is partially written (Figure 50) is referred to as operation example EX44. In operation example EX44, read operations are performed on pages PG_TF(1) and PG_TE(2) in steps S401 and S409, respectively. In operation example EX44, after subblock SB2 is put into a fully written state (Figure 51) from step S410 (Figure 45), the memory block BLK erase operation is performed in step S411, and all pages PG are put into the erased state Er (Figure 44).

[0283] The operation when subblock SB2 is in a fully written state is called operation example EX45. Operation example EX45 is basically the same as operation example EX44, but in operation example EX45, step S410 (Figure 45) is skipped.

[0284] [effect] In operation examples EX40 and EX41, the erase operation is performed only on subblock SB0 in step S405, which prevents the memory cells MC in subblocks SB1 and SB2 from entering an over-erased state.

[0285] In operation examples EX42 and EX43, the erase operation is performed only on subblocks SB0 and SB1 in step S408, which prevents the memory cell MC in subblock SB2 from entering an over-erased state.

[0286] In operation examples EX40, EX42, and EX44, the pre-programming in steps S404, S407, and S410 prevents some pages PG in erase state Er, which are included in subblocks SB0, SB1, and SB2, from entering an over-erased state.

[0287] In operation examples EX41, EX43, and EX45, the pre-program steps S404, S407, and S410 are skipped, preventing unnecessary stress on the memory cell MC due to pre-programming.

[0288] [Modified version of the fourth embodiment] The semiconductor memory device according to this modified example includes a controller die CD equipped with registers RG and the like that can record the erase state and write state of subblock units.

[0289] In steps S401 and S402 of this modified example, the controller refers to register RG, etc., to determine whether or not subblocks SB2 and SB1 are in a completely erased state.

[0290] In steps S403, S406, and S409 of this modified example, the controller refers to register RG, etc., to determine whether or not subblocks SB0, SB1, and SB2 are in a partially written state.

[0291] In steps S404, S407, and S410 of this modified example, the controller sends commands to the memory die MD to instruct the preprogramming of subblocks SB0, SB1, and SB2, respectively, and the memory die MD executes the preprogramming of subblocks SB0, SB1, and SB2, respectively.

[0292] In step S405 of this modified example, the controller sends a command to the memory die MD instructing it to perform the subblock SB0 erase operation, and the memory die MD performs the subblock SB0 erase operation.

[0293] In step S408 of this modified example, the controller sends a command to the memory die MD instructing it to erase subblocks SB0 and SB1, and the memory die MD executes the erase operation for subblocks SB0 and SB1.

[0294] In step S411 of this modified example, the controller sends a command to the memory die MD instructing it to perform a memory block erase operation, and the memory die MD executes the memory block erase operation (Figure 16).

[0295] [Fifth Embodiment] Next, a semiconductor memory device according to the fifth embodiment will be described. Note that in the following description, configurations and operations similar to those in the first to fourth embodiments may be omitted.

[0296] The semiconductor memory device according to this embodiment is basically configured the same as the semiconductor memory device according to the second embodiment. However, the semiconductor memory device according to this embodiment can record either 3 bits in the memory cell MC (Figure 10) or 1 bit in the memory cell MC (Figure 52). Hereinafter, the case in which 3 bits are recorded may be referred to as the 3-bit mode, and the case in which 1 bit is recorded may be referred to as the 1-bit mode.

[0297] [Threshold voltage of memory cell MC for recording 1 bit] Figure 52 is a schematic histogram illustrating the threshold voltage of a memory cell MC on which one bit of data is recorded. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC.

[0298] In the example shown in Figure 52, the threshold voltage of the memory cell MC is controlled to two different states. For example, the threshold voltage of the memory cell MC controlled to the lower state is the erase verify voltage V VFYEr It is smaller. Also, the threshold voltage of the memory cell MC controlled to the higher state is the verify voltage V VFYS Larger read path voltage V READ_S Smaller.

[0299] Furthermore, in the example shown in Figure 52, there is a readout voltage V between the threshold distribution corresponding to the lower state and the threshold distribution corresponding to the higher state. CGR It is set.

[0300] For example, a lower state corresponds to a low threshold voltage. A lower state memory cell MC is, for example, a memory cell MC in the erase state. A lower state memory cell MC is assigned data "1", for example.

[0301] Furthermore, higher states correspond to higher threshold voltages. A memory cell MC in a higher state is, for example, a memory cell MC in the write state. A memory cell MC in a higher state is assigned data "0", for example.

[0302] Furthermore, the semiconductor memory device according to this embodiment is configured to perform a selective erase operation (5).

[0303] [Selection and Deletion Operation (5)] Figure 53 is a flowchart illustrating the selective erase operation (5). Figures 54 to 57 are schematic diagrams showing examples of the writing status of subblocks.

[0304] Figures 54 to 57 show the writing status of the page PG corresponding to the multiple word lines WL provided in the memory block BLK and the four string units SU0, SU1, SU2, and SU3. The writing status of the page PG is shown as one of the following: a written state Pgs with 1 bit recorded, a written state Pgt with 3 bits recorded, a written state Pg after preprogramming, or an erased state Er.

[0305] In the examples shown in Figures 54 to 57, in the memory block BLK, the write operation is performed first on subblock SB0, and then on subblock SB1. The write operation is performed from word line WL0 to word line WL95, in ascending order of n in word line WL(n-1), and within each word line WL, the write operation is performed in the order of string units SU0, SU1, SU2, and SU3.

[0306] In step S501, if the selected memory block BLK has recorded 3 bits, the process proceeds to step S502; if it has recorded 1 bit, the process proceeds to step S506. In step S501, for example, the controller makes a determination by referring to information about the selected memory block BLK held in register RG, etc.

[0307] In step S502, it is determined whether or not there are subblocks SB0 and SB1 in a partially written state. If there are subblocks SB0 and SB1 in a partially written state, the process proceeds to step S503. If there are no subblocks SB0 and SB1 in a partially written state (subblocks SB0 and SB1 are in a fully written state), the process proceeds to step S505. In step S502, for example, the controller makes the determination by referring to information about subblocks SB0 and SB1 held in register RG, etc.

[0308] In step S503, preprogramming is performed on subblocks SB0 and SB1, which are in a partially written state, and the process proceeds to step S504. In step S503, the pages PG (unwritten pages) in the erase state Er contained in subblocks SB0 and SB1 (subblock SB0 in the example of Figure 54) are selected sequentially, and preprogramming is performed only on the pages PG in the erase state Er to set them to the written state Pg (Figure 55).

[0309] In step S504, a subblock erase operation is performed on the subblock that was preprogrammed in step S503 (subblock SB0 in the example of Figure 55).

[0310] In step S505, the memory block erase operation (Figure 16) is performed.

[0311] In step S506, it is determined whether or not there are subblocks SB0 and SB1 that are partially written. If there are subblocks SB0 and SB1 that are partially written, the process proceeds to step S507; otherwise, the process proceeds to step S509. In step S506, for example, the controller makes the determination by referring to information about subblocks SB0 and SB1 held in register RG, etc.

[0312] In step S507, preprogramming is performed for subblocks SB0 and SB1, which are in a partially written state, and then the process proceeds to step S508. Step S507 is performed in the same manner as, for example, steps S203 and S206 (Figure 30).

[0313] In step S508, a subblock erase operation is performed on the subblock that was preprogrammed in step S507 (subblock SB0 in the example of Figure 57).

[0314] In step S509, a block preprogram is executed on the memory block BLK. The block preprogram is basically performed in the same way as the preprogram. However, in the program operation in step S102 (Figure 13), the block preprogram selects the word lines WL of subblocks SB0 and SB1. S It will be done as follows.

[0315] In step S510, the memory block erase operation (Figure 16) is performed.

[0316] [Example of operation of selection and deletion operation (5)] The operation when subblock SB1 is in a fully erased state and subblock SB0 is in a partially written state in 3-bit mode (Figure 54) is called operation example EX50. In operation example EX50, in step S503, preprogramming is performed only on the unwritten pages, and the page PG in the erased state Er of subblock SB0 (Figure 54) becomes the written state Pg (Figure 55). Next, the erase operation on subblock SB0 is performed in step S504, and all pages PG contained in memory block BLK become the erased state Er (Figure 23).

[0317] The operation when subblocks SB0 and SB1 are in a fully written state in 3-bit mode is called operation example EX51. In operation example EX51, step S503 is skipped, and the memory block erase operation in step S505 is performed, and all pages PG contained in memory block BLK are erased to state Er (Figure 23).

[0318] The operation when subblock SB1 is in a fully erased state and subblock SB0 is in a partially written state in 1-bit mode (Figure 56) is called operation example EX52. In operation example EX52, preprogramming of subblock SB0 is performed in step S507, and all pages PG (Figure 54) of subblock SB0 are set to the written state Pg (Figure 57). Next, the erase operation on subblock SB0 is performed in step S508, and all pages PG included in memory block BLK are set to the erased state Er (Figure 23).

[0319] The operation when subblocks SB0 and SB1 are in 1-bit mode and fully written is referred to as operation example EX53. In operation example EX53, block preprogramming is performed in step S509, and all pages PG contained in memory block BLK are set to the written state Pg. Next, the block erase operation is performed in step S510, and all pages PG contained in memory block BLK are set to the erased state Er (Figure 23).

[0320] [effect] In 1-bit mode, when a random pattern is written, approximately half of the memory cells (MCs) may be in the Er state. If an erase operation is performed without pre-programming in such cases, there is a high probability of over-erasing the memory cells (MCs). Therefore, in 1-bit mode, performing block pre-programming targeting the entire memory block (BLK), as in step S509, can suppress the occurrence of over-erased memory cells (MCs).

[0321] In 3-bit mode, when a random pattern is written, approximately 1 / 8 of the memory cells (MCs) may be in the Er state. In such cases, the rate of over-erasing of memory cells (MCs) is relatively low. Therefore, in 3-bit mode, pre-programming is performed only on unwritten page data (PGs), such as in step S503. This prevents unnecessary stress on the memory cells (MCs) caused by pre-programming.

[0322] [Modified version of the fifth embodiment] In step S501, the controller does not need to perform a determination. The determination in step S501 may be made by a read operation performed by the memory die MD, for example. In such a read operation, information is read from a portion of the page PG that is first written to the memory block BLK, indicating whether that page PG is in 1-bit mode or 3-bit mode. This information may also be written to a portion of the page PG that is first written to the memory block BLK during a write operation.

[0323] [Other embodiments] The writing order of page PG as shown in the first to fifth embodiments can be modified in various ways. For example, the writing operation of page PG may be performed in descending order of n in word line WL(n-1) and m in word line WL(m-1), and within each word line WL, the writing operation does not have to be performed in the order of string units SU0, SU1, SU2, SU3.

[0324] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0325] 100... Semiconductor substrate, BLK... Memory block, SB0... Subblock, SB1... Subblock, BL... Bit line, SL... Source line, PC... Peripheral circuit, MC... Memory cell, WL... Word line, MCA... Memory cell array.

Claims

1. circuit board and A memory block including a first sub-memory block and a second sub-memory block arranged in a first direction intersecting the surface of the substrate, With respect to the memory block, a bit line is provided on one side in the first direction, With respect to the memory block, a source line provided on the other side in the first direction, Control circuit for controlling the memory block and Equipped with, The first sub-memory block is, A first memory cell electrically connected to the bit line and the source line, A first word line electrically connected to the first memory cell and Equipped with, The aforementioned second sub-memory block is A second memory cell electrically connected to the bit line and the source line, The second word line electrically connected to the second memory cell and Equipped with, The control circuit, in an erase operation on the memory block, A first determination operation to determine whether the second memory cell is in a write state, A first erase operation performed when the second memory cell is in a write state, A second erase operation performed when the second memory cell is in an erase state and Configured to be executable, In the first erasure operation, An erase voltage is applied to one or both of the bit line and the source line. A selective erase voltage lower than the erase voltage is applied to the first word line and the second word line. In the second erasure operation, The erase voltage is applied to one or both of the bit line and the source line. The selection-erasure voltage is applied to the first word line. A non-selective erase voltage lower than the erase voltage and higher than the selective erase voltage is applied to the second word line. Semiconductor memory device.

2. The aforementioned control circuit is In the first determination operation, the system is configured to enable a read operation before erasure on the second memory cell, In the aforementioned read operation before erasure, A read voltage is applied to the second word line. A non-selective read voltage higher than the read voltage is applied to the first word line. The semiconductor memory device according to claim 1.

3. The aforementioned control circuit is In the first determination operation, the control circuit is configured to be able to access the memory area, The aforementioned storage area holds information about the write status of the second sub-memory block. The semiconductor memory device according to claim 1.

4. The aforementioned control circuit is The command set that instructs the first erase operation, The command set that instructs the second erase operation and Configured to send The semiconductor memory device according to claim 1.

5. The control circuit is configured to perform a write operation, If the first memory cell and the second memory cell are in an erased state, the write operation to the first memory cell is performed before the write operation to the second memory cell. The semiconductor memory device according to claim 1.

6. The control circuit is configured to perform a write operation, The second sub-memory block includes a plurality of pages as the unit of the write operation, The second memory cell is included in the page where the write operation is performed first among the plurality of pages. The semiconductor memory device according to claim 1.

7. The first sub-memory block is, A plurality of first conductive layers arranged in the first direction, A first semiconductor portion extending in the first direction and facing the plurality of first conductive layers, The plurality of first conductive layers and the first charge storage film provided between the first semiconductor portion Equipped with, The aforementioned second sub-memory block is A plurality of second conductive layers arranged in the first direction, A second semiconductor portion extending in the first direction, facing the plurality of second conductive layers, and electrically connected to the first semiconductor portion, The plurality of second conductive layers and the second charge storage film provided between the second semiconductor portion Equipped with, One of the plurality of first conductive layers functions as the first word line, One of the plurality of second conductive layers functions as the second word line. The semiconductor memory device according to claim 1.

8. The semiconductor layer comprises the first semiconductor layer extending in the aforementioned direction, The aforementioned semiconductor layer is The first semiconductor section and, The second semiconductor section and, A third semiconductor unit is provided between the first sub-memory block and the second sub-memory block and is connected to the first semiconductor unit and the second semiconductor unit. Equipped with, The width of the end of the first semiconductor portion on the side of the third semiconductor portion in the second direction intersecting the first direction is defined as the first width. The width of the end portion of the second semiconductor portion on the third semiconductor portion side in the second direction is defined as the second width. If the width of the third semiconductor portion in the second direction is defined as the third width, The third width is greater than the first and second widths. The semiconductor memory device according to claim 7.

9. circuit board and A memory block including a first sub-memory block and a second sub-memory block, arranged in a first direction intersecting the surface of the substrate, With respect to the memory block, a bit line is provided on one side in the first direction, With respect to the memory block, a source line provided on the other side in the first direction, Control circuit for controlling the memory block and Equipped with, The first sub-memory block is, A plurality of first memory cells electrically connected to the bit line and the source line, Multiple first word lines electrically connected to the plurality of first memory cells and Equipped with, The aforementioned second sub-memory block is A plurality of second memory cells electrically connected to the bit line and the source line, Multiple second word lines electrically connected to the plurality of second memory cells and Equipped with, The control circuit, in an erase operation on the memory block, A first determination operation to determine whether at least one of the plurality of second memory cells is in a write state, A second determination operation for determining whether at least one of the plurality of second memory cells is in an erased state, A third determination operation for determining whether at least one of the plurality of first memory cells is in an erased state, A first pre-erase write operation performed when at least one of the plurality of second memory cells is in a write state and at least one is in an erase state, A second pre-erase write operation is performed when at least one of the plurality of first memory cells is in a write state and at least one is in an erase state. Configured to be executable, In the first write operation before erasure, A program voltage is applied to the plurality of second word lines. A non-selective write voltage lower than the program voltage is applied to the plurality of first word lines. In the second write operation before erasure, The program voltage is applied to the plurality of first word lines. The non-selective write voltage is applied to the plurality of second word lines. Semiconductor memory device.

10. The control circuit, in an erase operation on the memory block, The first erase operation performed after the first pre-erase write operation, The second erase operation performed after the second pre-erase write operation, Configured to be executable, In the first erasure operation, An erase voltage is applied to one or both of the bit line and the source line. A selective erase voltage lower than the erase voltage is applied to the plurality of first word lines and the plurality of second word lines. In the second erasure operation, The erase voltage is applied to one or both of the bit line and the source line. The selection and erasure voltage is applied to the plurality of first word lines. A non-selective erase voltage, lower than the erase voltage but higher than the selective erase voltage, is applied to the plurality of second word lines. The semiconductor memory device according to claim 9.

11. The aforementioned control circuit is In the first determination operation and the second determination operation, the system is configured to perform a read-before-erase operation on at least one of the plurality of second memory cells. In the aforementioned read operation before erasure, A read voltage is applied to at least one of the plurality of second word lines. A non-selective read voltage higher than the read voltage is applied to the plurality of first word lines. The semiconductor memory device according to claim 9.

12. The aforementioned control circuit is In the third determination operation, the system is configured to perform a read-before-erase operation on at least one of the plurality of first memory cells. In the aforementioned read operation before erasure, A read voltage is applied to at least one of the plurality of first word lines. A non-selective read voltage higher than the read voltage is applied to the plurality of second word lines. The semiconductor memory device according to claim 9.

13. The aforementioned control circuit is In the first determination operation, the second determination operation, and the third determination operation, the control circuit is configured to be able to access the memory area, The aforementioned storage area holds information about the write status of the first sub-memory block and the second sub-memory block. The semiconductor memory device according to claim 9.

14. The aforementioned control circuit is The command set that instructs the first write operation before erasure, The command set that instructs the second write operation before erasure, The command set that instructs the first erase operation, The command set that instructs the second erase operation and Configured to send The semiconductor memory device according to claim 10.

15. The control circuit is configured to perform a write operation, If the plurality of first memory cells and the plurality of second memory cells are in an erased state, the write operation to the plurality of first memory cells is performed before the write operation to the plurality of second memory cells. The semiconductor memory device according to claim 9.

16. The first sub-memory block is, A plurality of first conductive layers arranged in the first direction, A first semiconductor portion extending in the first direction and facing the plurality of first conductive layers, The plurality of first conductive layers and the first charge storage film provided between the first semiconductor portion Equipped with, The aforementioned second sub-memory block is A plurality of second conductive layers arranged in the first direction, A second semiconductor portion extending in the first direction, facing the plurality of second conductive layers, and electrically connected to the first semiconductor portion, The plurality of second conductive layers and the second charge storage film provided between the second semiconductor portion Equipped with, The plurality of first conductive layers function as the plurality of first word lines, The plurality of second conductive layers function as the plurality of second word lines. The semiconductor memory device according to claim 9.

17. The semiconductor layer comprises the first semiconductor layer extending in the aforementioned direction, The aforementioned semiconductor layer is The first semiconductor section and, The second semiconductor section and, A third semiconductor unit is provided between the first sub-memory block and the second sub-memory block and is connected to the first semiconductor unit and the second semiconductor unit. Equipped with, The width of the end of the first semiconductor portion on the side of the third semiconductor portion in the second direction intersecting the first direction is defined as the first width. The width of the end portion of the second semiconductor portion on the third semiconductor portion side in the second direction is defined as the second width. If the width of the third semiconductor portion in the second direction is defined as the third width, The third width is greater than the first and second widths. The semiconductor memory device according to claim 16.

Images