Memory controller and method for controlling the memory controller

Abstract

This invention provides a memory controller that generates refresh commands based on the priority of access requests, so that the periods for issuing read / write commands for multiple access requests do not overlap, and a method for controlling the memory controller. [Solution] The memory controller includes an access holding circuit that holds access requests including priority for memory, and a refresh control circuit that generates refresh commands specifying one or more banks for memory. The refresh control circuit generates refresh commands such that the period for issuing read / write commands for access requests with a first priority among the access requests held by the access holding circuit does not overlap with the period for issuing read / write commands for access requests with a second priority.

Description

Technical Field

[0001] The present disclosure relates to a memory controller and a method for controlling the memory controller.

Background Art

[0002] As a main memory device of a computer system, DRAM (Dynamic Random Access Memory) is widely adopted. With the increase in speed and functionality of computer systems, the requirements for DRAM access performance have been continuously increasing, and DRAMs that operate at higher speeds have been developed.

[0003] By the way, DRAM is a memory device that requires a refresh (memory retention operation) to continuously hold data. In DRAMs up to the DDR2 standard, a refresh is performed on all banks simultaneously at regular intervals, and memory access during the refresh is prohibited, which has contributed to a decrease in memory access performance.

[0004] In order to suppress the decrease in memory access performance due to refreshing, the LPDDR2 standard added a function to refresh DRAM in units of banks. In addition, the LPDDR4 standard added a function that allows the order of banks to be refreshed to be arbitrarily changed in bank - unit refreshing.

[0005] Patent Document 1 discloses a memory controller that controls the issuance of a refresh request based on attribute information attached to an access request for efficient memory access.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] The refresh cycle is standardized for each DRAM technology and is specified in the manufacturer's chip specifications. Since semiconductor leakage current increases with temperature, the refresh cycle needs to be shortened at high temperatures.

[0008] However, since the overhead of page control before the refresh and the refresh itself remain the same as at room temperature, the period during which read / write commands can be issued is shorter at high temperatures than at room temperature. Also, in bank-level refreshes, the period during which read / write commands can be issued overlaps between banks that are close together in refresh timing. Therefore, if high-priority memory access requests are concentrated in these banks, read / write commands will compete, and the bandwidth required for the memory access requests cannot be secured.

[0009] The purpose of this disclosure is to enable the generation of refresh commands based on the priority of access requests, so that the periods for issuing read / write commands for multiple access requests do not overlap. [Means for solving the problem]

[0010] The memory controller includes an access holding circuit that holds access requests including priority for the memory, and a refresh control circuit that generates refresh commands specifying one or more banks for the memory. The refresh control circuit generates the refresh commands such that the period for issuing read / write commands for access requests with a first priority among the access requests held by the access holding circuit does not overlap with the period for issuing read / write commands for access requests with a second priority. [Effects of the Invention]

[0011] According to this disclosure, based on the priority of access requests, refresh commands can be generated so that the periods for issuing read / write commands for multiple access requests do not overlap. [Brief explanation of the drawing]

[0012] [Figure 1] This is a diagram showing the configuration of the memory controller. [Figure 2] This is a diagram showing the configuration of the access retention circuit entry. [Figure 3] This diagram shows the mapping between memory access request addresses and DRAM addresses. [Figure 4] This is a diagram showing the configuration of the refresh control circuit. [Figure 5] This diagram shows the process of generating the refresh issuance timing. [Figure 6] This is a flowchart for determining the refresh issuance order. [Figure 7] This diagram shows the process for determining the priority of bank pairs to be refreshed. [Figure 8] This diagram shows the period during which read / write commands are issued. [Figure 9] This is a diagram showing the configuration of the refresh control circuit. [Figure 10] This is a flowchart for determining the refresh issuance order. [Modes for carrying out the invention]

[0013] (First embodiment) Figure 1 shows an example configuration of the memory controller 100 in the first embodiment. The memory controller 100 is connected to the DRAM 110 and the initiator 120. The initiator 120 sends a memory access request containing address information and write data to the memory controller 100. Also, if the type of transfer is read, the initiator 120 receives read data from the memory controller 100.

[0014] The memory controller 100 generates a DRAM command based on the memory access request received from the initiator 120 and sends it to the DRAM 110. The memory controller 100 also performs data transfer to the DRAM 110 based on the transmitted DRAM command.

[0015] The DRAM 110 of this embodiment is an example of a memory and has a configuration having four bank groups each having four banks. Also, when receiving a refresh command that designates a bank by (bank group address [0], bank address [1:0]), it will be described as refreshing the corresponding two banks.

[0016] For example, when receiving a refresh command in which (0, 0) is designated by the refresh command, it refreshes the banks indicated by (bank group address, bank address) = (0, 0) and (2, 0). However, this embodiment does not limit the number of bank groups, the number of banks within a bank group, or the number of banks designated by the refresh command, and any DRAM 110 in which there are three or more refresh targets designated by the refresh command may be used.

[0017] The memory controller 100 includes an access holding circuit 101, a read / write control circuit 102, a page control circuit 103, a refresh control circuit 104, a refresh frequency monitoring circuit 105, a bank state management circuit 106, and a command selector 107.

[0018] First, the access holding circuit 101 will be described. The access holding circuit 101 is a buffer that holds a plurality of memory access requests for the DRAM 110. The access holding circuit 101 is composed of m (m >= 2) entries. Here, this embodiment does not depend on the number of m.

[0019] FIG. 2 is a diagram showing a configuration example of the access holding circuit entry 1011 in this embodiment. In this embodiment, there are m access holding circuit entries 1011 shown in FIG. 2 in the access holding circuit 101. As shown in FIG. 2, the access holding circuit entry 1011 holds a memory access having fields of access type, priority, target bank group, target bank, target page, target column, and remaining number of read / write commands.

[0020] The DRAM110 has multiple (e.g., four) bank groups. Each of the multiple bank groups has multiple (e.g., four) banks. Each of the multiple banks is a grouping of multiple pages. Multiple pages cannot be opened within a single bank. Each page has multiple columns of memory cells. The memory cells store data. The DRAM110 can be refreshed on a bank-by-bank basis, and the order in which banks are refreshed can be arbitrarily changed. Refreshing is an operation that periodically replenishes the charge of memory cells to prevent data storage from being lost.

[0021] The access retention circuit 101 converts and retains the memory access request received from the initiator 120 so that it corresponds to each field of the access retention circuit entry 1011. The information stored in each field is as follows:

[0022] (a) Access type field The access type field indicates the access type of the memory access request stored in the entry. WRITE indicates that the memory access request is a write (writing data). READ indicates that the memory access request is a read (reading data).

[0023] (b) Priority field The priority field indicates the priority of the memory access request stored in that entry.

[0024] (c) Target bank group field The target bankgroup field indicates the bankgroup address accessed by the memory access request stored in that entry.

[0025] (d) Target bankfield The target bank field indicates the bank address accessed by the memory access request stored in that entry.

[0026] (e) Target page field The target page field indicates the page address accessed by the memory access request stored in that entry.

[0027] (f) Target column field The target column field indicates the address of the first column accessed by the memory access request stored in that entry.

[0028] (g) Number of remaining read / write commands The "Remaining Read / Write Commands" field indicates the number of remaining DRAM read / write commands to be executed by the memory access requests stored in that entry.

[0029] When a memory access request is stored in the access holding circuit 101, it is stored in the entry following the last of the stored memory access requests. When reading a memory access request from the access holding circuit 101, it can be read from any entry.

[0030] Next, the entry control signal input from the read / write control circuit 102 to the access holding circuit 101 will be explained. The entry control signal consists of an entry number field, a delete field, and an update field. If 1 is set in the delete field, the access holding circuit 101 deletes the entry indicated by the entry number field. If 1 is set in the update field, the access holding circuit 101 updates the target bank group field and target column field of the entry indicated by the entry number field to the bank group address and starting column address of the next read / write command. It also updates the remaining read / write command count field to a value obtained by subtracting 1. The bank group address and starting column address of the next read / write command are calculated based on the entry's address information and the mapping between the memory access request address and the DRAM address shown in Figure 3. The mapping assumes that the DRAM data is 32 bits wide and the burst length of the read / write command is 16, and the next read / write command is issued to a different bank group by toggling the first bit of the bank group address.

[0031] Next, the read / write control circuit 102 will be described. The read / write control circuit 102 can access all memory access requests stored in the access holding circuit 101. The read / write control circuit 102 selects any memory access request from among the memory access requests stored in the access holding circuit 101 for which the page to be accessed is open. Whether or not the page to be accessed by the memory access request is open is determined from the target bank group field, target bank field, and target page field of the access holding circuit entry 1011, and the bank state generated by the bank state management circuit 106. Then, the read / write control circuit 102 generates read commands and write commands from the selected memory access requests and outputs them to the command selector 107.

[0032] Next, the procedure for the read / write control circuit 102 to generate an entry control signal will be explained. When the read / write control circuit 102 issues the last read or write command executed by a memory access request, the processing of the corresponding memory access request is completed. Therefore, the read / write control circuit 102 generates an entry control signal to delete the corresponding entry from the access holding circuit 101. On the other hand, if the read / write control circuit 102 issues a read or write command that is not the last, it generates an entry control signal to update the corresponding entry in the access holding circuit 101. However, if the last read or write command is issued, it is not necessary to update the corresponding entry. Whether the issued read or write command is the last is determined by checking if the remaining read / write command count field in the access holding circuit entry 1011 is 1.

[0033] Next, the page control circuit 103 will be described. The page control circuit 103 can access all memory access requests stored by the access holding circuit 101. The inputs to the page control circuit 103 are the memory access requests stored by the access holding circuit 101, the precharge issuance requests output by the refresh control circuit 104, and the bank status output by the bank status management circuit 106. Based on the memory access requests and bank status stored by the access holding circuit 101, the page control circuit 103 generates page control commands such as active commands and precharge commands and outputs them to the command selector 107. Precharge commands are generated not only based on memory access requests and bank status, but also based on precharge issuance requests from the refresh control circuit 104.

[0034] Next, the refresh control circuit 104 will be described. The refresh control circuit 104 can access all memory access requests stored in the access holding circuit 101. The inputs to the refresh control circuit 104 are the memory access requests stored in the access holding circuit 101, the refresh cycle output by the refresh frequency monitoring circuit 105, and the bank state output by the bank state management circuit 106. The refresh control circuit 104 generates refresh requests based on the refresh cycle and generates multiple refresh commands to refresh all banks of the DRAM 110 for a single refresh request. The refresh control circuit 104 measures the timing of the refresh command issuance and outputs a refresh command specifying the bank to the command selector 107 at the issuance timing. Also, when the timing of the refresh command issuance approaches, the refresh control circuit 104 outputs a precharge issuance request to the page control circuit 103 to close the page, according to the bank state of the bank specified in the refresh command.

[0035] Next, the refresh frequency monitoring circuit 105 will be described. The refresh frequency monitoring circuit 105 periodically generates a mode register read command and outputs it to the command selector 107 in order to monitor the mode register in which the refresh frequency requested by the DRAM 110 is stored. The refresh frequency monitoring circuit 105 outputs the refresh period that realizes the refresh frequency read by the mode register read to the refresh control circuit 104. In this embodiment, the refresh frequency monitoring circuit 105 will be described as outputting a refresh period of 3.9 μs when the DRAM 110 is at room temperature (below 85°C) and 487.5 ns when it is at high temperature (85°C or higher). However, this embodiment is not limited to this, and the refresh frequency requested by the DRAM 110 may be more finely divided.

[0036] Next, the bank state management circuit 106 will be described. The bank state management circuit 106 updates the bank state based on the command issuance status input from the command selector 107. The command issuance status consists of the type of command issued to the DRAM 110, and the bank group, bank, and page to which the command was issued. The bank state includes whether a page is open for each bank that makes up the DRAM 110, and the address of the open page.

[0037] Finally, the command selector 107 will be explained. The command selector 107 selects one command from the commands input from the read / write control circuit 102, page control circuit 103, refresh control circuit 104, and refresh frequency monitoring circuit 105 and issues it to the DRAM 110. The command selector 107 also outputs the command type of the command issued to the DRAM 110, as well as the command issuance status consisting of the bank group, bank, and page to which the command was issued, to the bank status management circuit 106.

[0038] Figure 4 shows an example of the configuration of the refresh control circuit 104 in this embodiment. The refresh control circuit 104 includes a refresh request generation circuit 1041, a refresh issuance timing generation circuit 1042, a refresh issuance order determination circuit 1043, a refresh command generation circuit 1044, and a precharge issuance request generation circuit 1045.

[0039] The refresh request generation circuit 1041 generates a refresh request based on the refresh cycle input from the refresh frequency monitoring circuit 105.

[0040] The refresh issuance timing generation circuit 1042 generates the issuance timing for a refresh command corresponding to the refresh request generated by the refresh request generation circuit 1041. Figure 5 shows the operation of refresh issuance timing generation in this embodiment. The refresh issuance timing generation circuit 1042 determines whether the DRAM 110 is at room temperature based on the refresh cycle input from the refresh frequency monitoring circuit 105. Whether it is at room temperature is determined by whether the refresh cycle is less than a threshold. If it is determined that the DRAM 110 is at room temperature, as shown in Figure 5(A), the refresh command issuance timing is generated 8 times at intervals of (refresh cycle ÷ 8) from the timing when the refresh request is generated. If it is determined that the DRAM 110 is at a high temperature, as shown in Figure 5(B), the refresh command issuance timing is generated 8 times at intervals of tref2ref from the timing when the refresh request is generated. tref2ref is the timing constraint for issuing a refresh command specifying a bank in the shortest possible time. Furthermore, the refresh issuance timing generation circuit 1042 generates a precharge issuance request generation timing such that the page closing of the bank to be refreshed is completed at the time the refresh command is output to the command selector 107. This precharge issuance request generation timing is such that the issuance of the precharge command does not impose any constraints on the issuance of the refresh command.

[0041] The refresh issuance order determination circuit 1043 determines the order in which refresh commands corresponding to the refresh requests generated by the refresh request generation circuit 1041 are issued.

[0042] Figure 6 is a flowchart for determining the refresh order in this embodiment, and the control method of the refresh order determination circuit 1043 will be explained in more detail using this flowchart.

[0043] In step S100, the refresh order determination circuit 1043 determines whether the refresh request generation circuit 1041 has generated a refresh request. If no refresh request has been generated, the refresh order determination circuit 1043 returns to step S100 and waits until a refresh request is generated. If a refresh request has been generated, the circuit proceeds to step S101.

[0044] In step S101, the refresh order determination circuit 1043 determines the priority of the bank pairs to be refreshed based on the priority of memory access requests to those bank pairs. A bank pair to be refreshed is one or more banks that are refreshed simultaneously with a single refresh command. In this embodiment, there are eight bank pairs to be refreshed, specified by (bank group address[0], bank address). Each bank pair to be refreshed consists of two banks corresponding to (bank group address[0], bank address).

[0045] Figure 7 shows the operation for determining the priority of the bank pairs to be refreshed in this embodiment. The refresh issuance order determination circuit 1043 calculates the score of the bank pairs to be refreshed based on the state of the access holding circuit 101 when a refresh request is generated. The score is calculated by setting the [N]th bit of the score to 1 if there is a memory access request with priority N for the bank pairs to be refreshed, and setting the [N]th bit of the score to 0 if there is no memory access request with priority N.

[0046] For example, the score for the refresh target bank pair (1,2) in Figure 7 is 0101 because there are memory access requests with priorities of 2 and 0. The refresh order determination circuit 1043 assigns higher priorities to refresh target bank pairs in order from the one with the highest score. If the scores are the same, the refresh order determination circuit 1043 assigns a higher priority to the refresh target bank pair with a smaller (bank group address [0] × number of banks in the bank group + bank address).

[0047] In step S102, the refresh order determination circuit 1043 determines whether the refresh command issuance order for all refresh target bank pairs has been determined. The refresh command issuance order is determined in step S105 or S106, described later. If the issuance order for all refresh target bank pairs has been determined, the refresh order determination circuit 1043 returns to step S100 and waits until the next refresh request is generated. If the issuance order for all refresh target bank pairs has not been determined, the circuit proceeds to step S103.

[0048] In step S103, the refresh command order determination circuit 1043 selects the refresh target bank pair with the highest priority among the refresh command target bank pairs for which the refresh command order has not yet been determined.

[0049] In step S104, the refresh order determination circuit 1043 determines whether the DRAM 110 is at room temperature based on the refresh cycle requested by the DRAM 110, which is input from the refresh frequency monitoring circuit 105. Whether it is at room temperature is determined by whether the refresh cycle is less than a second threshold. If the refresh cycle is not equal to or greater than the second threshold, the DRAM 110 is considered to be at room temperature, and the process proceeds to step S105. If the refresh cycle is equal to or greater than the second threshold, the DRAM 110 is considered to be at a high temperature, and the process proceeds to step S106.

[0050] In step S105, the refresh command issuance order determination circuit 1043 determines the refresh command issuance order for the refresh target bank pair selected in step S103 to be the latest refresh command issuance order among the refresh command issuance orders that have not yet been determined. Then, the process returns to step S102.

[0051] In step S106, the refresh command issuance order determination circuit 1043 determines the refresh command issuance order according to the priority of the refresh target bank pair selected in step S103.

[0052] If the refresh target bank pair selected in step S103 has the highest priority, the refresh command issuance order determination circuit 1043 determines the refresh command issuance order for the refresh target bank pair selected in step S103 to be the latest refresh command issuance order among the refresh command issuance orders that have not yet been determined.

[0053] If the refresh target bank pair selected in step S103 does not have the highest priority, the refresh command issuance order determination circuit 1043 determines the refresh command issuance order for the refresh target bank pair selected in step S103 so that the read / write command issuance period of the refresh target bank pair selected in step S103 does not overlap with the read / write command issuance period of a refresh target bank pair with a higher priority than the selected refresh target bank pair. In other words, the refresh command issuance order determination circuit 1043 determines the refresh command issuance order so that the read / write command issuance period of a memory access request with the first priority among the memory access requests held in the access holding circuit 101 does not overlap with the read / write command issuance period of a memory access request with the second priority. Specifically, the refresh command issuance order determination circuit 1043 determines the refresh command issuance order so that the period during which the read / write command issuance period of a memory access request with the first priority among the memory access requests held in the access holding circuit 101 does not overlap with the read / write command issuance period of a memory access request with the second priority is greater than or equal to a first threshold. The second priority is the same as or higher than the first priority. Then, return to step S102.

[0054] Figure 8 shows the read / write command issuance period in step S106 of Figure 7. The read / write command issuance period is the period during which read / write commands can be issued to the bank pair to be refreshed, and it varies depending on the order in which the refresh commands are issued.

[0055] First, as shown in Figure 8(A), the period is calculated by subtracting the time required for page closing before issuing a refresh command (p1) and the time after issuing a refresh until the refresh is complete and a read / write command can be issued (p2) from the refresh cycle.

[0056] Next, as shown in Figure 8(B), the read / write command issuance period is the period calculated in Figure 8(A) minus the tRFC period from the most recent refresh command issued to the same bank pair to be refreshed. tRFC is a timing constraint from the issuance of a refresh command until the refresh is completed.

[0057] The refresh command issuance order determination circuit 1043 calculates the read / write command issuance period based on the refresh cycle, the refresh command issuance interval, the penalties incurred before and after the issuance of refresh commands, and / or the issuance order of refresh commands specifying banks.

[0058] Furthermore, the read / write command issuance period may be calculated more accurately by reflecting the total number of read / write commands in Figure 7 in the read / write command issuance period calculated in Figure 8(B), as shown in Figure 8(C), to represent the actual period during which read / write commands are issued. For example, when determining the refresh command issuance order for the refresh target bank pair (1,2) in Figure 7, the read / write command period for each calculated in Figure 8(B) is reduced to the period required to issue 20 read / write commands. After calculating the read / write command issuance period, a refresh command issuance order that satisfies the following two conditions is determined from among the refresh command issuance orders that have not yet been decided.

[0059] (a) There must be a read / write command issuance period (not 0). (i) The read / write command issuance period does not overlap with the read / write command issuance period of a refresh target bank pair with a higher priority.

[0060] Here, condition (i) is that there is a threshold or longer period during which the read / write command issuance period does not overlap with the read / write command issuance period of the refresh target bank pair with a higher priority. In this case, the refresh command issuance order that satisfies both conditions and has the longest period of non-overlapping periods is selected. If there are multiple refresh command issuance orders that satisfy both conditions, or if there are no refresh command issuance orders that satisfy both conditions, the earliest refresh command issuance order is selected.

[0061] The refresh command generation circuit 1044 generates a refresh command for the DRAM 110 according to the refresh command issuance timing of the refresh issuance timing generation circuit 1042 and the refresh command issuance order determined by the refresh issuance order determination circuit 1043. The banks specified in the refresh command are the refresh target bank pairs output by the refresh issuance order determination circuit 1043, and the refresh command generation circuit 1044 outputs the generated refresh command to the command selector 107. The refresh target bank pair consists of one or more banks.

[0062] The precharge request generation circuit 1045 determines whether the refresh target bank pair output by the refresh order determination circuit 1043 has an open page, according to the precharge request generation timing of the refresh timing generation circuit 1042. Only if the refresh target bank pair has an open page, the precharge request generation circuit 1045 outputs a precharge request for the refresh target bank pair to the page control circuit 103.

[0063] As described above, by specifying a bank to refresh so that read / write commands for high-priority memory access requests do not conflict, bandwidth for high-priority memory access requests can be secured even at high temperatures.

[0064] (Second embodiment) The configuration of the memory controller 100 in the second embodiment is the same as the configuration of the memory controller 100 in Figure 1. The second embodiment is a different configuration of the refresh control circuit 104 in the first embodiment, and is an embodiment in which the bank to be specified in the refresh command is determined at the timing of issuing the refresh command. Everything in the second embodiment that is not mentioned is the same as in the first embodiment.

[0065] Figure 9 shows an example of the configuration of the refresh control circuit 104 in the second embodiment. The refresh control circuit 104 includes a refresh request generation circuit 1041, a refresh issuance timing generation circuit 1042, a refresh issuance order determination circuit 1046, a refresh command generation circuit 1044, and a precharge issuance request generation circuit 1045.

[0066] Figure 9 shows the same result as in Figure 4, but with a refresh issuance order determination circuit 1046 instead of the refresh issuance order determination circuit 1043.

[0067] The refresh issuance order determination circuit 1046 determines the bank to be specified in the refresh command according to the precharge issuance request generation timing generated by the refresh issuance timing generation circuit 1042.

[0068] Figure 10 is a flowchart for determining the refresh order in the second embodiment, and the control method of the refresh order determination circuit 1046 will be explained in more detail using this flowchart.

[0069] In step S200, the refresh issuance order determination circuit 1046 determines whether the refresh request generation circuit 1041 has generated a refresh request. If a refresh request has been generated, the process proceeds to step S201; otherwise, the process proceeds to step S202.

[0070] In step S201, the refresh order determination circuit 1046 initializes the status of information such as the refresh target bank pair for which the refresh command was issued. Then, the process returns to step S200.

[0071] In step S202, the refresh issuance order determination circuit 1046 determines whether or not it is the timing for generating a precharge issuance request. If it is not the timing for generating a precharge issuance request, the process returns to step S200. If it is the timing for generating a precharge issuance request, the process proceeds to step S203.

[0072] In step S203, the refresh order determination circuit 1046 determines the priority of refresh target bank pairs for which a refresh command has not been issued, based on the priority of memory access requests. The priority is determined in the same manner as in the first embodiment, based on the state of the access holding circuit 101 at the precharge request issuance timing.

[0073] In step S204, the refresh order determination circuit 1046 determines whether the DRAM 110 is at room temperature based on the refresh cycle requested by the DRAM 110, which is input from the refresh frequency monitoring circuit 105. Whether it is at room temperature is determined by whether the refresh cycle is less than a second threshold. If the refresh cycle is not equal to or greater than the second threshold, the DRAM 110 is considered to be at room temperature, and the process proceeds to step S205. If the refresh cycle is equal to or greater than the second threshold, the DRAM 110 is considered to be at a high temperature, and the process proceeds to step S206.

[0074] In step S205, the refresh order determination circuit 1046 determines the bank pair with the lowest priority among the refresh target bank pairs that satisfy the following two conditions, and selects this bank to be specified in the refresh command generated by the refresh command generation circuit 1044. Then, the process returns to step S200.

[0075] (u) Not issuing (generating) a refresh command. (e) At the time of issuing (generating) the refresh command, tRFC (a specified period) must have elapsed since the last refresh command issued (generated) for the same bank pair to be refreshed.

[0076] In step S206, the refresh order determination circuit 1046 determines whether the number of refresh target bank pairs (sets) for which a refresh command has not been issued (generated) is two or more. If the number of refresh target bank pairs (sets) for which a refresh command has not been issued (generated) is two or more, the process proceeds to step S207. If the number of refresh target bank pairs (sets) for which a refresh command has not been issued (generated) is one, the process proceeds to step S208.

[0077] In step S207, the refresh order determination circuit 1046 determines the bank pair with the highest priority from among the refresh target bank pairs that satisfy the following three conditions, and designates it as the bank to be specified in the refresh command generated by the refresh command generation circuit 1044. Then, the process returns to step S200.

[0078] (o) The refresh command has not been issued (generated). (k) At the time of issuing (generating) the refresh command, tRFC (a specified period) has elapsed since the last refresh command issued (generated) for the same bank pair to be refreshed. (i) It must be the second or lower priority.

[0079] In step S208, the remaining bank pairs to be refreshed that have not yet been issued (generated) by the refresh command generation circuit 1044 are determined to be the banks specified in the refresh command generated by the refresh command generation circuit. Then, the process returns to step S200.

[0080] The refresh command generation circuit 1044 generates a refresh command specifying the bank determined by the refresh issuance order determination circuit 1046.

[0081] As described above, by specifying a bank to refresh so that read / write commands for high-priority memory access requests do not conflict, bandwidth for high-priority memory access requests can be secured even at high temperatures.

[0082] (Other embodiments) This disclosure can also be implemented by supplying a program that implements one or more of the functions of the embodiments described above to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be implemented by a circuit (e.g., an ASIC) that implements one or more functions.

[0083] Furthermore, the embodiments described above are merely examples illustrating how to implement this disclosure, and they should not be interpreted as limiting the technical scope of this disclosure. In other words, this disclosure can be implemented in various ways without departing from its technical concept or its main features.

[0084] This embodiment includes the following configurations and methods. (Composition 1) An access holding circuit that holds access requests including priority for memory, The memory includes a refresh control circuit that generates a refresh command specifying one or more banks, The refresh control circuit generates the refresh command such that the period during which read / write commands are issued for access requests with a first priority among the access requests held by the access holding circuit does not overlap with the period during which read / write commands are issued for access requests with a second priority. (Configuration 2) The memory controller according to configuration 1, characterized in that the second priority is the same as or higher than the first priority. (Composition 3) The memory controller according to configuration 1 or 2, characterized in that the refresh control circuit calculates the period for issuing read / write commands based on the refresh cycle, the interval between issuing refresh commands, the penalties incurred before and after issuing refresh commands, or the order in which refresh commands specifying banks are issued. (Composition 4) The memory controller according to configuration 3, further characterized in that the refresh control circuit calculates the period for issuing the read / write commands based on the total number of read / write commands. (Composition 5) The memory controller according to any one of configurations 1 to 4, characterized in that the refresh control circuit determines the bank specified by the refresh command such that the period during which read / write commands are issued for access requests with a first priority among the access requests held by the access holding circuit does not overlap with the period during which read / write commands are issued for access requests with a second priority is equal to or greater than a first threshold. (Composition 6) The memory controller according to any one of configurations 1 to 5, characterized in that the refresh control circuit generates the refresh command such that, when the refresh cycle requested by the memory is equal to or greater than a second threshold, the period during which read / write commands are issued for access requests with a first priority among the access requests held by the access holding circuit does not overlap with the period during which read / write commands are issued for access requests with a second priority. (Composition 7) The memory controller according to any one of configurations 1 to 6, characterized in that the refresh control circuit determines the order in which refresh commands are issued for a plurality of banks and generates the refresh commands in the determined order. (Composition 8) The refresh control circuit is If the refresh cycle requested by the memory is greater than or equal to the second threshold, the order in which refresh commands are issued for the multiple banks is determined such that the period for issuing read / write commands for the first priority access requests held by the access holding circuit does not overlap with the period for issuing read / write commands for the second priority access requests. The memory controller according to configuration 7, characterized in that, if the refresh cycle requested by the memory is not equal to or greater than a second threshold, the order in which refresh commands for the plurality of banks are issued is determined according to the priority of the access requests held in the access holding circuit. (Composition 9) The memory controller according to any one of configurations 1 to 6, characterized in that the refresh control circuit determines the bank to be specified in the refresh command and generates a refresh command specifying the determined bank. (Composition 10) The memory controller according to configuration 9, characterized in that, when the refresh control circuit is issued at a time when the issuance of a precharge command does not restrict the issuance of a refresh command, it determines the bank to be specified in the refresh command from among banks for which a refresh command has not been generated, according to the priority of the access request. (Composition 11) The refresh control circuit is Based on the priority of the aforementioned access requests, the priority of the banks to be refreshed is determined. If there are two or more pairs of banks to be refreshed for which the aforementioned refresh command has not been generated, the bank with the highest priority among the banks to be refreshed for which the aforementioned refresh command has not been generated, for which a predetermined period has elapsed since the most recently generated refresh command, and whose priority is second or lower, is determined to be the bank to be specified in the aforementioned refresh command. The memory controller according to configuration 9 or 10, characterized in that, if there is one set of banks to be refreshed for which no refresh command has been generated, the set of banks to be refreshed for which no refresh command has been generated is determined to be the banks to be specified in the refresh command. (Composition 12) The refresh control circuit is If the issuance of a precharge command does not restrict the issuance of a refresh command, the priority of the banks to be refreshed is determined based on the priority of the access requests. If the refresh cycle requested by the memory is equal to or greater than the second threshold, and there are two or more pairs of refresh target banks for which no refresh command has been generated, then the refresh target bank with the highest priority among the refresh target banks for which no refresh command has been generated, for which a predetermined period has elapsed since the most recently generated refresh command, and whose priority is second or lower, is determined to be the bank specified in the refresh command. If the refresh cycle requested by the memory is greater than or equal to the second threshold, and there is one set of refresh target banks for which no refresh command has been generated, then the set of refresh target banks for which no refresh command has been generated is determined to be the bank specified in the refresh command. The memory controller according to any one of configurations 9 to 11, characterized in that, if the refresh period requested by the memory is not equal to or greater than a second threshold, the refresh target bank with the lowest priority among the refresh target banks for which no refresh command has been generated and for which a predetermined period has elapsed since the most recently generated refresh command is determined as the bank to be specified in the refresh command. (Method 1) The access holding circuit includes an access holding step in which it holds access requests, including priority for memory, The refresh control circuit includes a refresh control step of generating a refresh command that specifies one or more banks for the memory, A memory controller control method characterized in that, in the refresh control step, the refresh command is generated such that the period for issuing read / write commands for access requests with a first priority among the access requests held in the access holding circuit does not overlap with the period for issuing read / write commands for access requests with a second priority. [Explanation of Symbols]

[0085] 100: Memory controller, 101: Access hold circuit, 102: Read / write control circuit, 103: Page control circuit, 104: Refresh control circuit, 105: Refresh frequency monitoring circuit, 106: Bank state management circuit, 107: Command selector, 110: DRAM, 120: Initiator, 1011: Access hold circuit entry, 1041: Refresh request generation circuit, 1042: Refresh issue timing generation circuit, 1043: Refresh issue order determination circuit, 1044: Refresh command generation circuit, 1045: Precharge issue request generation circuit, 1046: Refresh issue order determination circuit

Claims

1. An access holding circuit that holds access requests including priority for memory, The memory includes a refresh control circuit that generates a refresh command specifying one or more banks, The refresh control circuit generates the refresh command such that the period for issuing read / write commands for access requests with a first priority among the access requests held by the access holding circuit does not overlap with the period for issuing read / write commands for access requests with a second priority.

2. The memory controller according to claim 1, characterized in that the second priority is the same as or higher than the first priority.

3. The memory controller according to claim 1, characterized in that the refresh control circuit calculates the period for issuing read / write commands based on the refresh cycle, the interval between issuing refresh commands, penalties incurred before and after issuing refresh commands, or the order in which refresh commands specifying banks are issued.

4. The memory controller according to claim 3, wherein the refresh control circuit further calculates the period for issuing the read / write commands based on the total number of read / write commands.

5. The memory controller according to claim 1, characterized in that the refresh control circuit determines the bank specified by the refresh command such that the period during which read / write commands are issued for access requests having a first priority among the access requests held by the access holding circuit does not overlap with the period during which read / write commands are issued for access requests having a second priority, and this period is greater than or equal to a first threshold.

6. The memory controller according to claim 1, characterized in that the refresh control circuit generates the refresh command such that, when the refresh cycle requested by the memory is equal to or greater than a second threshold, the period during which read / write commands are issued for access requests with a first priority among the access requests held by the access holding circuit does not overlap with the period during which read / write commands are issued for access requests with a second priority.

7. The memory controller according to claim 1, characterized in that the refresh control circuit determines the order in which refresh commands are issued for a plurality of banks and generates the refresh commands in the determined order.

8. The refresh control circuit is If the refresh cycle requested by the memory is greater than or equal to the second threshold, the order in which refresh commands are issued for the multiple banks is determined such that the period for issuing read / write commands for the first priority access requests held by the access holding circuit does not overlap with the period for issuing read / write commands for the second priority access requests. The memory controller according to claim 7, characterized in that, if the refresh cycle requested by the memory is not equal to or greater than a second threshold, the order in which refresh commands for the plurality of banks are issued is determined according to the priority of the access requests held in the access holding circuit.

9. The memory controller according to claim 1, characterized in that the refresh control circuit determines the bank to be specified in the refresh command and generates a refresh command specifying the determined bank.

10. The memory controller according to claim 9, characterized in that, when the refresh control circuit is not constrained by the issuance of a precharge command, it determines the bank to be specified in the refresh command from among banks for which a refresh command has not been generated, according to the priority of the access request.

11. The refresh control circuit is Based on the priority of the aforementioned access requests, the priority of the banks to be refreshed is determined. If there are two or more pairs of refresh target banks for which the aforementioned refresh command has not been generated, the refresh target bank with the highest priority among the refresh target banks for which the aforementioned refresh command has not been generated, for which a predetermined period has elapsed since the most recently generated refresh command, and whose priority is second or lower, is determined to be the bank specified in the refresh command. The memory controller according to claim 9, characterized in that, if there is one set of banks to be refreshed for which no refresh command has been generated, the set of banks to be refreshed for which no refresh command has been generated is determined to be the banks to be specified in the refresh command.

12. The refresh control circuit is If the issuance of a precharge command does not restrict the issuance of a refresh command, the priority of the banks to be refreshed is determined based on the priority of the access requests. If the refresh cycle requested by the memory is equal to or greater than the second threshold, and there are two or more pairs of refresh target banks for which no refresh command has been generated, then the refresh target bank with the highest priority among the refresh target banks for which no refresh command has been generated, for which a predetermined period has elapsed since the most recently generated refresh command, and whose priority is second or lower, is determined to be the bank specified in the refresh command. If the refresh cycle requested by the memory is equal to or greater than the second threshold, and there is one set of refresh target banks for which no refresh command has been generated, then the set of refresh target banks for which no refresh command has been generated is determined to be the bank specified in the refresh command. The memory controller according to claim 9, characterized in that, if the refresh period requested by the memory is not equal to or greater than a second threshold, the memory controller determines the bank with the lowest priority among the refresh target banks for which a refresh command has not yet been generated and for which a predetermined period has elapsed since the most recently generated refresh command was issued, as the bank to be specified in the refresh command.

13. The access holding circuit includes an access holding step in which it holds access requests, including priority for memory, The refresh control circuit includes a refresh control step of generating a refresh command that specifies one or more banks for the memory, A memory controller control method characterized in that, in the refresh control step, the refresh command is generated such that the period for issuing read / write commands for access requests with a first priority among the access requests held in the access holding circuit does not overlap with the period for issuing read / write commands for access requests with a second priority.

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