Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present invention provides a semiconductor device that can maximize the height of its side electrodes, and a method for manufacturing such a semiconductor device. [Solution] One embodiment of the semiconductor device 1 comprises a first frame 30, a second frame 20, a first semiconductor element 10, wires 40, and a package member 50. The second frame is positioned opposite the first frame in a first direction X and has a stepped portion 25 at the end of its upper surface on the first frame side. The first semiconductor element is positioned on the bottom surface 25a of the stepped portion. The wires electrically connect the first semiconductor element and the first frame. The package member covers a portion of each of the first and second frames and seals the first semiconductor element and the wires. The lower surface S5 of the first frame and the side surface S6 of the first frame in the first direction are exposed from the package member. The lower surface S1 of the second frame and the side surface S2 of the second frame in the first direction are exposed from the package member.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] A semiconductor device including a lead frame on which a semiconductor element is mounted is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor device capable of maximizing the height of a side electrode and a method for manufacturing a semiconductor device.

Means for Solving the Problems

[0005] The semiconductor device according to this embodiment comprises a first frame, a second frame, a first semiconductor element, wires, and a package member. The second frame is positioned opposite the first frame in a first direction and has a stepped portion at the end of its upper surface that faces the first frame. The first semiconductor element is positioned on the bottom surface of the stepped portion of the second frame. The wires electrically connect the first semiconductor element and the first frame. The package member covers a portion of each of the first and second frames and seals the first semiconductor element and the wires. The lower surface of the first frame and the first side surface of the first frame that is farther from the second frame in the first direction are exposed from the package member. The lower surface of the second frame and the second side surface of the second frame that is farther from the first frame in the first direction are exposed from the package member. [Brief explanation of the drawing]

[0006] [Figure 1] A perspective view showing an example of the external shape of a semiconductor device according to the first embodiment. [Figure 2] A perspective view showing an example of the external shape of a semiconductor device according to the first embodiment. [Figure 3] A perspective view showing an example of the structure of a semiconductor device according to the first embodiment. [Figure 4] A plan view showing an example of the structure of a semiconductor device according to the first embodiment. [Figure 5] A plan view showing an example of the structure of a semiconductor device according to the first embodiment. [Figure 6] A cross-sectional view showing an example of the structure of a semiconductor device according to the first embodiment. [Figure 7] A cross-sectional view showing the structure of an example of a semiconductor device implementation according to the first embodiment. [Figure 8] A flowchart showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] A diagram showing the process in the manufacturing method of a semiconductor device according to the first embodiment. [Figure 10] A diagram showing the process in the manufacturing method of a semiconductor device according to the first embodiment. [Figure 11]A diagram showing the steps in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 12] A diagram showing the steps in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 13] A diagram showing the steps in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 14] A diagram showing the steps in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 15] A diagram showing the steps in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 16] A perspective view showing an example of the structure of the semiconductor device according to the second embodiment. [Figure 17] A plan view showing an example of the structure of the semiconductor device according to the second embodiment. [Figure 18] A plan view showing an example of the structure of the semiconductor device according to the second embodiment. [Figure 19] A flowchart showing an example of the manufacturing method of the semiconductor device according to the second embodiment. [Figure 20] A plan view showing an example of the structure of the semiconductor device according to the third embodiment. [Figure 21] A plan view showing an example of the structure of the semiconductor device according to the third embodiment. [Figure 22] A cross-sectional view showing an example of the structure of the semiconductor device according to the third embodiment. [Figure 23] A plan view showing an example of the structure of the semiconductor device according to the fourth embodiment. [Figure 24] A plan view showing an example of the structure of the semiconductor device according to the fourth embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. The dimensions and ratios in the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals, and repeated descriptions may be omitted. When particularly distinguishing between elements having similar configurations, different characters or numbers may be added to the end of the same reference numeral. Also, all descriptions of an embodiment apply as descriptions of another embodiment unless explicitly or implicitly excluded.

[0008] 1. First Embodiment A semiconductor device according to the first embodiment will be described. Hereinafter, a semiconductor device having a Wettable Flank (WF) structure will be described as an example. The semiconductor device according to this embodiment is applied to, for example, an in-vehicle semiconductor package.

[0009] 1.1 Structure of the Semiconductor Device First, the structure of the semiconductor device will be described using FIGS. 1 to 6. The semiconductor device 1 includes a semiconductor element, a lead frame, and bonding wires, and has a package structure in which the semiconductor element and the bonding wires are sealed with a package member.

[0010] FIGS. 1 and 2 are perspective views showing an example of the outer shape of the semiconductor device 1. FIG. 1 shows the structure of the semiconductor device 1 when viewed from the upper surface side, and FIG. 2 shows the structure of the semiconductor device 1 when viewed from the lower surface side.

[0011] As shown in FIGS. 1 and 2, the semiconductor device 1 includes lead frames 20 and 30, and a package member 50.

[0012] The lead frame 20 has surfaces exposed from the package member 50, namely a first surface (bottom surface) S1, a second surface (side surface) S2, a third surface S3, and a fourth surface S4. The first surface S1 is in contact with the second surface S2. The second surface S2 has a height H1. The height H1 is, for example, 150 μm or more and 200 μm or less. The third surface S3 is opposite the fourth surface S4. The first surface S1 and the second surface S2 are terminals (electrodes) of the lead frame 20. The first surface S1 and the second surface S2 function as external connection terminals that connect to the outside. The third surface S3 and the fourth surface S4 are suspension pins. The suspension pins are connecting parts that connect the part formed as the lead frame 20 and the part formed as the lead frame 30 when the lead frames 20 and 30 are in the state of lead frame substrate during manufacturing. During manufacturing, the lead frame 20 is separated from the lead frame substrate by dicing, which will be described later. The faces cut by dicing the suspension pin are the third face S3 and the fourth face S4.

[0013] The lead frame 30 has surfaces exposed from the package member 50, namely the fifth surface (bottom surface) S5, the sixth surface (side surface) S6, the seventh surface S7, and the eighth surface S8. The fifth surface S5 is in contact with the sixth surface S6. The sixth surface S6 has a height H2. The height H2 is approximately the same as the height H1. The height H2 is, for example, 150 μm or more and 200 μm or less. The seventh surface S7 faces the eighth surface S8. The fifth surface S5 and the sixth surface S6 are terminals (electrodes) of the lead frame 30. The fifth surface S5 and the sixth surface S6 function as external connection terminals that connect to the outside. The seventh surface S7 and the eighth surface S8 are suspension pins. During manufacturing, the lead frame 30 is separated from the lead frame substrate by dicing. The surfaces cut by dicing the suspension pins are the seventh surface S7 and the eighth surface S8.

[0014] In the following, the height H1 of the second face S2 and the height H2 of the sixth face S6 will also be referred to as the "WF length".

[0015] The lower surface of the semiconductor device 1 is the surface on which the terminals of the lead frame 20 (first surface S1) and the terminals of the lead frame 30 (fifth surface S5) are exposed from the package member 50, and is the surface on which the semiconductor device 1 is mounted on the main board, the so-called mounting surface of the semiconductor device 1.

[0016] In the following explanation, the XYZ Cartesian coordinate system is used. The X direction is parallel to the surface of the lead frame 20 and corresponds, for example, to the direction from the lead frame 20 toward the lead frame 30. The Y direction is parallel to the surface of the lead frame 20 and corresponds, for example, to the direction from the third surface S3 toward the fourth surface S4 of the lead frame 20. The Z direction is perpendicular to the surface of the lead frame 20, i.e., the up and down direction. Furthermore, the description "up" and related terms indicate a larger coordinate position on the Z axis, and the description "down" and related terms indicate a smaller coordinate position on the Z axis.

[0017] Figure 3 is a perspective view showing an example of the structure of the semiconductor device 1. Figure 3 shows the structure of the semiconductor device 1 as seen from the top side, through the package member 50, as in Figure 1. Figures 4 and 5 are plan views showing an example of the structure of the semiconductor device 1. Figure 4 shows the structure of the semiconductor device 1 as seen from the top side, through the package member 50, as in Figure 1. Figure 5 shows the structure of the semiconductor device 1 as seen from the bottom side, through the package member 50, as in Figure 2.

[0018] As shown in Figures 3 to 5, the semiconductor device 1 includes a semiconductor element 10, lead frames 20 and 30, and bonding wires 40.

[0019] The semiconductor device 10 is, for example, a diode, a field-effect transistor, a bipolar transistor, or an IGBT (Insulated Gate Bipolar Transistor). The following explanation will use the case where the semiconductor device 10 is a diode as an example.

[0020] The semiconductor element 10 is, for example, a semiconductor chip (or bare chip, die). The semiconductor element 10 includes an element portion 11 and pads (or nodes, terminals) 12.

[0021] The element portion 11 includes, for example, a semiconductor layer on which a diode is formed. The semiconductor layer is, for example, silicon, silicon carbide, silicon germanium, gallium nitride, or gallium arsenide.

[0022] The pad 12 is provided on the upper surface of the element portion 11. The pad 12 is electrically connected to the anode (not shown) of the semiconductor element 10 via a conductive member (not shown) formed by curing a conductive paste, for example. The pad 12 includes a metal layer such as aluminum or copper. Depending on the internal configuration of the element portion 11, the pad 12 may also be electrically connected to the cathode of the semiconductor element 10.

[0023] The lead frame 20 includes a base portion 21 and protrusions 22, 23a, 23b, 24a, and 24b.

[0024] The base portion 21 has, for example, a roughly rectangular parallelepiped shape and a portion of its upper surface that is recessed (hereinafter referred to as the "step portion 25"). That is, the base portion 21 includes the step portion 25 on its upper surface.

[0025] Each of the protrusions 22, 23a, 23b, 24a, and 24b has, for example, a roughly rectangular parallelepiped shape. Each of the protrusions 22, 23a, 23b, 24a, and 24b is a portion that protrudes from the base 21. In other words, each of the protrusions 22, 23a, 23b, 24a, and 24b is in contact with the base 21.

[0026] The protrusion 22 protrudes from one of the multiple sides of the base 21 in the X direction, on the side furthest from the lead frame 30. The height of the protrusion 22 is, for example, the same as the height of the base 21. The protrusion 23a protrudes from one of the two sides of the base 21 in the Y direction. The protrusion 23b protrudes from the other of the two sides of the base 21 in the Y direction. The protrusions 23a and 23b are spaced apart from and facing each other in the Y direction. The height of each of the protrusions 23a and 23b is, for example, lower than the height of the base 21. The height of the protrusion 23a is, for example, the same as the height of the protrusion 23b. The protrusions 24a and 24b each protrude from one of the multiple sides of the base 21 in the X direction, on the side closer to the lead frame 30. The protrusions 24a and 24b are spaced apart from and facing each other in the Y direction. The height of each of the protrusions 24a and 24b is, for example, lower than the height of the base 21. The height of protrusion 24a is, for example, the same as the heights of each of the protrusions 23a, 23b, and 24b.

[0027] The lower surface of the base 21 and the lower surface of the projection 22 correspond to the first surface S1. Of the multiple sides of the projection 22, the side that is not in contact with the base 21 in the X direction corresponds to the second surface S2. The height of the projection 22 corresponds to the height H1 of the second surface S2. Of the multiple sides of the projection 23a, the side that is not in contact with the base 21 in the Y direction corresponds to the third surface S3. Of the multiple sides of the projection 23b, the side that is not in contact with the base 21 in the Y direction corresponds to the fourth surface S4.

[0028] The stepped portion 25 is provided on the upper surface of the base portion 21. More specifically, the stepped portion 25 is provided at the end of the upper surface of the base portion 21 on the lead frame 30 side. In a top view, the stepped portion 25 has, for example, a substantially rectangular shape. The stepped portion 25 includes a bottom surface 25a, and side walls 25b, 25c, and 25d. The bottom surface 25a, and the side walls 25b, 25c, and 25d are included in the base portion 21. The bottom surface 25a is used as an external connection terminal and also functions as a mounting portion on which the semiconductor element 10 is mounted.

[0029] The lead frame 30 includes a base portion 31 and protrusions 32, 33a, 33b, and 34.

[0030] The base portion 31 has, for example, a substantially rectangular parallelepiped shape.

[0031] Each of the protrusions 32, 33a, 33b, and 34 has, for example, a substantially rectangular parallelepiped shape. Each of the protrusions 32, 33a, 33b, and 34 is a portion that protrudes from the base 31. In other words, each of the protrusions 32, 33a, 33b, and 34 is in contact with the base 31.

[0032] The protrusion 32 protrudes from one of the multiple sides of the base 31 in the X direction, on the side furthest from the lead frame 20. The height of the protrusion 32 is, for example, the same as the height of the base 31. The protrusion 33a protrudes from one of the two sides of the base 31 in the Y direction. The protrusion 33b protrudes from the other of the two sides of the base 31 in the Y direction. The protrusions 33a and 33b are spaced apart from and facing each other in the Y direction. The height of each of the protrusions 33a and 33b is, for example, lower than the height of the base 31. The height of the protrusion 33a is, for example, the same as the height of the protrusion 33b. The protrusion 34 protrudes from one of the multiple sides of the base 31 in the X direction, on the side closer to the lead frame 20. The height of the protrusion 34 is, for example, lower than the height of the base 31 and the same as the heights of the protrusions 33a and 33b.

[0033] The lower surface of the base 31 and the lower surface of the projection 32 correspond to the fifth surface S5. Of the multiple sides of the projection 32, the side that is not in contact with the base 31 in the X direction corresponds to the sixth surface S6. The height of the projection 32 corresponds to the height H2 of the sixth surface S6. Of the multiple sides of the projection 33a, the side that is not in contact with the base 31 in the Y direction corresponds to the seventh surface S7. Of the multiple sides of the projection 33b, the side that is not in contact with the base 31 in the Y direction corresponds to the eighth surface S8.

[0034] The lead frames 20 and 30 are arranged in the X direction, spaced apart from and facing each other.

[0035] A semiconductor element 10 is provided on the bottom surface 25a of the stepped portion 25. A portion of the semiconductor element 10 faces the lead frame 20. The stepped portion 25 has a side wall 25b in the X direction. The stepped portion 25 has mutually opposing side walls 25c and 25d in the Y direction. The three sides of the semiconductor element 10 are surrounded by the side walls 25b, 25c, and 25d of the stepped portion 25. The bottom surface 25a of the stepped portion 25 is electrically connected to the cathode (not shown) of the semiconductor element 10 via a conductive member (not shown) made of hardened conductive paste, for example. Depending on the internal configuration of the element portion 11, the bottom surface 25a of the stepped portion 25 may be electrically connected to the anode of the semiconductor element 10.

[0036] One end of the bonding wire 40 is connected to the upper surface of the pad 12. The other end of the bonding wire 40 is connected to the upper surface of the base 31 of the lead frame 30. The bonding wire 40 electrically connects the pad 12 of the semiconductor element 10 to the base 31 of the lead frame 30.

[0037] Figure 6 is a cross-sectional view showing an example of the structure of the semiconductor device 1. Figure 6 shows the cross-sectional structure of the semiconductor device 1 along the Sa-Sa line in Figures 4 and 5.

[0038] As shown in Figure 6, the package member (or sealing member, resin body, molding resin, package resin) 50 is provided on the semiconductor element 10, on the lead frame 20, and on the lead frame 30. The package member 50 covers a portion of each of the lead frames 20 and 30, covers the semiconductor element 10 placed on the bottom surface 25a of the stepped portion 25 of the lead frame 20, and seals the semiconductor element 10 and the bonding wire 40. The package member 50 is also provided in the space surrounded by the semiconductor element 10 and the lead frames 20 and 30. The package member 50 is an insulator and includes, for example, an insulating resin or ceramic, or polyimide.

[0039] The protruding portion 22 of the lead frame 20 has a notch NP at the end on the side of the lower surface that is not in contact with the base portion 21. A plating layer 41 is provided on the lower surface of the base portion 21 of the lead frame 20, the lower surface of the protruding portion 22 of the lead frame 20, and the notch NP of the protruding portion 22. The plating layer 41 includes, for example, tin or solder. Hereinafter, the lower surface of the plating layer 41 that is in contact with the base portion 21 and the protruding portion 22 will be referred to as the first surface S1 of the lead frame 20. The side of the protruding portion 22 of the lead frame 20 that is not in contact with the base portion 21, and the side of the plating layer 41 that is not in contact with the protruding portion 22 will be referred to as the second surface S2 of the lead frame 20. The first surface S1 and the second surface S2 of the lead frame 20 are exposed from the package member 50. The height H1 of the second surface S2 of the lead frame 20 is the height from the lower surface of the plating layer 41 to the upper surface of the protruding portion 22 of the lead frame 20.

[0040] The protruding portion 32 of the lead frame 30 has a notch NP at the end on the side of the lower surface that is not in contact with the base portion 31. A plating layer 41 is provided on the lower surface of the base portion 31 of the lead frame 30, the lower surface of the protruding portion 32 of the lead frame 30, and the notch NP of the protruding portion 32. Hereinafter, the lower surface of the plating layer 41 in contact with the base portion 31 and the protruding portion 32 will be referred to as the fifth surface S5 of the lead frame 30. The side of the protruding portion 32 of the lead frame 30 that is not in contact with the base portion 31, and the side of the plating layer 41 that is not in contact with the protruding portion 32 will be referred to as the sixth surface S6 of the lead frame 30. The fifth surface S5 and the sixth surface S6 of the lead frame 30 are exposed from the package member 50. The height H2 of the sixth surface S6 of the lead frame 30 is the height from the lower surface of the plating layer 41 to the upper surface of the protruding portion 32 of the lead frame 30.

[0041] Thus, in the semiconductor device 1, each of the terminals of the lead frame 20 (first surface S1 and second surface S2) and the terminals of the lead frame 30 (fifth surface S5 and sixth surface S6) has a WF structure.

[0042] The height H3 from the bottom surface of the lead frame 20 to the bottom surface 25a of the stepped portion 25 of the lead frame 20 (hereinafter referred to as "height H3 of the stepped portion 25") is designed, for example, taking into consideration the thickness of the semiconductor element 10. The height H3 of the stepped portion 25 is lower than the height H1. That is, height H3 is different from height H1. In order to reduce the height of the semiconductor device 1, it is preferable that height H3 is, for example, half or less of height H1. During manufacturing, half etching, which will be described later, is performed, so height H3 is, for example, about half of height H1.

[0043] The height H4 from the lower surface of the lead frame 20 to the upper surface of the notch NP of the protrusion 22 of the lead frame 20, and the height H5 from the lower surface of the lead frame 30 to the upper surface of the notch NP of the protrusion 32 of the lead frame 30 are designed, for example, to consider the visibility of the fillet when the semiconductor device 1 is mounted on the main board using a fillet, as described later. Height H5 is approximately the same as height H4. Heights H4 and H5 are, for example, 100 μm or more.

[0044] The length L1 of the protrusion 22 of the lead frame 20 in the X direction is designed to take into account, for example, the possibility that the package member 50 may be chipped during manufacturing due to dicing. The length L2 of the protrusion 32 of the lead frame 30 in the X direction is designed in the same manner as length L1. Lengths L1 and L2 are, for example, 50 μm or more.

[0045] The length L3 of the base 21 of the lead frame 20 in the X direction, from the position where it contacts the protrusion 22 to the stepped portion 25, is designed to be, for example, more than half or more than one-third of the thickness of the half-etching.

[0046] The length L4 of the bottom surface 25a of the stepped portion 25 of the lead frame 20 in the X direction is designed, for example, taking into consideration the size of the first surface S1 of the lead frame 20. The length L4 is, for example, 30 μm or more.

[0047] The semiconductor element 10 is placed on the bottom surface 25a of the stepped portion 25 of the lead frame 20 with a predetermined positional accuracy. If the area of ​​the lower surface of the semiconductor element 10 resting on (contacting) the bottom surface 25a is relatively small, the connection between the semiconductor element 10 and the lead frame 20 may not be sufficient. For this reason, it is preferable that the area of ​​the part of the semiconductor element 10 that is in contact with the bottom surface 25a of the stepped portion 25 of the lead frame 20 is at least half the area of ​​the lower surface of the element 11.

[0048] 1.2 Examples of Semiconductor Device Implementations Next, an example of the semiconductor device 1's implementation will be described. Figure 7 is a cross-sectional view showing the structure of an example of the semiconductor device 1's implementation. Figure 7 shows the structure in which the semiconductor device 1 is mounted on the main substrate 60.

[0049] As shown in Figure 7, the lead frame 20 is provided on the pads (e.g., wiring or terminals) 61 of the main substrate 60 via a conductive member 63. The conductive member 63 is provided between the first surface S1 of the lead frame 20 and the pads 61. Because the lead frame 20 has a WF structure, the conductive member 63 is also provided on the second surface S2 of the lead frame 20. This conductive member 63 is also called a fillet. The fillet 63 is in contact with the first surface S1 of the lead frame 20 and the pads 61, electrically connecting the first surface S1 of the lead frame 20 and the pads 61. The conductive member (or fillet) 63 includes, for example, solder. The pads 61 are provided on the mounting surface of the main substrate 60. The pads 61 include, for example, copper or aluminum.

[0050] The lead frame 30 is provided on the pads (e.g., wiring or terminals) 62 of the main substrate 60 via a conductive member 63. The conductive member 63 is provided between the fifth surface S5 of the lead frame 30 and the pad 62. Because the lead frame 30 has a WF structure, the conductive member 63 is also provided on the sixth surface S6 of the lead frame 30. The fillet 63 is in contact with the fifth surface S5 of the lead frame 30 and the pad 62, electrically connecting the fifth surface S5 of the lead frame 30 and the pad 62. The pad 62 is provided on the mounting surface of the main substrate 60. The pad 62 includes, for example, copper or aluminum.

[0051] 1.3 Method for Manufacturing Semiconductor Devices Next, the manufacturing method of the semiconductor device 1 will be explained using Figures 8 to 15. Figure 8 is a flowchart of an example of the manufacturing method of the semiconductor device 1. Figure 8 shows the main steps in the manufacturing method of the semiconductor device 1. Figures 9 to 15 are diagrams showing the steps in the manufacturing method of the semiconductor device 1. Figure 9 is a plan view of the lead frame substrate as seen from the top side. Figures 10 to 15 are cross-sectional views along the Sb-Sb line in Figure 9.

[0052] First, as shown in Figure 9, a lead frame substrate 100 is prepared (S101). The lead frame substrate 100 is formed, for example, using a mold. The lead frame substrate 100 includes a portion corresponding to the semiconductor device 1, including the lead frames 20 and 30 (hereinafter referred to as "frame portion FP"). The lead frame substrate 100 includes a plurality of frame portions FP. In the lead frame substrate 100, the plurality of frame portions FP are arranged in a line along the X and Y directions.

[0053] The lead frame base material 100 (frame portion FP) includes a base material 120 (hereinafter also simply referred to as "base material 120") corresponding to the lead frame 20, and a base material 130 (hereinafter also simply referred to as "base material 130") corresponding to the lead frame 30. In the frame portion FP, base material 120 is positioned opposite base material 130 in the X direction. Base material 120 and base material 130 are connected by connecting portions 201a and 201b. Connecting portions 201a and 201b correspond to suspension pins.

[0054] The frame sections FP on the left and right sides of the paper, which are adjacent in the X direction, are connected by a connecting section 202. The connecting section 202 is an outer lead.

[0055] The upper and lower frame sections FP, which are adjacent in the Y direction, are connected by a connecting section 203. The connecting section 203 includes a connecting section 201a of the upper frame section FP and a connecting section 201b of the lower frame section FP.

[0056] In the frame portion FP, the dotted lines shown in a rectangular shape on the outside of the base materials 120 and 130 represent the dicing cut surface SDC.

[0057] As shown in Figure 10, in the frame portion FP, the base material 120 has notches NP at both ends of its lower surface (hereinafter referred to as "surface 121"). In the base material 120, the notch NP on the side closer to the base material 130 includes the side surface (hereinafter referred to as "surface 122") that is in contact with the right end of surface 121, and the lower surface (hereinafter referred to as "surface 123") that is in contact with the upper end of surface 122. In the base material 120, the notch NP on the side further from the base material 130 includes the side surface (hereinafter referred to as "surface 124") that is in contact with the left end of surface 121, and the lower surface (hereinafter referred to as "surface 125") that is in contact with the upper end of surface 124.

[0058] In the frame portion FP, the base material 130 has notches NP at both ends of its lower surface (hereinafter referred to as "surface 131"). In the base material 130, the notch NP on the side closer to the base material 120 includes the side surface (hereinafter referred to as "surface 132") that is in contact with the left end of surface 131, and the lower surface (hereinafter referred to as "surface 133") that is in contact with the upper end of surface 132. In the base material 130, the notch NP on the side further from the base material 120 includes the side surface (hereinafter referred to as "surface 134") that is in contact with the right end of surface 131, and the lower surface (hereinafter referred to as "surface 135") that is in contact with the upper end of surface 134. In two adjacent frame portions FP in the X direction, surface 135 of the frame portion FP on the left side of the paper is flush with surface 125 of the frame portion FP on the right side of the paper.

[0059] The lead frame substrate 100 includes, for example, copper (or aluminum). The thickness of the lead frame substrate 100 is, for example, 150 μm or more and 200 μm or less. The height H6 from surface 121 to the upper surface of the notch NP, and the height H7 from surface 131 to the upper surface of the notch NP are lower than the height from the bottom surface to the top surface of the lead frame substrate 100 (the thickness of the lead frame substrate 100). Height H7 is approximately the same as height H6. Heights H6 and H7 are, for example, 100 μm or more.

[0060] Next, as shown in Figure 11, a stepped portion 25 is formed on the upper surface of the lead frame substrate 100 (S102). More specifically, the stepped portion 25 is formed on the end of the upper surface of the substrate 120 of the lead frame substrate 100 that is on the substrate 130 side. Specifically, for example, the end of the upper surface of the substrate 120 of the lead frame substrate 100 that is on the substrate 130 side is half-etched. At this time, etching is performed so that the substrate 120 remains on both sides of the stepped portion 25 in the Y direction. As a result, a stepped portion 25 is formed that has a side wall 25b in the X direction and opposing side walls 25c and 25d in the Y direction.

[0061] Next, as shown in Figure 12, the semiconductor element 10 is mounted on the lead frame substrate 100 (S103). Specifically, for example, the semiconductor element 10 is formed on the bottom surface 25a of the stepped portion 25 of the substrate 120 of the lead frame substrate 100 via a conductive member (not shown). Subsequently, a wire is bonded between the semiconductor element 10 and the lead frame substrate 100 (S104). Specifically, for example, a bonding wire 40 is bonded between the pad 12 of the semiconductor element 10 and the substrate 130 of the lead frame substrate 100. This electrically connects the pad 12 of the semiconductor element 10 and the substrate 130 via the bonding wire 40.

[0062] Next, as shown in Figure 13, a package member 50 is formed on the lead frame substrate 100 (S105). Specifically, for example, first, a backing tape 300 is attached to the lower surface of the lead frame substrate 100. The backing tape 300 is provided to prevent resin from leaking onto surfaces 121 and 131 of the lead frame substrate 100 when forming the package member 50. Next, the package member 50 is formed on the upper surface of the lead frame substrate 100 on which the semiconductor element 10 and bonding wire 40 are provided, and in the space surrounded by the semiconductor element 10 and the substrates 120 and 130. The package member 50 is formed, for example, using a mold. The package member 50 is injected from the injection port of the mold, and the package member 50 fills the space between the lead frame substrate 100 and the mold. As a result, the package member 50 is formed on the upper surface of the lead frame substrate 100 and in the space surrounded by the semiconductor element 10 and the substrates 120 and 130. In other words, a portion of each of the substrates 120 and 130 of the lead frame substrate 100 is covered with the package member 50. The semiconductor element 10 and bonding wire 40 on the lead frame substrate 100 are sealed by the package member 50. After the package member 50 is formed, the backing tape 300 is removed.

[0063] Next, as shown in Figure 14, the terminals of the lead frame substrate 100 are plated externally (S106). Specifically, for example, an electroplating method is used to form a plating layer 41 on the exposed lower and side surfaces (surfaces 121, 124, and 125) of the substrate 120 of the lead frame substrate 100 that are exposed from the package member 50, and on the exposed lower and side surfaces (surfaces 131, 134, and 135) of the substrate 130 of the lead frame substrate 100 that are exposed from the package member 50. The plating layer 41 contains, for example, tin or solder.

[0064] Next, as shown in Figure 15, the lead frame substrate 100 and the package member 50 are diced (S107). Specifically, for example, first, a dicing tape 400 is attached to the upper surface of the package member 50. The dicing tape 400 is provided to hold the multiple semiconductor devices 1 that have been separated into multiple semiconductor devices 1 by dicing. Next, the lead frame substrate 100 and the package member 50 are diced from the lower side of the lead frame substrate 100 using the dicing cut surface SDC. After dicing, the dicing tape 400 is removed. As a result, the lead frame substrate 100 is separated into multiple semiconductor devices 1, and a semiconductor device 1 as shown in Figure 6 is obtained. This completes the manufacturing process of the semiconductor device 1.

[0065] Subsequently, for example, the semiconductor device 1 is mounted on the main substrate 60 by a reflow process, as shown in Figure 7. Fillets 63 are formed on the side surface of the semiconductor device 1. The fillets 63 fix the semiconductor device 1 on the main substrate 60 and electrically connect the first surface S1 of the lead frame 20 to the pads 61 of the main substrate 60, and electrically connect the fifth surface S5 of the lead frame 30 to the pads 62 of the main substrate 60.

[0066] Furthermore, various inspections, such as Automated Optical Inspection (AOI), are then performed on the semiconductor device 1 on the main substrate 60 by the test equipment. For example, AOI inspects the shape of the fillets 63 formed on the lead frames 20 and 30, respectively. This determines the quality of the bonding between the semiconductor device 1 and the main substrate 60.

[0067] After various inspections, the main board 60 on which the semiconductor device 1 of this embodiment is mounted, or the equipment including the semiconductor device 1 of this embodiment, is shipped to the market or to a user.

[0068] In semiconductor devices with a WF (Wall Frame) structure mounted on a main substrate, generally, the greater the WF length, the better the visibility of the fillets (side fillets). Therefore, increasing the WF length, i.e., the thickness of the lead frame, is a possible approach. However, in low-profile semiconductor packages, there are constraints on the gap between the overall height (including the lead frame thickness, semiconductor element thickness, and wire looping) and the package thickness. Therefore, it is difficult to increase the lead frame thickness beyond what is necessary. Thus, in the manufacturing process of semiconductor devices with a WF structure, there is a trade-off between reducing the semiconductor device's height and increasing the lead frame thickness. In structures where semiconductor devices with equal WF length and lead frame thickness are mounted on a main substrate, the visibility of the fillets may decrease.

[0069] In the semiconductor device 1 of this embodiment, a stepped portion 25 is provided at the end of the upper surface of the lead frame 20 on the lead frame 30 side. The semiconductor element 10 is provided on the bottom surface 25a of the stepped portion 25. As a result, according to this embodiment, the WF length (height of the side electrodes), i.e., the height H1 of the second surface S2 of the lead frame 20 and the height H2 of the sixth surface S6 of the lead frame 30 can be maximized without increasing the thickness of the semiconductor device 1. Therefore, the height H4 from the lower surface of the lead frame 20 to the upper surface of the notch NP of the protruding portion 22 of the lead frame 20, and the height H5 from the lower surface of the lead frame 30 to the upper surface of the notch NP of the protruding portion 32 of the lead frame 30 can also be made relatively high, and the height of the plating layer 41 can also be increased. As a result, when mounting the semiconductor device 1 onto the main substrate 60, the fillet 63 is formed up to the height of the plating layer 41. Therefore, the visibility of the fillet 63 can be improved. That is, the mounting state of the semiconductor device 1 can be easily inspected by AOI. As a result, the semiconductor device 1 of this embodiment can improve the accuracy of inspection of the mounting state. Therefore, the reliability of the quality of the main board 60 or the equipment including the semiconductor device 1 of this embodiment can be improved.

[0070] Furthermore, during dicing of the lead frame substrate and package component, stress may cause delamination from the outer edge between the substrate corresponding to the lead frame and the package component.

[0071] In the semiconductor device 1 of this embodiment, the stepped portion 25 has a side wall 25b in the X direction and opposing side walls 25c and 25d in the Y direction. The three sides of the semiconductor element 10 are surrounded by the side walls 25b, 25c, and 25d of the stepped portion 25. As a result, the delamination between the substrate 120 and the package member 50 caused by stress generated during dicing cuts is stopped at the stepped portion 25 from the outer periphery. Therefore, the progression of delamination between the substrate 120 and the package member 50 can be suppressed. As a result, a decrease in moisture resistance in the semiconductor device 1 can be prevented, and the reliability of the semiconductor device 1 can be improved.

[0072] As described above, the semiconductor device 1 and its manufacturing method according to this embodiment can maximize the WF length (height of the side electrodes) of the semiconductor device 1 and improve the reliability of mounting the semiconductor device 1 on the main substrate 60. Furthermore, the reliability of the semiconductor device 1 can be improved.

[0073] 2. Second Embodiment A semiconductor device according to the second embodiment will now be described. In the semiconductor device 1A according to the second embodiment, the structure of the lead frame 20 and the manufacturing method of the semiconductor device 1A differ from those of the first embodiment. The differences from the first embodiment will be described below.

[0074] 2.1 Structure of a semiconductor device The structure of the semiconductor device 1A will be explained using Figures 16 to 18. Figure 16 is a perspective view showing an example of the structure of the semiconductor device 1A. Similar to Figure 3 shown in the first embodiment, Figure 16 shows the structure of the semiconductor device 1A as seen from the top side through the package member 50. Figures 17 and 18 are plan views showing an example of the structure of the semiconductor device 1A. Similar to Figure 4 shown in the first embodiment, Figure 17 shows the structure of the semiconductor device 1A as seen from the top side through the package member 50. Similar to Figure 5 shown in the first embodiment, Figure 18 shows the structure of the semiconductor device 1A as seen from the bottom side through the package member 50.

[0075] As shown in Figures 16 to 18, the semiconductor device 1A includes a semiconductor element 10, lead frames 20 and 30, and bonding wires 40.

[0076] The stepped portion 25 of the lead frame 20 includes a bottom surface 25a and a side wall 25b. The stepped portion 25 has a side wall 25b in the X direction. The bottom surface 25a of the stepped portion 25 has grooves 25e and 25f. Each of the grooves 25e and 25f has a V-shape when viewed from the X direction. Each of the grooves 25e and 25f extends along the X direction from the side wall 25b to the end of the bottom surface 25a on the lead frame 30 side. The grooves 25e and 25f are spaced apart from each other in the Y direction. The semiconductor element 10 is provided between the grooves 25e and 25f. The semiconductor element 10 faces the side wall 25b in the X direction.

[0077] The base 21 of the lead frame 20 has a roughly L-shape when viewed from the Y direction. The upper surfaces of the protrusions 23a and 23b of the lead frame 20 are flush with the bottom surface 25a of the stepped portion 25. The protrusions 24a and 24b have been eliminated from the lead frame 20.

[0078] The upper surfaces of the protrusions 33a and 33b of the lead frame 30 are at the same height as the upper surfaces of the protrusions 23a and 23b of the lead frame 20.

[0079] The three-dimensional and planar structures of semiconductor device 1A, other than those described above, are the same as those shown in Figures 3 to 5 of the first embodiment.

[0080] The cross-sectional structure of the semiconductor device 1A along the Sa-Sa line in Figures 17 and 18 is the same as that shown in Figure 6 in the first embodiment.

[0081] 2.2 Method for Manufacturing Semiconductor Devices The manufacturing method of semiconductor device 1A will be explained using Figure 19. Figure 19 is a flowchart of an example of the manufacturing method of semiconductor device 1A. Figure 19 shows the main steps in the manufacturing method of semiconductor device 1A.

[0082] In the flowchart shown in Figure 19, S102 is replaced with S102A in the flowchart of Figure 8 shown in the first embodiment, S103 is replaced with S103A, and S108 is added between S102A and S103A. Except for S102A, S103A, and S108, it is the same as the flowchart of Figure 8 shown in the first embodiment.

[0083] After S101 is carried out in the same manner as in the first embodiment, in S102A, a stepped portion 25 is formed on the upper surface of the lead frame substrate 100. More specifically, the stepped portion 25 is formed on the end of the upper surface of the substrate 120 of the lead frame substrate 100 that is on the substrate 130 side. Specifically, for example, the end of the upper surface of the substrate 120 of the lead frame substrate 100 that is on the substrate 130 side is half-etched. At this time, etching is performed so that no substrate 120 remains on both sides of the stepped portion 25 in the Y direction. As a result, a stepped portion 25 having side walls 25b in the X direction is formed.

[0084] After the stepped portion 25 is formed, two grooves are formed in the stepped portion 25 of the lead frame base material 100 (S108). More specifically, grooves 25e and 25f are formed on the bottom surface 25a of the stepped portion 25 of the lead frame base material 100. Specifically, for example, coining is performed on the bottom surface 25a of the stepped portion 25 of the lead frame base material 100. This forms grooves 25e and 25f that are spaced apart from each other in the Y direction and each extends along the X direction from the side wall 25b to the end of the bottom surface 25a on the lead frame 30 side.

[0085] After grooves 25e and 25f are formed, in S103A, the semiconductor element 10 is mounted on the lead frame substrate 100. Specifically, for example, the semiconductor element 10 is formed between grooves 25e and 25f on the bottom surface 25a of the stepped portion 25 of the substrate 120 of the lead frame substrate 100, via a conductive member (not shown).

[0086] From this point onward, steps S104 to S107 are carried out in the same manner as in the first embodiment.

[0087] According to the semiconductor device 1A and its manufacturing method of this embodiment, the WF length (height of the side electrodes) of the semiconductor device 1A can be maximized, similar to the first embodiment, and the reliability of mounting the semiconductor device 1A on the main substrate 60 can be improved.

[0088] Furthermore, in the semiconductor device 1A of this embodiment, the stepped portion 25 has a side wall 25b in the X direction. The bottom surface 25a of the stepped portion 25 has grooves 25e and 25f. Each of the grooves 25e and 25f extends along the X direction from the side wall 25b to the end of the bottom surface 25a on the lead frame 30 side. The grooves 25e and 25f are spaced apart from each other in the Y direction. The semiconductor element 10 is provided between the grooves 25e and 25f. The semiconductor element 10 faces the side wall 25b in the X direction. As a result, the progression of delamination between the substrate 120 and the package member 50 from the outer periphery due to stress generated during dicing cut is stopped at the grooves 25e and 25f. Therefore, the progression of delamination between the substrate 120 and the package member 50 can be suppressed. As a result, a decrease in moisture resistance in the semiconductor device 1 can be prevented, and the reliability of the semiconductor device 1A can be improved. As described above, the semiconductor device 1A and its manufacturing method according to this embodiment can improve the reliability of the semiconductor device 1A.

[0089] 3. Third Embodiment A semiconductor device according to the third embodiment will now be described. The semiconductor device 1B according to the third embodiment differs from the first embodiment in that it includes a semiconductor element 70. Furthermore, the semiconductor device 1B according to the third embodiment differs from the first embodiment in the structure of the lead frame 30 and the method of manufacturing the semiconductor device 1B. The differences from the first embodiment will be described below.

[0090] 3.1 Structure of a semiconductor device The structure of the semiconductor device 1B will be explained using Figures 20 to 22. Figures 20 and 21 are plan views showing an example of the structure of the semiconductor device 1B. Figure 20 shows the structure of the semiconductor device 1B as seen from the top side, through the package member 50, similar to Figure 4 shown in the first embodiment. Figure 21 shows the structure of the semiconductor device 1B as seen from the bottom side, through the package member 50, similar to Figure 5 shown in the first embodiment. Figure 22 is a cross-sectional view showing an example of the structure of the semiconductor device 1B. Figure 22 shows the cross-sectional structure of the semiconductor device 1B along the Sa-Sa line in Figures 20 and 21.

[0091] As shown in Figures 20 to 22, the semiconductor device 1B includes semiconductor elements 10 and 70, lead frames 20 and 30, bonding wires 40, and a package member 50.

[0092] The semiconductor element 70 has the same structure as the semiconductor element 10. The semiconductor element 70 includes an element portion 71 and a pad (or node, terminal) 72. The element portion 71 corresponds to the element portion 11. The pad 72 corresponds to the pad 12.

[0093] The lead frame 30 has the same structure as the lead frame 20. The lead frame 30 includes a base 31 and protrusions 32, 33a, 33b, 34a, and 34b. The base 31 corresponds to the base 21. The protrusions 32, 33a, 33b, 34a, and 34b correspond to the protrusions 22, 23a, 23b, 24a, and 24b, respectively. The base 31 has a stepped portion 35. The stepped portion 35 corresponds to the stepped portion 25. The lead frame 30 has a stepped portion 35 at the end of the upper surface on the lead frame 20 side. The stepped portion 35 has a bottom surface 35a and side walls 35b, 35c, and 35d. Note that the side walls 35b, 35c, and 35d are not shown. The bottom surface 35a and the side walls 35b, 35c, and 35d correspond to the bottom surface 25a and the side walls 25b, 25c, and 25d, respectively.

[0094] A semiconductor element 70 is provided on the bottom surface 35a of the stepped portion 35.

[0095] The other end of the bonding wire 40 is connected to the upper surface of the pad 72. The bonding wire 40 electrically connects the pad 12 of the semiconductor element 10 and the base 31 of the lead frame 30 via the pad 72 of the semiconductor element 70.

[0096] The planar and cross-sectional structures of semiconductor device 1B, other than those described above, are the same as those shown in Figures 4 to 6 of the first embodiment.

[0097] 3.2 Method for Manufacturing Semiconductor Devices A method for manufacturing semiconductor device 1B will be described.

[0098] In the manufacturing method of semiconductor device 1B, at S102 of the flowchart in Figure 8 shown in the first embodiment, a stepped portion 35 is formed on the end of the upper surface of the substrate 130 on the substrate 120 side, in the same manner as with the substrate 120. At S103 of the flowchart in Figure 8, a semiconductor element 70 is formed on the bottom surface 35a of the stepped portion 35 of the substrate 130, in the same manner as with the substrate 120. At S104 of the flowchart in Figure 8, a bonding wire 40 is bonded between the pad 12 of the semiconductor element 10 and the pad 72 of the semiconductor element 70.

[0099] The steps other than those mentioned above are the same as in the first embodiment.

[0100] This embodiment provides the same effects as the first embodiment.

[0101] 4. Fourth Embodiment A semiconductor device according to the fourth embodiment will now be described. The semiconductor device 1C according to the fourth embodiment differs from the second embodiment in that it includes a semiconductor element 70. Furthermore, the semiconductor device 1C according to the fourth embodiment differs from the second embodiment in the structure of the lead frame 30 and the method of manufacturing the semiconductor device 1C. The differences from the second embodiment will be described below.

[0102] 4.1 Structure of a semiconductor device The structure of the semiconductor device 1C will be described using Figures 23 and 24. Figures 23 and 24 are plan views showing an example of the structure of the semiconductor device 1C. Figure 23 shows the structure of the semiconductor device 1C as seen from the top side, through the package member 50, similar to Figure 4 shown in the first embodiment. Figure 24 shows the structure of the semiconductor device 1C as seen from the bottom side, through the package member 50, similar to Figure 5 shown in the first embodiment.

[0103] As shown in Figures 23 and 24, the semiconductor device 1B includes semiconductor elements 10 and 70, lead frames 20 and 30, and bonding wires 40.

[0104] The semiconductor element 70 has the same structure as the semiconductor element 10. The semiconductor element 70 includes an element portion 71 and a pad (or node, terminal) 72. The element portion 71 corresponds to the element portion 11. The pad 72 corresponds to the pad 12.

[0105] The lead frame 30 has the same structure as the lead frame 20. The lead frame 30 includes a base 31 and protrusions 32, 33a, and 33b. The base 31 corresponds to the base 21. The protrusions 32, 33a, and 33b correspond to the protrusions 22, 23a, and 23b, respectively. The base 31 has a stepped portion 35. The stepped portion 35 corresponds to the stepped portion 25. The lead frame 30 has a stepped portion 35 at the end of the upper surface on the lead frame 20 side. The stepped portion 35 has a bottom surface 35a and a side wall 35b. Note that the side wall 35b is not shown. The bottom surface 35a and the side wall 35b correspond to the bottom surface 25a and the side wall 25b, respectively. The bottom surface 35a has grooves 35e and 35f. The grooves 35e and 35f correspond to grooves 25e and 25f, respectively.

[0106] A semiconductor element 70 is provided between grooves 35e and 35f on the bottom surface 35a of the stepped portion 35.

[0107] The other end of the bonding wire 40 is connected to the upper surface of the pad 72. The bonding wire 40 electrically connects the pad 12 of the semiconductor element 10 and the base 31 of the lead frame 30 via the pad 72 of the semiconductor element 70.

[0108] The planar structure of semiconductor device 1C, other than that described above, is the same as that shown in Figures 17 and 18 of the second embodiment.

[0109] The cross-sectional structure of semiconductor device 1C along the Sa-Sa line in Figures 23 and 24 is the same as that shown in Figure 22 in the third embodiment.

[0110] 4.2 Method for Manufacturing Semiconductor Devices A method for manufacturing the semiconductor device 1C will be described.

[0111] In the manufacturing method of semiconductor device 1C, at S102A of the flowchart in Figure 19 shown in the second embodiment, a stepped portion 35 is formed on the end of the upper surface of the substrate 130 on the substrate 120 side, in the same manner as with the substrate 120. At S108 of the flowchart in Figure 19, grooves 35e and 35f are formed on the bottom surface 35a of the stepped portion 35 of the substrate 130, in the same manner as with the substrate 120. At S103A of the flowchart in Figure 19, a semiconductor element 70 is formed between the grooves 35e and 35f on the bottom surface 35a of the stepped portion 35 of the substrate 130, in the same manner as with the substrate 120. At S104 of the flowchart in Figure 19, a bonding wire 40 is bonded between the pad 12 of the semiconductor element 10 and the pad 72 of the semiconductor element 70.

[0112] The steps other than those mentioned above are the same as in the first embodiment.

[0113] This embodiment provides the same effects as the second embodiment.

[0114] 5. Variations, etc. As described above, the semiconductor device (1) according to the embodiment comprises a first frame (30), a second frame (20), a first semiconductor element (10), a wire (40), and a package member (50). The second frame (20) is positioned opposite the first frame (30) in a first direction (X) and has a stepped portion (25) at the end of its upper surface on the first frame side. The first semiconductor element (10) is positioned on the bottom surface (25a) of the stepped portion (25) of the second frame (20). The wire (40) electrically connects the first semiconductor element (10) and the first frame (30). The package member (50) covers a part of each of the first frame (30) and the second frame (20) and seals the first semiconductor element (10) and the wire (40). The lower surface (S5) of the first frame (30) and the first side surface (S6) of the first frame on the side furthest from the second frame (20) in the first direction (X) are exposed from the package member (50). The lower surface (S1) of the second frame (20) and the second side surface (S2) of the second frame on the side furthest from the first frame (30) in the first direction (X) are exposed from the package member (50).

[0115] It should be noted that the embodiments are not limited to the forms described above, and various modifications are possible.

[0116] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0117] 1, 1A, 1B, 1C… Semiconductor device, 10… Semiconductor element, 11… Element part, 12… Pad, 20… Lead frame, 21… Base, 22, 23a, 23b, 24a, 24b… Protruding part, 25… Stepped part, 25a… Bottom surface, 25b, 25c, 25d… Side wall, 25e, 25f… Groove, 30… Lead frame, 31… Base, 32, 33a, 33b, 34, 34a, 34b… Protruding part, 35… Stepped part, 35a...Bottom surface, 35e, 35f...Grooves, 40...Bonding wire, 41...Plating layer, 50...Package material, 60...Main substrate, 61, 62...Pads, 63...Conductive material, 70...Semiconductor element, 71...Element part, 72...Pad, 100...Lead frame substrate, 120, 130...Substrate, 201a, 201b, 202, 203...Connecting part, 300...Backside tape, 400...Dicing tape

Claims

1. The first frame and, A second frame is positioned opposite the first frame in a first direction and has a stepped portion at the end of its upper surface on the side of the first frame, A first semiconductor element is disposed on the bottom surface of the stepped portion of the second frame, A wire electrically connecting the first semiconductor element and the first frame, A package member that covers a portion of each of the first frame and the second frame and seals the first semiconductor element and the wire. Equipped with, The lower surface of the first frame and the first side surface of the first frame on the side furthest from the second frame in the first direction are exposed from the package member. The lower surface of the second frame and the second side surface of the second frame on the side furthest from the first frame in the first direction are exposed from the package member. Semiconductor equipment.

2. The height of the stepped portion of the second frame is 1 / 2 or less of the height of the second side surface of the second frame. The semiconductor device according to claim 1.

3. The area of ​​the portion of the first semiconductor element that is in contact with the bottom surface of the stepped portion of the second frame is at least half the area of ​​the bottom surface of the first semiconductor element. The semiconductor device according to claim 1.

4. A portion of the first semiconductor element faces the second frame. The semiconductor device according to claim 1.

5. The stepped portion of the second frame has a first side wall in the first direction, and a second side wall and a third side wall facing each other in the second direction intersecting the first direction. The three sides of the first semiconductor element are surrounded by the first to third side walls. The semiconductor device according to claim 4.

6. The stepped portion of the second frame has a first side wall in the first direction, The first semiconductor element is facing the first side wall in the first direction, The semiconductor device according to claim 4.

7. The bottom surface of the stepped portion of the second frame has two grooves, The first semiconductor element is positioned between the two grooves, The semiconductor device according to claim 6.

8. Each of the two grooves extends along the first direction from the first side wall to the end of the bottom surface of the stepped portion on the first frame side, The two grooves are spaced apart from each other in a second direction that intersects the first direction. The semiconductor device according to claim 7.

9. Second semiconductor element Furthermore, The first frame has a stepped portion at the end of its upper surface on the side of the second frame, The second semiconductor element is placed on the bottom surface of the stepped portion of the first frame, The wire electrically connects the first semiconductor element and the first frame via the second semiconductor element. The semiconductor device according to claim 1.

10. The height of the first side surface of the first frame and the height of the second side surface of the second frame are 150 μm or more and 200 μm or less. The semiconductor device according to claim 1.

11. A step is formed at the end of the upper surface of the second substrate on the first substrate side of the lead frame substrate, which includes a first substrate and a second substrate arranged opposite to the first substrate in a first direction. The first semiconductor element is formed on the bottom surface of the stepped portion of the second substrate, Connecting the first semiconductor element and the first substrate with a wire, The first substrate and the second substrate are each covered with a package member, and the first semiconductor element and the wire are sealed with the package member. A plating layer is formed on the lower surface and side surface of the first substrate exposed from the package member, and on the lower surface and side surface of the second substrate exposed from the package member. Dicing the lead frame substrate and the package member Equipped with, A method for manufacturing a semiconductor device.

12. Forming the stepped portion on the upper surface of the second substrate means Half-etching the end portion of the upper surface of the second substrate that is on the side of the first substrate. including, A method for manufacturing a semiconductor device according to claim 11.

13. Forming the stepped portion on the upper surface of the second substrate means The stepped portion is formed having a first side wall in the first direction and a second side wall and a third side wall facing each other in a second direction intersecting the first direction. including, A method for manufacturing a semiconductor device according to claim 11.

14. Forming the stepped portion on the upper surface of the second substrate means To form the stepped portion having a first side wall in the first direction. including, A method for manufacturing a semiconductor device according to claim 11.

15. Forming the stepped portion on the upper surface of the second substrate means Two grooves are formed on the bottom surface of the stepped portion. It further includes, Forming the first semiconductor device is The first semiconductor element is formed between the two grooves. including, A method for manufacturing a semiconductor device according to claim 14.

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