Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same that can improve reliability. [Solution] The semiconductor device of the embodiment comprises a semiconductor element 10, a lead frame 20, a package member 30, and lead terminals 21. The semiconductor element 10 is provided on the first surface of the lead frame 20. The package member 30 is provided on the lead frame 20 and the semiconductor element 10 and has a recessed portion 31. The lead terminals 21 are provided within the recessed portion 31 and extend in the X direction. The recessed portion 31 has a recessed shape with a first length L1 in the X direction, a second length L2 in the Z direction, and a third length L3 in the Y direction. The third length L3 of the recessed portion 31 is shorter than the length of the package member 30 in the Y direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A semiconductor device including a lead frame on which semiconductor elements are mounted is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor device and a method for manufacturing the same that can improve reliability.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a semiconductor element provided on a first surface of a lead frame, a package member provided on the lead frame and on the semiconductor element and having a first recess, and a first terminal provided in the first recess and extending in a first direction parallel to the first surface of the lead frame. The first recess has a recess shape having a first length in the first direction, a second length in a second direction perpendicular to the first surface of the lead frame, and a third length in a third direction perpendicular to the first direction and the second direction. The third length is shorter than the length of the package member in the third direction.

[0006] The method for manufacturing a semiconductor device according to the embodiment comprises: preparing a lead frame substrate including a terminal having a recessed shape; sandwiching the lead frame substrate with a mold such that a projection guide provided in the mold is positioned in the recessed shape; filling the mold with the material for the package member; hardening the material to form a package member on the lead frame substrate and providing a recessed portion including the recessed shape in the package member; and cutting the recessed shape of the lead frame substrate and the recessed portion of the package member by dicing to form a semiconductor device having the terminal having part of the recessed shape and the package member having part of the recessed portion. [Brief explanation of the drawing]

[0007] [Figure 1] This is a perspective view of the semiconductor device according to the embodiment, as seen from the top. [Figure 2] This is a perspective view of the semiconductor device according to the embodiment, seen from the bottom side. [Figure 3] This is a top view of the semiconductor device according to the embodiment, seen from above through the package member. [Figure 4] This is a cross-sectional view of the semiconductor device according to the embodiment. [Figure 5] This is an enlarged perspective view of the lead terminals and recessed portion of the semiconductor device according to the embodiment. [Figure 6] This is a perspective view from above of the main board on which the semiconductor device according to the embodiment is mounted. [Figure 7] This is a cross-sectional view of a semiconductor device mounted on a main board according to an embodiment. [Figure 8] This is an enlarged cross-sectional view of the lead terminals and recessed portion of the semiconductor device according to the embodiment. [Figure 9] This is a flowchart showing the main steps in the method for manufacturing a semiconductor device according to the embodiment. [Figure 10] This figure shows the steps in the manufacturing method of a semiconductor device according to the embodiment. [Figure 11] This figure shows the steps in the manufacturing method of a semiconductor device according to the embodiment. [Figure 12] This figure shows the steps in the manufacturing method of a semiconductor device according to the embodiment. [Figure 13] This figure shows the steps in the manufacturing method of a semiconductor device according to the embodiment. [Figure 14] This figure shows the steps in the manufacturing method of a semiconductor device according to the embodiment. [Figure 15] This figure shows the steps in the manufacturing method of a semiconductor device according to the embodiment. [Figure 16] This figure shows the steps in the manufacturing method of a semiconductor device according to the embodiment. [Figure 17] This figure shows the steps in the manufacturing method of a semiconductor device according to the embodiment. [Figure 18] This figure shows the steps in the manufacturing method of a semiconductor device according to the embodiment. [Modes for carrying out the invention]

[0008] Embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be denoted by the same reference numerals. Furthermore, the embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of this embodiment, and do not specify the materials, shapes, structures, and arrangements of the components as described below.

[0009] The semiconductor device and the method for manufacturing the semiconductor device according to the embodiment will be described below.

[0010] 1. Structure of a semiconductor device An example of the structure of the semiconductor device 1 of the embodiment will be described with reference to Figures 1 to 4. The semiconductor device 1 includes semiconductor elements, a lead frame, and bonding wires, and has a package structure in which these are held or sealed by a package member.

[0011] FIG. 1 and FIG. 2 are perspective views showing the outer shape of the semiconductor device 1 of the embodiment. FIG. 1 shows the structure of the semiconductor device 1 when viewed from the upper surface side. FIG. 2 shows the structure of the semiconductor device 1 when viewed from the lower surface side. The lower surface of the semiconductor device 1 is the surface where the terminals of the lead frame are exposed, and it is the surface on which the semiconductor device 1 is mounted on the main board, that is, the so-called mounting surface of the semiconductor device 1.

[0012] In the following description, an XYZ orthogonal coordinate system is used. The X direction is parallel to the surface of the lead frame and corresponds to the direction in which the lead frame extends. The Y direction corresponds to the direction in which the lead terminals are arranged. The Z direction corresponds to the direction perpendicular to the surface of the lead frame, that is, the vertical direction. Also, the description of "upper" and its related words indicate the position of a larger coordinate on the Z axis, and the description of "lower" and its related words indicate the position of a smaller coordinate on the Z axis.

[0013] FIG. 3 is a top view showing the structure of the semiconductor device 1 of the embodiment. FIG. 3 shows the structure of the semiconductor device 1 when viewed from the upper surface side through the package member in FIG. 1. FIG. 4 is a cross-sectional view showing the structure of the semiconductor device 1 of the embodiment. FIG. 4 shows the cross-sectional structure of the semiconductor device 1 along the line IV-IV in FIG. 3.

[0014] The semiconductor device 1 includes a semiconductor element 10, a lead frame 20, a package member 30, and bonding wires 40.

[0015] As shown in FIGS. 3 and 4, the semiconductor element 10 is provided on the lead frame 20 within the package member 30.

[0016] If the semiconductor device 1 is, for example, a discrete device, the semiconductor element 10 may be a field-effect transistor (e.g., a MOS field-effect transistor), a bipolar transistor, an IGBT (Insulated Gate Bipolar Transistor), or a diode. Specifically, the semiconductor element 10 may be a small-signal transistor that controls signal processing, or a power transistor that controls current and voltage (e.g., a high-voltage transistor, a high-voltage transistor). The following explanation will use the case where the semiconductor element 10 is a field-effect transistor as an example.

[0017] The semiconductor element 10 is, for example, a semiconductor chip (or bare chip, die). The semiconductor element 10 includes an element portion 11 and a plurality of pads (or nodes, terminals) 12, 13, 14.

[0018] The element portion 11 includes a semiconductor layer on which a field-effect transistor is formed. The semiconductor layer is, for example, silicon, silicon carbide, silicon germanium, gallium nitride, or gallium arsenide.

[0019] Pads 12 and 13 are provided on the upper surface of the element section 11. Pad 12 is connected to the gate of the field-effect transistor. Pad 13 is connected to the source of the field-effect transistor. Hereinafter, pad 12 will be referred to as the gate pad 12, and pad 13 as the source pad 13.

[0020] The pad 14 is located on the lower surface of the element portion 11. The pad 14 is connected to the drain of the field-effect transistor. Hereinafter, the pad 14 will be referred to as the drain pad 14.

[0021] Depending on the internal configuration of the element section 11, pad 14 may be used as a source pad and pad 13 as a drain pad. Pads 12, 13, and 14 include a metal layer such as aluminum or copper.

[0022] The package member (or sealing member, resin body, molding resin, package resin) 30 is provided on the semiconductor element 10 and on the lead frame 20. The package member 30 covers the semiconductor element 10 placed on the lead frame 20 and seals the semiconductor element 10 and the bonding wire 40. The package member 30 is also provided on the upper surface and the lower surface of the lead frame 20. The package member 30 includes an insulator, such as an insulating resin or ceramic, or polyimide.

[0023] The lead frame 20 comprises a plurality of lead terminals (or outer leads) 21 (including 21a, 21b, 21c, 21d, 21e, 21f), a die pad 22, a bonding pad (or inner lead) 23, and a plurality of connecting parts 102 (including 102a, 102b, 102c, 102d, 102e). The lead frame 20 is made of, for example, copper. Hereafter, when "lead terminal 21" is written, it refers to each of the lead terminals 21a, 21b, 21c, 21d, 21e, 21f. Similarly, when "connecting part 102" is written, it refers to each of the connecting parts 102a, 102b, 102c, 102d, 102e.

[0024] The lead terminals 21, die pads 22, and bonding pads 23 each have portions that are exposed from the package member 30. That is, a portion of each of the lead terminals 21, die pads 22, and bonding pads 23 is exposed from the package member 30 on the bottom or side surface of the semiconductor device 1. The portions of the lead terminals 21, die pads 22, and bonding pads 23 that are exposed from the package member 30 function as external connection terminals that connect to the outside.

[0025] The die pad 22 is adjacent to the bonding pad 23 in the Y direction. As described above, the die pad 22 is used as an external connection terminal and also functions as a mounting area on which the semiconductor element 10 is mounted.

[0026] The semiconductor element 10 is mounted on the upper surface of the die pad 22. The drain pad 14 of the semiconductor element 10 is electrically connected to the die pad 22, for example, via a conductive member 41 made of hardened conductive paste.

[0027] The bonding wires 40 (including 40a and 40b) electrically connect the semiconductor element 10 to the lead terminals 21f and the bonding pad 23. Bonding wire 40a is bonded between the gate pad 12 and the lead terminal 21f of the semiconductor element 10. The gate pad 12 is electrically connected to the lead terminal 21f via bonding wire 40a. Bonding wire 40b is bonded between the source pad 13 and the bonding pad 23 of the semiconductor element 10. The source pad 13 is electrically connected to the bonding pad 23 via bonding wire 40b.

[0028] The lead terminals 21a, 21b, and 21c are provided on one end of the semiconductor device 1 in the X direction. The lead terminals 21a and 21b are positioned on one end of the die pad 22 in the X direction. The lead terminals 21a and 21b are connected to the die pad 22 via connecting portions 102a and 102b, respectively.

[0029] The lead terminal 21c is positioned on one end of the bonding pad 23 in the X direction. The lead terminal 21c is connected to the bonding pad 23 via a connecting portion 102c. The lead terminal 21c is electrically isolated from the die pad 22 and the lead terminals 21a, 21b, 21d, 21e, and 21f.

[0030] The lead terminals 21d, 21e, and 21f are provided on the other end of the semiconductor device 1 in the X direction. The lead terminals 21d and 21e are positioned on the other end of the die pad 22 in the X direction. The lead terminals 21d and 21e are connected to the die pad 22 via connecting portions 102d and 102e, respectively.

[0031] The lead terminal 21f is positioned on the other end side of the bonding pad 23 in the X direction. The lead terminal 21f is electrically isolated from the die pad 22, the bonding pad 23, and the lead terminals 21a, 21b, 21c, 21d, and 21e.

[0032] The lead terminals 21a, 21b, 21d, and 21e are electrically connected to the drain pad 14 provided on the lower surface of the semiconductor element 10 via the connecting parts 102a, 102b, 102d, and 102e, the die pad 22, and the conductive member 41. The lead terminal 21c is electrically connected to the source pad 13 provided on the upper surface of the semiconductor element 10 via the connecting part 102c, the bonding pad 23, and the bonding wire 40b. The lead terminal 21f is electrically connected to the gate pad 12 provided on the upper surface of the semiconductor element 10 via the bonding wire 40a.

[0033] For example, a plating layer 42 is provided on the die pad 22, bonding pad 23, and the portion of the lead terminal 21 that is exposed from the package member 30. The connecting portion 102 is covered by the package member 30 and is not exposed from the package member 30.

[0034] The die pad 22, bonding pad 23, lead terminals 21, and connecting portion 102 included in the lead frame 20 contain a metal such as copper or aluminum. The plating layer 42 contains a metal such as tin or copper.

[0035] As shown in Figures 1 to 4, in the semiconductor device 1, the lead terminals 21 have a wettable flank (WF) structure. In the semiconductor device 1 of this embodiment, recesses 31a, 31b, 31c, 31d, 31e, and 31f are provided in the areas where the lead terminals 21a, 21b, 21c, 21d, 21e, and 21f are located. Hereafter, when the recess 31 is mentioned, it refers to each of the recesses 31a, 31b, 31c, 31d, 31e, and 31f.

[0036] The recessed portion 31 in the semiconductor device 1 where the lead terminals 21 are located will be described below with reference to Figure 5. The structures of recessed portions 31a, 31b, 31c, 31d, 31e, and 31f are similar. Figure 5 is an enlarged view of the recessed portion 31 in the semiconductor device 1 where the lead terminals 21 are located. Figure 5 is a perspective view of the recessed portion 31 as seen from the lower surface 30a side of the package member 30.

[0037] A recessed portion 31 is provided in the part of the package member 30 where the lead terminals 21 are located. The package member 30 has a lower surface 30a provided on the lower side of the lead frame 20 that faces the upper surface of the lead frame 20, an upper surface 30b facing the lower surface 30a, and a side surface 30c between the lower surface 30a and the upper surface 30b. The recessed portion 31 is located where the lower surface 30a and the side surface 30c of the package member 30 intersect.

[0038] The recessed portion 31 is recessed by a distance L1 in the X direction from the side surface 30c of the package member 30 (or semiconductor device 1), and by a distance L2 in the Z direction from the bottom surface 30a of the package member 30. The length of the recessed portion 31 in the Y direction (or the width of the recessed portion 31) is L3. The length L3 of the recessed portion 31 in the Y direction is shorter than the length of the package member 30 in the Y direction.

[0039] In other words, the recessed portion 31 of the package member 30 has a shape that is recessed by a length L1 in the X direction, a length L2 in the Z direction, and a length L3 in the Y direction in the area where the lead terminals 21 are located. The recessed portion 31 is a recess at the corner between the lower surface 30a and the side surface 30c of the package member 30, having a length L1 in the X direction, a length L2 in the Z direction, and a length L3 in the Y direction.

[0040] The lead terminal 21 extends in the X direction along the lower surface 30a of the package member 30, is bent along the inner surface of the recessed portion 31, that is, the side surface S1 and the bottom surface S2, and further has a shape arranged along the side surface 30c of the package member 30. That is, the lead terminal 21 has surfaces along the lower surface 30a of the package member 30, the side surface S1 in the recessed portion 31, the bottom surface S2, and the side surface 30c of the package member 30.

[0041] Let the Z - direction length (or the thickness of the lead terminal 21) of the lead terminal 21 exposed from the side surface 30c of the package member 30 be L5, and the Y - direction length (or the width of the lead terminal 21) of the lead terminal 21 be L6. Then, L5 is longer than L2, and L2 is longer than L1. That is, L5>L2>L1 holds. Also, the Y - direction length L3 of the recessed portion 31 is longer than the Y - direction length L6 of the lead terminal 21. That is, L3>L6 holds.

[0042] Also, as shown in FIGS. 2 and 3, in a plurality of recessed portions 31 (or lead terminals 21) arranged in the Y direction, let the distance between the central portions of two adjacent recessed portions 31 (or lead terminals 21) be L4. Then, the Y - direction length L3 of the recessed portion 31 is shorter than the distance L4. That is, L3<L4 holds.

[0043] 2. Mounting Example of Semiconductor Device Next, referring to FIG. 6, an example of mounting the semiconductor device 1 of the embodiment on the main board will be described. FIG. 6 is a perspective view of the main board on which the semiconductor device 1 of the embodiment is mounted, seen from the upper surface side of the semiconductor device 1. The main board shown in FIG. 6 may exist as a component or may be arranged inside an electrical device.

[0044] The semiconductor device 1 is arranged on the surface of the main board (or motherboard, printed wiring board) 50 (hereinafter also referred to as the mounting surface). Also, one or more other devices, for example, another semiconductor device 61 or an electronic component 62, are arranged on the surface of the main board 50.

[0045] The main board 50 includes a plurality of wirings 71, 72, 73 and a plurality of terminals (e.g., connectors, sockets, or slots) 74, 75. The plurality of wirings 71, 72, 73 are provided on the surface of the main board 50 or inside the main board 50. Each of the wirings 71, 72, 73 is connected to one or more of the plurality of terminals 74, 75, or to at least one of the semiconductor device 1, semiconductor device 61, or electronic component 62 on the main board 50. Each of the terminals 74, 75 is supplied with a corresponding voltage (e.g., power supply voltage VDD, or ground voltage GND) or signal.

[0046] The semiconductor device 1 is connected to multiple wirings 71 and 72 on the main board 50. For example, the semiconductor device 1 is connected to terminal 74 via wiring 71, or to semiconductor device 61 (or electronic component 62) via wiring 72.

[0047] The semiconductor device 61 includes, for example, a semiconductor integrated circuit or a discrete device. The semiconductor device 61 may also be a device modularized by a plurality of semiconductor chips and a plurality of passive elements. The electronic component 62 is a passive element such as a capacitor, inductor, resistor, and switch.

[0048] The semiconductor device 61 and electronic components 62 are connected to terminal 75 via wiring 73, or to each other via other wiring.

[0049] Next, with reference to Figures 7 and 8, the lead terminals 21 and recessed portions 31 of the semiconductor device 1 mounted on the main board 50 will be described in detail. Figure 7 is a cross-sectional view of the semiconductor device 1 mounted on the main board 50. Figure 7 shows a cross-section of the semiconductor device 1 along the line VII-VII (i.e., the XZ plane) in Figure 6. Figure 8 is an enlarged view of the lead terminals 21 and recessed portions 31 in the cross-section shown in Figure 7. Since the structures of the lead terminals 21a and recessed portions 31a to lead terminals 21f and recessed portions 31f are similar, they are referred to as lead terminals 21 and recessed portions 31 in Figure 8.

[0050] As shown in Figure 7, the die pad 22 of the lead frame 20 is provided on the pad (e.g., wiring or terminal) 51 of the main substrate 50 via a conductive member 81. This electrically connects the die pad 22 to the pad 51 of the main substrate 50 via the plating layer 42 and the conductive member 81. The pad 51 is provided on the mounting surface of the main substrate 50. The conductive member 81 includes, for example, solder. The pad 51 includes, for example, copper or aluminum.

[0051] As shown in Figure 8, the lead terminals 21 of the semiconductor device 1 are provided on pads (e.g., wiring or terminals) 52 of the main substrate 50 via a conductive member 82. The conductive member 82 is provided between the lead terminals 21 and the pads 52. Because the lead terminals 21 have a WF structure, the conductive member 82 is also provided on the lower surface of the lead terminals 21 and on the surface of the lead terminals 21 within the recessed portion 31. This conductive member 82 is also called a fillet. The fillet 82 is in contact with the lead terminals 21 and the pads 52, electrically connecting the lead terminals 21 and the pads 52. The conductive member (or fillet) 82 includes, for example, solder. The pads 52 are provided on the mounting surface of the main substrate 50. The pads 52 include, for example, copper or aluminum.

[0052] More specifically, the lead terminal 21 has a terminal surface 21aa exposed within the recess 31, a terminal surface 21ab exposed on the lower surface 30a of the package member 30, and a terminal surface 21ac exposed on the side surface 30c of the package member 30. In other words, the surface of the lead terminal is arranged along the lower surface 30a of the package member 30, the inner surface within the recess 31, and the side surface 30c of the package member 30. The terminal surfaces 21aa and 21ab of the lead terminal 21 are electrically connected to the pads 52 of the main substrate 50 via the plating layer 42 and the fillet 82. Note that the terminal surface 21ac of the lead terminal 21 is the surface exposed after the lead frame substrate 120 is cut by dicing, as will be described later. For this reason, the plating layer 42 is not provided on the terminal surface 21ac, and an oxide layer (not shown) is formed. Therefore, the fillet 82 is often not provided on the terminal surface 21ac of the lead terminal 21.

[0053] The semiconductor device 1 of the embodiment described above has a recess 31 on the side surface of the package member 30, and has lead terminals 21 arranged along the inner surface (or side and bottom surface) of the recess 31. When such a semiconductor device 1 is mounted on the main board 50, the fillet 82 enters the recess 31 and electrically connects the lead terminals 21 and the pad 52.

[0054] Since the fillet 82 is formed to fit into the recess 31, the shape and size of the fillet 82 can be formed to a predetermined shape and size. As a result, the mounting strength of the fillet 82 formed in the multiple recesses 31 of the semiconductor device 1 can be improved and variations in mounting strength can be reduced, and the electrical connection between the lead terminals 21 and the pads 52 can be stabilized. This makes it possible to improve the reliability of mounting the semiconductor device 1.

[0055] 3. Method for manufacturing semiconductor devices Next, the manufacturing method of the semiconductor device 1 according to the embodiment will be described with reference to Figures 9 to 18. Figure 9 is a flowchart showing the main steps in the manufacturing method of the semiconductor device 1. Figures 10 to 18 are diagrams showing the steps in the manufacturing method of the semiconductor device 1. Figures 10 and 11 are plan views seen from the bottom side of the lead frame substrate. Figures 12 and 18 are cross-sectional views along the line XII-XII in Figure 11, with the top surface of the semiconductor element 10 facing upwards. Figures 13 to 17 are cross-sectional views along the line XIII-XIII in Figure 11, with the bottom surface of the semiconductor element 10 facing upwards.

[0056] First, as shown in Figure 10, a lead frame substrate 100 is prepared that includes a terminal having a portion (or recess shape) 131 corresponding to a recess 31 (S1). The lead frame substrate 100 is made up of multiple lead frames 20 connected together, each corresponding to a multiple semiconductor device 1. In the region 101 of the lead frame substrate 100 corresponding to one semiconductor device 1, there is a portion 131 corresponding to the recess 31, a portion 121 corresponding to the lead terminal 21, a portion 122 corresponding to the die pad 22, a portion 123 corresponding to the bonding pad 23, a connecting portion 102 connecting the die pad 22 and the lead terminal 21, and a connecting portion 102 connecting the bonding pad 23 and the lead terminal 21.

[0057] The portion 131 corresponding to the recessed portion 31 of the lead frame base material 100 has a shape that is recessed in the Z direction. The portion 131 is formed, for example, by punching (or pressing) using a die. The lead frame base material 100 includes, for example, copper (or aluminum).

[0058] Hereafter, in order to simplify the diagrams, the manufacturing method will be explained using a lead frame substrate 120 that includes a region 101 corresponding to one semiconductor device 1, as shown in Figure 11.

[0059] Next, as shown in Figure 12, the semiconductor element 10 is mounted on the lead frame substrate 120 via a conductive member 41 (S2). Subsequently, a bonding wire 40a is bonded between the gate pad 12 of the semiconductor element 10 and the portion 121 corresponding to the lead terminal. Furthermore, a bonding wire 40b is bonded between the source pad 13 of the semiconductor element 10 and the portion 123 corresponding to the bonding pad (not shown) (S3). As a result, the gate pad 12 of the semiconductor element 10 and the portion 121 corresponding to the lead terminal are electrically connected via the bonding wire 40a. Furthermore, the source pad 13 of the semiconductor element 10 and the portion 123 corresponding to the bonding pad are electrically connected via the bonding wire 40b.

[0060] Next, as shown in Figures 13, 14, and 15, a package member 30 is formed on a portion of the upper and lower surfaces of the lead frame substrate 120 on which the semiconductor element 10 and bonding wires 40a and 40b are provided (S4). Specifically, as shown in Figures 13 and 14, first the lead frame substrate 120 is sandwiched between the lower mold 201 and the upper mold 202 of the mold. At this time, the projection guide 202a provided on the upper mold 202 is positioned in the portion 131 corresponding to the recessed portion 31 of the lead frame substrate 120. Subsequently, resin is filled into the space between the lower mold 201 and the upper mold 202, that is, the space between the upper surface of the lead frame substrate 120 and the lower mold 201, and the space between the lower surface of the lead frame substrate 120 and the upper mold 202, and molded.

[0061] As a result, as shown in Figure 15, a package member 30 is formed on the upper surface of the lead frame substrate 120, on the semiconductor element 10, and on a portion of the lower surface of the lead frame substrate 120. At this time, a recess including portion 131 is provided in the package member 30. The semiconductor element 10, bonding wires 40a and 40b on the lead frame substrate 120 are sealed by the package member 30.

[0062] In the lead frame substrate 120, the surfaces of the portion 131 corresponding to the recess 31, the portion 121 corresponding to the lead terminal 21, the portion 122 corresponding to the die pad 22, and the portion 123 corresponding to the bonding pad 23 are exposed from the package member 30. During the formation process of the package member 30, a thin burr, which is the material of the package member, is formed on the side surface of the portion 131 corresponding to the recess 31. This thin burr is removed, for example, by laser irradiation and a honing process.

[0063] Next, as shown in Figure 16, exterior plating is applied to portions 131, 121, 122, and 123 of the lead frame substrate 120 that are exposed from the package member 30 (S5). Specifically, for example, an electroplating method is used to form a plating layer 42 on the portion 131 corresponding to the recessed portion 31, the portion 121 corresponding to the lead terminal 21, the portion 122 corresponding to the die pad 22, and the portion 123 corresponding to the bonding pad 23 that are exposed from the package member 30. The plating layer 42 contains, for example, tin or solder.

[0064] Subsequently, as shown in Figure 17, the lead frame substrate 120 and the package member 30 are fully cut by dicing. This separates the lead frame substrate 120 into individual pieces, obtaining the semiconductor device 1 as shown in Figure 18 (S6). Specifically, the central part of portion 131 of the lead frame substrate 120 and the central part of the portion corresponding to the recessed portion 31 of the package member 30 are cut using the dicing blade 203. This forms a semiconductor device 1 having a lead terminal 21 with part of portion 131 and a package member 30 with a recessed portion 31. With this, the manufacturing process of the semiconductor device 1 is completed.

[0065] Subsequently, for example, the semiconductor device 1 is mounted on the main substrate 50 by a reflow process, as shown in Figure 6. Fillets 82 are formed on the side surface of the semiconductor device 1. The fillets 82 fix the semiconductor device 1 to the main substrate 50 and electrically connect the lead terminals 21 of the semiconductor device 1 to the pads 52 of the main substrate 50.

[0066] Furthermore, various inspections, such as Automated Optical Inspection (AOI), are then performed on the semiconductor device 1 on the main substrate 50 by a test device. For example, AOI inspects the shape of the fillet 82 formed on the lead terminal 21. This determines the quality of the bond between the semiconductor device 1 and the main substrate 50.

[0067] After various inspections, the main board 50 on which the semiconductor device 1 of the embodiment is mounted, or the equipment including the semiconductor device 1 of the embodiment, is shipped to the market or to a user.

[0068] As described above, in this embodiment, the central part of the portion 131 corresponding to the recess 31 provided on the lead frame substrate 120 is cut by the dicing blade 203. Therefore, the side surface of the lead terminal 21 within the recess 31 is less susceptible to defects caused by wear of the dicing blade 203, etc. As a result, the shape of the fillet 82 formed on the lead terminal 21 within the recess 31 can be stabilized when mounting the semiconductor device 1.

[0069] Furthermore, when mounting the semiconductor device 1, the conductive member that will become the fillet 82 fits into the recess 31 provided on the side surface of the package member 30, thereby enabling the formation of a fillet 82 with a stable shape and size.

[0070] As a result, when mounting the semiconductor device 1 onto the main board 50, the mounting strength is improved by the fillet 82 and variations in mounting strength are reduced, and the electrical connection between the lead terminals 21 and the pads 52 can be stabilized. This makes it possible to improve the reliability of mounting the semiconductor device 1.

[0071] Furthermore, in this embodiment, as described above, the shape and size of the fillet 82 formed on the lead terminal 21 can be stabilized. This makes it easy to inspect the mounting state of the semiconductor device 1 using AOI. As a result, the accuracy of the mounting state inspection can be improved in the semiconductor device 1 of this embodiment. Therefore, the reliability of the quality of the main board 50 including the semiconductor device 1 of this embodiment or the equipment can be improved.

[0072] Furthermore, during dicing of the lead frame substrate and package member, delamination may occur between the lead terminals and the package member. In the semiconductor device 1 of this embodiment, the cut surface during dicing has lead terminals protruding in the Z direction from a portion 131 corresponding to the recess 31, that is, the lead terminals 21 provided in the portion 131 corresponding to the recess 31 are formed in a protruding shape, so that the stress generated during dicing is relieved by the protruding lead terminals. As a result, delamination that occurs between the lead terminals 21 and the package member 30 can be reduced. This prevents a decrease in moisture resistance in the semiconductor device 1 and improves the reliability of the semiconductor device 1.

[0073] As described above, according to the semiconductor device 1 and its manufacturing method of the embodiment, the reliability of mounting the semiconductor device 1 on the main substrate can be improved. Furthermore, the reliability of the semiconductor device 1 can be improved.

[0074] 4. Others In the above-described embodiment, the semiconductor device 1 was explained as an example of a field-effect transistor, but the semiconductor device 1 may be a semiconductor integrated circuit, an image sensor, an optical device, or a memory device.

[0075] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0076] 1...Semiconductor device, 10...Semiconductor element, 20...Lead frame, 21(21a-21f)...Lead terminal, 30...Package material, 31(31a-31f)...Recessed part, 40(40a, 40b)...Bonding wire, 41...Conductive material, 42...Plating layer, 50...Main substrate, 82...Fillet (or conductive material), 100...Lead frame base material, 120...Lead frame base material, 201...Lower mold, 202...Upper mold, 202a...Protrusion guide, 203...Dicing blade.

Claims

1. A semiconductor element provided on the first surface of the lead frame, A package member having a first recess is provided on the lead frame and the semiconductor element, A first terminal is provided within the first recess and extends in a first direction parallel to the first surface of the lead frame, It is equipped with, The first recess has a recessed shape having a first length in the first direction, a second length in the second direction perpendicular to the first surface of the lead frame, and a third length in the third direction perpendicular to the first and second directions. The third length is shorter than the length of the package member in the third direction. Semiconductor equipment.

2. The package member has a lower surface provided on the second surface side facing the first surface of the lead frame, an upper surface facing the lower surface, and a side surface between the lower surface and the upper surface. The first recess is located at the point where the lower surface and the side surface of the package member intersect. The semiconductor device according to claim 1.

3. The device further comprises a second terminal extending in the first direction, The package member has a second recess portion arranged in the third direction adjacent to the first recess portion, The second terminal is provided within the second recessed portion. If the first length of the first recess is L1, the second length is L2, and the third length is L3, and the distance between the center of the first recess and the center of the second recess is L4, The following holds true: L4 > L3 > L2 > L1. The semiconductor device according to claim 1.

4. The first terminal is arranged so as to bend along the inner surface of the first recess. The semiconductor device according to claim 1.

5. The package member has a lower surface provided on the second surface side facing the first surface of the lead frame, an upper surface facing the lower surface, and a side surface between the lower surface and the upper surface. The first terminal has a first terminal surface exposed from the inner surface of the first recess and a second terminal surface exposed from the side surface of the package member. The length of the second terminal surface in the second direction is longer than the length of the first terminal surface in the second direction, and the length of the first terminal surface in the second direction is longer than the length of the first terminal surface in the first direction. The semiconductor device according to claim 1.

6. The package member has a lower surface provided on the second surface side facing the first surface of the lead frame, an upper surface facing the lower surface, and a side surface between the lower surface and the upper surface. The first terminal has a first terminal surface exposed from the inner surface of the first recess and a second terminal surface exposed from the lower surface of the package member. The semiconductor device according to claim 1.

7. The first terminal has a plating layer provided on the first terminal surface and the second terminal surface. The semiconductor device according to claim 6.

8. The system further comprises a wire connecting the semiconductor element and the first terminal. The semiconductor device according to claim 1.

9. A lead frame substrate including a terminal with a recessed shape is prepared, and the lead frame substrate is sandwiched in the mold such that a projection guide provided in the mold is positioned in the recessed shape, The package member material is filled into the mold, the material is cured to form the package member on the lead frame substrate, and the package member is provided with a recessed portion including the recessed shape. The recessed shape of the lead frame substrate and the recessed portion of the package member are cut by dicing to form a semiconductor device having the terminal having a part of the recessed shape and the package member having a part of the recessed portion. A method for manufacturing a semiconductor device comprising the above.

10. Before forming the package member, the recessed shape is formed on the lead frame substrate. A method for manufacturing a semiconductor device according to claim 9, further comprising

11. After forming the package member, and before cutting by dicing, a plating layer is formed on the recessed shape and terminals exposed from the package member. A method for manufacturing a semiconductor device according to claim 9, further comprising

12. Before forming the package member, the semiconductor element is mounted on the lead frame substrate, Bonding a wire between the semiconductor element and the terminal of the lead frame substrate, A method for manufacturing a semiconductor device according to claim 9, further comprising

Images