Capacitor and method for manufacturing a capacitor

Abstract

The present invention provides a capacitor capable of reducing damage to the circuit board and a method for manufacturing the same. [Solution] The method for manufacturing a capacitor according to the embodiment includes: providing one or more openings in a processing substrate 1 having a semiconductor substrate 2, a conductive layer and a dielectric layer 3 by opening the dielectric layer 3 and the conductive layer located on the main surface 2a of the semiconductor substrate 2; providing a conductive material portion 8 on the main surface 2a located within one or more openings 6; processing a pattern shape including a connection portion 10 extending from the conductive layer and connected to one or more openings 6 by dry etching the conductive layer; providing a first electrode electrically connected to the conductive layer and a second electrode electrically connected to the semiconductor substrate 2; and cutting the processing substrate 1 along a cutting position including a position where the connection portion 10 is cut along a direction intersecting the extension direction of the connection portion 10, thereby cutting the electrical connection between the connection portion 10 and the conductive material portion 8 and manufacturing one or more capacitor element portions A1, A2.

Description

Technical Field

[0001] Embodiments of the present invention relate to a capacitor and a method for manufacturing the capacitor.

Background Art

[0002] In the process of manufacturing a Si capacitor, after forming trenches in a Si substrate, a dielectric film and a poly-Si film are formed, and then the poly-Si film is patterned. The patterning of the poly-Si film is performed, for example, by chemical dry etching (CDE). CDE is performed while the Si substrate of the substrate to be processed is clamped by an electrostatic chuck. When the poly-Si film is patterned, the contact between the poly-Si film and the Si substrate is lost. As a result, charges remain in the poly-Si film, so even when de-chucking is performed, the Si substrate does not separate from the stage, and damage such as cracks occurs in the Si substrate when the Si substrate is pushed up from the stage with a conductive lift pin.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the invention is to provide a capacitor and a method for manufacturing the same that can reduce damage to the substrate.

Means for Solving the Problems

[0005] The method for manufacturing a capacitor according to the embodiment provides a method for manufacturing a capacitor having a capacitor element. The capacitor element comprises a semiconductor substrate having a main surface having one or more recesses, a conductive layer provided on the main surface of the semiconductor substrate and in one or more recesses, a dielectric layer disposed between the conductive layer and the semiconductor substrate, a first electrode electrically connected to the conductive layer, and a second electrode electrically connected to the semiconductor substrate. The manufacturing method of the capacitor of the embodiment involves providing one or more openings in a processed substrate having a semiconductor substrate, a conductive layer, and a dielectric layer, by opening the dielectric layer and the conductive layer located on the main surface of the semiconductor substrate. A conductive material portion is provided on the main surface located within one or more openings. Using dry etching on a conductive layer, a pattern shape is created that includes connecting portions extending from the conductive layer and connected to one or more openings. A first electrode electrically connected to a conductive layer and a second electrode electrically connected to a semiconductor substrate are provided. By cutting the processing substrate along a cutting position that includes a position where the connection is cut along a direction intersecting the extension direction of the connection, the electrical connection between the connection and the conductive material is severed, and one or more capacitor element parts are manufactured. Includes.

[0006] Furthermore, according to the capacitor of the embodiment, a semiconductor substrate having a main surface having one or more recesses, A conductive layer provided in one or more recesses and on the main surface of a semiconductor substrate, A dielectric layer is placed between the conductive layer and the semiconductor substrate, A connection portion formed by extending a conductive layer located on the main surface of a semiconductor substrate, An opening is provided at a location away from the connection point, with the main surface of the semiconductor substrate as its bottom wall, A conductive material portion provided in the opening and It is equipped with. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic plan view showing a first example of a processing substrate used in the method of the embodiment. [Figure 2] A plan view of a partially enlarged processing substrate shown in FIG. 1. [Figure 3] A cross-sectional view of the processing substrate shown in FIG. 2 cut along line III-III. [Figure 4] A schematic circuit diagram showing the connection state of the location where the fuse part (poly-Si fuse part) is formed. [Figure 5] A plan view of the processing substrate on which the second step of the method of the embodiment is performed. [Figure 6] A cross-sectional view of the processing substrate shown in FIG. 5 cut along line VI-VI. [Figure 7] A plan view of the processing substrate on which the third step of the method of the embodiment is performed. [Figure 8] A cross-sectional view of the processing substrate shown in FIG. 7 cut along line VIII-VIII. [Figure 9] A schematic circuit diagram showing the connection state of the fuse part (poly-Si fuse part). [Figure 10] A plan view of the processing substrate on which the fourth step of the method of the embodiment is performed. [Figure 11] A cross-sectional view of the processing substrate shown in FIG. 9 cut along line XI-XI. [Figure 12] A plan view of the processing substrate on which the fifth step of the method of the embodiment is performed. [Figure 13] A cross-sectional view of the processing substrate shown in FIG. 12 cut along line XIII-XIII. [Figure 14] A plan view of the processing substrate on which the sixth step of the method of the embodiment is performed. [Figure 15] A cross-sectional view of the processing substrate shown in FIG. 14 cut along line XV-XV. [Figure 16] A plan view of the processing substrate on which the seventh step of the method of the embodiment is performed. [Figure 17] A cross-sectional view of the processing substrate shown in FIG. 16 cut along line XVII-XVII. [Figure 18] A plan view of the processing substrate on which the eighth step of the method of the embodiment is performed. [Figure 19] A cross-sectional view of the processing substrate shown in FIG. 18 cut along line XVIII-XVIII. [Figure 20]Plan view of the processing substrate in which the ninth step of the method of the embodiment is performed. [Figure 21] Cross-sectional view of the processing substrate shown in FIG. 20 cut along the XXI-XXI line. [Figure 22] Cross-sectional view of the vicinity of the connection portion 10 of the processing substrate shown in FIG. 20 cut along the dicing line L. [Figure 23] Cross-sectional view of the vicinity of the fuse portion 8 of the processing substrate shown in FIG. 20 cut along the dicing line L. [Figure 24] Plan view showing a second example of the processing substrate used in the method of the embodiment. [Figure 25] Plan view showing a third example of the processing substrate used in the method of the embodiment. [Figure 26] Plan view showing a fourth example of the processing substrate used in the method of the embodiment. [Figure 27] Schematic diagram showing the step of attaching the processing substrate to be dry-etched to the stage of the electrostatic chuck. [Figure 28] Schematic diagram showing the state of the processing substrate attached to the stage of the electrostatic chuck. [Figure 29] Schematic diagram showing the state in which the processing substrate is clamped to the stage of the electrostatic chuck. [Figure 30] Schematic diagram showing the state of the processing substrate after dry etching when attached to the stage of the electrostatic chuck. [Figure 31] Schematic diagram showing the state of the processing substrate when de-chucking the processing substrate shown in FIG. 30 from the stage of the electrostatic chuck. [Figure 32] Schematic diagram showing the state in which damage has occurred to the processing substrate when de-chucking from the stage of the electrostatic chuck.

Mode for Carrying Out the Invention

[0008] Hereinafter, the embodiments will be described in detail with reference to the drawings. Note that components that exhibit the same or similar functions are assigned the same reference numerals throughout all the drawings, and redundant explanations are omitted.

[0009] Dry etching is performed in a reaction chamber with the substrate clamped to the stage of an electrostatic chuck (ESC). The electrostatic chuck used in dry etching will be explained with reference to Figures 27 to 32.

[0010] Figure 27 is a schematic diagram showing the process of attaching a substrate to be dry-etched to the stage of an electrostatic chuck. First, the substrate 100 to be dry-etched is pressed against the stage 200 of the electrostatic chuck using conductive lift pins 201.

[0011] As shown in Figure 28, the processing substrate 100 includes a semiconductor substrate 101, a dielectric layer 102, and a conductive layer 103. The semiconductor substrate 101 is a Si wafer having a doped layer 101b on one main surface 101a doped with impurities. A plurality of recesses (trenches) 104 are provided on one main surface 101a of the semiconductor substrate 101. The depth direction of each recess (trench) 104 is aligned with the z-axis direction. The plurality of recesses (trenches) 104 are arranged along the x-axis direction with spacing between them. Each recess (trench) 104 extends along the y-axis direction.

[0012] The dielectric layer 102 is provided on the main surface 101a and the inner surface of each recess 104 of the semiconductor substrate 101. The conductive layer 103 is embedded in each recess 104. The conductive layer 103 covers the dielectric layer 102 in the recess 104 and the dielectric layer 102 located on the main surface 101a of the semiconductor substrate 101. The conductive layer 103 also covers the opposite main surface 101c and the end surface 101d connecting the two main surfaces 101a and 101c. The conductive layer 103 is formed from, for example, polysilicon doped with impurities. Therefore, as shown in Figure 27, when the conductive lift pin 201 of the electrostatic chuck is brought into contact with the processing substrate 100, the charge 202 from the electrostatic chuck can be accumulated in the conductive layer 103. As a result, as shown in Figure 29, the semiconductor substrate 101 of the processing substrate 100 is electrostatically attracted to the stage 200 of the electrostatic chuck. As a result, the conductive layer 103 becomes electrically connected to the stage 200 of the electrostatic chuck. In this state, when the processing substrate 100 is removed from the electrostatic chuck by being pushed up by the conductive lift pin 201, the residual charge 202 in the conductive layer 103 can be discharged from the conductive layer 103 to the stage.

[0013] However, when the conductive layer 103 is patterned by dry etching, the electrical connection between the conductive layer 103 and the electrostatic chuck stage 200 is broken, as shown in Figure 30. As a result, residual charge 202 remains on the conductive layer 103, as shown in Figure 31. The area 203 where residual charge 202 remains is indicated by a dotted line frame. Therefore, as shown in Figure 32, even if the processed substrate 100 is pushed up with the conductive lift pin 201, it cannot be discharged, and the electrostatically adsorbed state of the processed substrate 100 to the stage 200 is not released, causing damage 204 such as cracks to the semiconductor substrate 101 of the processed substrate 100. Note that if the processed substrate 100 does not have a dielectric layer 102, even after the conductive layer 103 is processed into a pattern shape by dry etching, the charge 202 accumulated on the conductive layer 103 leaks to the stage 200 through the semiconductor substrate 101. Therefore, the problem of de-chuck failure does not occur.

[0014] The method for manufacturing the capacitor of the embodiment will be described with reference to Figures 1 to 26. In each figure, the z-axis direction is parallel to the thickness direction of the semiconductor substrate, the x-axis direction is parallel to the main surface of the semiconductor substrate, and the y-axis direction is parallel to the main surface of the semiconductor substrate and perpendicular to the x-axis direction. Furthermore, the connection state of the fuse section from the first to the tenth step is shown in Table 1 below.

[0015] [Table 1]

[0016] (1st step) The first step includes providing a dielectric layer and a first conductive layer on a semiconductor substrate having one or more recesses on one of its main surfaces. The first step will be explained with reference to Figures 1 to 4. Figure 1 is a plan view showing the processed substrate. Figure 2 is a plan view showing a part of the processed substrate. Figure 3 shows a cross-sectional view of the processed substrate shown in Figure 2, cut along line III-III. Figure 4 is a schematic circuit diagram showing the connection state of the fuse section (poly-Si fuse section).

[0017] The processing substrate 1 shown in Figure 1 includes a semiconductor substrate 2, a dielectric layer 3, and a first conductive layer 4. The semiconductor substrate 2 is, for example, a semiconductor wafer. In the cutting process described later, the processing substrate 1 is cut along the dicing line and divided into a plurality of capacitor element portions (chips of multiple capacitor elements). In Figure 1, two adjacent capacitor element portions are shown as A1 and A2. Figure 2 is an enlarged plan view of the two capacitor element portions (also called capacitor element chips) A1 and A2 in Figure 1. The two capacitor element portions A1 and A2 are aligned along the x-axis. The dicing line L is parallel to the y-axis and is located at the boundary between the two capacitor element portions A1 and A2.

[0018] Semiconductors are selected from, for example, semiconductors composed of compounds of Group III and Group V elements such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and gallium nitride (GaN), as well as silicon carbide (SiC). The term "group" used here refers to the "group" in the short-period periodic table.

[0019] The semiconductor wafer may be doped with impurities, and semiconductor elements such as transistors and diodes may be formed on it. Furthermore, the main surface of the semiconductor wafer may be parallel to any of the semiconductor's crystal planes. For example, a Si wafer (silicon wafer) with a (100) plane as the main surface, or a Si wafer (silicon wafer) with a (110) plane as the main surface, can be used.

[0020] Figure 3 is a cross-sectional view of the processing substrate 1 shown in Figure 2, cut along the line III-III. The semiconductor substrate 2 is a Si wafer having a doped layer 2b on one main surface 2a doped with P-type or N-type impurities. Multiple recesses (trenches) 5 are provided on one main surface 2a of the semiconductor substrate 2. Multiple recesses (trenches) 5 can be processed, for example, by MacEtch (Metal-Assisted Chemical Etching). The depth direction of each recess (trench) 5 is aligned with the z-axis direction. Furthermore, some recesses 5 are arranged along the x-axis direction with spacing between them, and other recesses 5 are arranged along the y-axis direction with spacing between them. Patterns of recesses 5 arranged along the x-axis direction and patterns of recesses arranged along the y-axis direction are arranged alternately along the x-axis and y-axis directions. Figure 3 shows the pattern of recesses 5 arranged along the x-axis direction, and omits the pattern of recesses arranged along the y-axis direction.

[0021] The dielectric layer 3 is provided on the main surface 2a and the inner surface of each recess 5 of the semiconductor substrate 2. The dielectric layer is made of, for example, an organic dielectric or an inorganic dielectric. As an organic dielectric, for example, polyimide can be used. As an inorganic dielectric, ferroelectrics can also be used, but examples of inorganic dielectric layers include oxide films and nitride films. Paraelectrics such as silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, and tantalum oxide are preferred. These paraelectrics have a small change in dielectric constant with temperature. Therefore, using a paraelectric as the dielectric layer can improve the heat resistance of the capacitor.

[0022] The first conductive layer 4 is embedded in each recess 5. The first conductive layer 4 is also in contact with the dielectric layer 3 within the recess 5. The first conductive layer 4 covers the dielectric layer 3 located on the main surface 2a of the semiconductor substrate 2. The first conductive layer 4 embedded in each recess 5 is connected to the first conductive layer 4 located on the main surface 2a of the semiconductor substrate 2 via the dielectric layer 3. Therefore, the first conductive layers 4 embedded in each recess 5 are electrically connected to each other. The first conductive layer 4 is, for example, polysilicon (polySi) doped with impurities. Polysilicon doped with impurities has low resistance. Examples of impurities include P-type or N-type impurities. The first conductive layer 4 is not limited to polySi, but can be formed from metals or alloys such as molybdenum, aluminum, gold, tungsten, platinum, nickel, and copper. The first conductive layer 4 may have a single-layer structure or a multilayer structure.

[0023] Furthermore, the dielectric layer 3 and the first conductive layer 4 may be formed not only on the main surface 2a of the semiconductor substrate 2, but also on the other main surface 2c and the end surface connecting these main surfaces 2a and 2c.

[0024] The fuse section has not yet been provided on the processing board 1. Therefore, the area that will become the fuse section is in state E1, where a MIM (Metal-Insulator-Metal) capacitor structure is formed by the first conductive layer 4, the dielectric layer 3, and the semiconductor substrate 2, as shown in Figure 4.

[0025] (2nd process) The second step includes providing one or more openings in the dielectric layer and the first conductive layer located on the main surface of the semiconductor substrate. The second step will be explained with reference to Figures 5 and 6. Figure 5 is a plan view of the processed substrate. Figure 6 is a cross-sectional view of the processed substrate shown in Figure 5, cut along the line VI-VI. Note that Figure 6 shows a pattern in which the recesses 5 are arranged along the x-axis direction. Figure 6 omits the pattern in which the recesses are arranged along the y-axis direction.

[0026] One or more openings 6 are provided in the dielectric layer 3 and the first conductive layer 4 located on the main surface 2a of the semiconductor substrate 2, penetrating them. It is desirable that the openings 6 be located away from the region where the recess pattern 5 is formed. In the example shown in Figure 5, the openings 6 are provided on the main surface 2a side of the semiconductor substrate 2 for both one capacitor element section A1 and the other capacitor element section A2, with the dicing line L as the boundary. The two openings 6 are located between the region where the recess pattern 5 of one capacitor element section A1 is formed and the region where the recess pattern 5 of the other capacitor element section A2 is formed. Each opening 6 is a cylindrical cavity with the dielectric layer 3 and the first conductive layer 4 as its inner walls and the main surface 2a of the semiconductor substrate 2 as its bottom wall. Although the openings 6 constitute the fuse section, the fuse section is not yet complete at the stage when the second process is finished. Therefore, the area that will become the fuse section is in state E1, where a capacitor with the same MIM structure as in the first process is formed.

[0027] In Figures 5 and 6, one opening 6 is provided in each of the capacitor element sections A1 and A2, but this is not limited to this, and it is possible to have multiple openings.

[0028] The opening 6 can be processed by dry etching, such as chemical dry etching (CDE). Reactive ion etching (RIE) is an example of CDE.

[0029] Dry etching is performed with the substrate 1 held in an electrostatic chuck (ESC chuck). The first conductive layer 4 is formed from, for example, polysilicon doped with impurities, and can accumulate charge from the electrostatic chuck. As a result, the semiconductor substrate 2 of the substrate 1 is electrostatically adsorbed onto the stage of the electrostatic chuck. Although not shown in the figure, the first conductive layer 4 is provided not only on the main surface 2a of the semiconductor substrate 2, but also on the other main surface 2c and the end surface connecting these main surfaces 2a and 2c. As a result, the first conductive layer 4 is electrically connected to the stage of the electrostatic chuck. After the dry etching process, when the substrate 1 is removed from the electrostatic chuck by being pushed up by conductive lift pins, residual charge in the first conductive layer 4 can be released from the first conductive layer 4 to the stage, so that the substrate 1 can be removed from the electrostatic chuck without damaging it.

[0030] (3rd step) The third step includes providing a conductive material portion in the opening. The conductive material portion constitutes a fuse portion (for example, a poly-Si fuse portion). The third step will be explained with reference to Figures 7 to 9. Figure 7 is a plan view of the processing substrate. Figure 8 shows a cross-sectional view of the processing substrate shown in Figure 7, cut along the line VIII-VIII. Figure 9 is a schematic circuit diagram showing the connection state of the fuse portion (poly-Si fuse portion).

[0031] For each of the capacitor element sections A1 and A2 of the processing substrate 1, a second conductive layer 7 is provided on a first conductive layer 4 located on the entire surface of the main surface 2a of the semiconductor substrate 2. At this time, a conductive material section 8 made of the same material as the second conductive layer 7 is embedded in the opening 6 of each of the capacitor element sections A1 and A2. The conductive material section 8 is in direct contact with the main surface 2a of the semiconductor substrate 2 located at the opening 6. The conductive material section 8 is also in contact with the first conductive layer 4. Therefore, the first conductive layer 4 is electrically connected to the semiconductor substrate 2 via the conductive material section 8. The conductive material section 8 is also called a fuse section (poly-Si fuse section). As shown in Figure 9, the electrical connection state in the fuse section (poly-Si fuse section) of each of the capacitor element sections A1 and A2 is a state E2 in which the first conductive layer 4 is directly electrically connected to the semiconductor substrate 2.

[0032] The second conductive layer 7 may be formed from the same material as the first conductive layer 4, for example. In Figure 8, the boundary between the first conductive layer 4 and the second conductive layer 7 is shown for ease of understanding, but the boundary (interface) between the first conductive layer 4 and the second conductive layer 7 may not be clear in some cases.

[0033] (4th step) The fourth step involves patterning the first and second conductive layers by dry etching. The fourth step will be explained with reference to Figures 10 and 11. Figure 10 is a plan view of the processed substrate. Figure 11 shows a cross-sectional view of the processed substrate shown in Figure 10, cut along the line XI-XI.

[0034] For each of the capacitor element sections A1 and A2 of the processing substrate 1, the first conductive layer 4 and the second conductive layer 7 are processed into a pattern shape using dry etching. Alternatively, a mask may be formed by photolithography before dry etching. The patterning is intended to separate the first conductive layer 4 and the second conductive layer 7 for each capacitor element chip (to achieve the desired area on one chip). However, if the first conductive layer 4 and the second conductive layer 7 are processed to the desired area, the conductivity between the first conductive layer 4 and the fuse section 8 will be severed. Therefore, the patterning is performed so that a connection section (wiring section) 10 is provided to connect the first conductive layer 4 and the fuse section 8. Specifically, in each of the capacitor element sections (capacitor element chips) A1 and A2, the first conductive layer 4 and the second conductive layer 7 are removed by dry etching, excluding the area corresponding to the region where the pattern of the recess 5 is formed and the area extending in the x-axis direction from this area to connect to the fuse section 8. The connection portion 10 consists of extensions that extend directly from the first conductive layer 4 and the second conductive layer 7, respectively. The extension direction of the connection portion 10 is parallel to the x-axis direction and intersects with the dicing line L direction, connecting to the opening 6. The connection portion 10 is located on the inner wall of the opening 6. The fuse portion 8 embedded in the opening 6 is in contact with the connection portion 10 located on the inner wall of the opening 6. The fuse portion 8 is also in contact with the main surface 2a of the semiconductor substrate 2 located on the bottom wall of the opening 6. As a result, the first conductive layer 4 and the second conductive layer 7 are electrically connected to the semiconductor substrate 2 by the connection portion 10 and the fuse portion 8. The electrical connection state in the fuse portion (poly-Si fuse portion) 8 is the same state E2 as in the third step.

[0035] Examples of dry etching include the same types described in the third step.

[0036] Dry etching is performed with the substrate 1 held in an electrostatic chuck (ESC chuck). After the dry etching process, when the substrate 1 is removed from the electrostatic chuck by being pushed up by conductive lift pins, the residual charge of the first conductive layer 4 and the second conductive layer 7 can flow from the fuse portion 8 to the semiconductor substrate 2 and then escape from the semiconductor substrate 2 to the stage, so that the substrate 1 can be removed from the electrostatic chuck without damaging it.

[0037] Furthermore, when the processed substrate 1, on which the fuse portion 8 is formed, was clamped to an electrostatic chuck, a pattern shape was processed onto the conductive layer by reactive ion etching, and the processed substrate 1 was removed from the electrostatic chuck 10 times, it was possible to remove the processed substrate 1 from the electrostatic chuck without causing any damage such as cracks in any of the attempts.

[0038] (5th step) The fifth step involves patterning the dielectric layer 3 by dry etching. The fifth step will be explained with reference to Figures 12 and 13. Figure 12 is a plan view of the processed substrate. Figure 13 shows a cross-sectional view of the processed substrate shown in Figure 12, cut along the line XIII-XIII.

[0039] For each of the capacitor element sections A1 and A2 of the processing substrate 1, the dielectric layer 3 is processed into a pattern shape by dry etching. Alternatively, a mask may be formed by photolithography before dry etching. Patterning is performed to divide the dielectric layer 3, which is formed on the entire main surface 2a of the semiconductor substrate 2, into sections for each capacitor element (each chip) (to achieve the desired area for one chip). Except for the positions where the first conductive layer 4 and the second conductive layer 7 are provided and where the connection section 10 is provided, the dielectric layer 3 is removed by dry etching. The electrical connection state at the fuse section 8 (poly-Si fuse section) is the same as state E2 as in the third step.

[0040] Examples of dry etching include the same types described in the third step.

[0041] Dry etching is performed with the substrate 1 held in an electrostatic chuck (ESC chuck). After the dry etching process, when the substrate 1 is removed from the electrostatic chuck by being pushed up by conductive lift pins, the residual charge of the first conductive layer 4 and the second conductive layer 7 can flow from the fuse portion 8 to the semiconductor substrate 2 and then escape from the semiconductor substrate 2 to the stage, so that the substrate 1 can be removed from the electrostatic chuck without damaging it.

[0042] (6th step) Step 6 includes providing a first contact electrode on the conductive layer and providing a second contact electrode on the semiconductor substrate. The formation of the first contact electrode and the second contact electrode may be performed sequentially, or all at once. Step 6 will be explained with reference to Figures 14 and 15. Figure 14 is a plan view of the processed substrate. Figure 15 shows a cross-sectional view of the processed substrate shown in Figure 14, cut along the line XV-XV.

[0043] Each of the capacitor element sections A1 and A2 of the processing substrate 1 has a conductive layer consisting of a first conductive layer 4 and a second conductive layer 7. The first contact electrode 11 is provided on the xy plane of the second conductive layer 7. On the other hand, the second contact electrode 12 is provided on the main surface 2a of the semiconductor substrate 2.

[0044] The first contact electrode 11 and the second contact electrode 12 are each formed from a metal such as aluminum. The first contact electrode 11 and the second contact electrode 12 are each obtained by forming a film, for example, by sputtering. With sputtering, the first contact electrode 11 and the second contact electrode 12 can be provided at once, thus reducing the number of manufacturing steps required.

[0045] Before Al sputtering, a barrier layer may be provided on the second conductive layer 7 and the semiconductor substrate 2. The barrier layer can be formed from, for example, Ti or TiN. The barrier layer can also be formed by, for example, sputtering.

[0046] (7th step) Step 7 includes forming an insulating layer (first insulating layer). Step 7 will be explained with reference to Figures 16 and 17. Figure 16 is a plan view of the processed substrate. Figure 17 shows a cross-sectional view of the processed substrate shown in Figure 16, cut along the line XVII-XVII.

[0047] For each of the capacitor element sections A1 and A2 of the processing substrate 1, a first insulating layer 14 is provided at the target location on the processing substrate 1 to insulate the first contact electrode 11, the second contact electrode 12, the fuse section 8, and the connection section 10, respectively. As shown in Figure 16, the first insulating layer 14 is provided on the main surface of the processing substrate 1, excluding the portions other than the first contact electrode 11 and the second contact electrode 12 of each capacitor element section A1 and A2. The first insulating layer 14 is also called an interlayer insulating film. The first insulating layer 14 is formed from an insulating material such as tetraethoxysilane (TEOS) or polyethyleneimine (PI).

[0048] The state of the fuse unit 8 is the same as state E2 in the 6th step.

[0049] (8th step) Step 8 includes providing a first pad electrode to the first contact electrode and providing a second pad electrode to the second contact electrode. The formation of the first pad electrode and the second pad electrode may be carried out in this order, in the reverse order, or at the same time. Step 8 will be explained with reference to Figures 18 and 19. Figure 18 is a plan view of the processing substrate. Figure 19 shows a cross-sectional view obtained by cutting the processing substrate shown in Figure 18 along the line XVIIII-XVIIII.

[0050] For each of the capacitor element sections A1 and A2 of the processing substrate 1, the first pad electrode 15 is in contact with the xy plane of the first contact electrode 11 and is electrically connected to the first contact electrode 11. The second pad electrode 16 is in contact with the xy plane of the second contact electrode 12 and is electrically connected to the second contact electrode 12.

[0051] The first pad electrode 15 and the second pad electrode 16 are each formed from a metal such as aluminum. Furthermore, the first pad electrode 15 and the second pad electrode 16 are each obtained by forming a film, for example, by sputtering.

[0052] In Figure 19, for ease of understanding, boundaries are depicted between the first contact electrode 11 and the first pad electrode 15, and between the second contact electrode 12 and the second pad electrode 16; however, boundaries (interfaces) are not necessarily present. The first electrode may consist of at least one of the first contact electrode 11 or the first pad electrode 15. The second electrode may consist of at least one of the second contact electrode 12 or the second pad electrode 16.

[0053] (9th step) Step 9 includes providing an insulating layer (second insulating layer). Step 9 will be explained with reference to Figures 20 and 21. Figure 20 is a plan view of the processing substrate. Figure 21 shows a cross-sectional view of the processing substrate shown in Figure 20, cut along the line XXI-XXI.

[0054] As shown in Figure 20, the second insulating layer 20 is provided on the main surface of the processing substrate 1, excluding the portions other than the first pad electrodes 15 and second pad electrodes 16 of each capacitor element section A1 and A2. As shown in Figure 21, an opening 21 is provided in the xy plane of the second insulating layer 20. The first pad electrodes 15 and second pad electrodes 16 are located in the opening 21 of the second insulating layer 20. The first pad electrodes 15 and second pad electrodes 16 are electrically insulated from each other by the second insulating layer 20 interposed between them. The second insulating layer 20 also surrounds the outer wall of the second pad electrode 16. Furthermore, the second insulating layer 20 is also provided on the first insulating layer 14 that covers the connection section 10 and the fuse section 8. The second insulating layer 20 is formed from an insulating material such as tetraethoxysilane (TEOS) or polyethyleneimine (PI).

[0055] In Figure 21, a boundary is depicted between the first insulating layer 14 and the second insulating layer 20 for ease of understanding, but a boundary (interface) is not necessarily present.

[0056] (10th step) The tenth step includes cutting the processing substrate 1 along the dicing line and dividing it into multiple capacitor element sections. The tenth step will be explained with reference to Figure 20.

[0057] The processing board 1 is cut along the dicing line L, dividing it into multiple capacitor element sections A1 and A2. The connection sections 10 extending parallel to the x-axis from each of the capacitor element sections A1 and A2 intersect the dicing line L. Therefore, cutting along the dicing line L disconnects the electrical connection between the connection section 10 extending from capacitor element section A1 and the fuse section 8 connected to it, and between the connection section 10 extending from capacitor element section A2 and the fuse section 8 connected to it. As a result, capacitor element sections A1 and A2 return to their original state E1, forming MIM capacitors. By dividing the processing board 1 into multiple sections, multiple capacitor element sections can be manufactured. Note that the cutting position of the connection section 10 is not limited to the vicinity of the fuse section 8, but can be any position.

[0058] The dicing method is not particularly limited and may be performed by laser dicing, stealth dicing, plasma dicing, blade dicing, etc.

[0059] By the method including the above steps 1 to 10, one or more capacitor element sections A1 and A2 are obtained. Figure 22 shows a schematic cross-sectional view including the vicinity of the connection section 10, and Figure 23 shows a schematic cross-sectional view including the vicinity of the fuse section 8, from among the cross-sectional views obtained by cutting each capacitor element section A1 and A2 along the dicing line L. Each capacitor element section A1 and A2 comprises a semiconductor substrate 2 having a main surface 2a having one or more recesses 5, conductive layers 4 and 7 provided in each recess 5 of the semiconductor substrate and on the main surface 2a, a dielectric layer 3 disposed between the conductive layers 4 and 7 and the semiconductor substrate 2, a connection section 10 extending directly from one or more locations in the conductive layers 4 and 7, and an opening 6 with the main surface 2a of the semiconductor substrate 2 as its bottom wall. As shown in Figure 22, in the cross-section obtained by cutting each capacitor element section A1 and A2 along the thickness direction z, the connection section 10 is located on the dielectric layer 3 and is insulated by being surrounded by a first insulating layer 14. Furthermore, as shown in Figure 23, in the cross-section obtained by cutting each capacitor element A1 and A2 along the thickness direction z, the conductive material of the fuse portion 8 is located within an opening in the dielectric layer 3. The opening filled with the conductive material is located away from the connection portion 10. Therefore, the fuse portion 8 is not electrically connected to the connection portion 10. Note that the opening is not limited to the dielectric layer 3, and depending on the etching conditions, it may reach from the dielectric layer 3 to the semiconductor substrate 2. In this case, the fuse portion 8 may also be filled into the semiconductor substrate 2.

[0060] In the method including steps 1 to 10, an insulating layer was provided at the boundary of the capacitor element section where the dicing line L is located and in its vicinity, but this example is not limited to this. The insulating layer at the boundary of the capacitor element sections A1 and A2 and in its vicinity can be omitted.

[0061] The embodiment may include all of the first to tenth steps, but some steps may be omitted. Furthermore, other steps such as mask layer formation, barrier layer formation, and cleaning may be performed between any of the first to tenth steps.

[0062] In the example described with reference to Figures 1 to 23, the capacitor elements A1 and A2 were adjacent in the x-axis direction, but the invention is not limited to this example. Another example is shown in Figures 24 to 26. In Figure 24, the capacitor elements A1 and A2 are arranged adjacent in the y-axis direction. The x-axis side of capacitor element A1 and the x-axis side of capacitor element A2 are shared. The shared side is located on the dicing line L. A connection portion 10 extending from capacitor element A1 is electrically connected to the fuse portion 8 of capacitor element A2. Also, a connection portion 10 extending from capacitor element A2 is electrically connected to the fuse portion 8 of capacitor element A1. After a dry process such as dry etching, it can be removed from the electrostatic chuck without causing damage such as cracks to the processed substrate. Furthermore, the extension direction of the connection portion 10 is parallel to the y-axis direction and intersects with the direction of the dicing line L. When the processing board is divided into capacitor element sections by cutting along the dicing line L, the electrical connection between the connection section 10 and the fuse section 8 can be severed.

[0063] Figure 25 shows an example where the extension direction of the connection portion 10 of capacitor element portion A1 is opposite to that of the connection portion 10 of capacitor element portion A2. However, as shown in Figure 25, the extension direction of the connection portion 10 of capacitor element portion A1 and the extension direction of the connection portion 10 of capacitor element portion A2 may be the same.

[0064] Figure 26 shows an example where capacitor element sections A1 and A2 are adjacent in the x-axis direction. The connection section 10 of each capacitor element section A1 and A2 is bent in the opposite direction to the extension direction (along the y-axis direction). The ends of the connection section 10 of each capacitor element section A1 and A2 are electrically connected to the fuse section 8 provided in the same capacitor element section. The dicing line L is provided parallel to the x-axis direction of the processing substrate 1 and intersects with the extension direction of the connection section 10. When the connection section 10 and the fuse section 8 are electrically connected, the processing substrate can be removed from the electrostatic chuck after a dry process such as dry etching without causing damage such as cracks to the substrate. Furthermore, by cutting the processing substrate along the dicing line L to divide it into capacitor element sections, the electrical connection between the connection section 10 and the fuse section 8 can be severed.

[0065] The method and capacitor of this embodiment can be applied, for example, to a capacitor that uses a Si wafer with a diameter of 8 inches or more as a semiconductor substrate (for example, a capacitor used in memory such as DRAM).

[0066] According to the method of at least one embodiment described above, after processing a pattern shape on the conductive layer using dry etching, the semiconductor substrate is electrically connected to the conductive layer by the conductive material portion and the connection portion. Therefore, after dry etching, the processed substrate can be removed from the electrostatic chuck without causing damage such as cracks. Furthermore, when manufacturing one or more capacitor element portions by dividing the processed substrate by cutting, the electrical connection between the connection portion and the conductive material portion can be severed by including a cutting position that intersects the extension direction of the connection portion. Thus, according to the method and capacitor of the embodiment, damage such as cracks to the processed substrate can be reduced without complicating the process.

[0067] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0068] 1...Processing substrate, 2...Semiconductor substrate, 2a...Main surface, 2b...Doped layer, 2c...Main surface, 3...Dielectric layer, 4...First conductive layer, 5...Recess (trench), 6...Opening, 7...Second conductive layer, 8...Conductive material part, 8...Fuse part (PolySi fuse part), 10...Connection part (wiring part), 10...Connection part, 11...First contact electrode, 12...Second contact electrode, 14...First insulating layer, 15...First pad electrode, 16 ...Second pad electrode, 20...Second insulating layer, 21...Opening, A1, A2...Capacitor element section, 100...Processing substrate, 101...Semiconductor substrate, 101a...Main surface, 101b...Doped layer, 101c...Main surface, 101d...Edge surface, 102...Dielectric layer, 103...Conductive layer, 104...Recess (trench), 200...Stage, 201...Conductive lift pin, 202...Residual charge, 203...Region, 204...Damage.

Claims

1. A method for manufacturing a capacitor having a capacitor element portion comprising: a semiconductor substrate having a main surface having one or more recesses; a conductive layer provided between the main surface of the semiconductor substrate and the one or more recesses; a dielectric layer disposed between the conductive layer and the semiconductor substrate; a first electrode electrically connected to the conductive layer; and a second electrode electrically connected to the semiconductor substrate, wherein the capacitor element portion comprises these components. In a processing substrate comprising the semiconductor substrate, the conductive layer, and the dielectric layer, one or more openings are provided by opening the dielectric layer and the conductive layer located on the main surface of the semiconductor substrate. A conductive material portion is provided on the main surface located within the one or more openings. A pattern shape is formed on the conductive layer by dry etching, including connecting portions that extend from the conductive layer and connect to the one or more openings. A first electrode electrically connected to the conductive layer and a second electrode electrically connected to the semiconductor substrate are provided. By cutting the processing substrate along a cutting position that includes a position where the connecting portion is cut along a direction intersecting the extending direction of the connecting portion, the electrical connection between the connecting portion and the conductive material portion is severed, and one or more capacitor element portions are manufactured. A method for manufacturing capacitors, including the manufacturing method itself.

2. The method for manufacturing a capacitor according to claim 1, wherein the cutting is performed by at least one of the following methods: laser dicing, stealth dicing, plasma dicing, or blade dicing.

3. A method for manufacturing a capacitor according to claim 1, wherein a plurality of capacitor element portions are provided on the processing substrate before cutting, and the connecting portion extending from the conductive layer of the first capacitor element portion is connected to one or more openings of a second capacitor element portion adjacent to the first capacitor element portion.

4. The method for manufacturing a capacitor according to claim 1, wherein the semiconductor substrate is a substrate containing Si, and the conductive layer and the conductive material portion each contain polySi.

5. The method for manufacturing a capacitor according to claim 1, wherein the dry etching is performed while the processing substrate is held in an electrostatic chuck.

6. A semiconductor substrate having a main surface with one or more recesses, The conductive layer provided in the one or more recesses of the semiconductor substrate and on the main surface, A dielectric layer disposed between the conductive layer and the semiconductor substrate, A connecting portion formed by extending the conductive layer located on the main surface of the semiconductor substrate, An opening provided at a position away from the aforementioned connection portion, with the main surface of the semiconductor substrate as its bottom wall, A conductive material portion provided in the aforementioned opening and A capacitor equipped with the following features.

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