Semiconductor equipment

Abstract

This makes it possible to suppress the turn-off time of the diode. [Solution] According to this embodiment, the semiconductor device comprises a semiconductor layer, a first electrode, and a second electrode. The first region of the transistor region in the semiconductor layer is a first conductivity type provided between the first surface of the semiconductor layer and the first region. The second region is a second conductivity type provided between the first surface of the semiconductor layer and the first region. The third region is electrically connected to the first electrode and is a first conductivity type provided between the second region and the first surface of the semiconductor layer. The fourth region is electrically connected to the second electrode and is a second conductivity type provided between the second surface and the first region of the semiconductor layer. The first trench contact is electrically connected to the first electrode and penetrates the third and second regions to reach the first region. The third electrode is provided in the trench that penetrates the third and second regions to reach the first region and is covered by an insulating film on the inner surface of the trench and an insulating film on the first surface side.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] A reverse conducting IGBT (RC-IGBT) is known as a semiconductor device having a transistor and a freewheeling diode connected in parallel to the transistor. In such a semiconductor device, the transistor is formed in the transistor region and the diode is generally formed in the diode region. When the diode in the diode region conducts, an electron current flows from the cathode region to the anode region of the diode region, and a hole current flows from the anode region.

[0003] However, since the base region of the transistor is at the same potential as the anode region, holes are also injected from the transistor region. This prolongs the time it takes for the carriers to disappear when the diode is turned off. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Patent No. 6261819 [Overview of the project] [Problems that the invention aims to solve]

[0005] The problem that this invention aims to solve is to provide a semiconductor device capable of suppressing the turn-off time of a diode. [Means for solving the problem]

[0006] According to this embodiment, the semiconductor device comprises a transistor region and a diode region, and includes a semiconductor layer, a first electrode, and a second electrode. The semiconductor layer has a first surface and a second surface facing the first surface. The transistor region has a first region, a second region, a third region, a fourth region, a first trench contact, and a third electrode. The first region is a first conductivity type provided between the first surface of the semiconductor layer and the first region. The second region is a second conductivity type provided between the first surface of the semiconductor layer and the first region. The third region is electrically connected to the first electrode and is a first conductivity type provided between the second region and the first surface of the semiconductor layer. The fourth region is electrically connected to the second electrode and is a second conductivity type provided between the second surface and the first region of the semiconductor layer. The first trench contact is electrically connected to the first electrode and penetrates the third and second regions to reach the first region. The third electrode is provided in a trench that penetrates the third and second regions and reaches the first region, and is covered by the insulating film on the inner surface of the trench and the insulating film on the first surface side. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic top view of the semiconductor device according to this embodiment. [Figure 2] Cross-sectional view AA' in Figure 1. [Figure 3] A schematic cross-sectional view of a part of a semiconductor device related to a comparative example. [Figure 4] A schematic cross-sectional view of a part of a semiconductor device according to the second embodiment. [Figure 5] A schematic cross-sectional view of a part of a semiconductor device according to the third embodiment. [Figure 6] A schematic cross-sectional view of a part of a semiconductor device according to the fourth embodiment. [Figure 7] A schematic cross-sectional view of a part of a semiconductor device according to the fifth embodiment. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same or similar components will be denoted by the same reference numerals, and components that have already been described will be omitted from the description as appropriate.

[0009] In this specification, n + shape, n shape, n - When the notation "shape" is used, n + shape, n shape, n - This means that the concentration of n-type impurities decreases in the order of the shapes. Also, p + shape, p shape, p - If there is a notation for the shape, p + shape, p shape, p - This means that the concentration of p-type impurities decreases in the order of the compounds.

[0010] In this specification, the distribution and absolute value of impurity concentrations in semiconductor regions can be measured, for example, using secondary ion mass spectrometry (SIMS). Furthermore, the relative magnitudes of impurity concentrations in two semiconductor regions can be determined, for example, using scanning capacitance microscopy (SCM). Additionally, the distribution and absolute value of impurity concentrations can be measured, for example, using spreading resistance analysis (SRA). SCM and SRA provide the relative magnitudes and absolute values ​​of carrier concentrations in the semiconductor regions. By assuming an activation rate for impurities, the relative magnitudes, distribution, and absolute values ​​of impurity concentrations between two semiconductor regions can be determined from the measurement results of SCM and SRA.

[0011] (First Embodiment) The semiconductor device 100 of the first embodiment is, for example, an RC-IGBT in which an IGBT (Insulated Gate Bipolar Transistor) and a diode are formed on the same semiconductor chip.

[0012] The semiconductor device 100 according to this embodiment has a trench gate type IGBT having a gate electrode in a trench formed in a semiconductor layer. Hereinafter, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example, but the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the conductivity types of the substrate, layers, regions, etc. in each embodiment will have opposite polarities.

[0013] FIG. 1 is a schematic top view of the semiconductor device 100 according to this embodiment. FIG. 2 is a cross-sectional view taken along the line AA' of FIG. 1.

[0014] In this specification, technical matters may be described using orthogonal coordinate axes of the x-axis, y-axis, and z-axis. In this specification, the x-direction parallel to the first surface F1 of the semiconductor layer 10 is referred to as the first direction. Also, the y-direction parallel to the first surface F1 and orthogonal to the first direction is referred to as the second direction. Also, the z-direction orthogonal to the x-direction and the y-direction and directed from the second surface F2 toward the first surface F1 is referred to as the third direction. Also, in this specification, the depth is the distance in the direction opposite to the third direction toward the second surface F2 with respect to the first surface F1. That is, being shallow means that the distance in the direction toward the second surface F2 with respect to the first surface F1 is shorter.

[0015] The semiconductor device 100 according to this embodiment has a transistor region 101, a diode region 102, and a first gate electrode pad 104. The transistor region 101 has a first transistor region (boundary region) 101a and a second transistor region 101b.

[0016] The transistor region 101 is a region where an IGBT is formed as a transistor. That is, the transistor region 101 operates as an IGBT.

[0017] The diode region 102 is a region where an RC is formed as a diode. The diode region 102 operates as, for example, a freewheeling diode. The freewheeling diode is, for example, a Fast Recovery Diode (FRD).

[0018] The boundary region 101a is provided between the second transistor region 101b and the diode region 102. The boundary region 101a suppresses interference between the operation of the transistor in the second transistor region 101b and the operation of the diode in the diode region 102, which would otherwise cause degradation of the characteristics of the semiconductor device 100. In other words, in the semiconductor device 100 according to this embodiment, the transistor in the second transistor region 101b is mainly used as an IGBT. The boundary region 101a operates as an IGBT, but it is a region that is highly likely to be affected by interference from the operation of the diode in the diode region 102. An example of interference here is, for example, the inflow of carriers from the diode region 102 to the transistor region 101.

[0019] The semiconductor device 100 of the first embodiment comprises a semiconductor layer 10, an upper electrode 12 (first electrode), and a lower electrode 14 (second electrode). The semiconductor layer 10 includes a first drift region 16 (first region), a base region 18 (second region), a cell emitter region 20 (third region), a collector region 22 (fourth region), a second drift region 24 (fifth region), a diode contact region 26 (sixth region), a cathode region 28 (seventh region), an anode region 30 (eighth region), a first buffer region 32 (ninth region), a second buffer region 34 (tenth region), a third electrode 41, a fourth electrode 51, and a first trench contact 60.

[0020] The semiconductor layer 10 has a first surface F1 and a second surface F2 facing the first surface F1. The semiconductor layer 10 is, for example, single-crystal silicon. The thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

[0021] The width of the boundary region 101a in the first direction is formed to be equivalent to the thickness of the semiconductor layer 10. For example, it is provided in a range where there is a high probability that the electron current diffused from the cathode region 28 will reach.

[0022] Here, a configuration example of the transistor region 101 will be described. The transistor region 101 includes a semiconductor layer 10, an upper electrode 12 (first electrode), and a lower electrode 14 (second electrode). The semiconductor layer 10 of the transistor region 101 includes a first drift region 16, a base region 18, a cell emitter region 20, a collector region 22, a first buffer region 32, a third electrode 41, and a fourth electrode 51. The boundary region 101a of the transistor region 101 is different from the second transistor region 101b in that a first trench contact 60 is further provided therein.

[0023] The upper electrode 12 is provided on the side of the first surface F1 of the semiconductor layer 10. At least a part of the upper electrode 12 is in contact with the first surface F1 of the semiconductor layer 10.

[0024] In the transistor region 101, the upper electrode 12 functions as the emitter electrode of the IGBT. The upper electrode 12 is, for example, made of metal. That is, the upper electrode 12 is electrically connected to the cell emitter region 20.

[0025] The lower electrode 14 is provided on the side of the second surface F2 of the semiconductor layer 10. At least a part of the lower electrode 14 is in contact with the second surface F2 of the semiconductor layer 10. That is, the lower electrode 14 is electrically connected to the collector region 22.

[0026] In the transistor region 101, the lower electrode 14 functions as the collector electrode of the IGBT. The lower electrode 14 is, for example, made of metal. The collector region 22 serves as a supply source of holes when the IGBT is in the on state.

[0027] The first drift region 16 is an n - -type semiconductor region. The first drift region 16 is provided between the base region 18 and the first buffer region 32 in the transistor region 101.

[0028] The first drift region 16 serves as a path for the on-current when the IGBT is in the on state. The first drift region 16 depletes when the IGBT is in the off state and has a function of maintaining the breakdown voltage of the IGBT.

[0029] The base region 18 is a p-type semiconductor region. The base region 18 is located between the first drift region 16 and the cell emitter region 20.

[0030] The base region 18 of the second transistor region 101b is in contact with the first gate insulating film 42. The base region 18 of the boundary region 101a is in contact with the first gate insulating film 42 and the first trench contact 60.

[0031] The depth of the base region 18 is, for example, 5 μm or less. An n-type inversion layer is formed in the region of the base region 18 facing the third electrode 41 when the IGBT is in the ON state. In other words, the base region 18 functions as the channel region of the transistor.

[0032] The base region 18 of the second transistor region 101b is in contact with the first gate insulating film 42. The base region 18 of the boundary region 101a is in contact with the first gate insulating film 42 and the first trench contact 60.

[0033] The n-type impurity concentration in the cell emitter region 20 is formed to be higher than the n-type impurity concentration in the first drift region 16. The cell emitter region 20 is electrically connected to the upper electrode 12. The cell emitter region 20 serves as an electron source when the transistor having the third electrode 41 is in the ON state.

[0034] The first buffer region 32 is, for example, an n-type buffer layer. The n-type impurity concentration in the first buffer region 32 is formed to be higher than the n-type impurity concentration in the first drift region 16. The first buffer region 32 is provided between the first drift region 16 and the collector region 22. The first buffer region 32 functions as a layer that prevents the depletion layer spreading from the lower surface of the base region 18 from reaching the collector region 22.

[0035] The cell emitter region 20 is n + This is a semiconductor region of a certain shape. The cell emitter region 20 is provided between the base region 18 and the first surface F1.

[0036] The cell emitter region 20 of the transistor region 101 is in contact with the first gate insulating film 42. The cell emitter region 20 of the boundary region 101a is in contact with the first gate insulating film 42 and the first trench contact 60.

[0037] The first gate trench 40 is provided on the side of the first surface F1 of the semiconductor layer 10. The first gate trench 40 is a groove provided in the semiconductor layer 10. The first gate trench 40 is part of the semiconductor layer 10.

[0038] The first gate trench 40 extends in a second direction parallel to the first surface F1 on the first surface F1. The first gate trench 40 has a stripe shape. Multiple first gate trenches 40 are repeatedly arranged in a first direction perpendicular to the second direction.

[0039] The first gate trench 40 is in contact with the first drift region 16, the base region 18, and the cell emitter region 20. The first gate trench 40 penetrates the base region 18 and reaches the first drift region 16. The depth of the first gate trench 40 is, for example, 8 μm or less.

[0040] The third electrode 41 is a gate electrode and is located within the first gate trench 40. The third electrode 41 is formed from, for example, a metal. The third electrode 41 is electrically connected to the first gate electrode pad 104.

[0041] The first gate insulating film 42 is provided between the third electrode 41 and the semiconductor layer 10 and the upper electrode 12. That is, the first gate insulating film 42 is provided between the third electrode 41 and the upper electrode 12, between the third electrode 41 and the first drift region 16, between the third electrode 41 and the base region 18, and between the third electrode 41 and the cell emitter region 20. The first gate insulating film 42 is in contact with the upper electrode 12, the first drift region 16, the base region 18, and the cell emitter region 20. The first gate insulating film 42 is, for example, silicon oxide. In this way, the third electrode 41 is provided in the first gate trench 40 that penetrates the cell emitter region 20 and the collector region 22 and reaches the first drift region 16, and is covered by the insulating film 42 on the inner surface of the first gate trench 40 and the insulating film 42 on the first surface F1 side.

[0042] In the boundary region 101a, the first trench contact 60 is provided on the side of the first surface F1 of the semiconductor layer 10. The first trench contact 60 is part of the semiconductor layer 10. That is, the first trench contact 60 is provided in the boundary region 101a, which is a predetermined first range from the boundary between the transistor region 101 and the diode region 102.

[0043] The first trench contact 60 extends in a second direction parallel to the first surface F1 on the first surface F1. The first trench contact 60 has a stripe shape. Multiple first trench contacts 60 are repeatedly arranged in a first direction perpendicular to the second direction.

[0044] The first trench contact 60 is in contact with the first drift region 16, the base region 18, and the cell emitter region 20. The first trench contact 60 penetrates the base region 18 and the cell emitter region 20 and reaches the first drift region 16.

[0045] Furthermore, the first trench contact 60 is joined to the first drift region 16, for example, by Schottky bonding. In this embodiment, the first trench contact 60 is formed to be shorter than the first gate trench 40.

[0046] Furthermore, the first trench contact 60 is electrically connected to the upper electrode 12. The material of the first trench contact 60 may be different from the material of the upper electrode 12. Alternatively, the material of the first trench contact 60 may be the same as the material of the upper electrode 12. In other words, the first trench contact 60 is formed from a material containing metal.

[0047] The end of the first trench contact 60 on the second surface F2 side is formed closer to the first surface F1 than the end of the third electrode 41 on the second surface F2 side. In other words, the end of the third electrode 41 on the second surface F2 side is formed deeper than the end of the first trench contact 60 on the second surface F2 side.

[0048] Here, an example of the configuration of the diode region 102 will be described. The semiconductor layer 10 of the diode region 102 is provided with a second drift region 24, a diode contact region 26, a cathode region 28, an anode region 30, a second buffer region 34, and a fourth electrode 51.

[0049] The upper electrode 12 functions as the anode electrode of the diode in the diode region 102. This upper electrode 12 is electrically connected to the diode contact region 26. The upper electrode 12 is also electrically connected to the anode region 30 via the diode contact region 26. Alternatively, the upper electrode 12 may be in direct contact with the anode region 30. In this case, for example, the upper electrode 12 and the anode region 30 have a Schottky junction.

[0050] The lower electrode 14 functions as the cathode electrode of the diode in the diode region 102. This lower electrode 14 is in contact with the cathode region 28.

[0051] The second drift region 24 is provided in the diode region 102 between the anode region 30 and the first buffer region 32. This second drift region 24 has the same thickness as the first drift region 16 in the third direction.

[0052] Furthermore, the n-type impurity concentration in the second drift region 24 is lower than that in the cathode region 28. The second drift region 24 serves as the path for the on-current when the diode is in the on state.

[0053] The diode contact region 26 is p + This is a semiconductor region of a certain shape. This diode contact region 26 is provided between the anode region 30 and the first surface F1.

[0054] Furthermore, the diode contact region 26 is in contact with the upper electrode 12. This diode contact region 26 is electrically connected to the upper electrode 12. In addition, the p-type impurity concentration in the diode contact region 26 is formed to be higher than the p-type impurity concentration in the anode region 30.

[0055] The cathode region 28 is n + This is a semiconductor region of a certain shape. This cathode region 28 is in contact with the second surface F2. The cathode region 28 is an electron source when the diode is in the ON state. The cathode region 28 is also in contact with the lower electrode 14.

[0056] The anode region 30 is a p-type semiconductor region. This anode region 30 is located between the second drift region 24 and the diode contact region 26. Furthermore, the anode region 30 serves as a hole source when the diode is ON. Moreover, the depth of the anode region 30 is, for example, the same as the depth of the base region 18.

[0057] The second buffer region 34 has the same thickness as the first buffer region 32 in the third direction. The n-type impurity concentration in this second buffer region 34 is formed to be higher than the n-type impurity concentration in the second drift region 24. Furthermore, the second buffer region 34 is provided between the second drift region 24 and the cathode region 28 in the third direction. For example, the second buffer region 34 functions as a layer that prevents the depletion layer spreading from the lower surface of the base region 18 from reaching the cathode region 28.

[0058] The diode trench 50 is provided on the first surface F1 side of the semiconductor layer 10, in contact with the anode region 30. This diode trench 50 is a groove provided in the semiconductor layer 10. Furthermore, the diode trench 50 is part of the semiconductor layer 10.

[0059] The diode trench 50 extends in a second direction parallel to the first surface F1 on the first surface F1. This diode trench 50 has a stripe shape. Furthermore, multiple diode trenches 50 are repeatedly arranged in the first direction perpendicular to the second direction.

[0060] The diode trench 50 penetrates the anode region 30 and reaches the second drift region 24. This diode trench 50 is in contact with the second drift region 24, the anode region 30, and the diode contact region 26. The depth of the diode trench 50 is, for example, 8 μm or less.

[0061] The fourth electrode 51 is provided in the diode trench 50. The fourth electrode 51 is, for example, made of metal. The diode trench 50 can also be a dummy trench in which the fourth electrode 51 is not fixed to a specific potential. Alternatively, a voltage can be applied to the fourth electrode 51.

[0062] The diode insulating film 52 is provided between the fourth electrode 51, the semiconductor layer 10, and the upper electrode 12. The diode insulating film 52 is provided between the fourth electrode 51 and the upper electrode 12, between the fourth electrode 51 and the second drift region 24, between the fourth electrode 51 and the diode contact region 26, and between the fourth electrode 51 and the anode region 30.

[0063] The diode insulating film 52 is in contact with the upper electrode 12, the second drift region 24, the diode contact region 26, and the anode region 30. The diode insulating film 52 is, for example, silicon oxide. Thus, the fourth electrode 51 is provided in a diode trench 50 that penetrates the diode contact region 26 and the anode region 30 and reaches the second drift region 24, and is covered by the diode insulating film 52 on the inner surface of the diode trench 50 and the diode insulating film 52 on the first surface F1 side.

[0064] Here, we will explain an example of the operation of the semiconductor device 100 and the effect of the first trench contact 60. A predetermined first gate voltage is applied to the first gate electrode pad 104 at a predetermined timing. After a first turn-on voltage is applied to the first gate electrode pad 104, a predetermined first turn-off voltage is applied to the first gate electrode pad 104.

[0065] An emitter voltage is applied to the upper electrode 12 in the transistor region 101. The emitter voltage is, for example, 0V. A collector voltage is applied to the lower electrode 14. The collector voltage is, for example, between 200V and 6500V.

[0066] In the off state of the IGBT, a first turn-off voltage is applied to the first gate electrode pad 104. Therefore, the first turn-off voltage is also applied to the third electrode 41. The first turn-off voltage is a voltage below the threshold voltage at which the transistor having the third electrode 41 does not turn on, for example, 0V or a negative voltage. In the off state, no n-type inversion layer is formed in the base region 18 that faces the third electrode 41 and is in contact with the first gate insulating film 42.

[0067] On the other hand, when the first turn-on voltage is applied to the first gate electrode pad 104, the first gate voltage becomes the first turn-on voltage, and the first turn-on voltage is also applied to the third electrode 41. The application of the first turn-on voltage turns the transistor having the third electrode 41 ON. In the ON state, an n-type inversion layer is formed in the base region 18 that faces the third electrode 41 and is in contact with the first gate insulating film 42. As a result, the IGBT becomes conductive.

[0068] On the other hand, when the diode region 102 conducts, an electron current flows from the cathode region 28 to the anode region 30, and a hole current flows from the anode region 30.

[0069] If the first trench contact 60 is absent, the base region 18 of the transistor region 101 is at the same potential as the anode region 30, so holes are injected from the transistor region 101 into the boundary region 101a. This increases the hole concentration in the semiconductor layer 10. As a result, the time until carriers disappear when the diode in the diode region 102 is turned off becomes longer.

[0070] In contrast, in the semiconductor device 100 according to this embodiment, the incoming electron current is absorbed by the first trench contact 60 that penetrates the base region 18. This makes it possible to shorten the time until the carriers disappear when the diode is turned off.

[0071] Furthermore, if the first trench contact 60 is deeper than the first gate trench 40, the contact area between the first trench contact 60 and the first drift region 16 increases, which shortens the time it takes for carriers to disappear when the diode region 102 is turned off. In other words, the electron efflux effect increases, making it possible to speed up the recovery operation.

[0072] Furthermore, in the blocking state of the RC-IGBT, the potential of the first trench contact 60 is the same potential (0V) as the cell emitter region 20. The third electrode 41 in the first gate trench 40 is, for example, at 0V or a negative voltage. As a result, the mesa region sandwiched between the trenches of the first gate trench 40 is close to 0V. Therefore, if the first trench contact 60 is shallower than the first gate trench 40, the electric field between the end of the first trench contact 60 on the lower electrode 14 side and the lower electrode 14 does not depend on the depth of the first trench contact 60. As a result, in the blocking state of the semiconductor device 100, if the first trench contact 60 is shallower than the first gate trench 40, the increase in leakage current is suppressed.

[0073] On the other hand, if the first trench contact 60 becomes deeper than the first gate trench 40, the 0V point will move closer to the second surface F2 side. Also, a collector voltage of, for example, 200V to 6500V is applied to the lower electrode 14. As a result, the electric field between the end of the first trench contact 60 on the lower electrode 14 side and the lower electrode 14 becomes larger, which may increase the leakage current. For this reason, the length of the first trench contact 60 in this embodiment can be changed, for example, depending on the purpose.

[0074] Figure 3 is a schematic cross-sectional view of a part of the semiconductor device 100a according to the comparative example. Figure 3 is the AA' cross-section of Figure 1. The semiconductor device 100a according to the comparative example differs from the semiconductor device 100 according to the first embodiment in that the second trench contact 70 does not penetrate the base region 18. The differences from the semiconductor device 100 according to the first embodiment will be explained below.

[0075] As shown in Figure 3, the second trench contact 70 is formed to penetrate the cell emitter region 20 but not the base region 18. The second trench contact 70 is connected to the upper electrode 12. The second trench contact 70 is joined to the base region 18 by, for example, a Schottky junction.

[0076] The material of the second trench contact 70 may be different from the material of the upper electrode 12. Alternatively, the material of the second trench contact 70 may be the same as the material of the upper electrode 12.

[0077] Furthermore, at the end of the second trench contact 70, p + A semiconductor region of a certain shape is provided as a second plug region 70a. The second plug region 70a corresponds, for example, to a p-contact layer. It is also possible to omit the second plug region 70a.

[0078] During turn-off, the presence of the second trench contact 70 reduces the resistance of the base region 18, making it easier to pull out the carrier. In addition, the second plug region 70a improves the resistance to failure, such as the latch-up resistance.

[0079] On the other hand, when the potential of the upper electrode 12 becomes higher than the potential of the lower electrode 14, and the diode region 102 conducts, an electron current flows from the cathode region 28 to the anode region 30. When the electron current reaches the anode region 30, conductivity modulation occurs, and a hole current flows from the anode region 30. As described above, the base region 18 of the transistor region 101 is at the same potential as the anode region 30, so holes are also injected from the transistor region 101 into the boundary region 101a. As a result, the hole concentration in the boundary region 101a increases.

[0080] In contrast, the first trench contact 60 according to this embodiment penetrates the base region 18, as described above. As a result, as described above, it absorbs the diffused electron current as the potential of the upper electrode 12 increases. Therefore, hole injection is suppressed more efficiently, and it becomes possible to shorten the width of the boundary region 101a in the first direction.

[0081] As described above, according to this embodiment, a first trench contact 60 is provided in the boundary region 101a adjacent to the diode region 102, connected to the upper electrode 12 and penetrating the base region 18. This makes it possible to absorb the electron current diffused from the cathode region 28 as the potential of the upper electrode 12 rises. Therefore, it is possible to shorten the time until carriers disappear when the diode region 102 is turned off.

[0082] (Second Embodiment) The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that a second trench contact 70 is further provided in the transistor region 101. The differences from the semiconductor device according to the first embodiment will be explained below.

[0083] Figure 4 is a schematic cross-sectional view of a part of the semiconductor device 100 according to the second embodiment. Figure 4 is the AA' cross-section of Figure 1.

[0084] As shown in Figure 4, a second trench contact 70 is provided in the second transistor region 101b of the transistor region 101. As described above, the second trench contact 70 is formed to penetrate the cell emitter region 20 but not the base region 18. The second trench contact 70 is connected to the upper electrode 12. The second trench contact 70 is connected to the base region 18 by, for example, a Schottky junction.

[0085] The material of the second trench contact 70 may be different from the material of the upper electrode 12. Alternatively, the material of the second trench contact 70 may be the same as the material of the upper electrode 12. That is, the second trench contact 70 is formed containing metal.

[0086] Furthermore, at the end of the second trench contact 70, p + A second plug region 70a is provided. The second plug region 70a corresponds to, for example, a p-contact layer. It is also possible to omit the second plug region 70a.

[0087] As a result, when the IGBT in the second transistor region 101b is turned off, the resistance of the base region 18 is reduced by providing the second trench contact 70, making it easier to extract the carrier. In addition, the second plug region 70a can improve the breakdown resistance, such as the latch-up resistance.

[0088] As described above, according to this embodiment, a second trench contact 70 is provided in the transistor region 101 that penetrates the cell emitter region 20 but does not penetrate the base region 18. This reduces the resistance of the base region 18 during turn-off, making it easier to extract carriers. Furthermore, the second plug region 70a improves breakdown tolerance, such as latch-up tolerance. In addition, the first trench contact 60 in the boundary region 101a absorbs the electron current diffused from the base region 18. Therefore, the second trench contact 70 can be made to function while suppressing the influence of the diffused electron current.

[0089] (Third embodiment) In the semiconductor device according to the third embodiment, at the end of the first trench contact 60 of the boundary region 101a, n + This semiconductor device differs from the semiconductor device according to the first embodiment in that it further provides a first plug region 60a of the shape. The differences from the semiconductor device according to the first embodiment will be explained below.

[0090] Figure 5 is a schematic cross-sectional view of a part of the semiconductor device 100 according to the third embodiment. Figure 5 is the AA' cross-section of Figure 1.

[0091] As shown in Figure 5, at the end of the first trench contact 60 of the boundary region 101a, n + A semiconductor region of a specific shape is further provided as the first plug region 60a. This improves the fracture resistance at the end of the first trench contact 60.

[0092] (Fourth Embodiment) The semiconductor device according to the fourth embodiment differs from the semiconductor device according to the first embodiment in that the lengths of the first trench contacts 60 and 62 in the boundary region 101a are different. The differences from the semiconductor device according to the first embodiment will be explained below.

[0093] Figure 6 is a schematic cross-sectional view of a part of the semiconductor device 100 according to the fourth embodiment. Figure 5 is the AA' cross-section of Figure 1.

[0094] Referring to Figure 1, as shown in Figure 6, multiple first trench contacts 60 are formed in a boundary region 101a, which is a predetermined range from the boundary, in a first direction perpendicular to the boundary between the transistor region 101 and the diode region 102 along the first surface F1. In addition, at least one other first trench contact 60 is formed in the boundary region 101a, which is longer than one of the first trench contacts 60. This other first trench contact 60 is formed to be longer on the second surface F2 side than the first gate trench 40. That is, the end of the other first trench contact 60 on the second surface F2 side is formed closer to the second surface F2 than the end of the third electrode 41 on the second surface F2 side.

[0095] Furthermore, the longer first trench contact 60 is configured to be closer to the diode region 102 than the first trench contact 60. The length of the first trench contact 60 can be set considering the leakage current, as described above.

[0096] By making the first trench contact 60 longer, it becomes possible to absorb more diffused electron current as the potential of the upper electrode 12 increases. Furthermore, by making the length of the first trench contact 60 on the diode region 102 side longer than the first trench contact 60, it becomes possible to absorb diffused electron current more efficiently. This further shortens the time until carriers disappear when the diode is turned off in the diode region 102, and also allows the width of the boundary region 101a in the first direction to be narrowed.

[0097] (Fifth embodiment) The semiconductor device according to the fifth embodiment differs from the semiconductor device according to the first embodiment in that a third trench contact 80 is further configured in the diode region 102. The differences from the semiconductor device according to the first embodiment will be explained below.

[0098] Figure 7 is a schematic cross-sectional view of a part of the semiconductor device 100 according to the fifth embodiment. Figure 7 is the AA' cross-section of Figure 1.

[0099] As shown in Figure 7, a third trench contact 80 is formed in the diode region 102 in the boundary region 101a. This third trench contact 80 is formed to penetrate the diode contact region 26 but not the anode region 30.

[0100] The material of the third trench contact 80 may be different from the material of the upper electrode 12. Alternatively, the material of the third trench contact 80 may be the same as the material of the upper electrode 12. In other words, the third trench contact 80 is formed containing metal.

[0101] Furthermore, the third trench contact 80 is connected to the upper electrode 12. The third trench contact 80 is joined to the anode region 30, for example, by a Schottky junction. Note that P is attached to the end of the third trench contact 80. + It is also possible to provide a semiconductor region of the type as a third plug region.

[0102] By providing the third trench contact 80, the resistance of the anode region 30 is reduced, making it easier to extract carriers (e.g., electrons). It is also possible to provide the third trench contact 80 in the first to fourth embodiments.

[0103] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0104] With regard to the embodiments described above, the following additional information is disclosed.

[16] The semiconductor device according to

[15] , wherein the boundary is the boundary between the fourth region and the seventh region.

[17] The transistor region is a semiconductor device in which an IGBT is formed, as described in

[16] .

[18] The semiconductor device described in

[17] , wherein the diode region is formed by a freewheeling diode.

[19] When the transistor region is turned on, the second region in contact with the insulating film has the inversion layer of the first conductivity type formed thereon, as described in

[18] .

[20] The semiconductor device according to

[19] , wherein the voltage applied to the third electrode is 0 volts or less when the transistor region is cut off. [Explanation of Symbols]

[0105] 10: Semiconductor layer, 12: Upper electrode (first electrode), 14: Lower electrode (second electrode), 16: First drift region (first region), 18: Base region (second region), 20: Cell emitter region (third region), 22: Collector region (fourth region), 24: Second drift region (fifth region), 26: Diode contact region (sixth region), 28: Cathode region (seventh region), 30: Anode region (eighth region), 32: First buffer Region (9th region), 34: 2nd buffer region (10th region), 41: 3rd electrode, 51: 4th electrode, 60: 1st trench contact, 60a: 1st plug region, 70: 2nd trench contact, 70a: 2nd plug region, 80: 3rd trench contact, 100: semiconductor device, 101: transistor region, 101a: 1st transistor region (boundary region), 101b: 2nd transistor region, 102: diode region

Claims

1. A semiconductor device having a transistor region and a diode region, A semiconductor layer having a first surface and a second surface facing the first surface, First electrode and A second electrode is provided, The transistor region of the semiconductor layer is A first region of a first conductivity type is provided between the first surface and the second surface of the semiconductor layer, A second region of a second conductivity type is provided between the first surface and the first region of the semiconductor layer, A third region of the first conductivity type is electrically connected to the first electrode and is provided between the second region and the first surface of the semiconductor layer, A fourth region of second conductivity type is electrically connected to the second electrode and provided between the second surface of the semiconductor layer and the first region, A first trench contact is electrically connected to the first electrode and penetrates the third region and the second region to reach the first region, A third electrode is provided in a trench that penetrates the third region and the second region and reaches the first region, and is covered by the insulating film on the inner surface of the trench and the insulating film on the first surface side, A semiconductor device having the following features.

2. The semiconductor device according to claim 1, wherein the first trench contact is provided in a predetermined first range from the boundary between the transistor region and the diode region.

3. The semiconductor device according to claim 2, wherein the end on the second surface side of the first trench contact is formed closer to the first surface than the end on the second surface side of the third electrode.

4. The semiconductor device according to claim 2, wherein the end of the first trench contact on the second surface side is formed closer to the second surface than the end of the third electrode on the second surface side.

5. The first range is a predetermined range from the boundary in a first direction perpendicular to the boundary along the first surface, and a plurality of first trench contacts are formed in the first range. The semiconductor device according to claim 2, wherein the lengths of the plurality of first trench contacts decrease as they move away from the boundary in the first direction.

6. The semiconductor device according to claim 3, wherein the end of a portion of the plurality of first trench contacts is formed closer to the second surface than the end of the third electrode on the second surface.

7. The semiconductor device according to any one of claims 1 to 6, wherein the first trench contact and the first region are Schottky bonded.

8. The semiconductor device according to any one of claims 1 to 6, wherein a first plug region of the first conductivity type with a carrier concentration higher than that of the first region is further provided at the end of the second surface side of the first trench contact.

9. The semiconductor device according to any one of claims 2 to 6, wherein the distance from the boundary to the end of the first range in a first direction perpendicular to the boundary along the first surface is less than or equal to the distance between the first surface and the second surface.

10. The transistor region, excluding the first region, further comprises a second trench contact that is electrically connected to the first electrode and penetrates the third region to reach the second region, The semiconductor device according to any one of claims 2 to 6, wherein a second plug region of a second conductivity type with a higher carrier concentration than the second region is further provided at the end of the second surface side of the second trench contact.

11. The semiconductor layer diode region is A fifth region of the first conductivity type is provided between the first and second surfaces of the semiconductor layer, A sixth region of the second conductivity type is electrically connected to the first electrode and is provided between the first region and the first surface of the semiconductor layer, A seventh region of a first conductivity type is electrically connected to the second electrode and provided between the second surface of the semiconductor layer and the first region, A fourth electrode is provided in a trench that penetrates the sixth region and reaches the fifth region, and is covered by the insulating film on the inner surface of the trench and the insulating film on the first surface side, A semiconductor device according to any one of claims 2 to 6, having the features of the semiconductor device according to any one of claims 2 to 6.

12. The diode region is The semiconductor device according to claim 11, further comprising an eighth region of a second conductivity type, provided between the fifth region and the sixth region, and having a carrier concentration lower than that of the sixth region.

13. The diode region is The semiconductor device according to claim 12, further comprising a third trench contact electrically connected to the first electrode and penetrating the sixth region.

14. The aforementioned transistor region is The semiconductor device according to claim 13, further comprising a ninth region of a first conductivity type having a higher carrier concentration than the first region, provided between the fourth region and the first region.

15. The diode region is The semiconductor device according to claim 14, further comprising a tenth region of a first conductivity type having a carrier concentration higher than that of the fifth region, provided between the fifth region and the seventh region.

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