Semiconductor equipment

Abstract

To provide a semiconductor device that can be made smaller. [Solution] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor region of a first conductivity type, a gate electrode, a plurality of fifth semiconductor regions of a second conductivity type, a plurality of sixth semiconductor regions of a second conductivity type, and a second electrode. The first semiconductor region includes a first portion and a second portion provided around the first portion on a first surface. The plurality of second semiconductor regions are separated from each other in a second and a third direction. The plurality of fifth semiconductor regions are provided in the second portion and are aligned with the plurality of second semiconductor regions in the second direction. The distance between adjacent fifth semiconductor regions is longer than the distance between adjacent second semiconductor regions. The plurality of sixth semiconductor regions are provided in the second portion and are aligned with the plurality of second semiconductor regions in the third direction.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for applications such as power conversion. There is a need for technologies that can miniaturize the size of these semiconductor devices. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 5052025 [Overview of the project] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor device that can be made smaller. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor region of a first conductivity type, a gate electrode, a plurality of fifth semiconductor regions of a second conductivity type, a plurality of sixth semiconductor regions of a second conductivity type, and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes a first portion and a second portion provided around the first portion in a first plane perpendicular to a first direction toward the first semiconductor region from the first electrode. The plurality of second semiconductor regions are provided on the first portion. The plurality of second semiconductor regions are separated from each other in a second direction perpendicular to the first direction and in a third direction perpendicular to the first and second directions. The third semiconductor region is provided on a portion of the plurality of second semiconductor regions aligned in the third direction. The impurity concentration of the second conductivity type in the third semiconductor region is higher than the impurity concentration of the second conductivity type in the portion of the plurality of second semiconductor regions. The fourth semiconductor region is provided on the third semiconductor region. The gate electrode faces the third semiconductor region via a gate insulating layer. The plurality of fifth semiconductor regions are provided in the second portion and are aligned with the plurality of second semiconductor regions in the second direction. The plurality of fifth semiconductor regions are separated from each other in the second direction. The distance between adjacent fifth semiconductor regions is longer than the distance between adjacent second semiconductor regions. The plurality of sixth semiconductor regions are provided in the second portion and are aligned with the plurality of second semiconductor regions in the third direction. The plurality of sixth semiconductor regions are separated from each other in the second and third directions. The second electrode is provided on the third and fourth semiconductor regions. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a plan view showing a semiconductor device according to an embodiment. [Figure 2] Figure 2 is a perspective cross-sectional view including the section II-II in Figure 1. [Figure 3] Figure 3 is an enlarged plan view of part III of Figure 1. [Figure 4] Figure 4 is an enlarged plan view of part III of Figure 1. [Figure 5] Figure 5 is a VV cross-sectional view of Figures 3 and 4. [Figure 6] Figure 6 is a cross-sectional view taken along the line VI-VI in Figures 3 and 4. [Figure 7] Figure 7(a) is an enlarged cross-sectional view of section A in Figure 4. Figure 7(b) is an enlarged cross-sectional view of section B in Figure 4. [Figure 8] Figure 8 is a cross-sectional view showing the manufacturing process of a semiconductor device according to the embodiment. [Figure 9] Figure 9 is a plan view showing the manufacturing process of a semiconductor device according to an embodiment. [Figure 10] Figure 10 is a plan view showing the manufacturing process of a semiconductor device according to an embodiment. [Figure 11] Figure 11 is a plan view showing the manufacturing process of a semiconductor device according to an embodiment. [Figure 12] Figures 12(a) and 12(b) are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment. [Figure 13] Figure 13 is a plan view showing a part of a semiconductor device related to a reference example. [Figure 14] Figure 14 is a plan view showing a part of a semiconductor device according to a first modified embodiment. [Figure 15] Figure 15 is a plan view showing a part of a semiconductor device according to a second modified embodiment. [Modes for carrying out the invention]

[0007] The embodiments of the present invention will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes of the parts, etc., are not necessarily the same as those of reality. Furthermore, even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In this specification and each drawing, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the following description, n + and n - and p + and p, p - notation represents the relative level of the impurity concentration in each conductivity type. That is, the notation with a "+" indicates that the impurity concentration is relatively higher than the notation without either a "+" or a "-", and the notation with a "-" indicates that the impurity concentration is relatively lower than the notation without any. When both p-type impurities and n-type impurities are included in each region, these notations represent the relative level of the net impurity concentration after they compensate each other. For each embodiment described below, the p-type and n-type of each semiconductor region may be inverted to implement each embodiment.

[0008] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. FIG. 2 is a perspective cross-sectional view including the II-II cross section of FIG. 1. FIGS. 3 and 4 are plan views obtained by enlarging a portion III of FIG. 1. FIG. 5 is a V-V cross-sectional view of FIGS. 3 and 4. FIG. 6 is a VI-VI cross-sectional view of FIGS. 3 and 4. The semiconductor device 100 according to the embodiment is a MOSFET. As shown in FIGS. 1 to 6, the semiconductor device 100 includes an n - -type (first conductivity type) drift region 1 (first semiconductor region), a p - -type (second conductivity type) pillar region 2 (second semiconductor region), a p-type base region 3 (third semiconductor region), an n + -type source region 4 (fourth semiconductor region), a p - -type pillar region 5 (fifth semiconductor region), a p - -type pillar region 6 (sixth semiconductor region), a p - -type pillar region 7 (seventh semiconductor region), an n + -type contact region 8, an n + -type drain region 9, a gate electrode 10, a gate insulating layer 11, an insulating layer 15, a drain electrode 21 (first electrode), a source electrode 22 (second electrode), and a gate pad 23. In FIG. 3, the n + -type source region 4, the p + -type contact region 8, the insulating layer 15, and the source electrode 22 are omitted. In FIG. 4, the p-type base region 3, the n+ Shape source region 4, p + The contact area 8, gate insulating layer 11, insulating layer 15, and source electrode 22 are omitted.

[0009] In describing the embodiments, the XYZ Cartesian coordinate system is used. From the drain electrode 21 to n - The direction toward the drift region 1 is defined as the Z direction (first direction). The two directions perpendicular to the Z direction and mutually orthogonal are defined as the X direction (second direction) and the Y direction (third direction). Also, for the sake of explanation, from the drain electrode 21 to n - The direction toward the drift region 1 is called "up," and the opposite direction is called "down." These directions are relative to the drain electrode 21 and n - Based on its relative position to the shape drift region 1, it is independent of the direction of gravity.

[0010] As shown in Figure 1, a source electrode 22 and a gate pad 23 are provided on the upper surface of the semiconductor device 100. The source electrode 22 and the gate pad 23 are separated from each other and electrically isolated.

[0011] As shown in Figure 2, a drain electrode 21 is provided on the lower surface of the semiconductor device 100. + The drain region 9 is provided above the drain electrode 21 and is electrically connected to the drain electrode 21. - Shape drift region 1 is n + It is located above the drain region 9. - Shape drift region 1 is n + It is electrically connected to the drain electrode 21 via the drain region 9. - The concentration of n-type impurities in the shape drift region 1 is n + It is lower than the n-type impurity concentration in the drain region 9.

[0012] n -The drift region 1 includes a first portion 1a and a second portion 1b, as shown in Figures 1 to 6. The second portion 1b is located around the first portion 1a in the XY plane (first plane). The first portion 1a is located in the cell region. The cell region is the region where current mainly flows when the semiconductor device 100 is operating. The second portion 1b is located in the termination region. The termination region is the region where the depletion layer spreads toward the outer periphery of the semiconductor device 100 when the semiconductor device 100 is withstand voltage.

[0013] As shown in Figure 2, p - The shaped pillar region 2 is provided in the first part 1a. - Multiple shaped pillar regions 2 are provided in the X and Y directions. - The shaped pillar regions 2 are separated from each other. Part of the first part 1a and p - The shaped pillar regions 2 are arranged alternately in the X and Y directions. - The length of the shaped pillar region 2 in the Y direction is p - It is longer than the length of the shaped pillar region 2 in the X direction. - The length of the shaped pillar region 2 in the Y direction is equal to the length of adjacent p in the Y direction. - It is longer than the distance between two shaped pillar regions 2.

[0014] The p-shaped base region 3 consists of multiple p-shaped regions aligned in the Y direction. - It is located on top of the shaped pillar region 2. + Shape source region 4 and p + The contact region 8 is located on the p-shaped base region 3. The gate electrode 10 is n - Part of the shape drift region 1, the p-shaped base region 3, and n + It is provided on the shaped source region 4 via a gate insulating layer 11.

[0015] The source electrode 22 has a p-type base region 3, n + Shape source region 4, and p + Located above the shaped contact area 8, the p-shaped base area 3, n + Shape source region 4, and p +The gate electrode 10 and source electrode 22 are electrically connected to the contact region 8. The gate electrode 10 and source electrode 22 are electrically isolated from each other by the insulating layer 15.

[0016] As shown in Figures 3 to 5, p - The shaped pillar region 5 is provided in the second part 1b. - The shaped pillar region 5 is p in the X direction. - It is aligned with the shaped pillar region 2. - Multiple shaped pillar regions 5 are provided in the X and Y directions. - The shaped pillar regions 5 are separated from each other. Part of the second part 1b and p - The shaped pillar regions 5 are arranged alternately in the X and Y directions. - The length of the shaped pillar region 5 in the Y direction is p - It is longer than the length of the shaped pillar region 5 in the X direction. - The length of the shaped pillar region 5 in the Y direction is equal to the length of adjacent p in the Y direction. - The distance between the shaped pillar regions 5 is longer than the distance between them. As shown in Figure 4, adjacent p in the X direction - The distance D2x between two shaped pillar regions 5 is equal to the distance between adjacent p in the X direction. - The distance between the two shaped pillar regions 2 is longer than D1x.

[0017] As shown in Figures 3, 4, and 6, p - The shaped pillar region 6 is provided in the second part 1b. - The shaped pillar region 6 is p in the Y direction. - It is aligned with the shaped pillar region 2. - Multiple shaped pillar regions 6 are provided in the X and Y directions, and multiple p - The shaped pillar regions 6 are separated from each other. Part of the second part 1b and p - The shaped pillar regions 6 are arranged alternately in the X and Y directions.

[0018] As shown in Figures 3 and 4, p - The shaped pillar region 7 is provided in the second part 1b. - The shaped pillar region 7 is p in the Y direction.- Alongside the shaped pillar region 5, in the X direction, p - It is aligned with the shaped pillar region 6. - Multiple shaped pillar regions 7 are provided in the X direction and the Y direction, and multiple p - The shaped pillar regions 7 are separated from each other. Part of the second part 1b and p - The shaped pillar regions 7 are arranged alternately in the X and Y directions.

[0019] For example, p - Pillar region 2, p - Shaped pillar region 5, p - Pillar region 6, and p - The positions of the lower ends of each of the shaped pillar regions 7 in the Z direction are the same. In other words, the drain electrode 21 and p - Distance in the Z direction between the shaped pillar region 2 and the drain electrode 21 and p - Distance in the Z direction between the shaped pillar region 5 and the drain electrode 21 and p - The distance in the Z direction between the shaped pillar region 6 and the drain electrode 21 and p - The distances in the Z direction between the shaped pillar region 7 and the other are the same.

[0020] Figure 7(a) is an enlarged cross-sectional view of section A in Figure 4. Figure 7(b) is an enlarged cross-sectional view of section B in Figure 4. As mentioned above, p - The distance in the X direction between the shaped pillar regions 5 is p - The distance between the shaped pillar regions 2 in the X direction is longer than the distance between them in the X direction, and multiple p in the X and Y directions - If the shaped pillar region 6 is provided, the specific configuration of the semiconductor device 100 can be changed as appropriate. Here, referring to Figures 7(a) and 7(b), p - Shaped pillar region 5 and p - Let's explain a specific example regarding the shaped pillar region 6.

[0021] adjacent p in the X direction -The distance between the columnar regions 5 is preferably longer as it approaches the outer periphery of the semiconductor device 100. For example, as shown in FIG. 7(a), a plurality of p - columnar regions 5 are adjacent to each other in the X direction. p - columnar regions 5 include columnar regions 5a to 5c. p - Columnar region 5a is one of the plurality of p - columnar regions 5. p - Columnar region 5b is another one of the plurality of p - columnar regions 5. p - Columnar region 5c is yet another one of the plurality of p - columnar regions 5. p - Columnar region 5a is located between columnar region 5b and p - columnar region 5c in the X direction. p - Columnar region 5b is located between columnar region 2 and p - columnar region 5a in the X direction. p - columnar region 2 and p - columnar region 5a in the X direction. p - The distance D4x in the X direction between columnar region 5a and p - columnar region 5c is longer than the distance D3x in the X direction between columnar region 5a and p - columnar region 5b. p - columnar region 5b.

[0022] The length in the Y direction of each p - columnar region 6 is preferably shorter as it approaches the outer periphery of the semiconductor device 100. For example, as shown in FIG. 7(b), a plurality of p - columnar regions 6 are adjacent to each other in the Y direction. p - columnar regions 6 include columnar regions 6a to 6c. p - Columnar region 6a is one of the plurality of p - columnar regions 6. p - Columnar region 6b is another one of the plurality of p - columnar regions 6. p - Columnar region 6c is yet another one of the plurality of p - columnar regions 6. p -The shaped pillar region 6a is p in the Y direction. - Shape pillar region 6b and p - It is located between the shaped pillar region 6c and p - The shaped pillar region 6b is p in the Y direction. - Shape pillar region 2 and p - It is located between the shaped pillar region 6a and p - The length L1y of the shaped pillar region 6a in the Y direction is p - The length L2y in the Y direction of the shaped pillar region 6b is shorter than p - It is longer than the length L3y in the Y direction of the shaped pillar region 6c.

[0023] adjacent p in the Y direction - The distances between the shaped pillar regions 6 may be uniform or may differ from one another. Preferably, each p - The distance between the shaped pillar regions 6 is the same. For example, p - Pillar region 6a and p - The distance D1y in the Y direction between the shaped pillar region 6b and the other is p - Pillar region 6a and p - The distance D2y in the Y direction is the same as the distance between the shaped pillar region 6c and adjacent p in the X direction. - The distance D3x between two shaped pillar regions 6 is equal to the distance between adjacent p in the X direction. - It is preferable that the distance D1x between the two shaped pillar regions 2 is the same.

[0024] multiple p - The arrangement of the shaped pillar region 7 in the X direction is that multiple p - This is substantially the same as the arrangement of the shaped pillar region 5 in the X direction. That is, each p - The shaped pillar region 7 is any p - The shaped pillar region 5 is aligned in the Y direction. Adjacent to p in the X direction - The distance between the shaped pillar regions 7 increases as it approaches the outer periphery of the semiconductor device 100.

[0025] multiple p - The arrangement of the shaped pillar region 7 in the Y direction is that multiple p- This is substantially the same as the arrangement of the shaped pillar region 6 in the Y direction. That is, each p - The shaped pillar region 7 is any p - The shaped pillar region 6 is aligned in the X direction. Each p - The length of the shaped pillar region 7 in the Y direction becomes shorter as it approaches the outer periphery of the semiconductor device 100.

[0026] The semiconductor device 100 is n - Part of the shape drift region 1 and p - It has a superjunction structure in which shaped pillar regions are arranged alternately along the XY plane. Here, p - n adjacent to the shaped pillar region - A portion of the shape drift region 1, n - Also called the shaped pillar region. In a superjunction structure, any of the p - The amount of p-type impurities contained in the shaped pillar region and the adjacent n - It is desirable that the difference between the amount of n-type impurities contained in the morphological pillar region and the other impurities is small.

[0027] An example of the materials used for each component is described below. - Shape drift region 1, p - Pillar region 2, p-shaped base region 3, n + Shape source region 4, p - Shaped pillar region 5, p - Pillar region 6, p - Shaped pillar region 7, p + Shaped contact area 8, and n + The drain region 9 contains silicon, silicon carbide, gallium nitride, or gallium arsenide as the semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity. The gate electrode 10 contains a conductive material such as polysilicon. The gate insulating layer 11 and insulating layer 15 contain insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 21, source electrode 22, and gate pad 23 contain metals such as titanium, aluminum, or copper.

[0028] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the drain electrode 21 relative to the source electrode 22, a voltage above a threshold is applied to the gate electrode 10. This forms a channel (inversion layer) in the p-type base region 3, and the semiconductor device 100 turns on. Electrons pass through the channel from the source electrode 22 to n - The current flows into the p-type drift region 1. Subsequently, when the voltage applied to the gate electrode 10 falls below a threshold, the channel in the p-type base region 3 disappears, and the semiconductor device 100 turns off.

[0029] When a positive voltage is applied to the drain electrode 21 and the semiconductor device 100 switches from the ON state to the OFF state, n - Shape drift region 1 and p - Pillar region 2, p - Shaped pillar region 5, p - Pillar region 6, and p - A depletion layer spreads from each of the shaped pillar regions 7 and from the pn junction surface between them. This spreading of the depletion layer can improve the breakdown voltage of the semiconductor device 100. Alternatively, while maintaining the breakdown voltage of the semiconductor device 100, - By increasing the n-type impurity concentration in the drift region 1, the on-resistance of the semiconductor device 100 can be reduced.

[0030] Figures 8, 12(a), and 12(b) are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment. Figures 9 to 11 are plan views showing the manufacturing process of a semiconductor device according to an embodiment. Figure 8 shows the manufacturing process at the location of the VV cross-section shown in Figures 3 and 4. Figures 12(a) and 12(b) show the manufacturing process at the location of the II-II cross-section shown in Figure 1. First, n + Semiconductor layer 9x and n - A semiconductor substrate Sub containing a shaped semiconductor layer 1x is prepared. By reactive ion etching (RIE), as shown in Figure 8, n - Multiple apertures OP1 are formed on the upper surface of the semiconductor layer 1x. The multiple apertures OP1 are arranged in the X direction, and each aperture OP1 extends in the Y direction.

[0031] n - The semiconductor layer 1x includes a first portion 1a and a second portion 1b. Some of the multiple apertures OP1 pass through the first portion 1a. Other portions of the multiple apertures OP1 do not pass through the first portion 1a and are located only in the second portion 1b. The distance between apertures OP1 formed in the second portion 1b is longer than the distance between apertures OP1 that pass through the first portion 1a. The distance between apertures OP1 formed in the second portion 1b increases as it approaches the outer periphery of the semiconductor device 100. The width (length in the X direction) of each aperture OP1 is the same.

[0032] n - A semiconductor layer containing p-type impurities is epitaxially grown on a p-type semiconductor layer 1x. The opening OP1 is filled by the semiconductor layer. The upper surface of the semiconductor layer is flattened by chemical mechanical polishing (CMP). As a result, as shown in Figure 9, p-type impurities are placed inside the opening OP1 through the first portion 1a. - A shaped semiconductor layer 2x is formed. Inside the opening OP1 formed in the second portion 1b, p - A shaped semiconductor layer 5x is formed.

[0033] According to RIE, n - Part of the shaped semiconductor layer 1x, p - A portion of the shaped semiconductor layer 2x, and p - A portion of the shaped semiconductor layer 5x is removed. This creates a plurality of apertures OP2, as shown in Figure 10. The plurality of apertures OP2 are arranged in the Y direction, and each aperture OP2 extends in the X direction. The apertures OP2 are formed in the first portion 1a and the second portion 1b. In the second portion 1b, the distance between apertures OP2 in the Y direction becomes shorter as it approaches the outer periphery of the semiconductor device 100. The width (length in the Y direction) of each aperture OP2 is the same.

[0034] A semiconductor layer containing n-type impurities is epitaxially grown to fill the opening OP2. The top surface of the semiconductor layer is planarized by CMP. As a result, as shown in Figure 11, n-type impurities are embedded inside the opening OP2. - A shaped semiconductor layer 1y is formed. For example, n- The concentration of n-type impurities in the n-type semiconductor layer 1y is n - This is the same as the n-type impurity concentration in the semiconductor layer 1x. - The concentration of n-type impurities in the n-type semiconductor layer 1y is n - The n-type impurity concentration in the semiconductor layer 1x may be different from that of p. - Semiconductor layer 2x and p - The semiconductor layer 5x is n - The semiconductor layer 1y divides the material into multiple sections in the Y direction.

[0035] In the state shown in Figure 11, multiple separated p - A portion of the shaped semiconductor layer 2x is located in the first portion 1a. Multiple p - The portion of the semiconductor layer 2x is composed of multiple p - This corresponds to the shaped pillar region 2. Multiple divided p - Another portion of the shaped semiconductor layer 2x is located in the second portion 1b. - The other part of the shaped semiconductor layer 2x is a plurality of p - This corresponds to the shaped pillar region 6. Also, p - A portion of the shaped semiconductor layer 5x consists of multiple n - The semiconductor layer 1y divides the multiple divided p - The semiconductor layer 5x has multiple p - Shaped pillar region 5 and multiple p - This corresponds to the shaped pillar region 7.

[0036] Multiple p aligned in the Y direction - P-type impurities are ion-implanted into the upper part of the shaped pillar region 2 to form a p-type base region 3. By thermal oxidation, n - A gate insulating layer 11 is formed on the upper surface of the p-type semiconductor layer 1x and the upper surface of the p-type base region 3. A polysilicon layer is formed on the gate insulating layer 11 by chemical vapor deposition (CVD). A gate electrode 10 is formed by patterning the polysilicon layer. An insulating layer 15 covering the gate electrode 10 is formed by CVD. As shown in Figure 12(a), a portion of the insulating layer 15 and a portion of the gate insulating layer 11 are removed by RIE, exposing the upper surface of the p-type base region 3.

[0037] n-type impurities and p-type impurities are sequentially ion-implanted onto the upper surface of the p-type base region 3, + Shape source region 4 and p + A contact region 8 is formed. By CVD, sputtering, etc., n + Shape source region 4, p + A metal layer is formed on the contact area 8 and the insulating layer 15. The source electrode 22 and gate pad 23 are formed by patterning this metal layer. + n + The back surface of the shaped semiconductor layer 9x is ground. As shown in Figure 12(b), n is processed by CVD, sputtering, etc. + A drain electrode 21 is formed on the back surface of the shaped semiconductor layer 9x. Through the above steps, the semiconductor device 100 according to the embodiment is manufactured.

[0038] Figure 13 is a plan view showing a part of a semiconductor device related to a reference example. In the semiconductor device 100r shown in Figure 13, the first part 1a and the second part 1b have multiple p - A shaped pillar region 2 is provided. Each p - The lengths of the shaped pillar regions 2 in the X direction are the same. Adjacent p in the X direction - The distances between the two shaped pillar regions 2 are also the same.

[0039] The advantages of the embodiment will be explained. In Part 1a, p - The amount of p-type impurities in the shaped pillar region 2 is n - It is preferable that the amount of n-type impurities is slightly greater than the amount of n-type impurities in the shaped pillar region. In the first part 1a, p - The potential in the p-shaped pillar region 2 is substantially the same as the potential in the p-shaped base region 3. - The potential of the shaped pillar region 2 propagates easily in the Y direction where the pillar region is continuous in the second part 1b, but not easily in the X direction. Therefore, in the first part 1a, p - The amount of p-type impurities in the shaped pillar region 2 is n -If the amount of n-type impurities in the shaped pillar region is the same, the way the depletion layer spreads in the second part 1b differs in the X direction and the Y direction. As a result, the breakdown voltage of the semiconductor device 100 may decrease. In the first part 1a, p - The amount of p-type impurities in the shaped pillar region 2 is n - If the amount of n-type impurities is slightly greater than that of the pillar region, the depletion layer tends to spread in the X direction in the second part 1b. In the second part 1b, the difference between the spread of the depletion layer along the X direction and the spread of the depletion layer along the Y direction can be reduced, thereby improving the breakdown voltage of the semiconductor device 100.

[0040] On the other hand, when the semiconductor device 100 is turned off, the depletion layer spreads from the first part 1a to the second part 1b. During normal use of the semiconductor device 100, the depletion layer extends to the outermost p - It is desirable that the depletion layer does not reach the shaped pillar region. Under normal use, the depletion layer is at the outermost p - When the depletion layer reaches the pillar region, if a large voltage is temporarily applied to the semiconductor device 100, the depletion layer cannot expand any further. In that case, concentrated collisional ionization occurs at the outermost edge of the depletion layer, potentially destroying the semiconductor device 100.

[0041] In the semiconductor device 100r, p provided in the first part 1a - The amount of p-type impurities in the shaped pillar region 2 is n - If the amount of n-type impurities in the shaped pillar region is greater than the amount of n-type impurities in the second part 1b, then p - The amount of p-type impurities in the shaped pillar region 2 is n - The amount of n-type impurities in the shaped pillar region becomes greater than that of n-type impurities. In the second part 1b, p - The amount of p-type impurities in the shaped pillar region 2 is n - If the amount of n-type impurities is greater than that of the morphological pillar region, the expansion of the depletion layer in the second part 1b is promoted. The depletion layer is the outermost p - To avoid reaching the shaped pillar region, the size of the second part 1b needs to be increased. As a result, the semiconductor device 100r becomes larger.

[0042] Regarding this issue, in the semiconductor device 100 according to this embodiment, the second part 1b has p - Shaped pillar region 5 and p - A shaped pillar region 6 is provided. As shown in Figure 4, adjacent p - The distance D2x between two shaped pillar regions 5 is equal to the distance between adjacent p - The distance D2x is longer than the distance D1x between two shaped pillar regions 2. If the distance D2x is longer than the distance D1x, then n - The amount of n-type impurities in the morphological pillar region is p - This results in a higher amount of p-type impurities than in the shaped pillar region 2. As a result, the expansion of the depletion layer along the X direction can be suppressed in the second part 1b.

[0043] Also, p - Pillar region 2 and p - As shown in Figure 4, multiple shaped pillar regions 6 are provided in the X and Y directions. In other words, in the X and Y directions, p - Between the shaped pillar regions 2 and p - Between the shaped pillar regions 6, n - A shaped pillar region is provided. In this case, the p extends continuously in the Y direction, as in the semiconductor device 100r. - Compared to the case where the shaped pillar region 2 is provided, n in the second part 1b - The proportion of the shaped pillar region can be increased. As a result, in the first part 1a, p - The amount of p-type impurities in the shaped pillar region 2 is n - Even when the amount of n-type impurities is greater than that of the shaped pillar region, the expansion of the depletion layer along the Y direction in the second part 1b can be suppressed.

[0044] According to this embodiment, the difference in the extent of the depletion layer along the X direction and the extent of the depletion layer along the Y direction can be reduced while suppressing the extent of the depletion layer in the second portion 1b. As a result, the semiconductor device 100 can be miniaturized while maintaining the breakdown voltage of the semiconductor device 100.

[0045] adjacent p in the X direction -The distance between the shaped pillar regions 5 is preferably longer as it approaches the outer periphery of the semiconductor device 100. With this arrangement, as it approaches the outer periphery of the semiconductor device 100, - The amount of n-type impurities in the morphological pillar region can be increased. For example, p - The distance between the shaped pillar regions 5 is p - The distance between the two shaped pillar regions 2 is made longer, and p - Compared to the case where the distance between the shaped pillar regions 5 is made equal, this method suppresses the increase in electric field strength on the inner circumference side of the second portion 1b while also suppressing the spread of the depletion layer along the X direction in the second portion 1b.

[0046] p - The length L2x in the X direction of the shaped pillar region 5 is p - The length L1x in the X direction of the shaped pillar region 2 may be different from the length L2x, but it is preferable that it be the same as the length L1x, as shown in Figure 7(a). When the lengths L1x and L2x are the same, the widths of each opening OP1 shown in Figure 8 are also the same. When the widths of the openings OP1 are different, the variation in the depth of the openings OP1 tends to be large. By having the same width for each opening OP1, the variation in the depth of the openings OP1 can be suppressed. As a result, n - n-type impurity amount in the morphological pillar region, p - The amount of p-type impurities in the shaped pillar region 2, and p - This facilitates the control of the amount of p-type impurities in the pillar region 5. It also suppresses variations in the depletion layer's spread in the second portion 1b, improving the reliability of the semiconductor device 100. Furthermore, it improves the manufacturing yield of the semiconductor device 100.

[0047] each p - The length of the shaped pillar region 6 in the Y direction is preferably shorter towards the outer periphery of the semiconductor device 100. With this arrangement, the length of the shaped pillar region 6 is shorter towards the outer periphery of the semiconductor device 100. - The proportion of the number of shaped pillar regions can be increased. For example, each p -Compared to the case where the length of the shaped pillar region 6 is uniform in the Y direction, it is possible to suppress the increase in electric field strength on the inner circumference side of the second portion 1b while suppressing the spread of the depletion layer along the Y direction in the second portion 1b.

[0048] p adjacent to each other - It is preferable that the distance in the Y direction between the shaped pillar regions 6 be the same. For example, as shown in Figure 7(b), p - Pillar region 6a and p - The distance D1y between the shaped pillar region 6b is p - Pillar region 6a and p - The distance D2y between the shaped pillar region 6c is the same as the adjacent p - The distance in the Y direction between the shaped pillar regions 6 depends on the width of the opening OP2 shown in Figure 10. When distances D1y and D2y are the same, the widths of each opening OP2 are also the same. Having the same width for each opening OP2 suppresses variations in the depth of the openings OP2. As a result, n - n-type impurity amount and p in the shaped pillar region - This facilitates the control of the amount of p-type impurities in the pillar region 6. It also suppresses variations in the depletion layer's spread in the second portion 1b, improving the reliability of the semiconductor device 100. Furthermore, it improves the manufacturing yield of the semiconductor device 100.

[0049] Also, as shown in Figure 7(b), adjacent p in the X direction - The distance D3x between two shaped pillar regions 6 is equal to the distance between adjacent p in the X direction. - It is preferable that the distance D1x between the two shaped pillar regions 2 is the same. If the distance D3x and the distance D1x are the same, p - Shape pillar region 2 and p - The shaped pillar region 6 can be formed by a common opening OP1. This facilitates the manufacturing of the semiconductor device 100 and improves the manufacturing yield of the semiconductor device 100.

[0050] (First variation) Figure 14 is a plan view showing a part of a semiconductor device according to a first modified embodiment. In the semiconductor device 110 shown in Figure 14, adjacent p in the Y direction - The distance between the shaped pillar regions 6 increases as it approaches the outer periphery of the semiconductor device 110. - As the distance between the shaped pillar regions 6 increases, the n increases as you move towards the outer edge of the semiconductor device 110. - The amount of n-type impurities in the morphological pillar region is increasing. - The length of the shaped pillar region 6 in the Y direction is shorter towards the outer periphery of the semiconductor device 110. Or, each p - The length of the shaped pillar region 6 in the Y direction may be the same. The semiconductor device 110, like the semiconductor device 100, can suppress the spreading of the depletion layer along the Y direction in the second portion 1b.

[0051] However, adjacent p - If the distances between the shaped pillar regions 6 differ, it becomes necessary to make the widths of the openings OP2 shown in Figure 10 different. In this case, the variation in the depth of the openings OP2 may increase. - n-type impurity amount and p in the shaped pillar region - The difference between the amount of p-type impurities in the pillar region 6 tends to increase, and the variation in the extent of the depletion layer in the second part 1b tends to increase. Therefore, from the standpoint of reliability, adjacent p - It is preferable that the distance between the shaped pillar regions 6 is the same.

[0052] (Second variation) Figure 15 is a plan view showing a part of a semiconductor device according to a second modified embodiment. In the semiconductor device 120 shown in Figure 15, each of the first part 1a and the second part 1b includes an extended portion 1c. In the first part 1a, the extended portion 1c is adjacent to p in the Y direction. - It extends in the X direction between the shaped pillar regions 2. In the second part 1b, the extended portion 1c is adjacent to p in the Y direction. -The extended portion 1c extends in the X direction between the shaped pillar regions 6. The n-type impurity concentration in the extended portion 1c is different from the n-type impurity concentration in the other parts of the first portion 1a and different from the n-type impurity concentration in the other parts of the second portion 1b. For example, the n-type impurity concentration in the extended portion 1c is higher than the n-type impurity concentration in the other parts of the first portion 1a and higher than the n-type impurity concentration in the other parts of the second portion 1b. By providing an extended portion 1c with a high n-type impurity concentration in the first portion 1a, the on-resistance of the semiconductor device 100 can be reduced. Furthermore, by providing an extended portion 1c in the second portion 1b, the spreading of the depletion layer along the Y direction can be suppressed. The difference between the spreading of the depletion layer along the X direction and the spreading of the depletion layer along the Y direction can be made smaller, further improving the breakdown voltage of the semiconductor device 100.

[0053] The extended portion 1c is embedded in the opening OP2 in the process shown in Figure 11. - This corresponds to the semiconductor layer 1y. - By adjusting the n-type impurity concentration in the semiconductor layer 1y, the n-type impurity concentration in the extended portion 1c can be controlled.

[0054] Embodiments of the present invention include the following features. (Feature 1) First electrode and, A first semiconductor region having a first conductivity type provided on the first electrode, the first semiconductor region comprising a first portion and a second portion provided around the first portion on a first plane perpendicular to a first direction toward the first semiconductor region from the first electrode, The first portion is provided with a plurality of second semiconductor regions of a second conductivity type that are separated from each other in a second direction perpendicular to the first direction and in a third direction perpendicular to the first and second directions, A third semiconductor region of a second conductivity type is provided on a portion of the plurality of second semiconductor regions arranged in the third direction, and has a higher impurity concentration of the second conductivity type than the portion of the plurality of second semiconductor regions. A fourth semiconductor region of the first conductivity type is provided on the third semiconductor region, The gate electrode facing the third semiconductor region via the gate insulating layer, A plurality of fifth semiconductor regions of a second conductivity type provided in the second portion, which are arranged in the plurality of second semiconductor regions in the second direction and are separated from each other in the second direction, wherein the distance between adjacent fifth semiconductor regions is longer than the distance between adjacent second semiconductor regions, The second portion is provided with a plurality of sixth semiconductor regions of a second conductivity type that are arranged in the third direction alongside the plurality of second semiconductor regions and are separated from each other in the second and third directions, A second electrode provided on the third semiconductor region and the fourth semiconductor region, A semiconductor device equipped with the following features. (Feature 2) The semiconductor device according to feature 1, wherein the distance between adjacent fifth semiconductor regions in the second direction increases as it approaches the outer periphery of the semiconductor device. (Feature 3) One of the plurality of fifth semiconductor regions is adjacent to and located between another of the plurality of fifth semiconductor regions and yet another of the plurality of fifth semiconductor regions in the second direction. The other one of the plurality of fifth semiconductor regions is located in the second direction between one of the plurality of second semiconductor regions and the one of the plurality of fifth semiconductor regions. The semiconductor device according to feature 1 or 2, wherein the distance between one of the plurality of fifth semiconductor regions and yet another of the plurality of fifth semiconductor regions is longer than the distance between one of the plurality of fifth semiconductor regions and yet another of the plurality of fifth semiconductor regions. (Feature 4) The semiconductor device according to any one of features 1 to 3, wherein the length of one of the plurality of fifth semiconductor regions in the second direction is the same as the length of one of the plurality of second semiconductor regions in the second direction. (Feature 5) The semiconductor device according to any one of features 1 to 4, wherein the length of each of the plurality of sixth semiconductor regions in the third direction is shorter towards the outer periphery of the semiconductor device. (Feature 6) One of the plurality of sixth semiconductor regions is located in the third direction between another of the plurality of sixth semiconductor regions and yet another of the plurality of sixth semiconductor regions. The other one of the plurality of sixth semiconductor regions is located in the third direction between one of the plurality of second semiconductor regions and the one of the plurality of sixth semiconductor regions. The semiconductor device according to any one of features 1 to 5, wherein the length of one of the plurality of sixth semiconductor regions in the third direction is shorter than the length of the plurality of sixth semiconductor regions in another third direction and longer than the length of the plurality of sixth semiconductor regions in yet another third direction. (Feature 7) One of the plurality of sixth semiconductor regions is adjacent in the third direction to another of the plurality of sixth semiconductor regions and yet another of the plurality of sixth semiconductor regions, The semiconductor device according to feature 6, wherein the distance between one of the plurality of sixth semiconductor regions and another of the plurality of sixth semiconductor regions is the same as the distance between one of the plurality of sixth semiconductor regions and yet another of the plurality of sixth semiconductor regions. (Feature 8) The semiconductor device according to any one of features 1 to 7, wherein the distance between adjacent sixth semiconductor regions in the second direction is the same as the distance between adjacent second semiconductor regions in the second direction. (Feature 9) The second portion further comprises a plurality of seventh semiconductor regions of a second conductivity type, which are arranged in the third direction with respect to the plurality of fifth semiconductor regions and in the second direction with respect to the plurality of sixth semiconductor regions. The semiconductor device according to any one of features 1 to 8, wherein the plurality of seventh semiconductor regions are separated from each other in the second and third directions.

[0055] The relative levels of impurity concentrations between semiconductor regions in each embodiment described above can be confirmed, for example, using a scanning capacitance microscope (SCM). The carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between semiconductor regions can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS).

[0056] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of Symbols]

[0057] 1:n - shaped drift region, 1a: first part, 1b: second part, 1c: extension part, 1x,1y:n - Semiconductor layer, 2:p - Pillar region shape, 2x:p - 3: p-type semiconductor layer, 4: n-type base region + shape source area, 5,5a,5b,5c,6,6a,6b,6c,7:p - Pillar shape region, 5x:p - Semiconductor layer, 8:p + Shape of contact area, 9:n + Shape of drain region, 9x:n +Shape of semiconductor layer, 10: gate electrode, 11: gate insulating layer, 15: insulating layer, 21: drain electrode, 22: source electrode, 23: gate pad, 100, 100r, 110, 120: semiconductor device, D1x, D1y, D2x, D2y, D3x, D4x: distance, L1x, L2x, L1y, L2y, L3y: length, OP1, OP2: aperture, Sub: semiconductor substrate

Claims

1. First electrode and, A first semiconductor region having a first conductivity type, provided on the first electrode, comprising a first portion and a second portion provided around the first portion on a first plane perpendicular to a first direction toward the first semiconductor region from the first electrode, The first portion is provided with a plurality of second semiconductor regions of a second conductivity type that are separated from each other in a second direction perpendicular to the first direction and in a third direction perpendicular to the first and second directions, A third semiconductor region of a second conductivity type is provided on a portion of the plurality of second semiconductor regions arranged in the third direction, and has a higher impurity concentration of the second conductivity type than the portion of the plurality of second semiconductor regions. A fourth semiconductor region of a first conductivity type is provided on the third semiconductor region, The gate electrode facing the third semiconductor region via the gate insulating layer, A plurality of fifth semiconductor regions of a second conductivity type provided in the second portion, which are arranged in the plurality of second semiconductor regions in the second direction and are separated from each other in the second direction, wherein the distance between adjacent fifth semiconductor regions is longer than the distance between adjacent second semiconductor regions, The second portion is provided with a plurality of sixth semiconductor regions of a second conductivity type that are arranged in the third direction alongside the plurality of second semiconductor regions and are separated from each other in the second and third directions, A second electrode provided on the third semiconductor region and the fourth semiconductor region, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the distance between adjacent fifth semiconductor regions in the second direction increases as it approaches the outer periphery of the semiconductor device.

3. One of the plurality of fifth semiconductor regions is adjacent to and located between another of the plurality of fifth semiconductor regions and yet another of the plurality of fifth semiconductor regions in the second direction. The other one of the plurality of fifth semiconductor regions is located in the second direction between one of the plurality of second semiconductor regions and the one of the plurality of fifth semiconductor regions. The semiconductor device according to claim 1, wherein the distance between one of the plurality of fifth semiconductor regions and yet another of the plurality of fifth semiconductor regions is longer than the distance between one of the plurality of fifth semiconductor regions and yet another of the plurality of fifth semiconductor regions.

4. The semiconductor device according to claim 1, wherein the length of one of the plurality of fifth semiconductor regions in the second direction is the same as the length of one of the plurality of second semiconductor regions in the second direction.

5. The semiconductor device according to claim 1, wherein the length of each of the plurality of sixth semiconductor regions in the third direction is shorter towards the outer periphery of the semiconductor device.

6. One of the plurality of sixth semiconductor regions is located in the third direction between another of the plurality of sixth semiconductor regions and yet another of the plurality of sixth semiconductor regions. The other one of the plurality of sixth semiconductor regions is located in the third direction between one of the plurality of second semiconductor regions and the one of the plurality of sixth semiconductor regions. The semiconductor device according to claim 1, wherein the length of one of the plurality of sixth semiconductor regions in the third direction is shorter than the length of the plurality of sixth semiconductor regions in another third direction and longer than the length of the plurality of sixth semiconductor regions in yet another third direction.

7. One of the plurality of sixth semiconductor regions is adjacent in the third direction to another of the plurality of sixth semiconductor regions and yet another of the plurality of sixth semiconductor regions. The semiconductor device according to claim 6, wherein the distance between one of the plurality of sixth semiconductor regions and another of the plurality of sixth semiconductor regions is the same as the distance between one of the plurality of sixth semiconductor regions and yet another of the plurality of sixth semiconductor regions.

8. The semiconductor device according to claim 1, wherein the distance between adjacent sixth semiconductor regions in the second direction is the same as the distance between adjacent second semiconductor regions in the second direction.

9. The second portion further comprises a plurality of seventh semiconductor regions of a second conductivity type, which are arranged in the third direction with respect to the plurality of fifth semiconductor regions and in the second direction with respect to the plurality of sixth semiconductor regions. The semiconductor device according to any one of claims 1 to 8, wherein the plurality of seventh semiconductor regions are separated from each other in the second and third directions.

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