Manufacturing method for semiconductor devices

Abstract

Embodiments of the present invention provide semiconductor devices with improved durability or reliability. [Solution] The method for manufacturing a semiconductor device according to the embodiment includes a first step of applying a first load to a semiconductor element to press the bumps of the semiconductor element against a wiring substrate, and deforming the bumps by applying ultrasonic vibrations to the bumps without applying ultrasonic vibrations to the bumps or by applying ultrasonic vibrations of a first intensity to the bumps; and a second step of applying a second load to the semiconductor element after the first step to press the bumps of the semiconductor element against a wiring substrate, and joining the bumps to the pads of the wiring substrate by applying ultrasonic vibrations of a second intensity stronger than the first intensity to the bumps.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device.

Background Art

[0002] In a semiconductor device using a flip chip, ultrasonic vibration can be applied to connect the bumps of the substrate and the flip chip. In a semiconductor device using a NAND memory chip, a technique for bonding the flip chip and the substrate has also been studied.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a method for manufacturing a semiconductor device with improved reliability.

Means for Solving the Problems

[0005] The method for manufacturing a semiconductor device according to an embodiment includes: a first step of applying a first load to a semiconductor element to press the bumps of the semiconductor element against a wiring substrate, and deforming the bumps without applying ultrasonic vibration to the bumps or applying ultrasonic vibration with a first intensity to the bumps; and a second step, after the first step, of applying a second load to the semiconductor element to press the bumps of the semiconductor element against the wiring substrate, and applying ultrasonic vibration with a second intensity stronger than the first intensity to the bumps to bond the bumps to pads of the wiring substrate.

Brief Description of the Drawings

[0006] [Figure 1] A flowchart of the method for manufacturing a semiconductor device according to an embodiment. [Figure 2] A partial schematic diagram of a semiconductor device according to an embodiment. [Figure 3] Profiles of deformation amounts of load, ultrasonic intensity, and bump height in a semiconductor device manufacturing method of an embodiment. [Figure 4] A schematic diagram illustrating the manufacturing method of the semiconductor device according to the embodiment. [Figure 5] A schematic diagram illustrating the manufacturing method of the semiconductor device according to the embodiment. [Figure 6] A schematic diagram illustrating the manufacturing method of the semiconductor device according to the embodiment. [Figure 7] Profiles of deformation amounts of load, ultrasonic intensity, and bump height in a semiconductor device manufacturing method of an embodiment. [Figure 8] Profiles of deformation amounts of load, ultrasonic intensity, and bump height in a semiconductor device manufacturing method of an embodiment. [Figure 9] Profiles of deformation amounts of load, ultrasonic intensity, and bump height in a semiconductor device manufacturing method of an embodiment. [Figure 10] A schematic diagram illustrating the manufacturing method of the semiconductor device according to the embodiment. [Figure 11] A flowchart illustrating the manufacturing method of the semiconductor device according to the embodiment. [Figure 12] Profiles of deformation amounts of load, ultrasonic intensity, and bump height in a semiconductor device manufacturing method of an embodiment. [Figure 13] A schematic diagram illustrating the manufacturing method of the semiconductor device according to the embodiment. [Figure 14] A flowchart illustrating the manufacturing method of the semiconductor device according to the embodiment. [Figure 15] Profiles of deformation amount of load, ultrasonic intensity and bump height in a semiconductor device manufacturing method according to an embodiment. [Figure 16] A schematic diagram illustrating the manufacturing method of the semiconductor device according to the embodiment. [Figure 17] A flowchart illustrating the manufacturing method of the semiconductor device according to the embodiment. [Figure 18] Profiles of deformation amount of load, ultrasonic intensity and bump height in a semiconductor device manufacturing method according to an embodiment. [Figure 19]A schematic diagram illustrating the manufacturing method of the semiconductor device according to the embodiment. [Figure 20] A flowchart illustrating the manufacturing method of the semiconductor device according to the embodiment. [Figure 21] A schematic diagram illustrating the manufacturing method of the semiconductor device according to the embodiment. [Figure 22] A schematic diagram illustrating the manufacturing method of the semiconductor device according to the embodiment. [Modes for carrying out the invention]

[0007] The embodiments will be described below with reference to the drawings.

[0008] This specification provides multiple examples of how certain elements can be expressed. These examples are merely illustrative and do not preclude the use of other expressions for these elements. Furthermore, elements for which multiple expressions are not provided may also be expressed in different ways.

[0009] Furthermore, the drawings are schematic, and the relationship between thickness and planar dimensions, as well as the ratio of thicknesses of each layer, may differ from reality. Also, there may be discrepancies in the dimensional relationships and ratios between drawings. Additionally, some reference numerals are omitted in the drawings.

[0010] (First Embodiment) The first embodiment relates to a method for manufacturing a semiconductor device. Figure 1 shows a flowchart of the method for manufacturing a semiconductor device. Figure 2 shows a partial schematic diagram of the semiconductor device 100. The semiconductor device 100 of the embodiment is a semiconductor package equipped with semiconductor elements including one or more selected from the group consisting of an arithmetic unit, a control unit, and a memory device. All schematic diagrams of the embodiment are schematic cross-sectional views.

[0011] The semiconductor device 100 includes a wiring board 1 and a semiconductor element 2. The wiring board 1 has pads 11. The semiconductor element 2 has electrodes 21 and bumps 22.

[0012] The preferred numerical ranges and other characteristics of the first embodiment are also applicable to other embodiments.

[0013] The wiring board 1 is a support substrate for the semiconductor element 2. More specifically, the wiring board 1 is a multilayer wiring board. The wiring board 1 is electrically connected to the semiconductor element 2 via pads 11. The wiring board 1 is provided with hemispherical electrodes, such as solder balls (not shown), for connection to the outside of the semiconductor device 100.

[0014] The pad 11 is a conductor composed of Cu, Ni / Au, Ni / Pd / Au, etc. The width of the pad 11 is, for example, 20 [μm] to 30 [μm], and the height is, for example, 10 [μm] to 20 [μm].

[0015] The semiconductor element 2 is, for example, an arithmetic element or a memory element. The semiconductor element 2 is connected using a flip-chip method. Bumps 22 are provided on the electrodes 21 of the semiconductor element 2. The semiconductor element 2 is connected to the wiring board 1 via the bumps 22. Bump 22 is, for example, solder and contains one or more metals selected from the group consisting of Sn, Ag, Cu, Ni, Pb, Bi, and In.

[0016] Electrode 21 is, for example, a Cu pillar of semiconductor device 2.

[0017] The semiconductor element 2 is either a bare chip or a semiconductor element sealed in a mold. The bump 22 of the semiconductor element 2, which is either a bare chip or a semiconductor element sealed in a mold, is connected to the wiring board 1.

[0018] Preferably, the semiconductor device 100 also includes other semiconductor elements. If the semiconductor device 100 is a memory device, the other semiconductor elements are NAND memory chips, and semiconductor element 2 is a controller chip that controls the reading, writing, and erasing of the NAND memory chips.

[0019] The bump height H1 is the height of the bump 22 after carrying out the manufacturing method of the semiconductor device 100 according to the embodiment. The crushed height H2 is the height of the crushed bump 22 in the manufacturing method of the semiconductor device 100, including the first embodiment and other embodiments. It is preferable that the bump height H1 and the like be the height of the bump 22 on the central side of the semiconductor element 2, rather than on the outer periphery side.

[0020] The crushing height H2 is preferably 40% to 72% of H1, more preferably 48% to 64%, and even more preferably 52% to 60%.

[0021] The crushing height H2 is preferably 10 [μm] or more and 18 [μm] or less, more preferably 12 [μm] or more and 16 [μm] or less, and even more preferably 13 [μm] or more and 15 [μm] or less.

[0022] The crushing height H2 is preferably 40% to 72% of H1 and 10 [μm] to 18 [μm], more preferably 48% to 62% of H1 and 12 [μm] to 16 [μm], and even more preferably 52% to 60% of H1 and 13 [μm] to 15 [μm].

[0023] The manufacturing method for the semiconductor device 100 shown in the flowchart of Figure 1 comprises: a first step of applying a first load P1 to the semiconductor device 2 to press the bump 22 of the semiconductor device 2 against the wiring substrate 1, and deforming the bump 22 by applying ultrasonic vibrations of a first intensity US1 or without applying ultrasonic vibrations; and a second step of applying a second load P2 to the semiconductor device 2 after the first step to press the bump 22 of the semiconductor device 2 against the wiring substrate 1, and joining the bump 22 to the pad 11 of the wiring substrate 1 by applying ultrasonic vibrations of a second intensity US2 which is stronger than the first intensity US1.

[0024] It is preferable that flux be applied to the surface of the connection portion between the bump 22 and the pad 11 by means of applying flux to the bump 22 and / or the pad 11 before the first step.

[0025] In the first step, the bump 22 is mainly compressed, and in the second step, the bump 22 and the pad 11 are mainly joined together.

[0026] The method for manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to the partial schematic diagram of the semiconductor device 100 in Figure 2, the profiles of the load, ultrasonic intensity and bump height deformation in the manufacturing method of the semiconductor device 100 in Figure 3, and the schematic diagrams representing the manufacturing method of the semiconductor device 100 in Figures 4 to 6.

[0027] In the first embodiment, the first step will describe two methods separately: one in which ultrasonic vibration is not applied to the bump 22, and the second in which ultrasonic vibration of a first intensity US1 is applied to the bump 22. First, the first step will describe the method in which ultrasonic vibration is not applied to the bump 22, and then the second in which ultrasonic vibration of a first intensity US1 is applied to the bump 22.

[0028] In Figure 3, the horizontal axis of the profile represents the elapsed time during the process of joining the semiconductor element 2 and the wiring board 1. The vertical axis of the profile shows the intensity of the load applied to the semiconductor element 2 as a dashed line, the intensity of the ultrasonic vibration (US power) applied to the bump 22 as a thick solid line, and the height of the deformation of the bump 22 as a dashed line.

[0029] Figure 4 shows a schematic diagram of Figure 3 when the elapsed time is zero (A, the start of the first process). Figure 5 shows a schematic diagram of Figure 3 when the elapsed time is B (from the middle of the first process to the end of the first process). Figure 6 shows a schematic diagram of Figure 3 when the elapsed time is C (from the middle of the second process to the end of the second process). Figure 3 shows the height H at which the bump 22 deforms in the first process. A This represents the height H at which the bump 22 deforms in the second step. B This represents the total height H at which the bump 22 deforms during the processing of the embodiment. C It represents.

[0030] In the first embodiment, the total height H to which the bump 22 deforms from the start to the end of the process of deforming the bump 22 and joining the bump 22 and the pad 11. CThis is the total height (=H) at which the bump 22 deforms in the first and second steps. A +H B ) However, in other embodiments, the total height H of the bump 22 that deforms C This includes the height at which the bump 22 deforms in processes other than the first and second processes.

[0031] The first step will be described with reference to the schematic diagrams in Figures 4 and 5. In the first step, a load is applied to the semiconductor element 2 to press the bump 22 of the semiconductor element 2 against the wiring board 1, and the bump 22 is deformed without applying ultrasonic vibration. Before the first step, neither load nor ultrasonic vibration is applied. For example, it is preferable to use a collet that vibrates with ultrasound in the chuck portion for adsorbing the semiconductor element 2 and placing it on the wiring board 1. The load strength and ultrasonic vibration strength of the embodiment can be adjusted by the load strength applied using the collet and the output of the ultrasonic vibration.

[0032] As shown in the schematic diagram of Figure 4, the first step begins with the bump 22 and pad 11 aligned. A first load P1 is applied to the semiconductor element 2 in the direction in which the wiring board 1 and semiconductor element 2 face each other, and the bump 22 is deformed as shown in the schematic diagram of Figure 5. In the first step of the first embodiment, the bump 22 is deformed by applying a load without applying ultrasonic vibration to the bump 22.

[0033] The height of the bump 22 before deformation is, for example, between 20 [μm] and 40 [μm]. The diameter of the bump 22 before deformation is, for example, between 30 [μm] and 50 [μm]. The height of the bump 22 and other parameters can be measured by observing the distance between the semiconductor element 2 and the wiring board 1 during manufacturing.

[0034] The first load P1 changes continuously or intermittently over time from the start of the first process, and once it reaches the set load strength, it is kept constant, then weakened, or kept constant, or weakened. In the profile of Figure 3, once the first load P1 reaches the set load strength, it is kept constant, and then weakened to the second load P2 of the second process.

[0035] In the first step, the bump 22 deforms when the first load P1 is applied, so the distance H3 between the semiconductor element 2 and the wiring board 1 (the distance between the planar portion of the semiconductor element 2 and the planar portion of the wiring board 1) in Figure 4 shrinks to the distance H4 between the semiconductor element 2 and the wiring board 1 in Figure 5. The height H of the bump 22 changes in the first step. A This is [distance H3 at the start of the first process] - [distance H4 at the end of the first process].

[0036] The second step will be explained with reference to the schematic diagram in Figure 6. In the second step, a second load P2 is applied to the semiconductor element 2 to press the bump 22 of the semiconductor element 2 against the wiring board 1, and ultrasonic vibration of second intensity US2 is applied to the bump 22 to bond the bump 22 to the pad 11 of the wiring board 1. In the second step, both load and ultrasonic vibration are applied to bond the bump 22 of the semiconductor element 2 to the pad 11 of the wiring board 1.

[0037] The second load P2 applies, for example, a constant load from the start of the second process, to press the bump 22 of the semiconductor element 2 against the wiring board 1. The second load P2 may be a constant load or it may change. The maximum value of the second load P2 is set to be weaker than the maximum value of the first load P1.

[0038] Because the bump 22 is deformed in the first step, even if the same load strength as in the first step is applied in the second step, the height of the bump 22 that changes in the second step will be smaller than the height of the bump 22 that changes in the first step.

[0039] In the second step, ultrasonic vibration of the second intensity US2 is applied to the bump 22 to heat the bump 22, raising the processing point temperature between the bump 22 and the pad 11 to join the bump 22 and the pad 11.

[0040] The ultrasonic vibration applied to the bump 22 is preferably applied to the bump 22 from the semiconductor element 2 side.

[0041] The second intensity US2 changes such that the intensity increases preferably linearly over time from the start of the second step. When the set intensity is reached, the intensity of the ultrasonic vibration is kept constant, or after keeping the intensity of the ultrasonic vibration constant, the intensity of the ultrasonic vibration is weakened. In the second step, ultrasonic vibration may be applied at the intensity of the maximum value of the second intensity US2 from the start of the second step.

[0042] In the second step, the bump 22 may be deformed by applying the ultrasonic vibration of the second intensity US2 and the second load P2. The distance (H4) between the semiconductor element 2 and the wiring board 1 in FIG. 5 shrinks to the distance (H5) between the semiconductor element 2 and the wiring board 1 in FIG. 6. The height H of the bump 22 that changes in the second step B is [distance H4 at the end of the first step] - [distance H5 at the end of the second step]. The height H of the bump 22 that changes in the second step B may be zero.

[0043] Regarding the method of applying the ultrasonic vibration of the first intensity US1 to the bump 22, reference will be made to the profiles of the load, ultrasonic intensity, and amount of deformation of the bump height in the manufacturing method of the semiconductor device 100 shown in FIGS. 7, 8, and 9 and the schematic diagrams showing the manufacturing method of the semiconductor device 100 in FIG. 10 for explanation.

[0044] The profile in FIG. 7 is different from the profile in FIG. 3 in that ultrasonic vibration of the first intensity US1 is applied to the bump 22 in the first step. Except for the ultrasonic vibration in the first step, the profiles in FIG. 3 and the profile in FIG. 7 are the same.

[0045] The profile in Figure 8 is a modified version of the profile in Figure 7. Except for the ultrasonic vibration in the first step, the profiles in Figure 7 and Figure 8 are identical.

[0046] The profile in Figure 9 is a modified version of the profile in Figure 7. Except for the ultrasonic vibration in the first step, the profiles in Figure 7 and Figure 9 are identical.

[0047] In the first step, as shown in the schematic diagram of Figure 10, a first load P1 is applied to the semiconductor element 2 while applying ultrasonic vibration of first intensity US1 to the bump 22, pressing the bump 22 of the semiconductor element 2 against the wiring board 1 and deforming the bump 22.

[0048] In the first step, by applying a first load P1 while applying ultrasonic vibration of first intensity US1 to the bump 22, the bump 22 deforms, and the distance H3 between the semiconductor element 2 and the wiring board 1 in Figure 4 shrinks to the distance H4 between the semiconductor element 2 and the wiring board 1 in Figure 10. The height H of the bump 22 changes in the first step. A This is [distance H3 at the start of the first process] - [distance H4 at the end of the first process (Figure 10)].

[0049] The first intensity US1 changes continuously or intermittently over time from the start of the first process so that the ultrasonic vibration increases. When the set ultrasonic vibration intensity is reached, the first process is terminated, or the ultrasonic vibration intensity is kept constant and then decreased, or the ultrasonic vibration intensity is kept constant or decreased. The first intensity US1 may also be a constant intensity that does not change or substantially changes over time. In the profile of Figure 7, the first intensity US1 shows a linear increase in ultrasonic vibration.

[0050] As a variation of the profile in Figure 7, ultrasonic vibrations of a first intensity US1, which are weaker than the second intensity US2 in the second step, may be applied to the bump 22, as shown in the profile in Figure 8. By applying a constant, weak first intensity US1 in the first step, it is possible to further strengthen the bond.

[0051] Furthermore, as shown in the profile of Figure 9, ultrasonic vibration of the first intensity US1 may be applied before the first step, i.e., before the first load P1 is applied. The time for applying ultrasonic vibration of the first intensity to the bump 22 before applying the first load P1 in the first step should be 0.1 [s] or more and 1.0 [s] or less. By applying ultrasonic vibration of the first intensity US1 before starting to apply the first load P1 in the first step, it is possible to further strengthen the joint. When applying ultrasonic vibration to the bump 22 in the first step with the profile of Figure 9, it is preferable to apply ultrasonic vibration of the first intensity US1 to the bump without applying the first load P1 before applying the first load.

[0052] It is preferable that the first load P1 is stronger than the second load P2 (the integral value of the first load P1 is greater than the integral value of the second load P2).

[0053] The maximum value of the first load P1 is preferably 100% to 250% of the maximum value of the second load P2, more preferably 110% to 200%, and even more preferably 120% to 140%.

[0054] It is preferable that the second ultrasonic vibration intensity US2 of the second step is stronger than the first ultrasonic vibration intensity US1 of the first step (i.e., the integrated value of the ultrasonic vibration intensity of the second step US2 is greater than the integrated value of the ultrasonic vibration intensity of the first step US1). It is preferable that the integrated value of the ultrasonic vibration intensity of the first step US1 is between 1500% and 2000% of the integrated value of the ultrasonic vibration intensity of the second step US2.

[0055] The maximum value of the first intensity US1 is preferably greater than 0% of the maximum value of the second intensity US2 and 70% or less, more preferably between 0% and 50%, and even more preferably between 0% and 30%.

[0056] The average value of the first intensity US1 is preferably greater than 0% of the average value of the second intensity US2 and 70% or less, more preferably between 0% and 50%, and more preferably between 0% and 30%.

[0057] It is preferable to significantly deform the bump 22 in the first step, where the first load P1 is a strong load and ultrasonic vibration is not applied or a first strength US1 ultrasonic vibration with low intensity is applied. By significantly deforming the bump 22 in the first step, since ultrasonic vibration is not applied or only weak ultrasonic vibration is applied, it is possible to suppress the formation of protrusions and other features that tend to form on the surface due to ultrasonic vibration in the first step.

[0058] For example, if a load that deforms the bump 22 and strong ultrasonic vibrations for bonding are applied to the bump 22 simultaneously, the shape of the bump 22 will change significantly, making it easy for the bump 22 to come into contact with the prepreg on the surface of the wiring board 1, or for large protrusions to form on the surface of the bump 22.

[0059] When the bump 22 comes into contact with the prepreg on the surface of the wiring board 1, a short circuit will not occur because the prepreg is an insulator. However, ultrasonic vibrations will be more easily transmitted to the wiring board 1, making it difficult for the intended ultrasonic vibrations to be sufficiently transmitted to the bump 22, which may result in insufficient bonding between the bump 22 and the pad 11. Insufficient bonding can lead to reduced yield and decreased reliability.

[0060] Furthermore, if strong ultrasonic vibrations are applied while a strong load that significantly deforms the bump 22 is being applied, large protrusions are likely to form on the surface of the bump 22, which is made of solder, for example. When large protrusions form on the bump 22, the bumps 22 may come into contact with each other, causing a short circuit. If the bump 22 is short-circuited or prone to short-circuiting, it can lead to reduced retention and decreased reliability.

[0061] The height H of the bump 22 changes in the first step. A The total height (H) at which the bump 22 deforms in the first and second steps is... A +H B It is preferable that it be 30% or more, more preferably 50% or more, and even more preferably 60% or more.

[0062] The height H of the bump 22 changes in the first step. A The total height (H) at which the bump 22 deforms in the first and second steps is... A +H B Preferably, it is 30% or more and 100% or less of ), more preferably 50% or more and 100% or less, and even more preferably 60% or more and 100% or less.

[0063] The height H of the bump 22 changes in the first step. A The total height (H) at which the bump 22 deforms in the first and second steps is... A +H B Preferably, the amount is 30% to 95%, more preferably 50% to 95%, and even more preferably 60% to 95%.

[0064] The height H of the deformed bump 22 in the second step B In the first step, the height H of the bump 22 that deforms is... A It is preferable that it be between 0% and 200%, more preferably between 0% and 100%, and even more preferably between 0% and 75%.

[0065] The height H of the deformed bump 22 in the second step B In the first step, the height H of the bump 22 that deforms is... A It is preferable that it is greater than 0% and 200% or less, more preferably greater than 0% and 100% or less, and even more preferably greater than 0% and 75% or less.

[0066] In the first and second steps, the temperature of the bump 22 is preferably below the melting point of the bump 22. The temperature of the bump 22 in the second step is preferably higher than the temperature of the bump 22 in the first step.

[0067] In the first step, where ultrasonic vibrations are not applied to the bump 22 or only a weak first-intensity ultrasonic vibration (US1) is applied to the bump 22, the bump 22 is deformed significantly. This reduces the deformation height of the bump 22 in the second step, and even when a strong second-intensity ultrasonic vibration (US2) is applied to the bump 22, unintended deformation of the bump 22 can be suppressed.

[0068] In this embodiment, the process is divided into a first step, which mainly crushes the bump 22, and a second step, which mainly joins the bump 22 to the pad 11. This allows for the suppression of unintended large deformations of the bump 22 in both the first and second steps, contributing to improved yield and reliability.

[0069] (Second Embodiment) The second embodiment relates to a method for manufacturing a semiconductor device 100. The second embodiment is a configuration in which a third step is added to the method for manufacturing the semiconductor device 100 of the first embodiment. Details common to both the second and first embodiments will not be explained.

[0070] Figure 11 shows a flowchart of the manufacturing method for the semiconductor device 100. The manufacturing method for the semiconductor device 100 of the second embodiment further includes a third step before the first step, in which a third load P3 is applied to the semiconductor element 2 to press the bump 22 of the semiconductor element 2 against the wiring substrate 1, and ultrasonic vibrations of a third intensity US3, which are weaker than the second intensity US2, are applied to the bump 22 to deform the bump 22.

[0071] It is preferable that flux be applied to the surface of the connection between the bump 22 and the pad 11 by means of applying flux to the bump 22 and / or the pad 11 before the third step.

[0072] The method for manufacturing the semiconductor device 100 according to the second embodiment will be explained with reference to the load, ultrasonic intensity, and bump height deformation profiles in the manufacturing method of the semiconductor device 100 shown in Figure 12, and the schematic diagram representing the manufacturing method of the semiconductor device 100 shown in Figure 13. The load, ultrasonic intensity, and bump height deformation profiles in the manufacturing method of the semiconductor device 100 shown in Figure 12 also show the load, ultrasonic intensity, and bump height deformation profiles for the third step.

[0073] Figure 13 shows a schematic diagram of the elapsed time in Figure 12 when the time is E (from the middle of the third process to its completion). Figure 12 shows the height H at which the bump 22 deforms in the first process. A In the second step, the height H at which the bump 22 deforms. B In the third step, the height H at which the bump 22 deforms. D In the processing of the second embodiment, the total height H of the bump 22 that deforms is C (=H A +H B +H D This represents ).

[0074] The third step begins with the bump 22 and pad 11 aligned as shown in the schematic diagram in Figure 4. Then, a third load P3 is applied to the semiconductor element 2 in the direction in which the wiring board 1 and semiconductor element 2 face each other, and ultrasonic vibrations of a third intensity US3 are applied to the bump 22 to deform the bump 22.

[0075] The third load P3 changes continuously or intermittently over time from the start of the third process, and once it reaches the set load strength, the third process is terminated, or the load strength is kept constant and then reduced, or the load strength is kept constant or reduced. In the profile of Figure 12, the third load P3 increases linearly until it reaches the strength of the first load P1.

[0076] The third intensity US3 changes continuously or intermittently over time from the start of the third process, increasing the ultrasonic vibration. Once the set ultrasonic vibration intensity is reached, the third process is terminated, or the ultrasonic vibration intensity is kept constant and then decreased, or the ultrasonic vibration intensity is kept constant or decreased. In the profile of Figure 12, the third intensity US3 shows a linear increase in ultrasonic vibration.

[0077] In the third step shown in the profile of Figure 12, ultrasonic vibrations of a constant intensity may be applied, as in the first step of the profile of Figure 8. Specifically, in the third step, ultrasonic vibrations of a constant intensity, third intensity US3, may be applied to the bump 22.

[0078] In the third step shown in the profile of Figure 12, ultrasonic vibration of a constant intensity may be applied, as in the first step of the profile of Figure 9. Specifically, in the third step, ultrasonic vibration of a constant third intensity US3 may be applied to the bump 22 before applying the third load P3.

[0079] In the third step, the bump 22 deforms when the third load P3 is applied, so the distance H3 between the semiconductor element 2 and the wiring board 1 in Figure 4 shrinks to the distance H6 between the semiconductor element 2 and the wiring board 1 in Figure 13. The height H of the bump 22 changes in the third step. D This is [distance H3 at the start of the third process] - [distance H6 at the end of the third process].

[0080] The height H of the bump 22 changes in the first step, which is performed after the third step. D This is [distance H6 at the start of the first process] - [distance H4 at the end of the first process].

[0081] The maximum value of the third load P3 is preferably smaller than the maximum value of the first load P1. The maximum value of the third load P3 is preferably 10% to 60% of the maximum value of the first load P1, more preferably 20% to 50%, and even more preferably 25% to 45%.

[0082] The maximum value of the third load P3 is preferably smaller than the maximum value of the second load P2. The maximum value of the third load P3 is preferably 20% to 80% of the maximum value of the second load P2, more preferably 30% to 70%, and even more preferably 60% to 40%.

[0083] The maximum value of the third intensity US3 is preferably 400% to 900% of the maximum value of the first intensity US1, more preferably 500% to 800%, and even more preferably 600% to 700%.

[0084] The maximum value of the third intensity US3 is preferably greater than 0% of the maximum value of the second intensity US2 and 100% or less, more preferably between 0% and 75%, and even more preferably between 0% and 50%.

[0085] The average value of the third intensity US3 is preferably 400% to 900% of the first intensity US1, more preferably 500% to 800%, and even more preferably 600% to 700%.

[0086] The average value of the third intensity US3 is preferably greater than 0% of the average value of the second intensity US2 and 70% or less, more preferably between 0% and 75%, and most preferably between 0% and 50%.

[0087] The height H of the bump 22 changes in the third step. D The total height (H) at which the bump 22 deforms in the first, second, and third steps is... A +H B+ H D It is preferable that it be 50% or less, more preferably 30% or less, and even more preferably 20% or less.

[0088] The height H of the bump 22 changes in the third step. D The total height (H) at which the bump 22 deforms in the first, second, and third steps is... A +H B+ H DPreferably, the amount is 5% to 50%, more preferably 5% to 30%, and even more preferably 5% to 20%.

[0089] The height H of the bump 22 changes in the third step. D This is the height (H) at which bump 22 deforms in the first step. A Preferably, the amount is 5% to 50%, more preferably 5% to 30%, and even more preferably 5% to 20%.

[0090] In the first, second, and third steps, the temperature of the bump 22 is preferably below the melting point of the bump 22. The temperature of the bump 22 in the second step is preferably higher than the temperature of the bump 22 in the first step.

[0091] It is preferable that the third load P3 is a weak load and that the bump 22 is slightly deformed in the third step of applying ultrasonic vibrations of a third strength US3 which have low strength. By weakly joining the bump 22 and the pad 11 before the first step of significantly deforming the bump 22, the bump 22 and the pad 11 can be joined more reliably in the subsequent steps.

[0092] (Third embodiment) The third embodiment relates to a method for manufacturing a semiconductor device 100. The third embodiment is a configuration in which a fourth step is added to the method for manufacturing the semiconductor device 100 of the first embodiment. The fourth step can also be performed after the second step of the second embodiment. Details common to the third embodiment, the first embodiment, and the second embodiment will not be explained.

[0093] Figure 14 shows a flowchart of the manufacturing method for the semiconductor device 100. The manufacturing method for the semiconductor device 100 of the third embodiment further includes a fourth step after the second step, in which a fourth load P4 is applied to the semiconductor element 2 to press the bump 22 of the semiconductor element 2 against the wiring substrate 1, and the bump 22 is deformed without applying ultrasonic vibration to the bump 22.

[0094] The manufacturing method for the semiconductor device 100 according to the third embodiment will be described with reference to the load, ultrasonic intensity, and bump height deformation profiles in the manufacturing method of the semiconductor device 100 shown in Figure 15, and the schematic diagram representing the manufacturing method of the semiconductor device 100 shown in Figure 16. The load, ultrasonic intensity, and bump height deformation profiles in the manufacturing method of the semiconductor device 100 shown in Figure 15 also show the load, ultrasonic intensity, and bump height deformation profiles for the fourth step.

[0095] Figure 16 shows a schematic diagram of the elapsed time in Figure 15 when the time is F (from the start to the end of the fourth process). Figure 15 shows the height H at which the bump 22 deforms in the first process. A In the second step, the height H at which the bump 22 deforms. B In the fourth step, the height H at which the bump 22 deforms E In the processing of the third embodiment, the total height H of the bump 22 that deforms is C (=H A +H B +H E This represents ).

[0096] The fourth step begins from the end of the second step. In the fourth step, a fourth load P4 is applied to the semiconductor element 2 to press the bump 22 of the semiconductor element 2 against the wiring board 1, and the bump 22 is deformed without applying ultrasonic vibration to the bump 22.

[0097] The fourth load P4 changes continuously or intermittently over time from the start of the fourth process, and once it reaches the set load strength, the fourth process is terminated, or the load strength is kept constant and then reduced, or the load strength is kept constant or reduced. In the profile of Figure 15, the fourth load P4 increases linearly from the strength of the second load P2.

[0098] In the fourth step, the bump 22 deforms when the fourth load P4 is applied, so the height of the bump 22 that was joined to the pad 11 in the second step is further compressed. The height H of the bump 22 changes in the fourth step. E This is [distance H5 at the end of the second process] - [distance H7 at the end of the fourth process].

[0099] The maximum value of the fourth load P4 is preferably greater than the maximum value of the first load P1. The maximum value of the fourth load P4 is preferably 80% to 250% of the maximum value of the first load P1, more preferably 90% to 200%, and even more preferably 100% to 150%.

[0100] The average value of the fourth load P4 is preferably smaller than the average value of the first load P1. The average value of the fourth load P4 is preferably 80% to 250% of the average value of the first load P1, more preferably 90% to 200%, and even more preferably 100% to 150%.

[0101] The maximum value of the fourth load P4 is preferably greater than the maximum value of the second load P2. The maximum value of the fourth load P4 is preferably 300% to 1200% of the maximum value of the second load P2, more preferably 500% to 1000%, and even more preferably 600% to 900%.

[0102] The average value of the fourth load P4 is preferably greater than the average value of the second load P2. The average value of the fourth load P4 is preferably 300% to 1200% of the average value of the second load P2, more preferably 500% to 1000%, and even more preferably 600% to 900%.

[0103] In the fourth step, it is preferable not to apply ultrasonic vibration to the bump 22.

[0104] In the third embodiment, the height H at which the bump 22 deforms in the second step is B The particle size is preferably 0 [μm] to 7 [μm], more preferably 0 [μm] to 5 [μm], and even more preferably 0 [μm] to 3 [μm].

[0105] The height H of the bump 22 changes in the fourth step. EThe total height (H) at which the bump 22 deforms in the first, second, and fourth steps is... A +H B+ H E It is preferable that it be less than 50%, more preferably 30% or less, and even more preferably 20% or less.

[0106] The height H of the bump 22 changes in the fourth step. E The total height (H) at which the bump 22 deforms in the first, second, and fourth steps is... A +H B+ H E Preferably, it is 5% or more but less than 50%, more preferably 5% or more but 30%, and even more preferably 5% or more but 20%.

[0107] The height H of the bump 22 changes in the fourth step. E This is the height (H) at which bump 22 deforms in the first step. A Preferably, it is 5% or more but less than 50%, more preferably 5% or more but 30%, and even more preferably 5% or more but 20%.

[0108] In the first, second, and fourth steps, the temperature of the bump 22 is preferably below the melting point of the bump 22. The temperature of the bump 22 in the second step is preferably higher than the temperature of the bump 22 in the first step and higher than the temperature of the bump 22 in the fourth step.

[0109] It is preferable that the fourth load P4 is a strong load that slightly deforms the bump 22. By further compressing the bump 22 without applying ultrasonic vibration after joining the bump 22, the bump 22 and pad 11 can be joined and deformed with greater reliability.

[0110] (Fourth Embodiment) The fourth embodiment relates to a method for manufacturing a semiconductor device 100. The fourth embodiment is a configuration in which a fifth step is added to the method for manufacturing the semiconductor device 100 of the first embodiment. The fifth step can also be performed after the second step of the second embodiment. The fifth step can also be performed before and / or after the fourth step of the third embodiment. Details common to the fourth embodiment and the first to third embodiments will not be explained.

[0111] Figure 17 shows a flowchart of the manufacturing method for the semiconductor device 100. The manufacturing method for the semiconductor device 100 of the fourth embodiment further includes a fifth step after the second step, in which a fifth load P5 is applied to the semiconductor element 2 to press the bump 22 of the semiconductor element 2 against the wiring substrate 1, and ultrasonic vibration of a fourth intensity US4 is applied to the bump 22 to deform the bump 22.

[0112] The manufacturing method for the semiconductor device 100 according to the fourth embodiment will be described with reference to the load, ultrasonic intensity, and bump height deformation profiles in the manufacturing method of the semiconductor device 100 shown in Figure 18, and the schematic diagram representing the manufacturing method of the semiconductor device 100 shown in Figure 19. The load, ultrasonic intensity, and bump height deformation profiles in the manufacturing method of the semiconductor device 100 shown in Figure 18 also show the load, ultrasonic intensity, and bump height deformation profiles for the fifth step.

[0113] Figure 19 shows a schematic diagram of the elapsed time in Figure 18 when the time is G (from the start to the end of the fourth process). Figure 18 shows the height H at which the bump 22 deforms in the first process. A In the second step, the height H at which the bump 22 deforms. B In the fifth step, the height H at which the bump 22 deforms F In the processing of the third embodiment, the total height H of the bump 22 that deforms is C (=H A +H B +H F This represents ).

[0114] Step 5 begins from the end of Step 2. In Step 5, a fourth load P4 is applied to the semiconductor element 2 to press the bump 22 of the semiconductor element 2 against the wiring board 1, and ultrasonic vibrations of a fourth intensity US4 are applied to the bump 22 to deform the bump 22.

[0115] The fifth load P5 changes continuously or intermittently over time from the start of the fifth process, and once it reaches the set load strength, the fifth process is terminated, or the load strength is kept constant and then reduced, or the load strength is kept constant or reduced. In the profile of Figure 18, the fifth load P5 increases linearly from the strength of the second load P2.

[0116] The fourth intensity US4 changes continuously or intermittently over time from the start of the fifth process, increasing the ultrasonic vibration. Once the set ultrasonic vibration intensity is reached, the fifth process is terminated, or the ultrasonic vibration intensity is kept constant and then decreased, or the ultrasonic vibration intensity is kept constant or decreased. In the profile of Figure 18, the ultrasonic vibration of the fourth intensity US4 increases linearly from the intensity of the second intensity US2.

[0117] In the fifth step, the bump 22 deforms when the fifth load P5 is applied, so the height of the bump 22 that was joined to the pad 11 in the second step is further compressed. The height H of the bump 22 changes in the fifth step. F This is [distance H5 at the end of the second process] - [distance H8 at the end of the fifth process].

[0118] The maximum value of the fifth load P5 is preferably greater than the maximum value of the first load P1. The maximum value of the fifth load P5 is preferably 40% to 120% of the maximum value of the first load P1, more preferably 60% to 100%, and even more preferably 70% to 90%.

[0119] The average value of the fifth load P5 is preferably smaller than the average value of the first load P1. The average value of the fifth load P5 is preferably 40% to 120% of the average value of the first load P1, more preferably 60% to 100%, and even more preferably 70% to 90%.

[0120] The maximum value of the fifth load P5 is preferably greater than the maximum value of the second load P2. The maximum value of the fifth load P5 is preferably 100% to 600% of the maximum value of the second load P2, more preferably 200% to 500%, and even more preferably 250% to 450%.

[0121] The average value of the fifth load P5 is preferably greater than the average value of the second load P2. The average value of the fifth load P5 is preferably 100% to 600% of the average value of the second load P2, more preferably 200% to 500%, and even more preferably 250% to 450%.

[0122] The maximum value of the fourth intensity US4 is preferably 800% to 1700% of the maximum value of the first intensity US1, more preferably 1000% to 1500%, and even more preferably 1100% to 1400%.

[0123] The maximum value of the fourth intensity US4 is preferably 70% to 130% of the maximum value of the second intensity US2, more preferably 80% to 120%, and even more preferably 90% to 110%.

[0124] The average value of the fourth intensity US4 is preferably 800% to 1700% of the first intensity US1, more preferably 1000% to 1500%, and even more preferably 1100% to 1400%.

[0125] The average value of the fourth intensity US4 is preferably 70% to 130% of the average value of the second intensity US2, more preferably 80% to 120%, and even more preferably 90% to 110%.

[0126] In the fourth embodiment, the height H at which the bump 22 deforms in the second step is B The particle size is preferably 0 [μm] to 7 [μm], more preferably 0 [μm] to 5 [μm], and even more preferably 0 [μm] to 3 [μm].

[0127] The height H of bump 22 changes in the 5th step. F The total height (H) at which the bump 22 deforms in the first, second, and fifth steps is... A +H B+ H F It is preferable that it be less than 50%, more preferably 30% or less, and even more preferably 20% or less.

[0128] The height H of bump 22 changes in the 5th step. F The total height (H) at which the bump 22 deforms in the first, second, and fifth steps is... A +H B+ H F Preferably, it is 5% or more but less than 50%, more preferably 5% or more but 30%, and even more preferably 5% or more but 20%.

[0129] The height H of bump 22 changes in the 5th step. FA This is the height (H) at which bump 22 deforms in the first step. A Preferably, it is 5% or more but less than 50%, more preferably 5% or more but 30%, and even more preferably 5% or more but 20%.

[0130] In the first, second, and fifth steps, the temperature of the bump 22 is preferably below the melting point of the bump 22. The temperature of the bump 22 in the second step and the temperature of the bump 22 in the fifth step are preferably higher than the temperature of the bump 22 in the first step.

[0131] It is preferable that the fifth load P5 is a strong load that slightly deforms the bump 22. By applying ultrasonic vibration after the bump 22 is joined, the bump 22 and the pad 11 can be joined and deformed further with greater reliability.

[0132] (Fifth embodiment) The fifth embodiment relates to a method for manufacturing a semiconductor device 100. The fifth embodiment is a modification of the method for manufacturing a semiconductor device 100 of the first to fourth embodiments, with the addition of a sixth and seventh step. The sixth step can also be performed after the second step of the second embodiment. Details common to the fifth embodiment and the first to fourth embodiments will not be explained.

[0133] Figure 20 shows a flowchart of the manufacturing method of the semiconductor device 100. The manufacturing method of the semiconductor device 100 according to the fifth embodiment will be described with reference to the schematic diagrams representing the manufacturing method of the semiconductor device 100 in Figures 21 and 22. The manufacturing method of the semiconductor device 100 according to the fifth embodiment further includes a sixth step of heating the semiconductor element 2 and the wiring substrate 1 after the second step, after the fourth step, or after the fifth step, and a seventh step of cleaning the annealed components.

[0134] The sixth step is performed after the processing of the first to fourth embodiments is completed, that is, after the deformation of the bump 22 and the joining of the bump 22 and the pad 11 are completed.

[0135] In the sixth step, heat X is applied to the semiconductor element 2 and the wiring substrate 1, as shown in the schematic diagram in Figure 21. Specifically, in the sixth step, the bonded semiconductor element 2 and the wiring substrate 1 are heated in an oven or the like to promote the growth of the alloy layer of the bonded bumps 22 and pads 11. The growth of the alloy of the bonded bumps 22 and pads 11 improves the bonding strength and contributes to improving the reliability of the semiconductor device 100.

[0136] The processing temperature for the sixth step (temperature of the bump 22) is preferably below the melting point of the bump 22. From the viewpoint of effectively growing the alloy in the sixth step, the processing temperature for the sixth step is preferably 80°C or higher. If flux has been applied to the bump 22 and / or pad 11 before the first or third step, from the viewpoint of preventing flux burning during the heat treatment, the processing temperature for the sixth step is preferably 150°C or lower. The processing temperature for the sixth step is preferably between 80°C and 150°C.

[0137] The heat treatment time for step 6 is preferably 15 minutes or more from the viewpoint of alloy growth. The heat treatment time for step 6 is preferably 10 hours or less from the viewpoint of preventing flux sticking. The heat treatment time for step 6 is preferably 15 minutes or more and 10 hours or less.

[0138] It is preferable to perform the seventh step, such as when flux is used. In the seventh step, the heated component in the sixth step is cleaned using a cleaning solution W, as shown in the schematic diagram of Figure 22. The cleaning solution W is preferably an alkaline cleaning solution, acetone, or isopropyl alcohol. Since the bump 22 and pad 11 are firmly bonded by the sixth step, the joint between the bump 22 and pad 11 is less likely to be damaged by the cleaning pressure in the seventh step.

[0139] The sixth step, heat treatment, improves the reliability of the joint between the bump 22 and the pad 11, contributing to improved reliability of the semiconductor device 100. Furthermore, even after the seventh step, cleaning, the reliability of the joint between the bump 22 and the pad 11 remains improved, making joint failure due to cleaning pressure less likely, thus contributing to improved reliability and yield of the semiconductor device 100.

[0140] The technical details of the invention are described below. Technical proposal 1 A first step involves applying a first load to a semiconductor element to press the bump of the semiconductor element against a wiring board, and either not applying ultrasonic vibration to the bump or applying ultrasonic vibration of a first intensity to the bump to deform the bump, A second step is performed after the first step, in which a second load is applied to the semiconductor element to press the bump of the semiconductor element against the wiring substrate, and ultrasonic vibrations of a second intensity stronger than the first intensity are applied to the bump to bond the bump to the pad of the wiring substrate, A method for manufacturing a semiconductor device having [a certain feature]. Technical proposal 2 A method for manufacturing a semiconductor device according to Technical Proposal 1, wherein ultrasonic vibration of the first intensity is not applied in the first step. Technical proposal 3 A method for manufacturing a semiconductor device according to Technical Proposal 1 or 2, wherein the maximum value of the second load is 100% or more and 250% or less of the maximum value of the first load. Technical proposal 4 A method for manufacturing a semiconductor device according to any one of Technical Proposals 1 to 3, wherein the first intensity is greater than 0% of the second intensity and 70% or less. Technical proposal 5 A method for manufacturing a semiconductor device according to any one of Technical Proposals 1 to 4, wherein the height of the bump that deforms in the first step is 30% or more of the total height of the bump that deforms in the first and second steps. Technical proposal 6 A method for manufacturing a semiconductor device according to any one of Technical Proposals 1 to 5, wherein the height of the bump that deforms in the first step is 60% or more and 100% or less of the total height of the bump that deforms in the first step and the second step. Technical proposal 7 A method for manufacturing a semiconductor device according to any one of Technical Proposals 1 to 6, wherein the height of the bump that deforms in the second step is 0% or more and 200% or less of the height of the bump that deforms in the first step. Technical proposal 8 A method for manufacturing a semiconductor device according to any one of Technical Proposals 1 to 7, wherein in the first step, ultrasonic vibration of the first intensity is applied to the bump to deform the bump before the first load is applied. Technical proposal 9 A method for manufacturing a semiconductor device according to any one of Technical Proposals 1 to 8, further comprising a third step of applying a third load to the semiconductor device to press the bump of the semiconductor device against the wiring substrate, and applying ultrasonic vibrations of a third intensity weaker than the second intensity to the bump to deform the bump. Technical proposal 10 The height of the bump that deforms in the third step is 50% or less of the sum of the heights of the bump that deform in the first, second, and third steps. A method for manufacturing a semiconductor device according to Technical Proposal 9, wherein the height of the bump that deforms in the first step is 30% or more of the sum of the heights of the bump that deform in the first, second, and third steps. Technical proposal 11 A method for manufacturing a semiconductor device according to Technical Proposal 9 or 10, wherein the third intensity is greater than 0% and less than or equal to 100% of the second intensity. Construction method. Technical proposal 12 A method for manufacturing a semiconductor device according to any one of Technical Proposals 9 to 11, wherein the third intensity is 400% or more and 900% or less of the first intensity. Technical proposal 13 A method for manufacturing a semiconductor device according to any one of Technical Proposals 9 to 12, wherein the third load is 10% or more and 60% or less of the maximum value of the first load. Technical proposal 14 The process further includes a fourth step in which, after the second step, a fourth load is applied to the semiconductor element to press the bump of the semiconductor element against the wiring substrate, and the bump is deformed without applying ultrasonic vibration to the bump. A method for manufacturing a semiconductor device according to any one of Technical Proposals 1 to 13, wherein in the fourth step, the maximum value of the fourth load is 300% or more and 1200% or less of the maximum value of the first load. Technical proposal 15 The height of the bump that deforms in the fourth step is less than 50% of the sum of the heights of the bump that deform in the first, second, and fourth steps. A method for manufacturing a semiconductor device according to Technical Proposal 14, wherein the height of the bump that deforms in the first step is 30% or more of the sum of the heights of the bump that deform in the first, second, and fourth steps. Technical proposal 16 The process further includes a fifth step, in which a fifth load is applied to the semiconductor element to press the bump of the semiconductor element against the wiring substrate, and ultrasonic vibration of a fourth intensity is applied to the bump to deform the bump. A method for manufacturing a semiconductor device according to any one of Technical Proposals 1 to 15, wherein the maximum value of the fifth load is 40% or more and 120% or less of the maximum value of the first load. Technical proposal 17 The height of the bump that deforms in the fourth step is less than 50% of the sum of the heights of the bump that deform in the first, second, and fifth steps. A method for manufacturing a semiconductor device according to Technical Proposal 16, wherein the height of the bump that deforms in the first step is 30% or more of the sum of the heights of the bump that deform in the first, second, third, and fifth steps. Technical proposal 18 In the first step described above, the temperature of the bump is below the melting point of the bump. In the second step, the temperature of the bump is below the melting point of the bump. In the third step described above, the temperature of the bump is below the melting point of the bump. In the fourth step described above, the temperature of the bump is below the melting point of the bump. A method for manufacturing a semiconductor device according to any one of Technical Proposals 1 to 17, wherein in the fifth step, the temperature of the bump is below the melting point of the bump. Technical proposal 19 A method for manufacturing a semiconductor device according to any one of Technical Proposals 1 to 17, further comprising a sixth step of heating the semiconductor element and the wiring substrate after the second step of Technical Proposal 1, after the fourth step of Technical Proposal 14, or after the fifth step of Technical Proposal 16. Technical proposal 20 The process further includes a seventh step of cleaning the heated component after the sixth step, The method for manufacturing a semiconductor device according to Technical Proposal 19, wherein the heating treatment temperature is below the melting point of the bump.

[0141] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0142] 1: Wiring board 2: Semiconductor elements 11: Pad 21: Electrode 22: Bump 100: Semiconductor Device

Claims

1. A first step involves applying a first load to a semiconductor element to press the bump of the semiconductor element against a wiring board, and either not applying ultrasonic vibration to the bump or applying ultrasonic vibration of a first intensity to the bump to deform the bump, A second step is performed after the first step, in which a second load is applied to the semiconductor element to press the bump of the semiconductor element against the wiring substrate, and ultrasonic vibrations of a second intensity stronger than the first intensity are applied to the bump to bond the bump to the pad of the wiring substrate, A method for manufacturing a semiconductor device having [a certain feature].

2. The method for manufacturing a semiconductor device according to claim 1, wherein ultrasonic vibration of the first intensity is not applied in the first step.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the maximum value of the second load is 100% or more and 250% or less of the maximum value of the first load.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the first intensity is greater than 0% of the second intensity and 70% or less.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the height of the bump that deforms in the first step is 30% or more of the total height of the bump that deforms in the first step and the second step.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the height of the bump that deforms in the first step is 60% or more and 100% or less of the total height of the bump that deforms in the first step and the second step.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the height of the bump that is deformed in the second step is 0% or more and 200% or less of the height of the bump that is deformed in the first step.

8. The method for manufacturing a semiconductor device according to claim 1, wherein in the first step, ultrasonic vibration of the first intensity is applied to the bump to deform the bump before the first load is applied.

9. The method for manufacturing a semiconductor device according to claim 1, further comprising a third step, before the first step, of applying a third load to the semiconductor element to press the bump of the semiconductor element against the wiring substrate, and applying ultrasonic vibrations of a third intensity weaker than the second intensity to the bump to deform the bump.

10. The height of the bump that deforms in the third step is 50% or less of the sum of the heights of the bump that deform in the first, second, and third steps. The method for manufacturing a semiconductor device according to claim 9, wherein the height of the bump that deforms in the first step is 30% or more of the total height of the bump that deforms in the first step, the second step and the third step.

11. The method for manufacturing a semiconductor device according to claim 9, wherein the third intensity is greater than 0% of the second intensity and less than or equal to 100%. Construction method.

12. The method for manufacturing a semiconductor device according to claim 9, wherein the third intensity is 400% or more and 900% or less of the first intensity.

13. The method for manufacturing a semiconductor device according to claim 9, wherein the third load is 10% or more and 60% or less of the maximum value of the first load.

14. The process further comprises a fourth step in which, after the second step, a fourth load is applied to the semiconductor element to press the bump of the semiconductor element against the wiring substrate, and the bump is deformed without applying ultrasonic vibration to the bump. The method for manufacturing a semiconductor device according to claim 1, wherein in the fourth step, the maximum value of the fourth load is 300% or more and 1200% or less of the maximum value of the first load.

15. The height of the bump that deforms in the fourth step is less than 50% of the sum of the heights of the bump that deform in the first, second, and fourth steps. The method for manufacturing a semiconductor device according to claim 14, wherein the height of the bump that deforms in the first step is 30% or more of the sum of the heights of the bump that deform in the first step, the second step and the fourth step.

16. The process further includes a fifth step, in which a fifth load is applied to the semiconductor element to press the bump of the semiconductor element against the wiring substrate, and ultrasonic vibrations of a fourth intensity are applied to the bump to deform the bump. The method for manufacturing a semiconductor device according to claim 1, wherein the maximum value of the fifth load is 40% or more and 120% or less of the maximum value of the first load.

17. The height of the bump that deforms in the fourth step is less than 50% of the sum of the heights of the bump that deform in the first, second, and fifth steps. The method for manufacturing a semiconductor device according to claim 16, wherein the height of the bump that deforms in the first step is 30% or more of the total height of the bump that deforms in the first, second, third, and fifth steps.

18. In the first step described above, the temperature of the bump is below the melting point of the bump. In the second step described above, the temperature of the bump is below the melting point of the bump. In the third step described above, the temperature of the bump is below the melting point of the bump. In the fourth step described above, the temperature of the bump is below the melting point of the bump. The method for manufacturing a semiconductor device according to any one of claims 1 to 17, wherein in the fifth step, the temperature of the bump is below the melting point of the bump.

19. A method for manufacturing a semiconductor device according to any one of claims 1 to 17, further comprising a sixth step of heating the semiconductor element and the wiring substrate after the second step of claim 1, after the fourth step of claim 14, or after the fifth step of claim 16.

20. The process further includes a seventh step of cleaning the heated member after the sixth step, The method for manufacturing a semiconductor device according to claim 19, wherein the heating treatment temperature is below the melting point of the bump.

Images