Semiconductor equipment

Abstract

The present invention provides a semiconductor device that includes an IGBT and an RC-IGBT having a diode, enabling reduced losses. [Solution] The semiconductor device of the embodiment comprises a transistor region, a diode region, and a termination region surrounding the transistor region and the diode region. The transistor region includes a first trench and a first conductive layer within the first trench. The diode region includes a second trench and a second conductive layer within the second trench. The termination region includes a third trench and a first electrode pad electrically connected to the first conductive layer in at least a portion of the first trench, and a second electrode pad electrically connected to the second conductive layer in the third trench closest to the third trench within the second trench.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] An example of a power semiconductor device is an Insulated Gate Bipolar Transistor (IGBT). In an IGBT, for example, a p-type collector region, an n-type drift region, and a p-type base region are provided on the collector electrode. A gate electrode is provided in a trench that penetrates the p-type base region and reaches the n-type drift region, with a gate insulating film in between. Furthermore, an n-type emitter region, connected to the emitter electrode, is provided in a region adjacent to the trench on the surface of the p-type base region.

[0003] In recent years, reverse-conducting IGBTs (RC-IGBTs), which integrate IGBTs and free-wheeling diodes (Free Wheeling Diodes) on the same semiconductor chip, have been widely developed and commercialized. RC-IGBTs are used, for example, as switching elements in inverter circuits. The free-wheeling diode has the function of allowing current to flow in the opposite direction to the IGBT's on-current. Integrating IGBTs and free-wheeling diodes on the same semiconductor chip offers many advantages, such as reducing chip size by sharing termination regions and distributing heat-generating areas.

[0004] For example, when using RC-IGBTs as switching elements in an inverter circuit, two RC-IGBTs are connected in series on the high-side and low-side, respectively. For instance, if the reverse recovery loss (Err) of the freewheeling diode of one RC-IGBT increases, the turn-on loss (Eon) of the other RC-IGBT increases, leading to an increase in the inverter circuit's losses. Therefore, reducing the reverse recovery loss (Err) of the freewheeling diode of the RC-IGBT is desirable. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2019-169575 [Patent Document 2] Japanese Patent Publication No. 2021-48338 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] The problem that this invention aims to solve is to provide a semiconductor device that includes an RC-IGBT having an IGBT and a diode, and that enables reduction of losses. [Means for solving the problem]

[0007] The semiconductor device of the embodiment comprises a transistor region, a diode region, and a termination region surrounding the transistor region and the diode region, with the diode region provided between it and the transistor region, wherein the transistor region comprises a semiconductor layer having a first surface and a second surface facing the first surface, a first semiconductor region of a first conductivity type provided within the semiconductor layer, a second semiconductor region of a second conductivity type provided within the semiconductor layer and between the first semiconductor region and the first surface, and the second semiconductor region provided within the semiconductor layer A third semiconductor region of a first conductivity type provided between the first surface and the semiconductor layer; a fourth semiconductor region of a second conductivity type provided within the semiconductor layer and between the third semiconductor region and the first surface; a plurality of first trenches provided on the side of the first surface within the semiconductor layer, extending in a first direction parallel to the first surface, repeatedly arranged in a second direction perpendicular to the first direction and parallel to the first surface, and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a first conductive layer provided within the first trenches; and the first conductive layer. The diode region includes a first insulating film provided between the semiconductor layer and the semiconductor layer, a first electrode provided on the side of the semiconductor layer facing the first surface and in contact with the fourth semiconductor region, and a second electrode provided on the side of the semiconductor layer facing the second surface and in contact with the first semiconductor region, wherein the diode region includes the semiconductor layer, the second semiconductor region, a fifth semiconductor region provided within the semiconductor layer and between the second semiconductor region and the second surface, having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the second semiconductor region, and within the semiconductor layer The semiconductor includes: a sixth semiconductor region of a first conductivity type provided between the second semiconductor region and the first surface; a plurality of second trenches provided on the side of the first surface within the semiconductor layer, extending in the first direction and repeatedly arranged in the second direction, and in contact with the second semiconductor region and the sixth semiconductor region; a second conductive layer provided within the second trenches; a second insulating film provided between the second conductive layer and the semiconductor layer; a first electrode electrically connected to the sixth semiconductor region; and a second electrode in contact with the fifth semiconductor region.The terminal region includes the semiconductor layer, the second semiconductor region, a seventh semiconductor region of a first conductivity type provided in the semiconductor layer, provided between the second semiconductor region and the first surface, and electrically connected to the first electrode, a third trench provided on the side of the first surface in the semiconductor layer, provided between the seventh semiconductor region and the first surface, extending in the first direction and contacting the seventh semiconductor region, a third conductive layer provided in the third trench, a third insulating film provided between the third conductive layer and the semiconductor layer, the first electrode, the second electrode, a first electrode pad provided on the side of the first surface with respect to the semiconductor layer and electrically connected to the first conductive layer provided in at least a part of the plurality of first trenches, and a second electrode pad provided on the side of the first surface with respect to the semiconductor layer and electrically connected to the second conductive layer provided in the second trench closest to the third trench among the plurality of second trenches.

Brief Description of the Drawings

[0008] [Figure 1] Schematic diagram of the semiconductor device of the first embodiment. [Figure 2] Schematic cross-sectional view of a part of the semiconductor device of the first embodiment. [Figure 3] Schematic top view of a part of the semiconductor device of the first embodiment. [Figure 4] Schematic cross-sectional view of a part of the semiconductor device of the first embodiment. [Figure 5] Schematic top view of a part of the semiconductor device of the first embodiment. [Figure 6] Schematic top view of a part of the semiconductor device of the first embodiment. [Figure 7] Schematic cross-sectional view of a part of the semiconductor device of the comparative example. [Figure 8] Explanation diagram of the problems of the semiconductor device of the comparative example. [Figure 9] Explanation diagram of the problems of the semiconductor device of the comparative example. [Figure 10] Explanation diagram of the operation and effect of the semiconductor device of the first embodiment. [Figure 11] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 12] A schematic cross-sectional view of a part of a semiconductor device of a first modified example of the first embodiment. [Figure 13] A schematic cross-sectional view of a part of a semiconductor device of a second modified example of the first embodiment. [Figure 14] A schematic cross-sectional view of a part of a semiconductor device of a third modified example of the first embodiment. [Figure 15] A schematic cross-sectional view of a part of the semiconductor device of the second embodiment. [Figure 16] A schematic top view of a part of the semiconductor device according to the second embodiment. [Figure 17] A diagram illustrating the operation and effects of the semiconductor device according to the second embodiment. [Figure 18] A schematic cross-sectional view of a part of the semiconductor device of the first modified example of the second embodiment. [Figure 19] A schematic cross-sectional view of a part of a semiconductor device of a second modified example of the second embodiment. [Figure 20] A schematic cross-sectional view of a part of a semiconductor device of a third modified example of the second embodiment. [Figure 21] A schematic cross-sectional view of a part of the semiconductor device of the third embodiment. [Figure 22] A schematic cross-sectional view of a part of a semiconductor device of a modified example of the third embodiment. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same or similar components will be denoted by the same reference numerals, and components that have already been described will be omitted from the description as appropriate.

[0010] In this specification, n + shape, n shape, n - When the notation "shape" is used, n + shape, n shape, n - This means that the concentration of n-type impurities decreases in the order of their shapes. Also, p + shape, p shape, p - If there is a notation for the shape, p+ shape, p shape, p - This means that the concentration of p-type impurities decreases in the order of their shapes.

[0011] In this specification, the n-type impurity concentration refers to the effective n-type impurity concentration after compensation, not the actual n-type impurity concentration. Similarly, the p-type impurity concentration refers to the effective p-type impurity concentration after compensation, not the actual p-type impurity concentration. For example, if the actual n-type impurity concentration is greater than the actual p-type impurity concentration, the n-type impurity concentration is calculated by subtracting the p-type impurity concentration from the actual n-type impurity concentration. The same applies to the p-type impurity concentration.

[0012] In this specification, the distribution and absolute value of impurity concentrations in semiconductor regions can be measured, for example, using secondary ion mass spectrometry (SIMS). Furthermore, the relative magnitudes of impurity concentrations in two semiconductor regions can be determined, for example, using scanning capacitance microscopy (SCM). Additionally, the distribution and absolute value of impurity concentrations can be measured, for example, using spreading resistance analysis (SRA). SCM and SRA provide the relative magnitudes and absolute values ​​of carrier concentrations in the semiconductor regions. By assuming an activation rate for impurities, the relative magnitudes, distribution, and absolute values ​​of impurity concentrations between two semiconductor regions can be determined from the measurement results of SCM and SRA.

[0013] Unless otherwise specified in the specification, the impurity concentration in the semiconductor region shall be represented by the impurity concentration near the center of that semiconductor region.

[0014] (First embodiment) The semiconductor device of the first embodiment comprises a transistor region, a diode region, and a termination region that surrounds the transistor region and the diode region, with the diode region provided between it and the transistor region. The transistor region comprises a semiconductor layer having a first surface and a second surface facing the first surface, a first semiconductor region of a first conductivity type provided within the semiconductor layer, a second semiconductor region of a second conductivity type provided within the semiconductor layer and between the first semiconductor region and the first surface, a third semiconductor region of a first conductivity type provided within the semiconductor layer and between the second semiconductor region and the first surface, a fourth semiconductor region of a second conductivity type provided within the semiconductor layer and between the third semiconductor region and the first surface, and the side of the first surface within the semiconductor layer The device includes: a plurality of first trenches provided in a first direction parallel to the first surface, repeatedly arranged in a second direction perpendicular to the first direction and parallel to the first surface, and in contact with a second semiconductor region, a third semiconductor region, and a fourth semiconductor region; a first conductive layer provided in the first trenches; a first insulating film provided between the first conductive layer and the semiconductor layer; a first electrode provided on the side of the semiconductor layer facing the first surface and in contact with the fourth semiconductor region; and a second electrode provided on the side of the semiconductor layer facing the second surface and in contact with the first semiconductor region. The diode region includes a semiconductor layer, a second semiconductor region, a fifth semiconductor region of a second conductivity type provided within the semiconductor layer and between the second semiconductor region and a second surface, having a second conductivity type impurity concentration higher than that of the second conductivity type impurity concentration in the second semiconductor region, a sixth semiconductor region of a first conductivity type provided within the semiconductor layer and between the second semiconductor region and a first surface, a plurality of second trenches provided on the side of the first surface in the semiconductor layer, extending in a first direction and repeatedly arranged in a second direction, in contact with the second semiconductor region and the sixth semiconductor region, a second conductive layer provided within the second trenches, a second insulating film provided between the second conductive layer and the semiconductor layer, a first electrode electrically connected to the sixth semiconductor region, and a second electrode in contact with the fifth semiconductor region.The termination region includes a semiconductor layer, a second semiconductor region, a seventh semiconductor region of a first conductivity type provided within the semiconductor layer and between the second semiconductor region and the first surface, and electrically connected to the first electrode, a third trench provided on the side of the first surface within the semiconductor layer and between the seventh semiconductor region and the first surface, extending in a first direction and in contact with the seventh semiconductor region, a third conductive layer provided in the third trench, a third insulating film provided between the third conductive layer and the semiconductor layer, a first electrode, a second electrode, a first electrode pad provided on the side of the first surface relative to the semiconductor layer and electrically connected to the first conductive layer provided in at least some of the first trenches among a plurality of first trenches, and a second electrode pad provided on the side of the first surface relative to the semiconductor layer and electrically connected to the second conductive layer provided in the second trench closest to the third trench among a plurality of second trenches.

[0015] The semiconductor device of the first embodiment is an RC-IGBT100 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip. The RC-IGBT100 has a trench-gate type IGBT with a gate electrode located in a trench formed in the semiconductor layer. The following explanation will be given using the case where the first conductivity type is p-type and the second conductivity type is n-type as an example.

[0016] Figure 1 is a schematic diagram of a semiconductor device according to the first embodiment.

[0017] Figure 2 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 2 is the AA' section of Figure 1.

[0018] Figure 3 is a schematic top view of a part of the semiconductor device of the first embodiment. Figure 3 is a top view of the first surface F1. Figure 2 is a cross-section AA' of Figure 3.

[0019] Figure 4 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 4 is the BB' section of Figure 1.

[0020] FIG. 5 is a schematic top view of a part of the semiconductor device according to the first embodiment. FIG. 5 is a top view in the first plane F1. FIG. 4 is a cross section taken along the line BB' of FIG. 5.

[0021] As shown in FIG. 1, the RC-IGBT 100 has a transistor region 101, a diode region 102, and a termination region 103. The termination region 103 surrounds the transistor region 101 and the diode region 102. The diode region 102 is provided between the transistor region 101 and the termination region 103.

[0022] The diode region 102 includes a first diode region 102a (first region) and a second diode region 102b (second region). The second diode region 102b is provided between the first diode region 102a and the transistor region 101.

[0023] When the RC-IGBT 100 is in the off state, the termination region 103 relaxes the strength of the electric field applied to the end portions of the pn junctions of the transistor region 101 and the diode region 102. The termination region 103 has a function of improving the breakdown voltage withstand of the RC-IGBT 100.

[0024] The transistor region 101 operates as an IGBT. The diode region 102 operates as a freewheeling diode. The freewheeling diode is, for example, a Fast Recovery Diode (FRD).

[0025] The RC-IGBT 100 according to the first embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a first insulating film 41, a second insulating film 42, a third insulating film 43, a first conductive layer 51, a second conductive layer 52, a third conductive layer 53, an interlayer insulating layer 61, a first gate electrode pad 104 (first electrode pad), and a second gate electrode pad 105 (second electrode pad).

[0026] In the semiconductor layer 10, there are a first trench 21, a second trench 22, a third trench 23, p +The collector region 26 (first semiconductor region) of the shape, n - The drift region 27 (second semiconductor region) of the p-shape, the cell base region 28 (third semiconductor region) of the p-shape, and n + Cell emitter region 29 (fourth semiconductor region), p + Shaped cell contact area 30, n + Cathode region 31 (5th semiconductor region), p - Anode region 32 (sixth semiconductor region) of the shape, p + A diode contact region 33 of type p, a guard ring region 34 (seventh semiconductor region), n + The terminal cathode region 35 (eighth semiconductor region) of the shape, and p + A guard ring contact area 36 of a specific shape is provided.

[0027] The semiconductor layer 10 has a first surface F1 and a second surface F2 facing the first surface F1. The semiconductor layer 10 is, for example, single-crystal silicon. The thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

[0028] In this specification, a direction parallel to the first surface F1 is referred to as the first direction. A direction parallel to the first surface F1 and perpendicular to the first direction is referred to as the second direction. In this specification, "depth" is defined as the distance in the direction toward the second surface F2 with respect to the first surface F1.

[0029] The transistor region 101 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a first insulating film 41, a first conductive layer 51, and an interlayer insulating layer 61.

[0030] Within the semiconductor layer 10 of the transistor region 101, there are a first trench 21, a collector region 26 (first semiconductor region), a drift region 27 (second semiconductor region), a cell base region 28 (third semiconductor region), a cell emitter region 29 (fourth semiconductor region), and a cell contact region 30.

[0031] The upper electrode 12 is provided on the side of the first surface F1 of the semiconductor layer 10. At least a portion of the upper electrode 12 is in contact with the first surface F1 of the semiconductor layer 10.

[0032] The upper electrode 12 functions as the emitter electrode of the IGBT in the transistor region 101. The upper electrode 12 is made of, for example, metal.

[0033] The upper electrode 12 is in contact with the cell emitter region 29. The upper electrode 12 is electrically connected to the cell emitter region 29.

[0034] The upper electrode 12 is in contact with the cell contact area 30. The upper electrode 12 is electrically connected to the cell contact area 30. The upper electrode 12 is electrically connected to the cell base area 28 via the cell contact area 30.

[0035] The lower electrode 14 is provided on the side of the second surface F2 of the semiconductor layer 10. At least a portion of the lower electrode 14 is in contact with the second surface F2 of the semiconductor layer 10.

[0036] The lower electrode 14 functions as the collector electrode of the IGBT in the transistor region 101. The lower electrode 14 is made of, for example, metal.

[0037] The lower electrode 14 is in contact with the collector region 26 in the transistor region 101. The lower electrode 14 is electrically connected to the collector region 26 in the transistor region 101.

[0038] The collector area 26 is p + This is a semiconductor region of a certain shape. The collector region 26 is in contact with the second surface F2. The collector region 26 is electrically connected to the lower electrode 14. The collector region 26 is in contact with the lower electrode 14. The collector region 26 is a source of holes when the IGBT is ON.

[0039] The drift region 27 is n - This is a semiconductor region of a certain shape. The drift region 27 is provided between the collector region 26 and the first surface F1.

[0040] The drift region 27 serves as the path for the on-current when the IGBT is on. The drift region 27 also functions to deplete when the IGBT is off, thus maintaining the IGBT's breakdown voltage.

[0041] The cell base region 28 is a p-type semiconductor region. The cell base region 28 is located between the drift region 27 and the first surface F1. The cell base region 28 has the drift region 27 between it and the collector region 26.

[0042] The depth of the cell base region 28 is, for example, 5 μm or less. An n-type inversion layer is formed in the region of the cell base region 28 facing the first conductive layer 51 to which the first gate voltage Vg1 is applied when the IGBT is in the ON state. The cell base region 28 functions as the channel region of the transistor.

[0043] The cell emitter region 29 is n + This is a semiconductor region of a certain shape. The cell emitter region 29 is provided between the cell base region 28 and the first surface F1. The cell emitter region 29 is in contact with the first insulating film 41.

[0044] The n-type impurity concentration in the cell emitter region 29 is higher than the n-type impurity concentration in the drift region 27.

[0045] The cell emitter region 29 is in contact with the upper electrode 12. The cell emitter region 29 is electrically connected to the upper electrode 12. The cell emitter region 29 serves as an electron source when the transistor is in the ON state.

[0046] The cell contact area 30 is p + This is a semiconductor region of a certain shape. The cell contact region 30 is provided between the cell base region 28 and the first surface F1. The cell contact region 30 is in contact with the upper electrode 12. The cell contact region 30 is electrically connected to the upper electrode 12.

[0047] The concentration of p-type impurities in the cell contact region 30 is higher than the concentration of p-type impurities in the cell base region 28.

[0048] The first trench 21 is provided on the side of the first surface F1 of the semiconductor layer 10. The first trench 21 is a groove provided in the semiconductor layer 10. The first trench 21 is part of the semiconductor layer 10.

[0049] The first trench 21 extends in a first direction parallel to the first surface F1, as shown in Figure 3. The first trench 21 has a stripe shape. Multiple first trenches 21 are repeatedly arranged in a second direction perpendicular to the first direction.

[0050] The first trench 21 is in contact with the drift region 27, the cell base region 28, and the cell emitter region 29. The first trench 21 penetrates the cell base region 28 and reaches the drift region 27. The depth of the first trench 21 is, for example, 8 μm or less.

[0051] The first conductive layer 51 is provided in the first trench 21. The first conductive layer 51 is, for example, a semiconductor or a metal. The first conductive layer 51 is, for example, amorphous silicon or polycrystalline silicon containing n-type or p-type impurities.

[0052] A portion of the first conductive layer 51 is electrically connected to the first gate electrode pad 104. In Figures 2 and 3, the first conductive layer 51, as shown when the first gate voltage Vg1 is applied, is electrically connected to the first gate electrode pad 104.

[0053] A portion of the first conductive layer 51 is electrically connected to the upper electrode 12. In Figure 2, the first conductive layer 51 in contact with the upper electrode 12 is electrically connected to the upper electrode 12.

[0054] Hereinafter, the first trench 21 in which the first conductive layer 51 electrically connected to the first gate electrode pad 104 is provided will be referred to as the first gate trench. The first trench 21 in which the first conductive layer 51 electrically connected to the upper electrode 12 is provided will be referred to as the first dummy trench.

[0055] The first gate trenches and the first dummy trenches are arranged alternately, one at a time, in the second direction. In the transistor region 101, the ratio of the first gate trenches to the first trenches 21 is 50%.

[0056] Furthermore, a first dummy trench is not required in the transistor region 101, and the ratio of the number of first gate trenches to the number of first trenches 21 in the transistor region 101 is not limited to 50% but may be any other ratio.

[0057] The first insulating film 41 is provided between the first conductive layer 51 and the semiconductor layer 10. The first insulating film 41 is provided between the first conductive layer 51 and the drift region 27, between the first conductive layer 51 and the cell base region 28, and between the first conductive layer 51 and the cell emitter region 29. The first insulating film 41 is in contact with the drift region 27, the cell base region 28, and the cell emitter region 29. The first insulating film 41 is, for example, silicon oxide.

[0058] The interlayer insulating layer 61 is provided between the first conductive layer 51 and the upper electrode 12. The interlayer insulating layer 61 electrically isolates a portion of the first conductive layer 51 from the upper electrode 12 and from the first conductive layer 51 from the semiconductor layer 10. The interlayer insulating layer 61 is, for example, silicon oxide.

[0059] The diode region 102 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a second insulating film 42, a second conductive layer 52, and an interlayer insulating layer 61.

[0060] Within the semiconductor layer 10 of the diode region 102, there are a second trench 22, a cathode region 31 (fifth semiconductor region), a drift region 27 (second semiconductor region), an anode region 32 (sixth semiconductor region), and a diode contact region 33.

[0061] The upper electrode 12 functions as the anode electrode of the diode in the diode region 102. The upper electrode 12 is in contact with the diode contact region 33. The upper electrode 12 is electrically connected to the diode contact region 33. The upper electrode 12 is electrically connected to the anode region 32 via the diode contact region 33. The upper electrode 12 may also be in direct contact with the anode region 32. In this case, for example, the upper electrode 12 and the anode region 32 have a Schottky junction.

[0062] The lower electrode 14 functions as the cathode electrode of the diode in the diode region 102. The lower electrode 14 is in contact with the cathode region 31.

[0063] The cathode region 31 is n + This is a semiconductor region of a certain shape. The cathode region 31 is in contact with the second surface F2. The cathode region 31 is an electron source when the diode is in the ON state. The cathode region 31 is in contact with the lower electrode 14.

[0064] The drift region 27 is n - This is a semiconductor region of a certain shape. The drift region 27 is located between the cathode region 31 and the first surface F1. The n-type impurity concentration in the drift region 27 is lower than the n-type impurity concentration in the cathode region 31.

[0065] The drift region 27 is the path of the on-current when the diode is in the ON state.

[0066] The anode region 32 is p - This is a semiconductor region of a certain shape. The anode region 32 is provided between the drift region 27 and the first surface F1. The anode region 32 has the drift region 27 between it and the cathode region 31.

[0067] The anode region 32 serves as a hole source when the diode is in the ON state.

[0068] The p-type impurity concentration in the anode region 32 is lower than, for example, the p-type impurity concentration in the cell base region 28. The p-type impurity concentration in the anode region 32 may also be the same as, for example, the p-type impurity concentration in the cell base region 28.

[0069] The p-type impurity concentration in the anode region 32 is lower than, for example, the p-type impurity concentration in the guard ring region 34. The depth of the anode region 32 is, for example, the same as the depth of the cell base region 28.

[0070] The diode contact region 33 is p + This is a semiconductor region of a certain shape. The diode contact region 33 is provided between the anode region 32 and the first surface F1.

[0071] The diode contact region 33 is in contact with the upper electrode 12. The diode contact region 33 is electrically connected to the upper electrode 12.

[0072] The p-type impurity concentration in the diode contact region 33 is higher than that in the anode region 32.

[0073] The second trench 22 is provided on the side of the first surface F1 of the semiconductor layer 10. The second trench 22 is a groove provided in the semiconductor layer 10. The second trench 22 is part of the semiconductor layer 10.

[0074] As shown in Figure 5, the second trench 22 extends in a first direction parallel to the first surface F1 on the first surface F1. The second trench 22 has a striped shape. Multiple second trenches 22 are repeatedly arranged in a second direction perpendicular to the first direction.

[0075] The second trench 22 is in contact with the drift region 27 and the anode region 32. The second trench 22 penetrates the anode region 32 and reaches the drift region 27. The depth of the second trench 22 is, for example, 8 μm or less.

[0076] The second conductive layer 52 is provided in the second trench 22. The second conductive layer 52 is, for example, a semiconductor or a metal. The second conductive layer 52 is, for example, amorphous silicon or polycrystalline silicon containing n-type or p-type impurities.

[0077] At least a portion of the second conductive layer 52 is electrically connected to the second gate electrode pad 105. In Figures 4 and 5, the second conductive layer 52, as shown when the second gate voltage Vg2 is applied, is electrically connected to the second gate electrode pad 105.

[0078] Within the second trench 22, the second conductive layer 52 provided in the second trench 22x closest to the third trench 23 provided in the terminal region 103 in the second direction is electrically connected to the second gate electrode pad 105. Note that a portion of the second trench 22x may be in contact with the guard ring region 34.

[0079] A portion of the second conductive layer 52 is electrically connected to the upper electrode 12. In Figure 4, the second conductive layer 52 in contact with the upper electrode 12 is electrically connected to the upper electrode 12.

[0080] Hereinafter, the second trench 22 in which the second conductive layer 52 electrically connected to the second gate electrode pad 105 is provided will be referred to as the second gate trench. Also, the second trench 22 in which the second conductive layer 52 electrically connected to the upper electrode 12 is provided will be referred to as the second dummy trench.

[0081] The first diode region 102a includes a plurality of second trenches 22. The first diode region 102a includes a second trench 22x that is closest to the third trench 23 provided in the termination region 103 in the second direction. The second trenches 22x are second gate trenches. In Figure 4, all second trenches 22 included in the first diode region 102a are second gate trenches.

[0082] The second diode region 102b includes a plurality of second trenches 22. In Figure 4, all of the second trenches 22 included in the second diode region 102b are second dummy trenches.

[0083] In the first diode region 102a, the ratio of the number of second trenches 22 in which a second conductive layer 52 electrically connected to the second gate electrode pad 105 is provided to the total number of second trenches 22 in the first diode region 102a is greater than the ratio of the number of second trenches 22 in which a second conductive layer 52 electrically connected to the second gate electrode pad 105 is provided to the total number of second trenches 22 in the second diode region 102b to the total number of second trenches 22 in the second diode region 102b.

[0084] In other words, the ratio of the number of second gate trenches in the first diode region 102a to the number of second trenches 22 is greater than the ratio of the number of second gate trenches in the second diode region 102b to the number of multiple second trenches 22 contained in the second diode region 102b.

[0085] For example, in Figure 4, the number of second trenches 22 in the first diode region 102a is 5, and the number of second gate trenches is 5. Therefore, the ratio of the number of second gate trenches to the number of second trenches 22 in the first diode region 102a is 100%. Also, the number of second trenches 22 in the second diode region 102b is 3, and the number of second gate trenches is 0. Therefore, the ratio of the number of second gate trenches to the number of second trenches 22 in the second diode region 102b is 0%.

[0086] For example, when comparing the ratio of the number of second gate trenches in the first diode region 102a to the number of second trenches 22 with the ratio of the number of second gate trenches in the second diode region 102b to the number of second trenches 22, five second gate trenches that are continuous in the second direction are extracted from each region, and the above ratios are compared.

[0087] In the second trench 22 in which the second conductive layer 52 is electrically connected to the second gate electrode pad 105, the distance (d in Figure 4) between the guard ring region 34 and the second trench 22y that is furthest away from the guard ring region 34 in the second direction is greater than or equal to the thickness (t in Figure 4) of the semiconductor layer 10 in the direction from the first surface F1 to the second surface F2.

[0088] The second insulating film 42 is provided between the second conductive layer 52 and the semiconductor layer 10. The second insulating film 42 is provided between the second conductive layer 52 and the drift region 27, and between the second conductive layer 52 and the anode region 32. The second insulating film 42 is in contact with the drift region 27 and the anode region 32. The second insulating film 42 is, for example, silicon oxide.

[0089] The interlayer insulating layer 61 is provided between the second conductive layer 52 and the upper electrode 12, and between the semiconductor layer 10 and the upper electrode 12. For example, the second conductive layer 52 and the upper electrode 12 are electrically connected using openings provided in the interlayer insulating layer 61.

[0090] The termination region 103 includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a third insulating film 43, a third conductive layer 53, and an interlayer insulating layer 61.

[0091] Within the semiconductor layer 10 of the termination region 103, a third trench 23, a termination cathode region 35 (eighth semiconductor region), a drift region 27 (second semiconductor region), a guard ring region 34 (seventh semiconductor region), and a guard ring contact region 36 are provided.

[0092] In the termination region 103, a parasitic diode is formed between the upper electrode 12 and the lower electrode 14.

[0093] The upper electrode 12 functions as the anode electrode of a parasitic diode in the termination region 103. The upper electrode 12 is in contact with the guard ring contact region 36. The upper electrode 12 is electrically connected to the guard ring contact region 36. The upper electrode 12 is electrically connected to the guard ring region 34 via the guard ring contact region 36. The upper electrode 12 may also be in direct contact with the guard ring region 34. In this case, for example, the upper electrode 12 and the guard ring region 34 have a Schottky junction.

[0094] The lower electrode 14 functions as the cathode electrode of a parasitic diode in the termination region 103. The lower electrode 14 is in contact with the termination cathode region 35.

[0095] The terminal cathode region 35 is n + This is a semiconductor region of a certain shape. The terminating cathode region 35 is in contact with the second surface F2. The terminating cathode region 35 is an electron source when the parasitic diode is in the ON state. The terminating cathode region 35 is in contact with the lower electrode 14.

[0096] The drift region 27 is n - This is a semiconductor region of a certain shape. The drift region 27 is provided between the terminal cathode region 35 and the first surface F1. The n-type impurity concentration in the drift region 27 is lower than the n-type impurity concentration in the terminal cathode region 35.

[0097] The drift region 27 becomes the path for the on-current when the parasitic diode is in the ON state.

[0098] The guard ring region 34 is a p-type semiconductor region. The guard ring region 34 is provided between the drift region 27 and the first surface F1. The guard ring region 34 sandwiches the drift region 27 between itself and the terminating cathode region 35.

[0099] The depth of the guard ring region 34 is greater than the depth of the anode region 32. Furthermore, the depth of the guard ring region 34 is greater than the depth of the third trench 23. Also, the depth of the guard ring region 34 is greater than the depth of the second trench 22.

[0100] The guard ring region 34 surrounds the transistor region 101 and the diode region 102. The guard ring region 34 is provided in a ring shape on the first surface F1. The guard ring region 34 has the function of mitigating the intensity of the electric field applied to the termination of the pn junction of the transistor region 101 and the diode region 102.

[0101] Furthermore, the guard ring region 34 becomes a source of holes when the parasitic diode is ON.

[0102] For example, it is also possible to provide an additional annular p-shaped region as a guard ring outside the guard ring region 34 of the terminal region 103, so as to surround the guard ring region 34.

[0103] The p-type impurity concentration in the guard ring region 34 is, for example, higher than the p-type impurity concentration in the anode region 32. The p-type impurity concentration in the guard ring region 34 is, for example, 5 times or more and 50 times or less than the p-type impurity concentration in the anode region 32.

[0104] The guard ring contact area 36 is p + This is a semiconductor region of a certain shape. The guard ring contact region 36 is provided between the guard ring region 34 and the first surface F1.

[0105] The guard ring contact area 36 is in contact with the upper electrode 12. The guard ring contact area 36 is electrically connected to the upper electrode 12.

[0106] The concentration of p-type impurities in the guard ring contact region 36 is higher than the concentration of p-type impurities in the guard ring region 34.

[0107] The third trench 23 is provided on the side of the first surface F1 of the semiconductor layer 10, in contact with the guard ring region 34. The third trench 23 is a groove provided in the semiconductor layer 10. The third trench 23 is part of the semiconductor layer 10.

[0108] As shown in Figure 5, the third trench 23 extends in a first direction parallel to the first surface F1 on the first surface F1. For example, multiple third trenches 23 may be provided.

[0109] The third trench 23 has, for example, a striped shape. Multiple third trenches 23 are repeatedly arranged in a second direction perpendicular to the first direction.

[0110] The third trench 23 is provided between the guard ring region 34 and the first surface F1. The depth of the third trench 23 is shallower than the depth of the guard ring region 34. The third trench 23 is separated from the drift region 27 by the guard ring region 34. The third trench 23 is in contact with the guard ring region 34. The depth of the third trench 23 is, for example, 8 μm or less.

[0111] The third conductive layer 53 is provided in the third trench 23. The third conductive layer 53 is, for example, a semiconductor or a metal. The third conductive layer 53 is, for example, amorphous silicon or polycrystalline silicon containing n-type or p-type impurities.

[0112] The third conductive layer 53 is electrically connected to the upper electrode 12. The third conductive layer 53 is in contact with the upper electrode 12.

[0113] The interlayer insulating layer 61 is provided between the third conductive layer 53 and the upper electrode 12, and between the semiconductor layer 10 and the upper electrode 12. For example, the third conductive layer 53 and the upper electrode 12 are electrically connected using an opening provided in the interlayer insulating layer 61.

[0114] Figure 6 is a schematic top view of a part of the semiconductor device of the first embodiment. Figure 6 is a top view of the first surface F1. Figure 6 is a top view of the region R enclosed by the dotted line in Figure 1.

[0115] As shown in Figure 6, in the first surface F1, the end of the second trench 22 in the first direction is in contact with the guard ring region 34.

[0116] Next, we will explain how to drive the RC-IGBT100.

[0117] In the off state of the IGBT in transistor region 101, for example, an emitter voltage is applied to the upper electrode 12. The emitter voltage is, for example, 0V. A collector voltage is applied to the lower electrode 14. The collector voltage is, for example, between 200V and 6500V.

[0118] In the off state of the IGBT, a turn-off voltage is applied to the first gate electrode pad 104. In the off state of the IGBT, a turn-off voltage is applied to the first conductive layer 51 in the first gate trench of the transistor region 101. The turn-off voltage is a voltage below a threshold voltage at which the transistor having the first gate trench does not turn on, for example, 0V or a negative voltage.

[0119] When the IGBT is turned on, a first gate voltage (Vg1) is applied to the first gate electrode pad 104. The first gate voltage (Vg1) is the so-called turn-on voltage. When the IGBT is turned on, the first gate voltage (Vg1) is applied to the first conductive layer 51 in the first gate trench of the transistor region 101.

[0120] The first gate voltage (Vg1) is a positive voltage exceeding the threshold voltage of the transistor having the first gate trench. The first gate voltage (Vg1) is, for example, 15V. When the first gate voltage (Vg1) is applied to the first conductive layer 51, an n-type inversion layer is formed in the cell base region 28 in contact with the first gate trench, and the transistor having the first gate trench is turned ON.

[0121] When the IGBT in transistor region 101 is in the off state and freewheeling current is flowed using the diode in diode region 102, a second gate voltage (Vg2) is applied to the second gate electrode pad 105. For example, the second gate voltage (Vg2) is applied to the second gate electrode pad 105 when the diode is conducting and when it is in reverse recovery state.

[0122] When a freewheeling current is passed using a diode, a second gate voltage (Vg2) is applied to the second conductive layer 52 in the second gate trench of the diode region 102.

[0123] The second gate voltage (Vg2) is a negative voltage. For example, the second gate voltage (Vg2) is -15V.

[0124] By applying a negative voltage, the second gate voltage (Vg2), to the second conductive layer 52, a p-type storage layer is formed in the anode region 32 in contact with the second gate trench. Furthermore, by applying the second gate voltage (Vg2) to the second conductive layer 52, a p-type inversion layer is formed in the drift region 27 in contact with the second gate trench.

[0125] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0126] Figure 7 is a schematic cross-sectional view of a part of the semiconductor device of the comparative example. Figure 7 corresponds to Figure 4 of the first embodiment.

[0127] The comparative example semiconductor device is an RC-IGBT900, in which an IGBT and a freewheeling diode are formed on the same semiconductor chip. The comparative example RC-IGBT900 differs from the RC-IGBT100 of the first embodiment in that the second conductive layer 52 in all the second trenches 22 provided in the diode region 102 is electrically connected to the upper electrode 12. In other words, the comparative example RC-IGBT900 differs from the RC-IGBT100 of the first embodiment in that all the second trenches 22 provided in the diode region 102 are second dummy trenches.

[0128] Figures 8 and 9 are explanatory diagrams illustrating the problems of the comparative semiconductor device. Figure 8 shows the flow of hole current when the diode in diode region 102 is in a conducting state. Figure 9 shows the flow of hole current when the diode in diode region 102 is in a reverse recovery state. Figures 8 and 9 correspond to Figure 7.

[0129] As shown in Figure 8, when the diode in diode region 102 is conducting, holes are injected from the anode region 32 into the drift region 27. Also, the parasitic diode in terminal region 103 becomes conducting, and holes are injected from the guard ring region 34 into the drift region 27. As a result, there is an excess of holes in the drift region 27 near the end of diode region 102 on the terminal region 103 side.

[0130] As shown in Figure 9, when the diode in diode region 102 is in a reverse recovery state, holes are discharged from the drift region 27 through the anode region 32 to the upper electrode 12. Also, holes are discharged from the drift region 27 through the guard ring region 34 to the upper electrode 12.

[0131] In the drift region 27 near the end of the diode region 102 on the terminal region 103 side, there is an excess of holes, which delays the discharge of holes to the upper electrode 12. Consequently, the reverse recovery current (Irr) during the reverse recovery of the diode increases, and the reverse recovery loss (Err) of the diode increases.

[0132] For example, when using RC-IGBT900 as a switching element in an inverter circuit, two RC-IGBT900s are installed in series on the high-side and low-side, respectively. For instance, if the reverse recovery loss (Err) of the diode in one RC-IGBT900 increases, the turn-on loss (Eon) of the IGBT in the other RC-IGBT900 increases, increasing the losses in the inverter circuit. Therefore, it is desirable to reduce the reverse recovery loss (Err) of the diodes in the RC-IGBT900.

[0133] Figure 10 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 10 is a diagram showing the flow of hole current when the diode in the diode region 102 is in the reverse recovery state. Figure 10 corresponds to Figure 4.

[0134] In the first embodiment of the RC-IGBT 100, the second conductive layer 52 in the second trench 22 near the end of the diode region 102 on the termination region 103 side is electrically connected to the second gate electrode pad 105. In other words, the second trench 22 near the end of the diode region 102 on the termination region 103 side is the second gate trench.

[0135] For example, when the diode in diode region 102 is in a reverse recovery state, a second gate voltage (Vg2) is applied to the second conductive layer 52 in the second gate trench. The second gate voltage (Vg2) is a negative voltage.

[0136] By applying a negative voltage, the second gate voltage (Vg2), to the second conductive layer 52, a p-type storage layer is formed in the anode region 32 in contact with the second gate trench. As a result, the electrical resistance of the anode region 32 in contact with the second gate trench is reduced.

[0137] Furthermore, by applying a second gate voltage (Vg2) to the second conductive layer 52, a p-type inversion layer is formed in the drift region 27 in contact with the second gate trench, where holes are induced. As a result, the electrical resistance of the drift region 27 in contact with the second gate trench is reduced.

[0138] Therefore, as shown in Figure 10, near the end of the diode region 102 on the terminal region 103 side, the discharge of holes from the drift region 27 to the upper electrode 12 is promoted. As a result, the reverse recovery current (Irr) during the reverse recovery of the diode is reduced, and the reverse recovery loss (Err) of the diode is reduced.

[0139] By reducing the diode's reverse recovery loss (Err), the turn-on loss (Eon) is also reduced when the RC-IGBT100 is used as a switching element in an inverter circuit. Therefore, the losses in the inverter circuit using the RC-IGBT100 are reduced.

[0140] Figure 11 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 11 is a diagram showing the flow of hole current when the diode in the diode region 102 is in a conducting state. Figure 11 corresponds to Figure 4.

[0141] For example, when the diode in the diode region 102 is in a conductive state, a second gate voltage (Vg2) is applied to the second conductive layer 52 in the second gate trench. The second gate voltage (Vg2) is a negative voltage.

[0142] By applying a negative voltage, the second gate voltage (Vg2), to the second conductive layer 52, a p-type storage layer is formed in the anode region 32 in contact with the second gate trench. As a result, the hole density in the anode region 32 in contact with the second gate trench increases.

[0143] Furthermore, the application of a second gate voltage (Vg2) to the second conductive layer 52 causes a p-type inversion layer to form in the drift region 27 in contact with the second gate trench. As a result, the hole density in the drift region 27 in contact with the second gate trench increases.

[0144] Therefore, as shown in Figure 11, the injection of holes from the anode region 32 to the drift region 27 is promoted. Thus, the forward voltage (V) when the diode conducts is FThe coefficient of the diode decreases. Therefore, the conduction loss of the diode is reduced.

[0145] According to the first embodiment, the reverse recovery loss (Err), turn-on loss (Eon), and conduction loss of the RC-IGBT100 are reduced.

[0146] In the RC-IGBT100, from the viewpoint of reducing charge and discharge losses caused by the second gate voltage (Vg2) applied to the second gate electrode pad 105, it is preferable to provide a second diode region 102b with a lower ratio of second gate trenches compared to the first diode region 102a. By reducing the number of second gate trenches, the power consumed for charging and discharging the second conductive layer 52 can be reduced.

[0147] In the second trench 22, where the second conductive layer 52 is electrically connected to the second gate electrode pad 105, the distance between the second trench 22y furthest from the guard ring region 34 and the guard ring region 34 (d in Figure 4) is preferably greater than or equal to the thickness of the semiconductor layer 10 in the direction from the first surface F1 to the second surface F2 (t in Figure 4). The diffusion distance of holes injected from the guard ring region 34 in the second direction is approximately the thickness t of the semiconductor layer 10, and by satisfying the above condition, the reverse recovery loss of the diode can be effectively suppressed.

[0148] As shown in Figure 6, in the first surface F1, it is preferable that the end of the second trench 22 in the first direction is in contact with the guard ring region 34. With this configuration, the discharge of holes from the drift region 27 to the upper electrode 12 is promoted not only near the end of the diode region 102 in the second direction, but also near the end of the diode region 102 in the first direction, thereby reducing the reverse recovery loss (Err) of the diode.

[0149] (First variation) The semiconductor device of the first modification of the first embodiment differs from the semiconductor device of the first embodiment in that a second conductive layer provided in a portion of the second trench within the first region of the diode region is electrically connected to the first electrode.

[0150] Figure 12 is a schematic cross-sectional view of a part of a semiconductor device of a first modification of the first embodiment. Figure 12 corresponds to Figure 4 of the first embodiment.

[0151] As shown in Figure 12, the second conductive layer 52 in the second trench 22, which is part of the second trench 22 within the first diode region 102a, is electrically connected to the upper electrode 12. In other words, part of the second trench 22 within the first diode region 102a is the second dummy gate trench.

[0152] In Figure 12, the number of second trenches 22 in the first diode region 102a is 5, and the number of second gate trenches is 3. Therefore, the ratio of the number of second gate trenches to the number of second trenches 22 in the first diode region 102a is 60%. Also, the number of second trenches 22 in the second diode region 102b is 3, and the number of second gate trenches is 0. Therefore, the ratio of the number of second gate trenches to the number of second trenches 22 in the second diode region 102b is 0%.

[0153] For example, a portion of the second conductive layer 52 within the second trench 22 in the second diode region 102b may be electrically connected to the second gate electrode pad 105. For example, in Figure 12, if one second gate trench is provided in the second diode region 102b, the ratio of the number of second gate trenches to the number of second trenches 22 in the second diode region 102b will be 33.3%.

[0154] In Figure 12, the arrangement pattern of the second gate trench and the second dummy trench in the second direction in the first diode region 102a is the same as the arrangement pattern of the first gate trench and the first dummy trench in the second direction in the transistor region 101 shown in the figure of the first embodiment. By making the arrangement pattern of the second gate trench and the second dummy trench in the second direction in the first diode region 102a the same as the arrangement pattern of the first gate trench and the first dummy trench in the second direction in the transistor region 101, the pattern design of an RC-IGBT, for example, becomes easier.

[0155] According to the first modification of the first embodiment, the reverse recovery loss (Err), turn-on loss (Eon), and conduction loss of the RC-IGBT are reduced, similar to the first embodiment.

[0156] (Second variation) The semiconductor device of the second modification of the first embodiment differs from the semiconductor device of the first embodiment in that the second conductive layer provided in all of the plurality of second trenches is electrically connected to the second electrode pad.

[0157] Figure 13 is a schematic cross-sectional view of a part of a semiconductor device of a second modification of the first embodiment. Figure 13 corresponds to Figure 4 of the first embodiment.

[0158] As shown in Figure 13, the second conductive layer 52 provided in all of the second trenches 22 is electrically connected to the second gate electrode pad 105.

[0159] According to the second modification of the first embodiment, the reverse recovery loss (Err), turn-on loss (Eon), and conduction loss of the RC-IGBT are reduced, similar to the first embodiment. Furthermore, by increasing the second gate trench of the diode region 102, the forward voltage (V) when the diode conducts is further reduced. F This reduces the voltage, thereby lowering the conduction loss of the diode.

[0160] (Third variation) The semiconductor device of the third modification of the first embodiment differs from the semiconductor device of the first embodiment in that the termination region is provided within the semiconductor layer and provided between the second semiconductor region and the second surface, further including a ninth semiconductor region having a first conductivity type with a first conductivity type impurity concentration higher than that of the seventh semiconductor region, and the second electrode is in contact with the ninth semiconductor region.

[0161] Figure 14 is a schematic cross-sectional view of a part of a semiconductor device of a third modification of the first embodiment. Figure 14 corresponds to Figure 4 of the first embodiment.

[0162] As shown in Figure 14, the terminal region 103 is between the drift region 27 and the second surface F2, p + The terminal back surface p region 37, which includes the shaped terminal back surface p region 37, is in contact with the lower electrode 14.

[0163] The p-type impurity concentration in the terminal back surface p-region 37 is higher than the p-type impurity concentration in the guard ring region 34.

[0164] According to the third modification of the first embodiment, the reverse recovery loss (Err), turn-on loss (Eon), and conduction loss of the RC-IGBT are reduced, similar to the first embodiment. Furthermore, since the termination region 103 includes the termination back surface p region 37, hole injection from parasitic diodes in the termination region 103 is suppressed. Therefore, the reverse recovery loss (Err) and turn-on loss (Eon) are further reduced.

[0165] As described above, according to the first embodiment and its variations, a semiconductor device can be realized that includes an RC-IGBT having an IGBT and a diode, enabling loss reduction.

[0166] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the third conductive layer provided in the third trench is electrically connected to the second electrode pad. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0167] The semiconductor device of the second embodiment is an RC-IGBT200 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip.

[0168] Figure 15 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment. Figure 15 corresponds to Figure 4 of the first embodiment.

[0169] Multiple third trenches 23 are provided within the semiconductor layer 10 of the termination region 103 of the RC-IGBT200. As shown in Figure 15, the third conductive layer 53 provided within all of the third trenches 23 is electrically connected to the second gate electrode pad 105.

[0170] Figure 16 is a schematic top view of a part of the semiconductor device of the second embodiment. Figure 16 is a top view of the first surface F1. Figure 16 corresponds to Figure 6 of the first embodiment.

[0171] As shown in Figure 16, in the first surface F1, the end of the second trench 22 in the first direction is in contact with the guard ring region 34.

[0172] In the second embodiment of the RC-IGBT200, similar to the RC-IGBT100 of the first embodiment, the second conductive layer 52 in the second trench 22 near the end of the diode region 102 on the termination region 103 side is electrically connected to the second gate electrode pad 105. Therefore, the RC-IGBT200, similar to the RC-IGBT100, has reduced reverse recovery loss (Err), turn-on loss (Eon), and conduction loss.

[0173] Figure 17 is an explanatory diagram of the operation and effects of the semiconductor device of the second embodiment. Figure 17 shows the flow of hole current when the diode in diode region 102 is in the reverse recovery state. Figure 17 corresponds to Figure 15.

[0174] In the second embodiment of the RC-IGBT200, the third conductive layer 53 in the third trench 23 of the termination region 103 is electrically connected to the second gate electrode pad 105.

[0175] For example, when the diode in diode region 102 is in a reverse recovery state, a second gate voltage (Vg2) is applied to the third conductive layer 53 in the third gate trench. The second gate voltage (Vg2) is a negative voltage.

[0176] By applying a negative voltage second gate voltage (Vg2) to the third conductive layer 53, a p-type storage layer is formed in the guard ring region 34 in contact with the third trench 23. As a result, the electrical resistance of the guard ring region 34 in contact with the third trench is reduced.

[0177] Therefore, as shown in Figure 17, the discharge of holes from the drift region 27 to the upper electrode 12 via the guard ring region 34 is promoted. As a result, the reverse recovery current (Irr) during the reverse recovery of the diode is further reduced, and the reverse recovery loss (Err) of the diode is further reduced.

[0178] By reducing the diode's reverse recovery loss (Err), the turn-on loss (Eon) is further reduced when the RC-IGBT200 is used as a switching element in an inverter circuit.

[0179] Furthermore, the end of the second trench 22 in the first direction is in contact with the guard ring region 34. Therefore, when the diode is in the reverse recovery state, a p-type accumulation layer is formed in the guard ring region 34 that is in contact with the second gate trench at the end of the first direction that is located within the guard ring region 34. Thus, the discharge of holes from the drift region 27 to the upper electrode 12 via the guard ring region 34 is further promoted.

[0180] In particular, at the corners of the diode region 102 as shown in Figure 16, guard ring regions 34 of the termination region 103 are provided in both the first and second directions. As a result, the injection of holes into the drift region 27 when the diode conducts is concentrated, and the density of holes in the drift region 27 becomes particularly high. Consequently, the hole discharge effect due to the end of the second trench 22 in the first direction contacting the guard ring region 34 becomes particularly pronounced.

[0181] The p-type impurity concentration in the guard ring region 34 is preferably higher than the p-type impurity concentration in the anode region 32. A higher p-type impurity concentration in the guard ring region 34 further promotes the discharge of holes through the guard ring region 34, thereby further reducing the diode's reverse recovery loss (Err).

[0182] Furthermore, it is also acceptable for only the third conductive layer 53 provided in some of the third trenches 23 to be electrically connected to the second gate electrode pad 105.

[0183] Furthermore, the number of third trenches can be as few as one.

[0184] (First variation) The semiconductor device of the first modification of the second embodiment differs from the semiconductor device of the second embodiment in that a second conductive layer provided in a portion of the second trench within the first region of the diode region is electrically connected to the first electrode.

[0185] Figure 18 is a schematic cross-sectional view of a part of the semiconductor device of the first modified example of the second embodiment. Figure 18 corresponds to Figure 15 of the second embodiment.

[0186] As shown in Figure 18, the second conductive layer 52 in the second trench 22, which is part of the second trench 22 within the first diode region 102a, is electrically connected to the upper electrode 12. In other words, part of the second trench 22 within the first diode region 102a is the second dummy gate trench.

[0187] According to the first modification of the second embodiment, the reverse recovery loss (Err), turn-on loss (Eon), and conduction loss of the RC-IGBT are reduced, similar to the second embodiment.

[0188] (Second variation) The semiconductor device of the second modification of the second embodiment differs from the semiconductor device of the second embodiment in that the second conductive layer provided in all of the plurality of second trenches is electrically connected to the second electrode pad.

[0189] Figure 19 is a schematic cross-sectional view of a part of a semiconductor device of a second modification of the second embodiment. Figure 19 corresponds to Figure 15 of the second embodiment.

[0190] As shown in Figure 19, the second conductive layer 52 provided in all of the second trenches 22 is electrically connected to the second gate electrode pad 105.

[0191] According to the second modification of the second embodiment, the reverse recovery loss (Err), turn-on loss (Eon), and conduction loss of the RC-IGBT are reduced, similar to the second embodiment. Furthermore, by increasing the second gate trench of the diode region 102, the forward voltage (V) when the diode conducts is further reduced. F This reduces the voltage, thereby lowering the conduction loss of the diode.

[0192] (Third variation) The semiconductor device of the third modification of the second embodiment differs from the semiconductor device of the first embodiment in that the termination region is provided within the semiconductor layer and provided between the second semiconductor region and the second surface, further including a ninth semiconductor region having a first conductivity type with a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the seventh semiconductor region, and the second electrode is in contact with the ninth semiconductor region.

[0193] Figure 20 is a schematic cross-sectional view of a part of a semiconductor device of a third modification of the second embodiment. Figure 20 corresponds to Figure 15 of the second embodiment.

[0194] As shown in Figure 20, the terminal region 103 is between the drift region 27 and the second surface F2, p + The terminal back surface p region 37 (the ninth semiconductor region), which includes the terminal back surface p region 37, is in contact with the lower electrode 14.

[0195] The p-type impurity concentration in the terminal back surface p-region 37 is higher than, for example, the p-type impurity concentration in the anode region 32.

[0196] According to the third modification of the second embodiment, the reverse recovery loss (Err), turn-on loss (Eon), and conduction loss of the RC-IGBT are reduced, similar to the second embodiment. Furthermore, since the termination region 103 includes the termination back surface p region 37, hole injection from parasitic diodes in the termination region 103 is suppressed. Therefore, the reverse recovery loss (Err) and turn-on loss (Eon) are further reduced.

[0197] As described above, according to the second embodiment and its modifications, a semiconductor device can be realized that includes an RC-IGBT having an IGBT and a diode, enabling loss reduction.

[0198] (Third embodiment) The semiconductor device of the third embodiment comprises a transistor region, a diode region, and a termination region that surrounds the transistor region and the diode region, with the diode region provided between it and the transistor region. The transistor region comprises a semiconductor layer having a first surface and a second surface facing the first surface, a first semiconductor region of a first conductivity type provided within the semiconductor layer, a second semiconductor region of a second conductivity type provided within the semiconductor layer and between the first semiconductor region and the first surface, a third semiconductor region of a first conductivity type provided within the semiconductor layer and between the second semiconductor region and the first surface, a fourth semiconductor region of a second conductivity type provided within the semiconductor layer and between the third semiconductor region and the first surface, and the side of the first surface within the semiconductor layer The device includes: a plurality of first trenches provided in a first direction parallel to the first surface, repeatedly arranged in a second direction perpendicular to the first direction and parallel to the first surface, and in contact with a second semiconductor region, a third semiconductor region, and a fourth semiconductor region; a first conductive layer provided in the first trenches; a first insulating film provided between the first conductive layer and the semiconductor layer; a first electrode provided on the side of the semiconductor layer facing the first surface and in contact with the fourth semiconductor region; and a second electrode provided on the side of the semiconductor layer facing the second surface and in contact with the first semiconductor region. The diode region includes a semiconductor layer, a second semiconductor region, a fifth semiconductor region of a second conductivity type provided within the semiconductor layer and between the second semiconductor region and a second surface, having a second conductivity type impurity concentration higher than that of the second conductivity type impurity concentration in the second semiconductor region, a sixth semiconductor region of a first conductivity type provided within the semiconductor layer and between the second semiconductor region and a first surface, a plurality of second trenches provided on the side of the first surface in the semiconductor layer, extending in a first direction and repeatedly arranged in a second direction, in contact with the second semiconductor region and the sixth semiconductor region, a second conductive layer provided within the second trenches, a second insulating film provided between the second conductive layer and the semiconductor layer, a first electrode electrically connected to the sixth semiconductor region and electrically connected to the second conductive layers provided in all of the plurality of second trenches, and a second electrode in contact with the fifth semiconductor region.The termination region includes a semiconductor layer, a second semiconductor region, a seventh semiconductor region of a first conductivity type provided within the semiconductor layer and between the second semiconductor region and a first surface, electrically connected to a first electrode, a third trench provided on the side of the first surface within the semiconductor layer and between the seventh semiconductor region and the first surface, extending in a first direction and in contact with the seventh semiconductor region, a third conductive layer provided within the third trench, a third insulating film provided between the third conductive layer and the semiconductor layer, a first electrode, a second electrode, a first electrode pad provided on the side of the first surface relative to the semiconductor layer and electrically connected to a first conductive layer provided in at least some of the first trenches among a plurality of first trenches, and a second electrode pad provided on the side of the first surface relative to the semiconductor layer and electrically connected to a third conductive layer. The semiconductor device of the third embodiment differs from the semiconductor device of the second embodiment in that the second conductive layer provided in all of the multiple second trenches is electrically connected to the first electrode. Hereafter, some descriptions that overlap with the first and second embodiments may be omitted.

[0199] The semiconductor device of the third embodiment is an RC-IGBT300 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip.

[0200] Figure 21 is a schematic cross-sectional view of a part of the semiconductor device of the third embodiment. Figure 21 corresponds to Figure 15 of the second embodiment.

[0201] Multiple third trenches 23 are provided within the semiconductor layer 10 of the termination region 103 of the RC-IGBT300. As shown in Figure 21, the third conductive layer 53 provided within all of the third trenches 23 is electrically connected to the second gate electrode pad 105.

[0202] Therefore, the discharge of holes from the drift region 27 to the upper electrode 12 via the guard ring region 34 is promoted. As a result, the reverse recovery current (Irr) during the reverse recovery of the diode is reduced, and the reverse recovery loss (Err) of the diode is reduced.

[0203] By reducing the diode's reverse recovery loss (Err), the turn-on loss (Eon) is further reduced when the RC-IGBT300 is used as a switching element in an inverter circuit.

[0204] Furthermore, it is also acceptable for only the third conductive layer 53 provided in some of the third trenches 23 to be electrically connected to the second gate electrode pad 105.

[0205] Furthermore, the number of third trenches can be as few as one.

[0206] The p-type impurity concentration in the guard ring region 34 is preferably higher than the p-type impurity concentration in the anode region 32. A higher p-type impurity concentration in the guard ring region 34 further promotes the discharge of holes through the guard ring region 34, thereby further reducing the diode's reverse recovery loss (Err).

[0207] (modified version) The semiconductor device of the modified third embodiment differs from the semiconductor device of the third embodiment in that the termination region is provided within the semiconductor layer and provided between the second semiconductor region and the second surface, further including a ninth semiconductor region having a first conductivity type with a first conductivity type impurity concentration higher than that of the seventh semiconductor region, and the second electrode is in contact with the ninth semiconductor region.

[0208] Figure 22 is a schematic cross-sectional view of a part of the semiconductor device of the third embodiment. Figure 22 corresponds to Figure 21 of the third embodiment.

[0209] As shown in Figure 22, the terminal region 103 is between the drift region 27 and the second surface F2, p + The terminal back surface p region 37 (the ninth semiconductor region), which includes the terminal back surface p region 37, is in contact with the lower electrode 14.

[0210] The p-type impurity concentration in the terminal back surface p-region 37 is higher than, for example, the p-type impurity concentration in the anode region 32.

[0211] As described above, according to the third embodiment and its modifications, a semiconductor device can be realized that includes an RC-IGBT having an IGBT and a diode, enabling loss reduction.

[0212] In the first to third embodiments, the case where the semiconductor layer is single-crystal silicon was described as an example, but the semiconductor layer is not limited to single-crystal silicon. For example, it may be other single-crystal semiconductors such as single-crystal silicon carbide.

[0213] In the first to third embodiments, the case where the first conductivity type is p-type and the second conductivity type is n-type was described as an example, but it is also possible to have the first conductivity type be n-type and the second conductivity type be p-type.

[0214] In the first to third embodiments, it is also possible to employ a so-called trench contact, in which the upper electrode 12 is embedded in a trench provided in the semiconductor layer 10.

[0215] In the first to third embodiments, lifetime control is also possible.

[0216] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0217] 10 Semiconductor Layers 12 Upper electrode (first electrode) 14. Lower electrode (second electrode) 21 The first trench 22 The second trench 23 The Third Trench 26. Collector region (first semiconductor region) 27. Drift region (second semiconductor region) 28. Cell-based region (third semiconductor region) 29. Cell emitter region (fourth semiconductor region) 31. Cathode region (5th semiconductor region) 32. Anode region (6th semiconductor region) 34. Guard Ring Region (7th Semiconductor Region) 35. Termination cathode region (8th semiconductor region) 41 First insulating film 42 Second insulating film 43 Third insulating film 51 First conductive layer 52 Second conductive layer 53 Third conductive layer 100 RC-IGBT (Semiconductor Device) 101 Transistor Region 102 Diode region 102a First diode region (first region) 102b Second diode region (second region) 103 Termination area 104 First gate electrode pad (first electrode pad) 105 Second gate electrode pad (second electrode pad) 200 RC-IGBT (Semiconductor Device) 300 RC-IGBT (Semiconductor Device) F1 First Side F2 Second side

Claims

1. The transistor region and Diode region and The system comprises a terminal region that surrounds the transistor region and the diode region, and between the transistor region and the diode region, The aforementioned transistor region is A semiconductor layer having a first surface and a second surface facing the first surface, A first semiconductor region of a first conductivity type provided within the semiconductor layer, A second semiconductor region of a second conductivity type is provided within the semiconductor layer and between the first semiconductor region and the first surface, A third semiconductor region of a first conductivity type is provided within the semiconductor layer and between the second semiconductor region and the first surface, A fourth semiconductor region of a second conductivity type is provided within the semiconductor layer and between the third semiconductor region and the first surface, A plurality of first trenches are provided on the side of the first surface within the semiconductor layer, extending in a first direction parallel to the first surface, repeatedly arranged in a second direction perpendicular to the first direction and parallel to the first surface, and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region. A first conductive layer provided in the first trench, A first insulating film is provided between the first conductive layer and the semiconductor layer, A first electrode is provided on the side of the first surface of the semiconductor layer and is in contact with the fourth semiconductor region, The semiconductor layer includes a second electrode provided on the second surface side and in contact with the first semiconductor region, The diode region is The semiconductor layer and, The second semiconductor region described above, A fifth semiconductor region of a second conductivity type is provided within the semiconductor layer, between the second semiconductor region and the second surface, and having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the second semiconductor region. A sixth semiconductor region of a first conductivity type is provided within the semiconductor layer and is located between the second semiconductor region and the first surface, A plurality of second trenches are provided on the side of the first surface within the semiconductor layer, extending in the first direction, repeatedly arranged in the second direction, and in contact with the second semiconductor region and the sixth semiconductor region. A second conductive layer provided in the second trench, A second insulating film is provided between the second conductive layer and the semiconductor layer, The first electrode electrically connected to the sixth semiconductor region, The second electrode in contact with the fifth semiconductor region, Includes, The aforementioned termination region is The semiconductor layer and, The second semiconductor region described above, A seventh semiconductor region of a first conductivity type is provided within the semiconductor layer, between the second semiconductor region and the first surface, and electrically connected to the first electrode, A third trench is provided on the side of the first surface within the semiconductor layer, between the seventh semiconductor region and the first surface, extending in the first direction and in contact with the seventh semiconductor region, A third conductive layer provided in the third trench, A third insulating film is provided between the third conductive layer and the semiconductor layer, The first electrode and, The first electrode 2, A first electrode pad is provided on the first surface side of the semiconductor layer and is electrically connected to the first conductive layer provided in at least some of the first trenches among the plurality of first trenches, A second electrode pad is provided on the first surface side of the semiconductor layer and is electrically connected to the second conductive layer, which is provided in the second trench closest to the third trench among a plurality of second trenches. Semiconductor equipment, including

2. The termination region is provided within the semiconductor layer and between the second semiconductor region and the second surface, further including an eighth semiconductor region of a second conductivity type having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the second semiconductor region. The semiconductor device according to claim 1, wherein the second electrode is in contact with the eighth semiconductor region.

3. The semiconductor device according to claim 1, wherein the second conductive layer provided in some of the second trenches among the plurality of second trenches is electrically connected to the first electrode.

4. The diode region includes a first region and a second region provided between the first region and the transistor region in the second direction. The semiconductor layer in the first region includes a plurality of second trenches, including the second trench closest to the third trench. The semiconductor layer in the second region includes a plurality of the second trenches, The semiconductor device according to claim 1, wherein, among a plurality of the second trenches in the first region, the number of second trenches in which a second conductive layer electrically connected to the second electrode pad is provided is greater than the number of second trenches in a plurality of the second trenches in the second region in which a second conductive layer electrically connected to the second electrode pad is provided is greater than the number of second trenches in a plurality of the second trenches in the second region in which a second conductive layer electrically connected to the second electrode pad is provided is greater than the number of second trenches in a plurality of the second trenches in the second region.

5. The semiconductor device according to claim 1, wherein the second conductive layer provided in all of the plurality of second trenches is electrically connected to the second electrode pad.

6. The semiconductor device according to claim 1, wherein in the second trench provided therein, which contains the second conductive layer electrically connected to the second electrode pad, the distance between the seventh semiconductor region and the seventh semiconductor region of the second trench that is furthest from the seventh semiconductor region in the second direction is greater than or equal to the thickness of the semiconductor layer in the direction from the first surface to the second surface.

7. The semiconductor device according to claim 1, wherein the third conductive layer is electrically connected to the second electrode pad.

8. The semiconductor device according to claim 1, wherein the concentration of the first conductivity type impurity in the seventh semiconductor region is higher than the concentration of the first conductivity type impurity in the sixth semiconductor region.

9. The semiconductor device according to claim 1, wherein there are multiple third trenches, the third trenches are repeatedly arranged in the second direction, and the third conductive layers in the multiple third trenches are electrically connected to the second electrode pad.

10. The semiconductor device according to claim 1, wherein the seventh semiconductor region surrounds the transistor region and the diode region.

11. The semiconductor device according to claim 1, wherein the ends of the plurality of second trenches in the first direction are in contact with the seventh semiconductor region.

12. The semiconductor device according to claim 1, wherein the first conductive layer provided in another portion of the first trenches among the plurality of first trenches is electrically connected to the first electrode.

13. The transistor region and Diode region and The system comprises a terminal region that surrounds the transistor region and the diode region, and between the transistor region and the diode region, The aforementioned transistor region is A semiconductor layer having a first surface and a second surface facing the first surface, A first semiconductor region of a first conductivity type provided within the semiconductor layer, A second semiconductor region of a second conductivity type is provided within the semiconductor layer and between the first semiconductor region and the first surface, A third semiconductor region of a first conductivity type is provided within the semiconductor layer and between the second semiconductor region and the first surface, A fourth semiconductor region of a second conductivity type is provided within the semiconductor layer and between the third semiconductor region and the first surface, A plurality of first trenches are provided on the side of the first surface within the semiconductor layer, extending in a first direction parallel to the first surface, repeatedly arranged in a second direction perpendicular to the first direction and parallel to the first surface, and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region. A first conductive layer provided in the first trench, A first insulating film is provided between the first conductive layer and the semiconductor layer, A first electrode is provided on the side of the first surface of the semiconductor layer and is in contact with the fourth semiconductor region, The semiconductor layer includes a second electrode provided on the second surface side and in contact with the first semiconductor region, The diode region is The semiconductor layer and, The second semiconductor region described above, A fifth semiconductor region of a second conductivity type is provided within the semiconductor layer, between the second semiconductor region and the second surface, and having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the second semiconductor region. A sixth semiconductor region of a first conductivity type is provided within the semiconductor layer and is located between the second semiconductor region and the first surface, A plurality of second trenches are provided on the side of the first surface within the semiconductor layer, extending in the first direction, repeatedly arranged in the second direction, and in contact with the second semiconductor region and the sixth semiconductor region. A second conductive layer provided in the second trench, A second insulating film is provided between the second conductive layer and the semiconductor layer, The first electrode is electrically connected to the sixth semiconductor region and to the second conductive layer provided in all of the plurality of second trenches, The second electrode in contact with the fifth semiconductor region, Includes, The aforementioned termination region is The semiconductor layer and, The second semiconductor region described above, A seventh semiconductor region of a first conductivity type is provided within the semiconductor layer, between the second semiconductor region and the first surface, and electrically connected to the first electrode, A third trench is provided on the side of the first surface within the semiconductor layer, between the seventh semiconductor region and the first surface, extending in the first direction and in contact with the seventh semiconductor region, A third conductive layer provided in the third trench, A third insulating film is provided between the third conductive layer and the semiconductor layer, The first electrode and, The first electrode 2, A first electrode pad is provided on the first surface side of the semiconductor layer and is electrically connected to the first conductive layer provided in at least some of the first trenches among the plurality of first trenches, A second electrode pad is provided on the first surface side of the semiconductor layer and is electrically connected to the third conductive layer, Semiconductor equipment, including

14. The termination region is provided within the semiconductor layer and between the second semiconductor region and the second surface, further including an eighth semiconductor region of a second conductivity type having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the second semiconductor region. The semiconductor device according to claim 13, wherein the second electrode is in contact with the eighth semiconductor region.

15. The semiconductor device according to claim 13, wherein the concentration of the first conductivity type impurity in the seventh semiconductor region is higher than the concentration of the first conductivity type impurity in the sixth semiconductor region.

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