Semiconductor device and method for manufacturing a semiconductor device.

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same that improve the switching speed of a transistor. [Solution] The semiconductor device 100 has a silicon carbide epitaxy layer 101 which includes a p-type well region PW, a heavily doped n-type region 107 located on the surface of the p-type well region, and a heavily doped p-type region 105 located below the heavily doped n-type region and within the p-type well region. The semiconductor device further includes a first gate pole trench TR1 that penetrates the p-type well region, and a first deeply doped p-type region DP1 whose width is narrower than the width of the first gate pole trench.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a power MOS (Metal-Oxide-Semiconductor) transistor.

Background Art

[0002] In a conventional power MOS transistor, since there is a strong electric field at the edge of the trench, the drain-to-source breakdown voltage (BVDSS) is low, and there is a problem of reduced reliability. In order to overcome these problems, a new semiconductor device and a method for manufacturing a semiconductor device are required.

Summary of the Invention

[0003] In view of the above, the semiconductor device of the present invention includes a p-type well region, a heavily doped n-type region on the surface of the p-type well region, and a heavily doped p-type region below the heavily doped n-type region and within the p-type well region, a silicon carbide epitaxial layer including the above, and the semiconductor device further includes a first gate electrode trench penetrating the p-type well region, a first deep doped p-type region below the first gate electrode trench, a gate electrode oxide layer on the bottom surface and side surfaces of the first gate electrode trench and on the heavily doped n-type region, a polysilicon layer on the gate electrode oxide layer, an interlayer dielectric layer on the polysilicon layer, and a source electrode trench penetrating the interlayer dielectric layer and the gate electrode oxide layer and extending into the heavily doped n-type region and the heavily doped p-type region, and the width of the first deep doped p-type region is narrower than the width of the first gate electrode trench.

[0004] The present invention provides a silicon carbide epitaxy layer in which a p-type well region, a heavily doped n-type region on the surface of the p-type well region, and a heavily doped p-type region located below the heavily doped n-type region and within the p-type well region are predetermined; a first gate electrode trench is formed in the silicon carbide epitaxy layer through the p-type well region; and a width narrower than the width of the first gate electrode trench is formed in the silicon carbide epitaxy layer below the first gate electrode trench. A method for manufacturing a semiconductor device, comprising: forming a first deep-doped p-type region; forming a gate pole oxide layer on the bottom surface and side surface of the first gate pole trench and on the heavily doped n-type region; forming a polysilicon layer on the gate pole oxide layer; forming an interlayer dielectric layer on the polysilicon layer; and forming a source pole trench that penetrates the interlayer dielectric layer and the gate pole oxide layer and extends into the heavily doped n-type region and the heavily doped p-type region.

[0005] In summary, the first deep-doped p-type region below the first gate electrode trench and the second deep-doped p-type region below the second gate electrode trench release the strong electric field at the edge, thereby increasing the breakdown voltage between the drain electrode and the source electrode. Furthermore, the on-resistance (Rdson) can be optimized by adjusting the distance between the first and second deep-doped p-type regions. The junctions formed by the first and second deep-doped p-type regions with the N-type silicon carbide epitaxy layer 101 reduce the parasitic capacitance Cgd, thereby improving the switching speed of the transistor. [Brief explanation of the drawing]

[0006] [Figure 1] This is a cross-sectional view of the semiconductor device 100 according to the present invention.

[0007] [Figure 2] This is a flowchart of the semiconductor device manufacturing method 200 according to the present invention.

[0008] [Figure 3] Another cross-sectional view of the semiconductor device 100.

[0009] [Figure 4] Another cross-sectional view of the semiconductor device 100.

[0010] [Figure 5] Another cross-sectional view of the semiconductor device 100.

[0011] [Figure 6] Another cross-sectional view of the semiconductor device 100.

[0012] [Figure 7] Another cross-sectional view of the semiconductor device 100.

[0013] [Figure 8] Another cross-sectional view of the semiconductor device 100.

[0014] [Figure 9] Another cross-sectional view of the semiconductor device 100.

[0015] [Figure 10] Another cross-sectional view of the semiconductor device 100.

[0016] [Figure 11] Another cross-sectional view of the semiconductor device 100.

[0017] [Figure 12] Another cross-sectional view of the semiconductor device 100.

[0018] [Figure 13] Another cross-sectional view of the semiconductor device 100.

[0019] [Figure 14]Another cross-sectional view of the semiconductor device 100.

[0020] [Figure 15] Another cross-sectional view of the semiconductor device 100.

[0021] [Figure 16] Another cross-sectional view of the semiconductor device 100.

[0022] [Figure 17] Another cross-sectional view of the semiconductor device 100.

Embodiments for Carrying Out the Invention

[0023] Figure 1 is a cross-sectional view of a semiconductor device 100 according to the present invention. As shown in Figure 1, the semiconductor device 100 includes a silicon carbide epitaxy layer 101, gate electrode trenches TR1 and TR2, deep-doped p-type regions DP1 and DP2, gate electrode oxide layer 102, polysilicon layer 103, interlayer dielectric layer 104, and source electrode trench STR. More specifically, the silicon carbide epitaxy layer 101 includes a p-type well region PW, a heavily doped n-type region 107 on the surface of the p-type well region, and a heavily doped p-type region 105 located below the heavily doped n-type region 107 and within the p-type well region PW. In some embodiments, to reduce roughness due to the trenches, the interlayer dielectric layer 104 has two interlayer dielectric layers ILD1 and ILD2. The semiconductor device 100 further includes a metal silicide SC, a metal layer 106 located below the metal silicide SC, a silicon carbide substrate 111 located below the silicon carbide epitaxy layer 101, and a metal layer 112 located below the silicon carbide substrate 111. More specifically, the metal layer 106 is located in a source electrode trench STR and contacts a heavily doped p-type region 105 and a heavily doped n-type region 107 via the metal silicide SC. The patterned metal layer 106 acts as a gate electrode pad and is electrically connected to the polysilicon layer 103 in the gate electrode trenches TR1 and TR2 belonging to different transistor cells. The metal layer 106 in the source electrode trench STR can constitute a source electrode pad. The composition of the metal layers 106 and 112 includes, but is not limited to, Ni, Ti, TiN, Al, Cu, etc. In a preferred embodiment of the present invention, the metal layers 106 and 112 are aluminum-copper alloys.

[0024] The gate electrode trenches TR1 and TR2 penetrate the p-type well region PW. The deeply doped p-type region DP1 is below the gate electrode trench TR1, and the deeply doped p-type region DP2 is below the gate electrode trench TR2. In some embodiments, the width of the deeply doped p-type region DP1 is narrower than the width of the gate electrode trench TR1. The gate electrode oxide layer 102 is on the bottom and side surfaces of the gate electrode trench TR1, on the bottom and side surfaces of the gate electrode trench TR2, and on a portion of the heavily doped n-type region 107. The polysilicon layer 103 is on the gate electrode oxide layer 102, the interlayer dielectric layer 104 is on the polysilicon layer 103, and the source electrode trench STR penetrates the interlayer dielectric layer 104 and the gate electrode oxide layer 102, extending into the heavily doped n-type region 107 and the heavily doped n-type region 105. As shown in Figure 1, the gate electrode trench TR1 and the deeply doped p-type region DP1 are contained within one transistor cell, while the gate electrode trench TR2 and the deeply doped p-type region DP2 are contained within another transistor cell adjacent to the aforementioned transistor cell.

[0025] In Figure 1, the bottom surface of gate electrode trench TR2 is lower than the bottom surface of gate electrode trench TR1. The width of the deep-doped p-type region DP2 is wider than the width of gate electrode trench TR2. Gate electrode trench TR1 and deep-doped p-type region DP1 and gate electrode trench TR2 and deep-doped p-type region DP2 belong to different transistor cells.

[0026] In some embodiments, the configuration of gate electrode trench TR2 can be replaced with the configuration of gate electrode trench TR1 to form gate electrode trench TR3 as shown in Figure 16. In other words, the configuration of gate electrode trench TR3 in Figure 16 is the same as the configuration of gate electrode trench TR1. Referring to Figure 16, the height of the bottom surface of gate electrode trench TR3 is the same as the height of the bottom surface of gate electrode trench TR1, and the width of the bottom surface of gate electrode trench TR3 is the same as the width of the bottom surface of gate electrode trench TR1. As a result, the width of the deep-doped p-type region DP3 (which may be symmetrical to the deep-doped p-type region DP1) below gate electrode trench TR3 is narrower than the width of gate electrode trench TR3. The polysilicon layer 103 in gate electrode trench TR3 is cut open during the etching process, exposing the gate electrode oxide layer 102, so that the interlayer dielectric layer 104 can contact the gate electrode oxide layer 102 in gate electrode trench TR3, as shown in Figure 16. The gate electrode trench TR1 and deep-doped p-type region DP1, and the gate electrode trench TR3 and deep-doped p-type region DP3, can each belong to different transistor cells.

[0027] In some embodiments, the configuration of the gate electrode trench TR2 can be changed to the configuration of the gate electrode trench TR4 as shown in Figure 17. Referring to Figure 17, the height of the bottom surface of the gate electrode trench TR4 is the same as that of the gate electrode trench TR1, and the width of the bottom surface of the gate electrode trench TR4 is narrower than that of the gate electrode trench TR1. As a result, the width of the deep-doped p-type region DP4 (which can be similar to the deep-doped p-type region DP2 except for its depth) located below the gate electrode trench TR4 is wider than the width of the gate electrode trench TR4, but the interlayer dielectric layer 104 does not come into contact with the gate electrode oxide layer 102 in the gate electrode trench TR4. The gate electrode trench TR1 and the deep-doped p-type region DP1 and the gate electrode trench TR4 and the deep-doped p-type region DP4 can each belong to different transistor cells.

[0028] Figure 2 is a flowchart of the semiconductor device manufacturing method 200 according to the present invention, and Figures 3 to 15 are cross-sectional views of the semiconductor device 100, which illustrate steps 201 to 207 of the method 200.

[0029] First, in step 201, a silicon carbide epitaxy layer 101 is provided. As shown in Figure 3, a p-type well region PW, a heavily doped n-type region 107 on the surface of the p-type well region PW, a heavily doped p-type region 105 located below the heavily doped n-type region 107 and within the p-type well region PW, a protective ring region GR, and a deep-doped p-type region DP2 (i.e., a second deep-doped p-type region) are predefined on the silicon carbide epitaxy layer 101. As shown in Figure 4, a hard mask layer HM1 is deposited on the silicon carbide epitaxy layer 101, and the hard mask layer HM1 is patterned so that the opening OP1 of the patterned hard mask layer HM1 is positioned between the two heavily doped n-type regions 107. The opening OP1 defines the region of the gate pole trench TR1. The step of patterning the hard mask layer HM1 includes forming a photoresist on top of the hard mask layer HM1, performing a lithography process to pattern the photoresist, performing an etching process to form an opening OP1 in the hard mask layer HM1, and then removing the photoresist.

[0030] In step 202, a first gate electrode trench is formed in the silicon carbide epitaxy layer 101, penetrating the p-type well region PW. As shown in Figure 5, an etching process is performed to remove the portion exposed by the opening OP1 in the silicon carbide epitaxy layer 101, forming a gate electrode trench TR1 (i.e., the first gate electrode trench) penetrating the p-type well region PW. As shown in Figure 6, hard mask layers HM2 and HM3 are deposited on the etched hard mask layer HM1 in this order, and the etching selectivity of hard mask layer HM3 is higher than that of hard mask layer HM2.

[0031] In step 203, a first deep-doped p-type region is formed in the silicon carbide epitaxy layer below the first gate electrode trench. As shown in Figure 7, the hard mask layer HM3 is etched back, exposing the hard mask layer HM2 at the bottom of the gate electrode trench TR1. The ion implantation process forms a deep-doped p-type region DP1 (i.e., the first deep-doped p-type region) in the silicon carbide epitaxy layer 101 below the gate electrode trench TR1. Since a portion of the hard mask layer HM3 remains in the gate electrode trench TR1, the width of the deep-doped p-type region DP1 is smaller than the width of the gate electrode trench TR1.

[0032] As shown in Figure 8, an ion implantation process is performed before depositing the hard mask layer HM4. As shown in Figure 9, the hard mask layer HM4 is patterned to create an opening OP2 that defines the region of the gate electrode trench TR2. The step of patterning the hard mask layer HM4 includes forming a photoresist on top of the hard mask layer HM4, performing a lithography process to pattern the photoresist, performing an etching process to form an opening OP2 in the hard mask layer HM4, and then removing the photoresist. As shown in Figure 10, the etching process is performed to remove the portion of the silicon carbide epitaxy layer 101 exposed by the opening OP2 and to create the gate electrode trench TR2, but the etching is stopped at the deep-doped p-type region DP2. The deep-doped p-type region DP2 is deeper than the deep-doped p-type region DP1. In other words, the bottom surface of the gate electrode trench TR1 is higher than the bottom surface of the gate electrode trench TR2. As shown in Figure 11, the hard mask layers HM4, HM3, HM2, and HM1 are removed, and then thermal annealing is performed. As shown in Figure 12, after thermal annealing, oxides are deposited, and then the oxides are patterned to form the electro-oxide layer FOX.

[0033] In step 204, a gate electrode oxide layer is formed on the bottom and side surfaces of the first and second gate electrode trenches, and on the heavily doped n-type region. In step 205, a polysilicon layer is formed on the gate electrode oxide layer. As shown in Figure 13, the gate electrode oxide layer 102 is deposited, and then the polysilicon layer 103 is deposited on top of the gate electrode oxide layer 102. As shown in Figure 14, a photoresist is formed on the polysilicon layer 103, and then a lithography process is performed to pattern the photoresist. An etching process is performed to remove the polysilicon layer 103 outside the gate electrode trench TR1 and gate electrode trench TR2 (i.e., the second gate electrode trench). With respect to the gate electrode trench TR1, once the polysilicon layer 103 is etched, the gate electrode oxide layer 102 is exposed at the bottom of the gate electrode trench TR1, and the polysilicon layer 103 is present only on the side walls and part of the bottom of the gate electrode trench TR1, but since the channel is formed on the side walls of the gate electrode trench TR1, the ON characteristics of the semiconductor are not affected.

[0034] In step 206, an interlayer dielectric layer is formed on the polysilicon layer. As shown in Figure 15, interlayer dielectric layer ILD1 and interlayer dielectric layer ILD2 are deposited in sequence. Interlayer dielectric layer ILD2 has a planarization effect that reduces the step height at the location of the trench (e.g., gate pole trench TR1).

[0035] In step 207, a source electrode trench is formed that penetrates the interlayer dielectric layer and the gate electrode oxide layer, extending into the heavily doped n-type region and the heavily doped p-type region. More specifically, a photoresist is formed on the interlayer dielectric layer ILD2, and then a lithography process is performed to pattern the photoresist and form a source electrode contact mask. An etching process is performed to form a source electrode trench STR in the source electrode region that penetrates the interlayer dielectric layer ILD2, the interlayer dielectric layer ILD1, and the gate electrode oxide layer 102, reaching the heavily doped n-type region 107 and the heavily doped p-type region 105, and then the photoresist is removed. Metal silicide SC is formed in the source electrode trench STR. A patterned photoresist layer is formed by the lithography process, and a trench used for the gate electrode pad is generated by the etching process, and the patterned photoresist layer is removed. A metal layer 106 is deposited, a patterned photoresist layer is formed by a lithography process, and an etching process is performed to pattern the metal layer 106 to generate a gate electrode pad and a source electrode pad. A passivation layer 109 is deposited, a patterned photoresist layer is formed by a lithography process, and an etching process is performed to pattern the passivation layer 109 so that it is formed on top of the metal layer 106 and the interlayer dielectric layer 104. As shown in Figure 1, a polyimide layer 110 can be further placed on top of the passivation layer 109.

[0036] In this invention, the deep-doped p-type regions DP1 and DP2 release the strong electric field at the trench edge, thereby increasing the drain-to-source breakdown voltage (BVDSS). Furthermore, the on-resistance (Rdson) can be optimized by adjusting the distance between the deep-doped p-type regions DP1 and DP2. The junctions formed by each of the deep-doped p-type regions DP1 and DP2 with the N-type silicon carbide epitaxy layer 101 reduce the parasitic capacitance Cgd, thereby improving the switching speed of the transistor.

[0037] As described above, several embodiments have been outlined to help those skilled in the art better understand this specification. As those skilled in the art will understand, the same objectives and / or advantages as those described above can be achieved by designing or modifying other processes and structures based on the present invention. Also as those skilled in the art will understand, various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention, as long as they are equivalent structures that do not depart from the spirit and scope of the invention. [Explanation of Symbols]

[0038] 100: Semiconductor device 200: Method 101: Silicon carbide epitaxy layer 102: Gate polar oxide layer 103: Polysilicon layer 104: Interlayer dielectric layer 105: Severely doped p-type region 106: Metal layer 107: Severely doped n-type region 109: Passivation layer 110: Polyimide layer 111: Silicon carbide substrate 112: Metal layer ILD1: Interlayer dielectric layer ILD2: Interlayer dielectric layer DP1: Deep-doped p-type region DP2: Deep-doped p-type region PW: p-type well region FOX: Field oxide layer SC: Metal silicide GR: Protective ring area OP1: Opening OP2: Opening HM1: Hard mask layer HM2: Hard Mask Layer HM3: Hard Mask Layer HM4: Hard Mask Layer TR1: Gate terminal trench TR2: Gate terminal trench STR: Source Extreme Trench TR3: Gate plate trench TR4: Gate plate trench 201: Step 202: Step 203: Step 204: Step 205: Step 206: Step 207: Step

Claims

1. A semiconductor device, p-type well region, A heavily doped n-type region on the surface of the aforementioned p-type well region, A silicon carbide epitaxy layer comprising a heavily doped p-type region below the heavily doped n-type region and within the p-type well region, A first gate pole trench that penetrates the aforementioned p-type well region, A first deep-doped p-type region located below the first gate pole trench and having a width narrower than the width of the first gate pole trench, A gate electrode oxide layer located on the bottom surface and side surface of the first gate electrode trench and above the heavily doped n-type region, A polysilicon layer on top of the gate polar oxide layer, An interlayer dielectric layer located on the aforementioned polysilicon layer, A semiconductor device having a source electrode trench that penetrates the interlayer dielectric layer and the gate electrode oxide layer and extends into the heavily doped n-type region and the heavily doped p-type region.

2. In the semiconductor device described in claim 1, further, A second gate pole trench penetrates the p-type well region and whose bottom surface is lower than the bottom surface of the first gate pole trench, It has a second deep-doped p-type region located below the second gate pole trench and having a width narrower than the width of the second gate pole trench, The first gate electrode trench and the first deep-doped p-type region, and the second gate electrode trench and the second deep-doped p-type region, each belong to a different transistor cell.

3. In the semiconductor device described in claim 1, further, A third gate pole trench extends through the p-type well region, and its bottom surface is at the same height as the bottom surface of the first gate pole trench, A third deep doped p-type region is located below the third gate pole trench and has a width narrower than the width of the third gate pole trench, The first gate electrode trench and the first deep-doped p-type region, and the third gate electrode trench and the third deep-doped p-type region, each belong to different transistor cells.

4. In the semiconductor device described in claim 1, further, A fourth gate pole trench extends through the p-type well region, and its bottom surface is at the same height as the bottom surface of the first gate pole trench, It has a fourth deep doped p-type region located below the fourth gate pole trench and having a width narrower than the width of the fourth gate pole trench, The first gate electrode trench and the first deep-doped p-type region, and the fourth gate electrode trench and the fourth deep-doped p-type region, each belong to different transistor cells.

5. In the semiconductor device described in claim 1, further, The first metal layer is located within the source electrode trench and contacts the heavily doped p-type region and the heavily doped n-type region via a metal silicide.

6. In the semiconductor device described in claim 1, further, A silicon carbide substrate located below the silicon carbide epitaxy layer, It has a second metal layer located below the silicon carbide substrate.

7. A method for manufacturing a semiconductor device, To provide a silicon carbide epitaxy layer in which a p-type well region, a heavily doped n-type region on the surface of the p-type well region, and a heavily doped p-type region located below the heavily doped n-type region and within the p-type well region are predetermined, To form a first gate electrode trench in the silicon carbide epitaxy layer that penetrates the p-type well region, A first deep-doped p-type region is formed in the silicon carbide epitaxy layer below the first gate electrode trench, with a width narrower than the width of the first gate electrode trench. Forming a gate electrode oxide layer on the bottom surface and side surface of the first gate electrode trench, and on the heavily doped n-type region, Forming a polysilicon layer on the aforementioned gate polar oxide layer, Forming an interlayer dielectric layer on the aforementioned polysilicon layer, A method for manufacturing a semiconductor device, comprising forming a source electrode trench that penetrates the interlayer dielectric layer and the gate electrode oxide layer and extends into the heavily doped n-type region and the heavily doped p-type region.

8. In the method for manufacturing a semiconductor device described in claim 7, further, A second gate pole trench is formed that penetrates the p-type well region and whose bottom surface is lower than the bottom surface of the first gate pole trench, This includes forming a second deep-doped p-type region below the second gate pole trench, the width of which is narrower than the width of the second gate pole trench, The first gate electrode trench and the first deep-doped p-type region, and the second gate electrode trench and the second deep-doped p-type region, each belong to a different transistor cell.

9. In the method for manufacturing a semiconductor device described in claim 7, further, A third gate pole trench is formed that penetrates the p-type well region and whose bottom surface is at the same height as the bottom surface of the first gate pole trench, This includes forming a third deep-doped p-type region below the third gate pole trench, the width of which is narrower than the width of the third gate pole trench, The first gate electrode trench and the first deep-doped p-type region, and the third gate electrode trench and the third deep-doped p-type region, each belong to different transistor cells.

10. In the method for manufacturing a semiconductor device described in claim 7, further, A fourth gate pole trench is formed that penetrates the p-type well region and whose bottom surface is at the same height as the bottom surface of the first gate pole trench, This includes forming a fourth deep-doped p-type region below the fourth gate pole trench, the width of which is narrower than the width of the fourth gate pole trench, The first gate electrode trench and the first deep-doped p-type region, and the fourth gate electrode trench and the fourth deep-doped p-type region, each belong to different transistor cells.

11. In the method for manufacturing a semiconductor device described in claim 7, further, This includes forming a first metal layer in the source electrode trench that contacts the heavily doped p-type region and the heavily doped n-type region via a metal silicide.

12. In the method for manufacturing a semiconductor device described in claim 7, further, A silicon carbide substrate is formed below the silicon carbide epitaxy layer, This includes forming a second metal layer below the silicon carbide substrate.

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