semiconductor element

Abstract

To provide semiconductor devices with improved reliability. [Solution] The present invention relates to a semiconductor device, and more particularly to a transistor on a substrate, comprising a conductive pattern, a first metal layer on the transistor comprising a first wiring and a first via beneath the first wiring, and a corrosion-stopping film between the transistor and the first metal layer, wherein the first via penetrates the corrosion-stopping film and connects the conductive pattern and the first wiring, and the first via comprises a first barrier pattern, a second barrier pattern on the first barrier pattern, and a side barrier pattern interposed between the second barrier pattern and the corrosion-stopping film, the side barrier pattern comprising a transition metal oxide.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a field effect transistor and a method for manufacturing the same.

Background Art

[0002] Semiconductor devices include integrated circuits composed of MOS (Metal Oxide Semiconductor) field effect transistors (MOS FETs). As the size and design rules of semiconductor devices are gradually reduced, the size reduction of MOS field effect transistors is also accelerating. The operating characteristics of semiconductor devices may deteriorate in response to the size reduction of MOS field effect transistors. Therefore, various methods for forming semiconductor devices with better performance while overcoming the limitations due to the high integration of semiconductor devices have been studied.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device with improved reliability.

[0005] The problem to be solved by the present invention is to provide a semiconductor device with improved electrical characteristics.

Means for Solving the Problems

[0006] A semiconductor device according to the concept of the present invention is a transistor on a substrate, comprising a transistor including a conductive pattern, a first metal layer on the transistor including a first wiring and a first via beneath the first wiring, and a corrosion-stopping film between the transistor and the first metal layer, wherein the first via penetrates the corrosion-stopping film and connects the conductive pattern and the first wiring, and the first via comprises a first barrier pattern, a second barrier pattern on the first barrier pattern, and a side barrier pattern interposed between the second barrier pattern and the corrosion-stopping film, wherein the side barrier pattern comprises a transition metal oxide.

[0007] A semiconductor device according to another concept of the present invention is a transistor on a substrate, comprising a transistor including a conductive pattern, a first metal layer on the transistor, and an etching stop film between the transistor and the first metal layer, wherein the first metal layer includes a first wiring and a first via beneath the first wiring, the first via penetrating the etching stop film and connecting the conductive pattern and the first wiring, the first via containing a first transition metal at its lower part, the concentration of the first transition metal increasing as it approaches the etching stop film from the first via, and having a maximum value at the interface between the first via and the etching stop film.

[0008] A semiconductor device according to another concept of the present invention includes a substrate including an active pattern, a source / drain pattern on the active pattern, a channel pattern provided on the active pattern and connected to the source / drain pattern, the channel pattern including a plurality of semiconductor patterns stacked spaced apart from each other, a gate electrode extending in a first direction across the channel pattern, a gate insulating film interposed between the channel pattern and the gate electrode, a gate spacer on the side wall of the gate electrode, a gate capping pattern on the upper surface of the gate electrode, a first interlayer insulating film on the gate capping pattern, and an active contact penetrating the first interlayer insulating film and connected to each of the source / drain patterns. The device comprises a gate contact that penetrates the first interlayer insulating film and connects to the gate electrode, a corrosion-stopping film on the first interlayer insulating film, a second interlayer insulating film on the corrosion-stopping film, and a first metal layer provided within the second interlayer insulating film, wherein the first metal layer includes a first wiring and a first via beneath the first wiring, the first via connecting the active contact and the first metal layer, and the first via includes a first barrier pattern, a second barrier pattern on the first barrier pattern, and a side barrier pattern interposed between the second barrier pattern and the corrosion-stopping film, the side barrier pattern comprising a transition metal oxide containing a transition metal different from each of the first and second barrier patterns. [Effects of the Invention]

[0009] In the three-dimensional field-effect transistor according to the present invention, a side barrier pattern can be interposed between the lower part of the first via and the etching-stopping film. The side barrier pattern contains a transition metal oxide and can prevent the conductive material of the first via from diffusing. Furthermore, by omitting the first barrier pattern in the lower part adjacent to the conductive pattern of the first via, it is possible to prevent the conductive material of the conductive pattern from diffusing toward the first via and forming a void. As a result, the reliability of the semiconductor device according to the present invention can be improved.

[0010] The manufacturing method for a three-dimensional field-effect transistor according to the present invention allows for the formation of a side barrier pattern below the first via by performing a Post Reflow Anneal (PRA) process. The PRA process allows the transition metal to move toward the corrosion-stopping film. The oxygen in the corrosion-stopping film reacts with the transition metal to form the side barrier pattern. Therefore, profiling defects between the first via and the conductive pattern can be improved, and corrosion of the conductive pattern can be prevented. As a result, the semiconductor device according to the present invention can have improved electrical characteristics. [Brief explanation of the drawing]

[0011] [Figure 1] This is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the present invention. [Figure 2] This is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the present invention. [Figure 3] This is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the present invention. [Figure 4] This is a plan view illustrating a semiconductor device according to an embodiment of the present invention. [Figure 5A] This is a cross-sectional view along the line A-A' in Figure 4. [Figure 5B] This is a cross-sectional view along the line B-B' in Figure 4. [Figure 5C] This is a cross-sectional view along the line C-C' in Figure 4. [Figure 5D] This is a cross-sectional view along the line D-D' in Figure 4. [Figure 6A] This is an enlarged view of region M in Figure 5C. [Figure 6B] This is an enlarged view of the N region shown in Figure 6A. [Figure 7A] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8A]It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8B] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9A] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9B] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9C] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10A] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10B] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10C] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11A] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11B] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11C] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11D] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12A] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12B] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention'. [Figure 12C] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12D] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13A]This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13B] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13C] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] This is an enlarged view illustrating the method of forming the M region in Figure 13C. [Figure 15] This is an enlarged view illustrating the method of forming the M region in Figure 13C. [Figure 16] This is an enlarged view illustrating the method of forming the M region in Figure 13C. [Figure 17A] This is an enlarged view illustrating the method of forming the M region in Figure 13C. [Figure 17B] This is an enlarged view of the N region shown in Figure 17A. [Modes for carrying out the invention]

[0012] Figures 1 to 3 are conceptual diagrams illustrating the logic cell of a semiconductor device according to an embodiment of the present invention.

[0013] Referring to Figure 1, a single height cell (SHC) can be provided. Specifically, a first power trace M1_R1 and a second power trace M1_R2 can be provided on the substrate 100. The first power trace M1_R1 may be a path through which a source voltage VSS, for example, a ground voltage, is provided. The second power trace M1_R2 may be a path through which a drain voltage VDD, for example, a power voltage, is provided.

[0014] A single-height cell SHC can be defined between the first power wiring M1_R1 and the second power wiring M1_R2. The single-height cell SHC may include one first active region AR1 and one second active region AR2. One of the first and second active regions AR1 and AR2 may be a PMOSFET region, and the other of the first and second active regions AR1 and AR2 may be an NMOSFET region. Again, the single-height cell SHC may have a CMOS structure provided between the first power wiring M1_R1 and the second power wiring M1_R2.

[0015] Each of the first and second active regions AR1 and AR2 may have a width W1 in the first direction D1. The length of the single-height cell SHC in the first direction D1 can be defined as the vertical height HE1. The vertical height HE1 may be substantially the same as the distance (e.g., pitch) between the first power wiring M1_R1 and the second power wiring M1_R2.

[0016] A single-height cell (SHC) can constitute a single logic cell. In this specification, a logic cell can mean a logic element that performs a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). That is, a logic cell may include transistors for constituting the logic element and wiring connecting the transistors to each other.

[0017] Referring to Figure 2, a Double Height Cell (DHC) can be provided. Specifically, a first power wiring M1_R1, a second power wiring M1_R2, and a third power wiring M1_R3 can be provided on the substrate 100. The first power wiring M1_R1 can be placed between the second power wiring M1_R2 and the third power wiring M1_R3. The third power wiring M1_R3 may be a passage through which the source voltage VSS is provided.

[0018] A double-height cell DHC can be defined between the second power wiring M1_R2 and the third power wiring M1_R3. The double-height cell DHC may contain two first active regions AR1 and two second active regions AR2.

[0019] Of the two second active regions AR2, one can be adjacent to the second power wiring M1_R2. Of the two second active regions AR2, the other can be adjacent to the third power wiring M1_R3. The two first active regions AR1 can be adjacent to the first power wiring M1_R1. In a plan view, the first power wiring M1_R1 can be positioned between the two first active regions AR1.

[0020] The length of a double-height cell DHC in the first direction D1 can be defined as the second longitudinal height HE2. The second longitudinal height HE2 may be approximately twice the longitudinal height HE1 in Figure 1. The two first active regions AR1 of the double-height cell DHC can be bundled together to function as a single active region.

[0021] In the present invention, the double-height cell DHC shown in Figure 2 can be defined as a multi-height cell. Although not shown, the multi-height cell may include a triple-height cell in which the cell height is approximately three times that of a single-height cell SHC.

[0022] Referring to Figure 3, a first single-height cell SHC1, a second single-height cell SHC2, and a double-height cell DHC can be arranged two-dimensionally on the substrate 100. The first single-height cell SHC1 can be placed between the first and second power wirings M1_R1 and M1_R2. The second single-height cell SHC2 can be placed between the first and third power wirings M1_R1 and M1_R3. The second single-height cell SHC2 can be adjacent to the first single-height cell SHC1 in the first direction D1.

[0023] The double-height cell DHC can be positioned between the second and third power wirings M1_R2 and M1_R3. The double-height cell DHC can be adjacent to the first and second single-height cells SHC1 and SHC2 and in the second direction D2.

[0024] An isolation structure DB can be provided between the first single-height cell SHC1 and the double-height cell DHC, and between the second single-height cell SHC2 and the double-height cell DHC. The upper isolation structure DB allows the active region of the double-height cell DHC to be electrically isolated from the active regions of the first and second single-height cells SHC1 and SHC2, respectively.

[0025] Figure 4 is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Figures 5A to 5D are cross-sectional views along lines A-A', B-B', C-C', and D-D' in Figure 4, respectively. Figure 6 is an enlarged view showing region M in Figure 5C. The semiconductor devices shown in Figures 4 and 5A to 5D are examples that more specifically illustrate the single-height cell SHC of Figure 1.

[0026] Referring to Figures 4 and 5A to 5D, a single-height cell SHC can be provided on the substrate 100. Logic transistors constituting a logic circuit can be arranged on the single-height cell SHC. The substrate 100 may be a semiconductor substrate containing silicon, germanium, silicon-germanium, etc., or a compound semiconductor substrate. As an example, the substrate 100 may be a silicon substrate.

[0027] The substrate 100 may include a first active region AR1 and a second active region AR2. Each of the first and second active regions AR1 and AR2 may be extended in a second direction D2. In one embodiment, the first active region AR1 may be an NMOSFET region, and the second active region AR2 may be a PMOSFET region.

[0028] A trench TR formed on the upper part of the substrate 100 can define a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 can be provided on a first active region AR1, and the second active pattern AP2 can be provided on a second active region AR2. The first and second active patterns AP1 and AP2 can be extended in a second direction D2. The first and second active patterns AP1 and AP2 may be vertically protruding portions as part of the substrate 100.

[0029] An element isolation film ST can be provided on the substrate 100. The element isolation film ST can fill the trench TR. The element isolation film ST can contain a silicon oxide film. The element isolation film ST does not need to cover the first and second channel patterns CH1 and CH2, which will be described later.

[0030] A first channel pattern CH1 can be provided on a first active pattern AP1. A second channel pattern CH2 can be provided on a second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 that are sequentially stacked. The first to third semiconductor patterns SP1, SP2, and SP3 can be separated from each other in the vertical direction (i.e., the third direction D3).

[0031] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may contain silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 may contain crystalline silicon, more specifically single-crystal silicon. In one embodiment of the present invention, the first to third semiconductor patterns SP1, SP2, and SP3 may be stacked nanosheets.

[0032] Multiple first source / drain patterns SD1 can be provided on a first active pattern AP1. Multiple first recesses RS1 can be formed on top of the first active pattern AP1. Each first source / drain pattern SD1 can be provided within a first recess RS1. The first source / drain pattern SD1 may be an impurity region of a first conductivity type (e.g., n-type). A first channel pattern CH1 can be interposed between a pair of first source / drain patterns SD1. In other words, stacked first to third semiconductor patterns SP1, SP2, SP3 can link pairs of first source / drain patterns SD1 to each other.

[0033] Multiple second source / drain patterns SD2 can be provided on a second active pattern AP2. Multiple second recesses RS2 can be formed on top of the second active pattern AP2. Each second source / drain pattern SD2 can be provided within a second recess RS2. The second source / drain pattern SD2 may be an impurity region of a second conductivity type (e.g., p-type). A second channel pattern CH2 can be interposed between a pair of second source / drain patterns SD2. In other words, stacked first to third semiconductor patterns SP1, SP2, SP3 can connect pairs of second source / drain patterns SD2 to each other.

[0034] The first and second source / drain patterns SD1 and SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. For example, the upper surfaces of each of the first and second source / drain patterns SD1 and SD2 may be higher than the upper surface of the third semiconductor pattern SP3. As another example, at least one upper surface of the first and second source / drain patterns SD1 and SD2 may be at substantially the same level as the upper surface of the third semiconductor pattern SP3.

[0035] In one embodiment of the present invention, the first source / drain pattern SD1 may include the same semiconductor element (e.g., Si) as the substrate 100. The second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element (e.g., Si) of the substrate 100. Thus, a pair of second source / drain patterns SD2 can provide compressive stress to the second channel pattern CH2 between them.

[0036] In one embodiment of the present invention, the sidewall of the second source / drain pattern SD2 may have an uneven embossed shape. In other words, the sidewall of the second source / drain pattern SD2 may have a wave-like profile. The sidewall of the second source / drain pattern SD2 may protrude toward the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE, which will be described later.

[0037] Electrode gates GE can be provided on first and second channel patterns CH1 and CH2. Each gate electrode GE can extend across the first and second channel patterns CH1 and CH2 in a first direction D1. Each gate electrode GE can be superimposed perpendicularly to the first and second channel patterns CH1 and CH2. The gate electrode GEs can be arranged in a second direction D2 according to a first pitch.

[0038] The gate electrode GE may include a first inner electrode PO1 interposed between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second inner electrode PO2 interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third inner electrode PO3 interposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and an outer electrode PO4 on the third semiconductor pattern SP3.

[0039] Referring to Figure 5D, the gate electrode GE can be provided on the top, bottom, and side walls of the first to third semiconductor patterns SP1, SP2, and SP3, respectively. Again, the transistor according to this embodiment may be a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds the channel.

[0040] On the first active region AR1, an inner spacer ISP can be interposed between the first to third portions PO1, PO2, and PO3 of the gate electrode GE and the first source / drain pattern SD1. Each of the first to third inner electrodes PO1, PO2, and PO3 of the gate electrode GE can be separated from the first source / drain pattern SD1 via the inner spacer ISP. The inner spacer ISP can prevent leakage current from the gate electrode GE.

[0041] Referring again to Figures 4 and 5A to 5D, a pair of gate spacers GS can be positioned on the side walls of the outer electrode PO4 of the gate electrode GE. The gate spacers GS can be extended along the gate electrode GE in a first direction D1. In one embodiment, the gate spacers GS can include at least one of SiCN, SiCON, and SiN. As another example, the gate spacers GS can include a multi-layer made of at least two of SiCN, SiCON, and SiN. In one embodiment of the present invention, the gate spacers GS can include a Si-containing insulating material. The gate spacers GS can function as an etching stop film when forming the active contact structure (AC in Figure 4), which will be described later. The gate spacers GS can enable the active contact structure (AC in Figure 4) to be formed in a self-aligned manner.

[0042] A gate capping pattern GP can be provided on the gate electrode GE. The gate capping pattern GP can be extended along the gate electrode GE in a first direction D1. The gate capping pattern GP may contain materials that are etching selective to the first and second interlayer insulating films 110 and 120, which will be described later. Specifically, the gate capping pattern GP may contain at least one of SiON, SiCN, SiCON, and SiN.

[0043] A gate insulating film GI can be interposed between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate insulating film GI can cover the top surface TS, bottom surface BS, and side walls SW of the first to third semiconductor patterns SP1, SP2, and SP3, respectively. The gate insulating film GI can cover the top surface of the element isolation film ST located beneath the gate electrode GE.

[0044] In one embodiment of the present invention, the gate insulating film GI may include a silicon oxide film, a silicon oxidnitride film, and / or a high dielectric film. For example, the gate insulating film GI may have a structure in which a silicon oxide film and a high dielectric film are laminated. The high dielectric film may include a high dielectric constant material with a dielectric constant higher than that of the silicon oxide film. As an example, the high dielectric constant material may include at least one from among hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0045] In other embodiments, the semiconductor device of the present invention may include a Negative Capacitance (NC) FET utilizing a negative capacitor. For example, the gate insulating film GI may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0046] As an example, the gate insulating film GI may include a single ferroelectric material film. As another example, the gate insulating film GI may include multiple ferroelectric material films spaced apart from each other. The gate insulating film GI may have a multilayer structure in which multiple ferroelectric material films and multiple paraelectric material films are alternately stacked.

[0047] Referring again to Figures 4 and 5A to 5D, the gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern is provided on the gate insulating film GI and may be adjacent to first to third semiconductor patterns SP1, SP2, SP3. The first metal pattern may include a work function metal that adjusts the threshold voltage of the transistor. The desired threshold voltage of the transistor can be achieved by adjusting the thickness and composition of the first metal pattern. For example, the first to third inner electrodes PO1, PO2, PO3 of the gate electrode GE may be composed of a first metal pattern that is a work function metal.

[0048] The first metallic pattern may include a metal nitride film. For example, the first metallic pattern may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), and nitrogen (N). Furthermore, the first metallic pattern may further include carbon (C). The first metallic pattern may include a plurality of stacked work function metallic films.

[0049] The second metal pattern may include a metal with lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the outer electrode PO4 of the gate electrode GE may include a first metal pattern and a second metal pattern on top of the first metal pattern.

[0050] A first interlayer insulating film 110 can be provided on the substrate 100. The first interlayer insulating film 110 can cover the gate spacer GS and the first and second source / drain patterns SD1 and SD2. The upper surface of the first interlayer insulating film 110 can be substantially coplane with the upper surface of the gate capping pattern GP and the upper surface of the gate spacer GS. A second interlayer insulating film 120 can be placed on top of the first interlayer insulating film 110, covering the gate capping pattern GP.

[0051] A corrosion-resistant film ESL can be provided on the second interlayer insulating film 120. The corrosion-resistant film ESL may contain an oxide. For example, the corrosion-resistant film ESL may be a metal oxide film.

[0052] A third interlayer insulating film 130 can be provided on the corrosion-stopping film ESL. A fourth interlayer insulating film 140 can be provided on the third interlayer insulating film 130. As an example, the first to fourth interlayer insulating films 110-140 may include silicon oxide films.

[0053] A single-height cell SHC may have a first boundary BD1 and a second boundary BD2 facing each other in a second direction D2. The first and second boundaries BD1 and BD2 may be extended in the first direction D1. A single-height cell SHC may have a third boundary BD3 and a fourth boundary BD4 facing each other in the first direction D1. The third and fourth boundaries BD3 and BD4 may be extended in the second direction D2.

[0054] A pair of isolation structures DB can be provided on both sides of a single-height cell SHC, facing each other in a second direction D2. For example, the pair of isolation structures DB can be provided on the first and second boundaries BD1 and BD2 of the single-height cell SHC, respectively. The isolation structures DB can extend in the first direction D1 parallel to the gate electrode GE. The pitch between the isolation structure DB and its adjacent gate electrode GE may be the same as the first pitch.

[0055] The isolation structure DB can penetrate the first and second interlayer insulating films 110 and 120 and extend into the interior of the first and second active patterns AP1 and AP2. The isolation structure DB can penetrate the top of each of the first and second active patterns AP1 and AP2. The isolation structure DB can electrically isolate the active region of a single-height cell SHC from the active regions of other adjacent cells.

[0056] Active contacts AC can be provided that penetrate the first and second interlayer insulating films 110 and 120 and are electrically connected to the first and second source / drain patterns SD1 and SD2, respectively. A pair of active contacts AC can be provided on each side of the gate electrode GE. In plan view, the active contacts AC can have a bar shape extending in the first direction D1.

[0057] The active contact AC can be a self-aligned contact. Again, the active contact AC can be formed in a self-aligned manner using the gate capping pattern GP and the gate spacer GS. For example, the active contact AC can cover at least a portion of the sidewall of the gate spacer GS. Although not shown, the active contact AC can cover a portion of the upper surface of the gate capping pattern GP.

[0058] A metal-semiconductor compound layer SC, such as a silicide layer, can be interposed between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2. The active contact AC can be electrically coupled to the source / drain patterns SD1 and SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound film SC may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0059] A gate contact GC can be provided that penetrates the second interlayer insulating film 120 and the gate capping pattern GP and is electrically connected to the gate electrode GE, respectively. In plan view, the gate contact GC can be arranged so as to superimpose on the first active region AR1 and the second active region AR2, respectively. As an example, the gate contact GC can be provided on the second active pattern AP2 (see Figure 5D).

[0060] As an embodiment of the present invention, referring to Figure 5B, the upper part of the active contact AC adjacent to the gate contact GC can be filled with an upper insulating pattern. The bottom surface of the upper insulating pattern can be lower than the bottom surface of the gate contact GC. In other words, the upper surface of the active contact AC adjacent to the gate contact GC can be lower than the bottom surface of the gate contact GC by the upper insulating pattern UIP. Thus, the problem of the gate contact GC coming into contact with the adjacent active contact AC and causing a short circuit can be prevented.

[0061] Each of the active contact AC and gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal from among aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the sidewalls and bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal film / metal nitride film. The metal film may include at least one from among titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride film may include at least one from among titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0062] A first metal layer M1 can be provided within the third interlayer insulating film 130. For example, the first metal layer M1 may include a first power wiring M1_R1, a second power wiring M1_R2, and a first wiring M1_I. Each of the wirings M1_R1, M1_R2, and M1_I of the first metal layer M1 may extend parallel to each other in the second direction D2.

[0063] Specifically, the first and second power wirings M1_R1 and M1_R2 can be provided on the third and fourth boundaries BD3 and BD4 of the single-height cell SHC, respectively. The first power wiring M1_R1 can be extended in the second direction D2 along the third boundary BD3. The second power wiring M1_R2 can be extended in the second direction D2 along the fourth boundary BD4.

[0064] The first wiring M1_I of the first metal layer M1 can be positioned between the first and second power wirings M1_R1 and M1_R2. The first wiring M1_I of the first metal layer M1 can be arranged along the first direction D1 with a second pitch. The second pitch can be smaller than the first pitch. The line width of each of the first wirings M1_I can be smaller than the line width of each of the first and second power wirings M1_R1 and M1_R2.

[0065] The first metal layer M1 may further include first vias VI1. The first vias VI1 may be provided beneath the wirings M1_R1, M1_R2, and M1_I of the first metal layer M1, respectively. The active contact AC and the wiring of the first metal layer M1 can be electrically connected to each other through the first vias VI1. The gate contact GC and the wiring of the first metal layer M1 can be electrically connected to each other through the first vias VI1.

[0066] The wiring of the first metal layer M1 and the first via VI1 beneath it can be formed by separate processes. In other words, each of the wiring of the first metal layer M1 and the first via VI1 can be formed by a single damascene process. The semiconductor device according to this embodiment may be formed using processes of less than 20 nm.

[0067] A second metal layer M2 can be provided within the fourth interlayer insulating film 140. The second metal layer M2 can contain a plurality of second wirings M2_I. Each of the second wirings M2_I of the second metal layer M2 may have a line shape or a bar shape that extends in a first direction D1. In other words, the second wirings M2_I may extend parallel to each other in the first direction D1.

[0068] The second metal layer M2 may further include second vias VI2 provided beneath each second wiring M2_I. The wiring of the first metal layer M1 and the wiring of the second metal layer M2 can be electrically connected to each other through the second vias VI2. As an example, the wiring of the second metal layer M2 and the second vias VI2 beneath it can be formed together in a dual damascene process.

[0069] The wiring in the first metal layer M1 and the wiring in the second metal layer M2 may be identical to each other or may contain different conductive materials. For example, the wiring in the first metal layer M1 and the wiring in the second metal layer M2 may contain at least one metallic material selected from aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt. Although not shown, additional metal layers (e.g., M3, M4, M5...) can be arranged on the fourth interlayer insulating film 140. Each of the stacked metal layers may contain wiring for routing between cells.

[0070] The etching stop film ESL and the first via VI1 will be described in more detail with reference to Figures 5C, 6A, and 6B. Figure 6A is an enlarged view of region M in Figure 5C. Figure 6B is an enlarged view of region N in Figure 6A.

[0071] Referring to Figure 6A, the first via VI1 can connect the wiring M1_R1, M1_R2, and M1_I of the first metal layer M1 to the conductive pattern FM. The conductive pattern may be a component containing a conductive material. For example, the conductive pattern may be any one of the conductive pattern FM of the active contact AC, the conductive pattern FM of the gate contact GC, or the wiring of the gate electrode GE, first and second metal layers M1 and M2. In Figure 6A, the first via VI1 can vertically connect the first power wiring M1_R1 to the active contact AC.

[0072] The first via VI1 may include a via conductive pattern VFM and a via barrier pattern VBM surrounding the via conductive pattern VFM. The via barrier pattern VBM may include a first barrier pattern VBM1 and a second barrier pattern VBM2 on the first barrier pattern VBM1. The via conductive pattern VFM may include at least one metal from among aluminum, copper, tungsten, molybdenum, and cobalt.

[0073] The first barrier pattern VBM1 can cover the sidewall of the via conductive pattern VFM. The first barrier pattern VBM1 does not have to be provided below the first via VI1. For example, the first barrier pattern VBM1 does not have to be provided between the first via VI1 and the corrosion-stopping film ESL. The first barrier pattern VBM1 and the conductive pattern FM can be separated by the corrosion-stopping film ESL. The second barrier pattern VBM2 can cover the sidewall and bottom surface of the via conductive pattern VFM. The second barrier pattern VBM2 can extend between the bottom surface of the via conductive pattern VFM and the top surface of the conductive pattern FM. Therefore, only the second barrier pattern VBM2 can be provided below the first via VI1. The lowest level of the second barrier pattern VBM2 can be lower than the lowest level of the first barrier pattern VBM1.

[0074] The first barrier pattern VBM1 may contain transition metals. The first barrier pattern VBM1 may contain multiple metal films / metal nitride films. The metal film may contain at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride film may contain at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0075] As an example, the first barrier pattern VBM1 may include alternatingly stacked tantalum nitride (TaN) and ruthenium (Ru) films. The first barrier pattern VBM1 may be tantalum nitride (TaN) - ruthenium (Ru) - tantalum nitride (TaN) - ruthenium (Ru). By including ruthenium (Ru) in the first barrier pattern VBM1, the second barrier pattern VBM2 does not need to include ruthenium (Ru). Therefore, the second barrier pattern VBM2 can react with the conductive material (e.g., copper) of the conductive pattern FM of the active contact AC to prevent corrosion of the conductive pattern FM. If corrosion of the conductive pattern FM occurs, voids can be formed on top of the conductive pattern FM, significantly degrading its electrical properties.

[0076] The second barrier pattern VBM2 may contain different transition metals from the first barrier pattern VBM1. The second barrier pattern VBM2 may contain at least one of titanium, tantalum, tungsten, nickel, cobalt, platinum, and combinations thereof. Preferably, the second barrier pattern VBM2 may contain cobalt. As another example, the second barrier pattern VBM2 may also contain a metal film / metal nitride film.

[0077] The barrier pattern BM of the active contact AC may include a first active barrier pattern BM1a and a second active barrier pattern BM1b. The second active barrier pattern BM1b may be provided on top of the first active barrier pattern BM1a. The first active barrier pattern BM1a may include a metal film, a metal nitride film, or a combination thereof. Unlike the first barrier pattern VBM1, the first active barrier pattern BM1a may be a tantalum nitride film (TaN-ruthenium film (Ru)-tantalum nitride film (TaN)). As another example, the first active barrier pattern BM1a may be substantially identical to the first barrier pattern VBM1. The second active barrier pattern BM1b may include a metal film, a metal nitride film, or a combination thereof. The second active barrier pattern BM1b may be cobalt-ruthenium (Co-Ru). As another example, the second active barrier pattern BM1b may be substantially identical to the second barrier pattern VBM2.

[0078] Erosion-stopping films (ESLs) can contain oxygen. Erosion-stopping films (ESLs) can contain metal oxides. For example, Erosion-stopping films (ESLs) can contain aluminum oxide (AlOx).

[0079] A side barrier pattern SBP can be provided below the first via VI1. The side barrier pattern SBP can be interposed between the second barrier pattern VBM2 and the etching stop film ESL. As another example, the side barrier pattern SBP can extend from the side wall of the second barrier pattern VBM2 to the bottom surface of the second barrier pattern VBM2.

[0080] The side barrier pattern SBP may contain transition metal oxides. The side barrier pattern SBP may include oxides of manganese (Mn), titanium (Ti), hafnium (Hf), chromium (Cr), niobium (Nb), tantalum (Ta), and vanadium (V). The side barrier pattern SBP may contain different transition metals from the first and second barrier patterns VBM1 and VBM2. For example, the first barrier pattern VBM1 may contain a ruthenium film and a tantalum nitride film, the second barrier pattern VBM2 may contain cobalt (Co), and the side barrier pattern SBP may contain manganese oxide. In the manufacturing method described later, the side barrier pattern SBP may be formed by the reaction of a transition metal with oxygen in the etching-stopping film ESL.

[0081] Referring to Figure 6B, the lower part of the first via VI1 may include a projection PTP that protrudes toward the etching stop film ESL. The projection PTP allows the width of the lower part of the first via VI1 to be greater than the width of the upper part of the first via VI1. A side barrier pattern SBP may be interposed between the projection PTP2 and the etching stop film ESL. The projection PTP does not necessarily have to be provided with a first barrier pattern VBM1. A second barrier pattern VBM2 may cover the side walls and bottom surface of the projection PTP.

[0082] The graph in Figure 6B shows the concentration of a transition metal (e.g., manganese) along the X direction. The manganese concentration in the via conductive pattern VFM can increase along the X direction. The second barrier pattern VBM2 can have a first manganese concentration C1. The first manganese concentration C1 can be defined as the concentration of manganese (Mn) contained in the second barrier pattern VBM2. The first manganese concentration C1 can be greater than the manganese concentration in the via conductive pattern VFM. The first manganese concentration C1 can increase along the X direction.

[0083] The side barrier pattern SBP may have a secondary manganese concentration C2. This secondary manganese concentration C2 may be the maximum manganese (Mn) concentration contained in the side barrier pattern SBP. The side barrier pattern SBP may have a higher manganese concentration than the etching stopper film ESL, the secondary barrier pattern VBM2, and the via conductive pattern VFM. The manganese concentration of the etching stopper film ESL may decrease along the X direction and converge to 0. The units of the first and second manganese concentrations C1 and C2 are atoms / cm³. 3 It is possible.

[0084] In other words, the manganese concentration can increase as the protruding portion PTP of the first via VI1 approaches the etching-stopping film ESL. The manganese concentration increases as it approaches the etching-stopping film ESL from the first via VI1, and can reach a maximum value at the interface between the first via VI1 and the etching-stopping film ESL. Subsequently, the manganese concentration can decrease again as it approaches the etching-stopping film ESL at the interface.

[0085] Referring again to Figure 6A, the first wiring M1_I may include a trench barrier pattern. The trench barrier pattern TBM may be substantially identical to the via barrier pattern VBM. The trench barrier pattern TBM may include a first trench barrier pattern TBM1 and a second trench barrier pattern TBM2 on the first trench barrier pattern TBM1. The first trench barrier pattern TBM1 may be substantially identical to the first barrier pattern VBM1, and the second trench barrier pattern TBM2 may be substantially identical to the second barrier pattern VBM2. However, unlike the first barrier pattern VBM1, the first trench barrier pattern TBM1 can cover the bottom surface of the conductive pattern of the first wiring M1_I.

[0086] A trench barrier pattern TBP can be formed below the first wiring M1_I. The trench barrier pattern TBP may be substantially identical to the side barrier pattern SBP. However, the manganese concentration of the trench barrier pattern TBP can be lower than that of the side barrier pattern SBP. This is because the trench barrier pattern TBP is separated from the etching-stopping film ESL, which contains a large amount of oxygen. The trench barrier pattern TBP can be interposed between the first trench barrier pattern TBM1 and the second trench barrier pattern TBM2.

[0087] The description of the first via VI1 according to the present invention can also be applied to the gate contact GC, the active contact AC, and the first and second wirings M1_I and M2_l. For example, the description of the via barrier pattern VBM can be applied substantially similarly to the barrier pattern BM of the gate contact GC, the barrier pattern BM of the active contact AC, and the first and second wirings M1_I and M2_l.

[0088] According to the present invention, a side barrier pattern SBP can be interposed between the protruding portion PTP of the first via VI1 and the corrosion-stopping film ESL. The side barrier pattern SBP contains a transition metal oxide and can prevent the diffusion of the conductive material of the first via VI1. Furthermore, the first barrier pattern VBM1 does not necessarily contain ruthenium (Ru), while the second barrier pattern VBM2 does not. Therefore, corrosion of the conductive pattern FM caused by contact between ruthenium (Ru) and the conductive pattern FM, and the resulting void formation of the conductive pattern FM, can be prevented. As a result, the reliability and electrical characteristics of the semiconductor device can be improved.

[0089] Figures 7A to 18 are diagrams illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention. Specifically, Figures 7A, 8A, 9A, 10A, 11A, 12A, and 13A are cross-sectional views corresponding to the line A-A' in Figure 4. Figures 9B, 10B, 11B, 12B, and 13B are cross-sectional views corresponding to the line B-B' in Figure 4. Figures 9C, 10C, 11C, 12C, and 13C are cross-sectional views corresponding to the line C-C' in Figure 4. Figures 7B, 8B, 11D, and 12D are cross-sectional views corresponding to the line D-D' in Figure 4. Figures 14, 15, 16, and 17A are enlarged views illustrating a method for forming the M region in Figure 13C. Figure 17B is an enlarged view showing the N region in Figure 17A.

[0090] Referring to Figures 7A and 7B, a substrate 100 including first and second active regions AR1 and AR2 can be provided. Active layers ACL and sacrificial layers SAL can be formed on the substrate 100, alternately stacked on each other. The active layer ACL may contain one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and the sacrificial layer SAL may contain another one of silicon (Si), germanium (Ge), and silicon germanium (SiGe).

[0091] The sacrificial layer SAL may contain a material that has an etching selectivity ratio with respect to the active layer ACL. For example, the active layer ACL may contain silicon (Si), and the sacrificial layer SAL may contain silicon germanium (SiGe). The concentration of each germanium (Ge) in the sacrificial layer SAL may be between 10 at% and 30 at%.

[0092] Mask patterns can be formed on the first and second active regions AR1 and AR2 of the substrate 100, respectively. The mask patterns may have a line shape or a bar shape that extends in the second direction D2.

[0093] The aforementioned mask pattern can be used as an etching mask to perform a patterning process, thereby forming trenches TR that define the first active pattern AP1 and the second active pattern AP2. The first active pattern AP1 can be formed on the first active region AR1. The second active pattern AP2 can be formed on the second active region AR2.

[0094] A layered pattern STP can be formed on the respective first and second active patterns AP1 and AP2. The layered pattern STP may include alternately stacked active layers ACL and sacrificial layers SAL. The layered pattern STP can be formed together with the first and second active patterns AP1 and AP2 during the patterning process.

[0095] An element isolation film ST can be formed that fills the trench TR. Specifically, an insulating film can be formed on the front surface of the substrate 100 to cover the first and second active patterns AP1 and AP2 and the laminated pattern STP. The element isolation film ST can be formed by recessing the insulating film until the laminated pattern STP is exposed.

[0096] The element isolation film ST may contain an insulating material such as a silicon oxide film. The stacked pattern STP can be exposed on the element isolation film ST. Again, the stacked pattern STP can protrude perpendicularly onto the element isolation film ST.

[0097] Referring to Figures 8A and 8B, sacrificial patterns PP can be formed on the substrate 100, crossing the laminated pattern STP. Each sacrificial pattern PP can be formed in the shape of a line hape or a bar extending in the first direction D1. The sacrificial patterns PP can be arranged along the second direction D2 at a first pitch.

[0098] Specifically, forming a sacrificial pattern PP may include forming a sacrificial film on the entire surface of the substrate 100, forming a hard mask pattern MP on the sacrificial film, and patterning the sacrificial film using the hard mask pattern MP as an etching mask. The sacrificial film may contain polysilicon.

[0099] A pair of gate spacers GS can be formed on each side wall of the sacrificial pattern PP. Forming the gate spacers GS may include conformally forming a gate spacer film over the entire surface of the substrate 100 and anisotropically etching the gate spacer film. In one embodiment of the present invention, the gate spacers GS may be a multilayer film comprising at least two films.

[0100] Referring to Figures 9A to 9C, a first recess RS1 can be formed within the stacked pattern STP on the first active pattern AP1. A second recess RS2 can be formed within the stacked pattern STP on the second active pattern AP2. Between the formation of the first and second recesses RS1 and RS2, the element isolation film ST on both sides of the first and second active patterns AP1 and AP2 can be further recessed (see Figure 11C).

[0101] Specifically, the first recess RS1 can be formed by etching the laminated pattern STP on the first active pattern AP1 using the hard mask pattern MP and gate spacer GS as etching masks. The first recess RS1 can be formed between a pair of sacrificial patterns PP.

[0102] From the active layer ACL, first to third semiconductor patterns SP1, SP2, and SP3 can be sequentially stacked between adjacent first recesses RS1. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent first recesses RS1 can constitute a first channel pattern CH1.

[0103] A first recess RS1 can be formed between adjacent sacrificial patterns PP. The width of the first recess RS1 in the second direction D2 can be reduced as it approaches the substrate 100.

[0104] The first recess RS1 can expose the sacrificial layer SAL. A selective etching process can be performed on the exposed sacrificial layer SAL. The etching process may include a wet etching process that selectively removes only silicon germanium. The etching process can indent each sacrificial layer SAL to form an indented region IDR. The indented region IDR can cause the sidewalls of the sacrificial layer SAL to be recessed. An insulating film can be formed within the first recess RS1 to fill the indented region IDR. The first to third semiconductor patterns SP1, SP2, SP3 and the sacrificial layer SAL exposed by the first recess RS1 can become seed layers for the insulating film. The insulating film can be grown as a crystalline dielectric film on the crystalline semiconductors constituting the first to third semiconductor patterns SP1, SP2, SP3 and the sacrificial layer SAL.

[0105] An inner spacer ISP can be formed that fills the indentation region IDR. Specifically, forming an inner spacer ISP may involve wet etching of an epitaxial dielectric film until the sidewalls of the first to third semiconductor patterns SP1, SP2, and SP3 are exposed. Therefore, the epitaxial dielectric film can remain only within the indentation region IDR to constitute an inner spacer ISP.

[0106] The second recess RS2 in the laminated pattern STP on the second active pattern AP2 can be formed in a manner similar to that used to form the first recess RS1. A selective etching process can be performed on the sacrificial layer SAL exposed by the second recess RS2 to form an indentation region IDE on the second active pattern AP2 as well. The indentation region IDE allows the second recess RS2 to have a wave-patterned inner wall. An inner spacer ISP does not need to be formed within the indentation region IDE on the second active pattern AP2. The first to third semiconductor patterns SP1, SP2, and SP3 between adjacent second recesses RS2 can constitute the second channel pattern CH2.

[0107] Referring to Figures 10A to 10C, the first source / drain pattern SD1 can be formed within the first recess RS1. Specifically, an epitaxial layer filling the first recess RS1 can be formed by performing a SEG process using the inner wall of the first recess RS1 as a seed layer. The epitaxial layer can be grown using the first to third semiconductor patterns SP1, SP2, SP3 and the substrate 100 exposed by the first recess RS1 as seeds. As an example, the SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0108] In one embodiment of the present invention, the first source / drain pattern SD1 may contain the same semiconductor element (e.g., Si) as the substrate 100. While the first source / drain pattern SD1 is being formed, impurities (e.g., phosphorus, arsenic, or antimony) that cause the first source / drain pattern SD1 to have an n-type can be injected in situ. As another example, impurities can be injected into the first source / drain pattern SD1 after it has been formed.

[0109] A second source / drain pattern SD2 can be formed within the second recess RS2. Specifically, the second source / drain pattern SD2 can be formed by performing a SEG process using the inner wall of the second recess RS2 as a seed layer.

[0110] In one embodiment of the present invention, the second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor elements of the substrate 100. While the second source / drain pattern SD2 is being formed, an impurity (e.g., boron, gallium, or indium) that causes the second source / drain pattern SD2 to have a p-type can be injected in situ. As another example, an impurity can be injected into the second source / drain pattern SD2 after it has been formed.

[0111] Referring to Figures 11A to 11C, a first interlayer insulating film 110 can be formed covering the first and second source / drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS. As an example, the first interlayer insulating film 110 may include a silicon oxide film.

[0112] The first interlayer insulating film 110 can be planarized until the upper surface of the sacrificial pattern PP is exposed. The planarization of the first interlayer insulating film 110 can be carried out using an etch-back or CMP (Chemical Mechanical Polishing) process. During the planarization process, the hard mask pattern MP can be completely removed. As a result, the upper surface of the first interlayer insulating film 110 can be coplane with the upper surface of the sacrificial pattern PP and the upper surface of the gate spacer GS.

[0113] The exposed sacrificial pattern PP can be selectively removed. By removing the sacrificial pattern PP, an outer region ORG can be formed that exposes the first and second channel patterns CH1 and CH2 (see Figure 11D). Removing the sacrificial pattern PP may include wet etching using an etching solution that selectively etches polysilicon.

[0114] The sacrificial layer SAL exposed through the outer region ORG can be selectively removed to form the inner region IRG (see Figure 11D). Specifically, by performing an etching process that selectively etches the sacrificial layer SAL, only the sacrificial layer SAL can be removed while the first to third semiconductor patterns SP1, SP2, and SP3 remain intact. The etching process can have a high etching rate for silicon germanium with a relatively high germanium concentration. For example, the etching process can have a high etching rate for silicon germanium with a germanium concentration greater than 10 at%.

[0115] During the etching process, the sacrificial layer SAL on the first and second active regions AR1 and AR2 can be removed. The etching process may be wet etching. The etching material used in the etching process can quickly remove the sacrificial layer SAL which has a relatively high germanium concentration.

[0116] Referring again to Figure 11D, by selectively removing the sacrificial layer SAL, only the stacked first to third semiconductor patterns SP1, SP2, and SP3 can remain on the respective first and second active patterns AP1 and AP2. The first to third inner regions IRG1, IRG2, and IRG3 can be formed through the region from which the sacrificial layer SAL has been removed.

[0117] Specifically, a first inner region IRG1 can be formed between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second inner region IRG2 can be formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third inner region IRG3 can be formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3.

[0118] Referring again to Figures 11A to 11D, a gate insulating film GI can be formed on the exposed first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating film GI can be formed so as to surround each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating film GI can be formed within each of the first to third inner regions IRG1, IRG2, and IRG3. The gate insulating film GI can be formed within the outer region ORG.

[0119] Referring to Figures 12A to 12D, a gate electrode GE can be formed on the gate insulating film GI. The gate electrode GE may include first to third inner electrodes PO1, PO2, and PO3 formed in first to third inner regions IRG1, IRG2, and IRG3, respectively, and an outer electrode PO4 formed in the outer region ORG. The gate electrode GE can be recessed to reduce its height. A gate capping pattern GP can be formed on the recessed gate electrode GE.

[0120] A second interlayer insulating film 120 can be formed on the first interlayer insulating film 110. The second interlayer insulating film 120 may include a silicon oxide film. Active contacts AC can be formed that penetrate the second interlayer insulating film 120 and the first interlayer insulating film 110 and are electrically connected to the first and second source / drain patterns SD1 and SD2. Gate contacts GC can be formed that penetrate the second interlayer insulating film 120 and the gate capping pattern GP and are electrically connected to the gate electrode GE.

[0121] Forming the active contact AC and gate contact GC may include forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may be conformally formed and may include a metal film / metal nitride film. The conductive pattern FM may include a low-resistance metal.

[0122] Separation structures DB can be formed at the first boundary BD1 and the second boundary BD2 of the single-height cell SHC, respectively. The separation structures DB can be extended from the second interlayer insulating film 120 through the gate electrode GE into the interior of the active pattern AP1 or AP2. The separation structures DB may include an insulating material such as a silicon oxide film or a silicon nitride film.

[0123] Referring to Figures 13A to 13C, an etching stop film ESL can be formed on the active contact AC and the gate contact GC. A third interlayer insulating film 130 can be formed on the etching stop film ESL. A first metal layer M1 can be formed within the third interlayer insulating film 130.

[0124] Referring again to Figures 5A to 5D, a fourth interlayer insulating film 140 can be formed on the third interlayer insulating film 130. A second metal layer M2 can be formed within the fourth interlayer insulating film 140.

[0125] Referring to Figures 14 to 18, the method for forming the M region in Figure 13C will be explained in more detail.

[0126] Referring to Figure 14, the third interlayer insulating film 130 can be etched to form wiring holes MH, via holes VH, and trench holes TH. The wiring holes MH, via holes VH, and trench holes TH can later be filled with conductive material to become the first power wiring M1_R1, the first via VI1, and the first wiring M1_I, respectively. The wiring holes MH, via holes VH, and trench holes TH can be formed by a single damascene process or a dual damascene process, but are not limited to these.

[0127] A portion of the etching stop film ESL can be exposed by a via hole VH. The exposed etching stop film ESL can be removed to form a blocking film BLL. The blocking film BLL may be an oxide or nitride film deposited by a CVD (Chemical Vapor Deposition) process. The thickness TH1 of the blocking film BLL can be the same as or smaller than the thickness TH2 of the etching stop film ESL. The blocking film BLL may include a silicon oxide film or a silicon nitride film. For example, the blocking film BLL may include a material that is etching selective for ruthenium (Ru).

[0128] A first barrier pattern VBM1 can be conformally formed on the inner walls of each of the wiring holes MH, via holes VH, and trench holes TH. Specifically, the first barrier pattern VBM1 can be formed by alternately depositing multiple metal films and metal nitride films. For example, forming the first barrier pattern VBM1 can include forming a first tantalum nitride film (TaN) on the inner wall, forming a first ruthenium film (Ru) on the first tantalum nitride film (TaN), forming a second tantalum nitride film (TaN) on the first ruthenium film (Ru), and forming a second ruthenium film (Ru) on the second tantalum nitride film (TaN). The formation of the first and second tantalum nitride films (TaN) can be carried out by a mechanism similar to the ALD (Atomic Layer Deposition) process. The formation of the first and second ruthenium films (Ru) can be carried out by the CVD (Chemical Vapor Deposition) process.

[0129] The first barrier pattern VBM1 does not necessarily have to be formed on the upper surface of the blocking film BLL. This allows the upper surface of the blocking film BLL to still be exposed by the via hole VH. The blocking film BLL separates the first barrier pattern VBM1 from the conductive pattern FM. The first barrier pattern VBM1 does not necessarily have to be formed below the via hole VH.

[0130] Referring to Figure 15, plasma treatment can be performed on wiring holes MH, via holes VH, and trench holes TH. Plasma treatment can be performed on the first barrier pattern VBM1 and blocking film BLL. As an example, plasma treatment can be performed on the surface of the first barrier pattern VBM1 using argon (Ar) ions PLT in a plasma state.

[0131] Furthermore, the plasma process can cause argon (Ar) ions PLT in a plasma state to collide at high speed with the surface of the blocking film BLL. This allows the blocking film BLL to be removed, exposing the sidewall E_SW of the etching stop film ESL and the upper surface AC_TS of the conductive pattern RM. The exposed sidewall E_SW of the etching stop film ESL can be further recessed by the plasma process. This allows the etching stop film ESL to have a sidewall that is recessed inward (see recessed sidewall RSW in Figure 16, described later). While the etching stop film ESL is recessed, the width of the lower part of the via hole VH can be greater than the width of the upper part.

[0132] As another example, an etching process can be additionally performed to selectively remove the blocking film BLL prior to the plasma process. Subsequently, the plasma process can remove all of the blocking film BLL that was not removed in the etching process.

[0133] Referring to Figure 16, the wiring hole MH, via hole VH, and trench hole TH can be conformally formed with a second barrier pattern VBM2. Forming the second barrier pattern VBM2 may involve a CVD (Chemical Vapor Deposition) process. The second barrier pattern VBM2 can be formed on top of the first barrier pattern VBM1. The second barrier pattern VBM2 can cover the top surface of the exposed conductive pattern FM and the recessed side wall RSW of the corrosion-stopping film ESL. The second barrier pattern VBM2 can be formed down to the bottom of the via hole VH. The second barrier pattern VBM2 can be extended to the bottom surface of the via hole VH. This allows the lowest level of the second barrier pattern VBM2 to be lower than the lowest level of the first barrier pattern VBM1.

[0134] The second barrier pattern VBM2 may include at least one of titanium, tantalum, tungsten, nickel, cobalt, platinum, and combinations thereof. The second barrier pattern VBM2 may contain transition metals different from those of the first barrier pattern VBM1. For example, the second barrier pattern VBM2 may not contain ruthenium (Ru). The second barrier pattern VBM2 formed within the trench hole TH may be the second trench barrier pattern TBM2. The second trench barrier pattern TBM2 may be substantially identical to the second barrier pattern VBM2.

[0135] Referring to Figure 17A, a preliminary via conductive pattern VFM_P can be formed by filling the wiring holes MH and via holes VH with a filling material. A preliminary trench conductive pattern TFM_P can be formed by filling the trench holes TH with a filling material. Specifically, this may involve depositing the filling material into the wiring holes MH, via holes VH, and trench holes TH, and repeatedly performing a reflow process on the filling material. In this case, the first filling material provided initially may be different from the second filling material provided after the reflow process. The first filling material may be an alloy containing two or more metals. On the other hand, the second filling material may contain only one metal. For example, the first filling material may contain more transition metals than the second filling material.

[0136] As an example, the first filling material may be at least two metallic substances selected from the group consisting of manganese, aluminum, copper, tungsten, molybdenum, and cobalt. As an example, the first filling material may be copper-manganese (CuMn). The manganese (Mn) of the first filling material can be provided at the bottom of the via hole VH. By repeatedly depositing the filling material and subsequently performing a reflow process, a via conductive pattern VFM can be formed in the via hole VH to form the first via VI1. A first power wiring M1_R1 can be formed in the wiring hole MH, and a first wiring M1_I can be formed in the trench hole TH.

[0137] Referring to Figure 17B, a Post Reflow Anneal (PRA) process can be performed on the first via VI1. Specifically, the annealing process can be performed after the final reflow process shown in Figure 17A. The annealing process can be performed at a temperature of approximately 300°C to 600°C. This annealing process allows the manganese (Mn) particles PAT located at the bottom of the first via VI1 to move towards the etching stop film ESL. This is because manganese (Mn) has a greater tendency to react with oxygen (O) than copper (Cu) in the conductive pattern FM.

[0138] By the same principle, manganese (Mn) particles located at the bottom of the first wiring M1_I can move toward the third interlayer insulating film 130. In other words, manganese (Mn) particles located at the bottom of the first wiring M1_I can move toward the edge of the first wiring M1_I.

[0139] Referring again to Figure 6A, the migrated manganese (Mn) particles can react with oxygen in the etching-stopping film ESL to form manganese oxide (MnO). This allows the side barrier pattern SBP to be formed between the second barrier pattern VBM2 and the etching-stopping film ESL. The manganese (Mn) concentration can be maximized in the side barrier pattern SBP. The closer the first via VI1 is to the side barrier pattern SBP, the higher the manganese concentration can be.

[0140] By the same principle, a trench barrier pattern TBP can be formed between the first trench barrier pattern TBM1 and the second trench barrier pattern VBM2. Since the trench barrier pattern TBP is separated from the etching stop film ESL, the concentration of manganese oxide (MnO) can be lower than that of the side barrier pattern SBP.

[0141] According to the semiconductor device manufacturing method of the present invention, a Post Reflow Anneal (PRA) process can be performed to form a side barrier pattern (SBP) below the first via VI1. During the PRA process, manganese migrates toward the etching stop film (ESL), and the migrated manganese reacts with the oxygen in the etching stop film (ESL) to form the side barrier pattern (SBP). Therefore, profiling defects between the first via and the conductive pattern can be improved.

[0142] While embodiments of the present invention have been described above with reference to the attached drawings, those with ordinary skill in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without altering its technical idea or essential features. Therefore, the embodiments described above should be understood to be illustrative and not limiting in all respects. [Explanation of Symbols]

[0143] 110-140 Interlayer insulating film AC Activated Contact AR1, AR2 active region CH1, CH2 Channel Pattern DB separation structure ESL Etching Stop Membrane FM conductive pattern GC gate contact GE Terminal GI gate insulating film GS Gate Spacer GP gate capping pattern M1, M2 metal layer M1_I, M2_I wiring SBP Side Barrier Pattern ST element separation membrane VBM1, VBM2 Barrier Patterns VI1, VI2 vias

Claims

1. A transistor on a substrate, which includes a conductive pattern, A first metal layer on the transistor, the first metal layer including a first wiring and a first via beneath the first wiring, The transistor and the first metal layer include an etching-stopping film, The first via penetrates the etching-stopping film and connects the conductive pattern and the first wiring, The first via is The first barrier pattern, The second barrier pattern on the first barrier pattern, The invention includes a side barrier pattern interposed between the second barrier pattern and the etching-stopping film, The aforementioned side barrier pattern is a semiconductor device containing a transition metal oxide.

2. The semiconductor device according to claim 1, wherein the side barrier pattern includes a transition metal different from that of the first barrier pattern.

3. The semiconductor device according to claim 1, wherein the side barrier pattern contains a transition metal different from that of the second barrier pattern.

4. The semiconductor element according to claim 1, wherein the side barrier pattern extends to the bottom surface of the second barrier pattern.

5. The first via further includes a via conductive pattern, The second barrier pattern covers the sidewall of the via conductive pattern. The semiconductor element according to claim 1, wherein the second barrier pattern extends between the bottom surface of the via conductive pattern and the top surface of the conductive pattern.

6. The semiconductor element according to claim 1, wherein the side barrier pattern is formed by a reaction between a transition metal and oxygen in the etching-stopping film.

7. The semiconductor element according to claim 1, wherein the lower part of the first via includes a projection that protrudes toward the etching-stopping film.

8. The semiconductor element according to claim 7, wherein the concentration of the transition metal increases as the protrusion of the first via approaches the etching-stopping film.

9. The semiconductor element according to claim 1, wherein the first barrier pattern and the conductive pattern are separated via the etching-stopping film.

10. The semiconductor device according to claim 1, wherein the etching-stopping film comprises an oxide.

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