Semiconductor equipment

Abstract

To provide a semiconductor device that can be miniaturized. [Solution] The semiconductor device of the embodiment comprises a first element region, a second element region, and an intermediate region between the first element region and the second element region. The silicon carbide layer of the intermediate region includes a silicon carbide region extending in a first direction and repeatedly arranged in a first period in a second direction perpendicular to the first direction, and another silicon carbide region extending in a first direction and repeatedly arranged in a first period in the second direction, shifted by half a period of the first period from the silicon carbide region.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] There is a bidirectional switching device in which two MOSFETs are connected in reverse. For example, by applying the bidirectional switching device to an inverter circuit, the power loss of the inverter circuit can be reduced. In order to miniaturize the bidirectional switching device, it is conceivable to integrate two MOSFETs on one chip.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device that can be miniaturized.

Means for Solving the Problems

[0005] A semiconductor device according to one aspect of the present invention comprises a first element region, a second element region, and an intermediate region provided between the first element region and the second element region, wherein the first element region is a silicon carbide layer having a first surface and a second surface facing the first surface, and comprises a first silicon carbide region of a first conductivity type in contact with the second surface, a second silicon carbide region of a first conductivity type provided between the first silicon carbide region and the first surface, having a first conductivity type impurity concentration lower than that of the first conductivity type impurity concentration of the first silicon carbide region, and the first silicon carbide region and the A plurality of third silicon carbide regions of a second conductivity type are provided between the first surface and the first surface, extending in a first direction parallel to the first surface, and repeatedly arranged in a first period with the second silicon carbide region in between in a second direction parallel to the first surface and perpendicular to the first direction, with the second silicon carbide region in between; a fourth silicon carbide region of a first conductivity type is provided between the second silicon carbide region and the first surface and is in contact with the second silicon carbide region; a fifth silicon carbide region of a second conductivity type is provided between the third silicon carbide region and the first surface and is in contact with the third silicon carbide region; and the third silicon carbide region and the A silicon carbide layer including a sixth silicon carbide region of a first conductivity type provided between it and a first surface; a first gate electrode facing the fourth silicon carbide region and the fifth silicon carbide region; a first gate insulating layer provided between the first gate electrode and the fourth silicon carbide region and between the first gate electrode and the fifth silicon carbide region; and a first electrode provided on the side of the first surface of the silicon carbide layer, in contact with the fourth silicon carbide region and the sixth silicon carbide region, and electrically connected to the fifth silicon carbide region, wherein the second element region is the A first silicon carbide region, a second silicon carbide region, a plurality of seventh silicon carbide regions of second conductivity type provided between the first silicon carbide region and the first surface, extending in the first direction and repeatedly arranged in the second direction with the second silicon carbide region in between in the first period, an eighth silicon carbide region of first conductivity type provided between the second silicon carbide region and the first surface and in contact with the second silicon carbide region, a ninth silicon carbide region of second conductivity type provided between the seventh silicon carbide region and the first surface and in contact with the seventh silicon carbide region,A silicon carbide layer comprising: a silicon carbide layer including a 10th silicon carbide region of a first conductivity type provided between the 9th silicon carbide region and the first surface; a second gate electrode facing the 8th silicon carbide region and the 9th silicon carbide region; a second gate insulating layer provided between the second gate electrode and the 8th silicon carbide region and between the second gate electrode and the 9th silicon carbide region; and a device provided on the side of the first surface of the silicon carbide layer, in contact with the 8th silicon carbide region and the 10th silicon carbide region, electrically connected to the 9th silicon carbide region, and electrically connected to the first electrode. The intermediate region includes a silicon carbide layer comprising a gas-separated second electrode, the first silicon carbide region, the second silicon carbide region, the third silicon carbide region, the seventh silicon carbide region, and an eleventh silicon carbide region of a first conductivity type provided between the third silicon carbide region and the first surface, and between the seventh silicon carbide region and the first surface, wherein in the intermediate region, the arrangement of the seventh silicon carbide region in the second direction is shifted by half a period of the first period with respect to the arrangement of the third silicon carbide region in the second direction. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic top view of the semiconductor device according to the first embodiment. [Figure 2] Equivalent circuit diagram of the semiconductor device of the first embodiment. [Figure 3] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 5] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 6] A schematic cross-sectional view of a semiconductor device, a modified example of the first embodiment. [Figure 7] A schematic cross-sectional view of a semiconductor device, a modified example of the first embodiment. [Figure 8] A schematic cross-sectional view of the semiconductor device according to the second embodiment. [Figure 9] A schematic cross-sectional view of a semiconductor device of a modified example of the second embodiment. [Figure 10] Schematic cross-sectional view of a semiconductor device according to a modified example of the second embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described may be omitted as appropriate.

[0008] Also, in the following description, n + , n, n - and, p + , p, p - If there is such notation, those notations represent the relative levels of impurity concentrations in each conductivity type. That is, n + has a relatively higher n-type impurity concentration than n, and n - has a relatively lower n-type impurity concentration than n. Also, p + has a relatively higher p-type impurity concentration than p, and p - has a relatively lower p-type impurity concentration than p. Note that n + type and n - type may be simply described as n-type, and p + type and p - type may be simply described as p-type.

[0009] In this specification, unless otherwise specified, "impurity concentration" means the concentration obtained by compensating for the concentration of impurities of the opposite conductivity type. That is, the n-type impurity concentration in the n-type silicon carbide region means the concentration obtained by subtracting the p-type impurity concentration from the n-type impurity concentration. Also, the p-type impurity concentration in the p-type silicon carbide region means the concentration obtained by subtracting the n-type impurity concentration from the p-type impurity concentration. In this specification, unless otherwise specified, the "impurity concentration in the silicon carbide region" is the maximum impurity concentration in the corresponding silicon carbide region.

[0010] Impurity concentrations can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). The relative levels of impurity concentrations can also be determined, for example, from the carrier concentrations obtained by Scanning Capacitance Microscopy (SCM). Furthermore, distances such as depth and thickness of impurity regions can be determined, for example, by SIMS or Scanning Electron Microscope (SEM). Additionally, distances such as depth, thickness, width, and spacing of impurity regions can be determined, for example, from a composite image of SCM and Atomic Force Microscope (AFM) images.

[0011] (First embodiment) The semiconductor device of the first embodiment comprises a first element region, a second element region, and an intermediate region provided between the first element region and the second element region. The first element region is a silicon carbide layer having a first surface and a second surface facing the first surface, and comprises a first silicon carbide region of a first conductivity type in contact with the second surface, a second silicon carbide region of a first conductivity type provided between the first silicon carbide region and the first surface, having a first conductivity type impurity concentration lower than that of the first conductivity type impurity concentration of the first silicon carbide region, a plurality of third silicon carbide regions of a second conductivity type provided between the first silicon carbide region and the first surface, extending in a first direction parallel to the first surface and in a second direction parallel to the first surface and perpendicular to the first direction, with the second silicon carbide region in between and arranged repeatedly in a first period, and provided between the second silicon carbide region and the first surface, and the second silicon carbide region A silicon carbide layer including a fourth silicon carbide region of a first conductivity type that is in contact with the third silicon carbide region and the first surface, a fifth silicon carbide region of a second conductivity type provided between the third silicon carbide region and the first surface and in contact with the third silicon carbide region, and a sixth silicon carbide region of a first conductivity type provided between the third silicon carbide region and the first surface; a first gate electrode facing the fourth silicon carbide region and the fifth silicon carbide region; a first gate insulating layer provided between the first gate electrode and the fourth silicon carbide region and between the first gate electrode and the fifth silicon carbide region; and a first electrode provided on the side of the first surface of the silicon carbide layer, in contact with the fourth silicon carbide region and the sixth silicon carbide region, and electrically connected to the fifth silicon carbide region.The second element region is provided between the first silicon carbide region and the first surface, extending in a first direction, and in a second direction, it is repeatedly arranged in a first period with the second silicon carbide region in between, comprising a plurality of seventh silicon carbide regions of second conductivity, provided between the second silicon carbide region and the first surface, and in contact with the second silicon carbide region, comprising an eighth silicon carbide region of first conductivity, provided between the seventh silicon carbide region and the first surface, and in contact with the seventh silicon carbide region, comprising a ninth silicon carbide region of second conductivity, and the ninth silicon carbide A silicon carbide layer including a 10th silicon carbide region of a first conductivity type provided between a silicon carbide region and a first surface; a second gate electrode facing the 8th silicon carbide region and the 9th silicon carbide region; a second gate insulating layer provided between the second gate electrode and the 8th silicon carbide region and between the second gate electrode and the 9th silicon carbide region; and a second electrode provided on the side of the first surface of the silicon carbide layer, in contact with the 8th and 10th silicon carbide regions, electrically connected to the 9th silicon carbide region, and electrically isolated from the first electrode. The intermediate region includes a silicon carbide layer comprising a first silicon carbide region, a second silicon carbide region, a third silicon carbide region, a seventh silicon carbide region, an eleventh silicon carbide region of first conductivity provided between the third silicon carbide region and the first surface, and between the seventh silicon carbide region and the first surface. In the intermediate region, the arrangement of the seventh silicon carbide region in the second direction is shifted by half a period of the first period relative to the arrangement of the third silicon carbide region in the second direction.

[0012] Figure 1 is a schematic top view of the semiconductor device according to the first embodiment. Figure 1 is a layout diagram of the semiconductor device according to the first embodiment. Figure 1 shows the layout patterns of the first element region, the second element region, the intermediate region, the termination region, the first gate electrode pad, and the second gate electrode pad.

[0013] The semiconductor device of the first embodiment is a bidirectional switching device 100 using silicon carbide. The bidirectional switching device 100 includes a structure in which two planar gate type vertical MOSFETs are connected such that their drain electrodes are common. The bidirectional switching device 100 is a bidirectional switching device in which two planar gate type vertical MOSFETs are integrated into a single chip. In addition, each of the two planar gate type vertical MOSFETs is equipped with a Schottky Barrier Diode (SBD) as an internal diode.

[0014] The following explanation will use the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. The MOSFET included in the bidirectional switching device 100 of the first embodiment is a vertical n-channel MOSFET that uses electrons as carriers.

[0015] The bidirectional switching device 100 comprises a first element region 101a, a second element region 101b, an intermediate region 102, and a termination region 103.

[0016] The intermediate region 102 is provided between the first element region 101a and the second element region 101b. The termination region 103 surrounds the first element region 101a, the second element region 101b, and the intermediate region 102.

[0017] The first element region 101a includes multiple MOSFETs and multiple SBDs. The second element region 101b includes multiple MOSFETs and multiple SBDs.

[0018] The intermediate region 102 and the termination region 103 reduce the intensity of the electric field applied to the termination of the first element region 101a or the second element region 101b when the bidirectional switching device 100 is in the off state. The intermediate region 102 and the termination region 103 have the function of improving the dielectric breakdown voltage of the bidirectional switching device 100. In particular, the intermediate region 102 reduces the intensity of the electric field applied between the first element region 101a and the second element region 101b.

[0019] Figure 2 is an equivalent circuit diagram of the semiconductor device according to the first embodiment.

[0020] As shown in Figure 2, the drain of the MOSFET in the first element region 101a is connected to the drain of the MOSFET in the second element region 101b. The source of the MOSFET in the first element region 101a is connected to the first source electrode 12a. The source of the MOSFET in the second element region 101b is connected to the second source electrode 12b. The gate electrode of the MOSFET in the first element region 101a is connected to the first gate electrode pad 150a. The gate electrode of the MOSFET in the second element region 101b is connected to the second gate electrode pad 150b.

[0021] The MOSFET in the first element region 101a and the MOSFET in the second element region 101b are equipped with a pn junction diode and an SBD as built-in diodes, respectively.

[0022] The MOSFETs in the first element region 101a and the MOSFETs in the second element region 101b can conduct current using their built-in diodes even when the MOSFETs are in the off state. In particular, the MOSFETs in the first element region 101a and the second element region 101b are equipped with unipolar operating SBDs as built-in diodes. By providing unipolar operating SBDs, current loss in the low-current region can be reduced when current is conducted using the built-in diodes, and furthermore, the growth of stacking faults in the silicon carbide layer can be suppressed.

[0023] Furthermore, the MOSFETs in the first element region 101a and the MOSFET in the second element region 101b are equipped with a superjunction structure (hereinafter referred to as "SJ structure"). The SJ structure is a structure in which p-type semiconductor regions and n-type semiconductor regions are arranged alternately. High breakdown voltage of the MOSFET is achieved by depleting the p-type and n-type semiconductor regions. At the same time, low on-resistance of the MOSFET can be achieved by passing current through the high impurity concentration region.

[0024] Figure 3 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 3 is the AA' cross-section of Figures 1 and 4. Figure 4 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 4 is the CC' cross-section of Figures 3 and 5. Figure 5 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 5 is the BB' cross-section of Figures 1 and 4.

[0025] The bidirectional switching device 100 comprises a silicon carbide layer 10, a first source electrode 12a (first electrode), a second source electrode 12b (second electrode), a back metal layer 14, a first gate insulating layer 16a, a second gate insulating layer 16b, a first gate electrode 18a, a second gate electrode 18b, an interlayer insulating layer 20, a field insulating layer 22, a first gate electrode pad 150a, and a second gate electrode pad 150b.

[0026] The silicon carbide layer 10 is n + The back surface region 30 of the n-shape (first silicon carbide region), the drift region 31 of the n-shape (second silicon carbide region), the first pillar region 32a of the p-shape (third silicon carbide region), the second pillar region 32b of the p-shape (seventh silicon carbide region), the first JFET region 33a of the n-shape (fourth silicon carbide region), the second JFET region 33b of the n-shape (eighth silicon carbide region), the first base region 34a of the p-shape (fifth silicon carbide region), the second base region 34b of the p-shape (ninth silicon carbide region), n + The first source region 35a (sixth silicon carbide region) of type n + The second source region 35b (10th silicon carbide region) of the type, n - It includes the surface region 36 of the shape (the 11th silicon carbide region).

[0027] The first element region 101a comprises a silicon carbide layer 10, a first source electrode 12a (first electrode), a back metal layer 14, a first gate insulating layer 16a, a first gate electrode 18a, and an interlayer insulating layer 20.

[0028] The silicon carbide layer 10 of the first element region 101a is n +The back surface region 30 of the n-shape (first silicon carbide region), the drift region 31 of the n-shape (second silicon carbide region), the first pillar region 32a of the p-shape (third silicon carbide region), the first JFET region 33a of the n-shape (fourth silicon carbide region), the first base region 34a of the p-shape (fifth silicon carbide region), n + It includes the first source region 35a (sixth silicon carbide region) of the type.

[0029] The silicon carbide layer 10 is provided between the first source electrode 12a and the back metal layer 14. The silicon carbide layer 10 is single-crystal SiC. For example, the silicon carbide layer 10 is 4H-SiC.

[0030] The silicon carbide layer 10 comprises a first surface ("F1" in Figure 3) and a second surface ("F2" in Figure 3). The first surface F1 is the surface of the silicon carbide layer. The second surface F2 is the back surface of the silicon carbide layer. Hereinafter, the first surface F1 may be referred to as the surface and the second surface F2 as the back surface. The first surface F1 is located on the side of the silicon carbide layer 10 toward the first source electrode 12a. The second surface F2 is located on the side of the silicon carbide layer 10 toward the back metal layer 14. The first surface F1 and the second surface F2 face each other. The term "surface" in the first surface F1 and the second surface F2 refers to, for example, the interface between the silicon carbide layer and the insulating film, or between the silicon carbide layer and the metal.

[0031] The first face is parallel to the first and second directions. The second direction is perpendicular to the first direction.

[0032] The first surface F1 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (0001) surface. The second surface F2 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (000-1) surface. The (0001) surface is referred to as the silicon surface. The (000-1) surface is referred to as the carbon surface.

[0033] The thickness of the silicon carbide layer 10 is, for example, 5 μm to 350 μm.

[0034] n + The back surface region 30 of the mold is in contact with the second surface F2.

[0035] The back surface region 30 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the back surface region 30 is, for example, 5 × 10⁻⁶ 19 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0036] The back surface region 30 functions, for example, as a current path between the first element region 101a and the second element region 101b.

[0037] The n-type drift region 31 is provided between the back surface region 30 and the first surface F1. The drift region 31 is, for example, in contact with the back surface region 30.

[0038] The drift region 31 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drift region 31 is lower than the concentration of n-type impurities in the back surface region 30. The concentration of n-type impurities in the drift region 31 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 18 cm -3 The following applies: The thickness of the drift region 31 is, for example, between 3 μm and 100 μm.

[0039] The drift region 31 functions, for example, as a current path during the ON operation of the MOSFET. It also functions as a current path during the ON operation of the SBD. Furthermore, it functions as part of the SJ structure.

[0040] The first p-shaped pillar region 32a is provided between the back surface region 30 and the first surface F1. The first pillar region 32a is in contact with, for example, the back surface region 30.

[0041] Multiple first pillar regions 32a extend in a first direction. Multiple first pillar regions 32a are repeatedly arranged in a second direction with a drift region 31 in between. Multiple first pillar regions 32a are repeatedly arranged in a second direction with a first period (P1 in Figure 4).

[0042] The first pillar region 32a contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the first pillar region 32a is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 18 cm -3 The following applies:

[0043] The first pillar region 32a is electrically connected to the first source electrode 12a. The first pillar region 32a is fixed at the potential of the first source electrode 12a.

[0044] The first pillar regions 32a and drift regions 31, which are alternately arranged in the second direction, form an SJ structure.

[0045] The n-shaped first JFET region 33a is provided between the drift region 31 and the first surface F1. The first JFET region 33a is in contact with the drift region 31. The first JFET region 33a is in contact with the first surface F1. The first JFET region 33a is sandwiched, for example, between two first base regions 34a in a first direction.

[0046] The first JFET region 33a contains, for example, nitrogen (N) as an n-type impurity. The concentration of the n-type impurity in the first JFET region 33a is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 18 cm -3 The following applies:

[0047] The first JFET region 33a functions as a current path when the MOSFET is turned on. It also functions as a current path when the SBD is turned on.

[0048] The first p-shaped base region 34a is provided between the first pillar region 32a and the first surface F1. The first base region 34a is in contact with the first surface F1. The first base region 34a is in contact with the first pillar region 32a.

[0049] The first base region 34a extends, for example, in a second direction. For example, multiple first base regions 34a are repeatedly arranged in the first direction.

[0050] The first base region 34a contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the first base region 34a is, for example, 5 × 10⁻⁶ 16 cm -3 The above 5 x 10 19 cm -3 The following applies:

[0051] The first base region 34a functions as the channel region of the MOSFET.

[0052] n + The first source region 35a of the mold is provided between the first base region 34a and the first surface F1. The first source region 35a is in contact with the first surface F1. The first source region 35a extends, for example, in a second direction.

[0053] The first source region 35a contains, for example, phosphorus (P) or nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the first source region 35a is higher than the concentration of n-type impurities in the first JFET region 33a.

[0054] The n-type impurity concentration in the first source region 35a is, for example, 1 × 10⁻⁶ 19 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0055] The first gate electrode 18a is provided on the side of the first surface F1 of the silicon carbide layer 10. The first gate electrode 18a extends, for example, in a second direction. Multiple first gate electrodes 18a are arranged, for example, parallel to each other in the first direction. The first gate electrodes 18a have, for example, a stripe shape.

[0056] The first gate electrode 18a is a conductive layer. The first gate electrode 18a is, for example, polycrystalline silicon containing p-type or n-type impurities.

[0057] The first gate electrode 18a faces the first JFET region 33a. The first gate electrode 18a faces the first base region 34a.

[0058] The first gate electrode 18a is electrically connected to the first gate electrode pad 150a.

[0059] The first gate insulating layer 16a is provided between the first gate electrode 18a and the first JFET region 33a. The first gate insulating layer 16a is provided between the first gate electrode 18a and the first base region 34a.

[0060] The first gate insulating layer 16a is, for example, silicon oxide.

[0061] The interlayer insulating layer 20 is provided on the first gate electrode 18a and the silicon carbide layer 10. The interlayer insulating layer 20 is, for example, silicon oxide.

[0062] The first source electrode 12a is provided on the side of the first surface F1 of the silicon carbide layer 10 of the first element region 101a. The first source electrode 12a is provided on the interlayer insulating layer 20.

[0063] The first source electrode 12a is in contact with the silicon carbide layer 10. The first source electrode 12a is in contact with the first source region 35a. The first source electrode 12a is in contact with the first JFET region 33a.

[0064] The contact between the first source electrode 12a and the first source region 35a is, for example, ohmic contact. The contact between the first source electrode 12a and the first JFET region 33a is, for example, Schottky contact.

[0065] The back metal layer 14 is in contact with the second surface F2. The back metal layer 14 is in contact with the back region 30. The back metal layer 14 functions, for example, as a current path between the first element region 101a and the second element region 101b.

[0066] The second element region 101b has the same configuration as the first element region 101a.

[0067] The second element region 101b comprises a silicon carbide layer 10, a second source electrode 12b (second electrode), a back metal layer 14, a second gate insulating layer 16b, a second gate electrode 18b, and an interlayer insulating layer 20.

[0068] The silicon carbide layer 10 of the second element region 101b is n + The back surface region 30 of the n-shape (first silicon carbide region), the drift region 31 of the n-shape (second silicon carbide region), the second pillar region 32b of the p-shape (seventh silicon carbide region), the second JFET region 33b of the n-shape (eighth silicon carbide region), the second base region 34b of the p-shape (ninth silicon carbide region), n + It includes the second source region 35b (10th silicon carbide region) of the type.

[0069] The p-shaped second pillar region 32b is provided between the back surface region 30 and the first surface F1. The second pillar region 32b is in contact with, for example, the back surface region 30.

[0070] Multiple second pillar regions 32b extend in the first direction. Multiple second pillar regions 32b are repeatedly arranged in the second direction with the drift region 31 in between. Multiple second pillar regions 32b are repeatedly arranged in the second direction with the same first period (P1 in Figure 4) as the first pillar region 32a.

[0071] The second pillar region 32b contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the second pillar region 32b is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 19 cm -3 The following applies:

[0072] The second pillar region 32b is electrically connected to the second source electrode 12b. The second pillar region 32b is fixed at the potential of the second source electrode 12b.

[0073] The second pillar regions 32b and drift regions 31, which are alternately arranged in the second direction, form an SJ structure.

[0074] The n-shaped second JFET region 33b is provided between the drift region 31 and the first surface F1. The second JFET region 33b is in contact with the drift region 31. The second JFET region 33b is in contact with the first surface F1. The second JFET region 33b is sandwiched between two second base regions 34b in a first direction, for example.

[0075] The second JFET region 33b contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the second JFET region 33b is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 18 cm -3 The following applies:

[0076] The second JFET region 33b functions as a current path when the MOSFET is turned on. The second JFET region 33b also functions as a current path when the SBD is turned on.

[0077] The p-shaped second base region 34b is provided between the second pillar region 32b and the first surface F1. The second pillar region 32b is in contact with the first surface F1. The second pillar region 32b is in contact with the first pillar region 32a.

[0078] The second base region 34b extends, for example, in a second direction. For example, multiple second base regions 34b are repeatedly arranged in the second direction.

[0079] The second base region 34b contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the second base region 34b is, for example, 5 × 10⁻⁶ 16 cm -3 The above 5 x 10 19 cm -3 The following applies:

[0080] The second base region 34b functions as the channel region of the MOSFET.

[0081] n + The second source region 35b of the mold is provided between the second base region 34b and the first surface F1. The second source region 35b is in contact with the first surface F1. The second source region 35b extends, for example, in a second direction.

[0082] The second source region 35b contains, for example, phosphorus (P) or nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the second source region 35b is higher than the concentration of n-type impurities in the second JFET region 33b.

[0083] The n-type impurity concentration in the second source region 35b is, for example, 1 × 10⁻⁶ 19 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0084] The second gate electrode 18b is provided on the side of the first surface F1 of the silicon carbide layer 10. The second gate electrode 18b extends, for example, in a second direction. Multiple second gate electrodes 18b are arranged, for example, parallel to each other in the first direction. The second gate electrodes 18b have, for example, a stripe shape.

[0085] The second gate electrode 18b faces the second JFET region 33b. The second gate electrode 18b faces the second base region 34b.

[0086] The second gate electrode 18b is electrically connected to the second gate electrode pad 150b.

[0087] The second gate insulating layer 16b is provided between the second gate electrode 18b and the second JFET region 33b. The second gate insulating layer 16b is provided between the second gate electrode 18b and the second base region 34b.

[0088] The interlayer insulating layer 20 is provided on the second gate electrode 18b and the silicon carbide layer 10.

[0089] The second source electrode 12b is provided on the side of the first surface F1 of the silicon carbide layer 10 of the second element region 101b. The second source electrode 12b is provided on the interlayer insulating layer 20. The second source electrode 12b is physically and electrically isolated from the first source electrode 12a.

[0090] The second source electrode 12b is in contact with the silicon carbide layer 10. The second source electrode 12b is in contact with the second source region 35b. The second source electrode 12b is in contact with the second JFET region 33b.

[0091] The contact between the second source electrode 12b and the second source region 35b is, for example, ohmic contact. The contact between the second source electrode 12b and the second JFET region 33b is, for example, Schottky contact.

[0092] The intermediate region 102 comprises a silicon carbide layer 10 and a field insulating layer 22.

[0093] The silicon carbide layer 10 in the intermediate region 102 is n + The back surface region 30 of the n-shape (first silicon carbide region), the drift region 31 of the n-shape (second silicon carbide region), the first pillar region 32a of the p-shape (third silicon carbide region), the second pillar region 32b of the p-shape (seventh silicon carbide region), n - It includes the surface region 36 of the shape (the 11th silicon carbide region).

[0094] In the intermediate region 102, the multiple first pillar regions 32a are repeatedly arranged in the second direction with the drift region 31 in between, similar to the first element region 101a. The multiple first pillar regions 32a are repeatedly arranged in the second direction with a first period (P1 in Figure 4).

[0095] In the intermediate region 102, the multiple second pillar regions 32b are repeatedly arranged in the second direction with the drift region 31 in between, similar to the second element region 101b. The multiple second pillar regions 32b are repeatedly arranged in the second direction with the first period (P1 in Figure 4).

[0096] As shown in Figure 4, in the intermediate region 102, the arrangement of the multiple second pillar regions 32b in the second direction is shifted by half a period of the first period P1 relative to the arrangement of the multiple first pillar regions 32a in the second direction.

[0097] In the intermediate region 102, as shown in Figure 4, the shortest distance (d1 in Figure 4) between the first pillar region 32a and the second pillar region 32b in a cross section parallel to the first plane F1 is, for example, less than or equal to the first period P1.

[0098] n - The surface region 36 of the shape is provided between the first pillar region 32a and the first surface F1. The surface region 36 is provided between the second pillar region 32b and the first surface F1.

[0099] The provision of the surface region 36 separates the first pillar region 32a from the first surface F1. Furthermore, the provision of the surface region 36 separates the second pillar region 32b from the first surface F1.

[0100] The surface region 36 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in the surface region 36 is lower than, for example, the n-type impurity concentration in the drift region 31. The n-type impurity concentration in the surface region 36 is lower than, for example, the n-type impurity concentration in the first JFET region 33a and the n-type impurity concentration in the second JFET region 33b. The n-type impurity concentration in the surface region 36 is, for example, 1 × 10⁻⁶ 15 cm -3 The above 1 x 10 18 cm -3 The following applies:

[0101] The field insulating layer 22 is provided on the first surface F1 of the silicon carbide layer 10. The field insulating layer 22 is in contact with the surface region 36. The field insulating layer 22 is, for example, silicon oxide.

[0102] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0103] The intermediate region 102 reduces the intensity of the electric field applied between the first element region 101a and the second element region 101b. By reducing the intensity of the electric field, the dielectric breakdown voltage of the bidirectional switching device is improved. From the viewpoint of reducing the area occupied by the intermediate region 102 within the chip and realizing miniaturization of the bidirectional switching device, it is desirable to shorten the length of the intermediate region 102 in the first direction.

[0104] In the bidirectional switching device 100 of the first embodiment, an SJ structure is formed in the intermediate region 102, extending from both the first element region 101a and the second element region 101b. By providing the SJ structure, the electric field strength in the intermediate region 102 is effectively reduced compared to when the SJ structure is not provided. Therefore, the length of the intermediate region 102 in the first direction can be shortened.

[0105] Furthermore, in the bidirectional switching device 100 of the first embodiment, the arrangement of the plurality of second pillar regions 32b in the second direction in the intermediate region 102 is shifted by half a period of the first period P1 relative to the arrangement of the plurality of first pillar regions 32a in the second direction. In other words, the SJ structure extending from the first element region 101a and the SJ structure extending from the second element region 101b are provided with a half-period shift in the second direction. This arrangement further effectively mitigates the electric field strength in the intermediate region 102. Therefore, the length of the intermediate region 102 in the first direction can be shortened compared to the case where the SJ structure is not shifted by half a period.

[0106] In the first embodiment of the bidirectional switching device 100, the first pillar region 32a and the first surface F1 are separated by the provision of the surface region 36. Furthermore, the second pillar region 32b and the first surface F1 are separated by the provision of the surface region 36.

[0107] If a pn junction is provided on the surface of the silicon carbide layer 10 in the intermediate region 102, when an electric field is applied between the first element region 101a and the second element region 101b, the electric field distribution generated at the pn junction directly beneath the field insulating layer 22 may cause, for example, holes to be injected into the field insulating layer 22 or mobile ions to move within the field insulating layer 22. In this case, for example, a region with a locally high electric field strength may be created, which may reduce the dielectric breakdown voltage of the bidirectional switching device.

[0108] As described above, the influence of the pn junction directly beneath the field insulating layer 22 becomes particularly apparent in devices using silicon carbide to which a high electric field is applied.

[0109] In the bidirectional switching device 100 of the first embodiment, the first pillar region 32a and the first surface F1 are separated by the provision of the surface region 36. Furthermore, the second pillar region 32b and the first surface F1 are separated by the provision of the surface region 36. Therefore, the pn junction of the SJ structure is not in contact directly beneath the field insulating layer 22 of the intermediate region 102. Thus, the decrease in dielectric breakdown voltage is suppressed.

[0110] From the viewpoint of improving the dielectric breakdown voltage of the bidirectional switching device 100, it is preferable that the n-type impurity concentration in the surface region 36 be low, especially in devices using silicon carbide to which a particularly high electric field is applied. From the viewpoint of improving the dielectric breakdown voltage of the bidirectional switching device 100, it is preferable that the n-type impurity concentration in the surface region 36 be lower than the n-type impurity concentration in the drift region 31. Furthermore, from the viewpoint of improving the dielectric breakdown voltage of the bidirectional switching device 100, it is preferable that the n-type impurity concentration in the surface region 36 be lower than the n-type impurity concentration in the first JFET region 33a and the n-type impurity concentration in the second JFET region 33b.

[0111] From the viewpoint of shortening the length of the intermediate region 102 of the bidirectional switching device 100 in the first direction, it is preferable that in the intermediate region 102, in a cross section parallel to the first plane F1, the shortest distance (d1 in Figure 4) between the first pillar region 32a and the second pillar region 32b is less than or equal to the first period P1.

[0112] (modified version) A modified semiconductor device of the first embodiment differs from the semiconductor device of the first embodiment in that the silicon carbide layer in the intermediate region further includes a twelfth silicon carbide region of second conductivity type within the second silicon carbide region, which is separated from the third silicon carbide region and the seventh silicon carbide region in a first direction, extends in a second direction, and is provided between the third silicon carbide region and the seventh silicon carbide region.

[0113] Figure 6 is a schematic cross-sectional view of a modified semiconductor device of the first embodiment. Figure 6 is the DD' section of Figure 7. Figure 7 is a schematic cross-sectional view of a modified semiconductor device of the first embodiment. Figure 7 is the EE' section of Figure 6.

[0114] Figure 6 corresponds to Figure 3 of the first embodiment. Figure 7 corresponds to Figure 4 of the first embodiment.

[0115] A semiconductor device of the first embodiment is a bidirectional switching device 110.

[0116] In the bidirectional switching device 110, the silicon carbide layer 10 in the intermediate region 102 includes a p-type separation region 37 (12th silicon carbide region).

[0117] The separation region 37 is located within the drift region 31. The separation region 37 is separated from the first pillar region 32a and the second pillar region 32b in a first direction. The separation region 37 extends in a second direction. The separation region 37 is located between the first pillar region 32a and the second pillar region 32b.

[0118] The separation region 37 is provided between the surface region 36 and the second surface F2. The separation region 37 is separated from the first surface F1.

[0119] The separation region 37 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the separation region 37 is, for example, 5 × 10⁻⁶. 16 cm -3 The above 5 x 10 18 cm -3 The following applies:

[0120] For example, two separation regions 37 are provided. The separation regions 37 may also consist of one, three or more, for example.

[0121] According to the bidirectional switching device 110, a modified version of the first embodiment, the presence of the isolation region 37 further effectively reduces the electric field intensity in the intermediate region 102. Therefore, the length of the intermediate region 102 in the first direction can be further shortened.

[0122] As described above, according to the first embodiment and its modifications, the length of the intermediate region 102 in the first direction can be shortened, and a miniaturized semiconductor device can be realized.

[0123] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that, in the intermediate region, the position of the first end in the first direction on the side of the second element region of the third silicon carbide region is closer to the second element region than the position of the second end in the first direction on the side of the first element region of the seventh silicon carbide region. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0124] Figure 8 is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 8 corresponds to Figure 4 of the first embodiment.

[0125] The semiconductor device of the second embodiment is a bidirectional switching device 200.

[0126] In the bidirectional switching device 200, in the intermediate region 102, the position of the first end (E1 in Figure 8) of the first pillar region 32a in the first direction on the side of the second element region 101b is closer to the second element region 101b than the position of the second end (E2 in Figure 8) of the second pillar region 32b in the first direction on the side of the first element region 101a.

[0127] In the intermediate region 102, a second pillar region 32b is provided in the second direction of the first pillar region 32a. The positions of the first pillar region 32a and the second pillar region 32b overlap in the first direction.

[0128] The width of the first pillar region 32a in the second direction decreases, for example, toward the first end E1. For example, the width of the second pillar region 32b in the second direction decreases toward the second end E2.

[0129] According to the bidirectional switching device 200 of the second embodiment, the positions of the first pillar region 32a and the second pillar region 32b overlap in the first direction, thereby further shortening the length of the intermediate region 102 in the first direction.

[0130] (modified version) The semiconductor device of the modified second embodiment differs from the semiconductor device of the second embodiment in that the silicon carbide layer in the intermediate region further includes a 13th silicon carbide region, which is provided between the third silicon carbide region and the seventh silicon carbide region in the second direction, and has a lower concentration of the first conductivity type impurity than the first conductivity type impurity concentration in the second silicon carbide region.

[0131] Figure 9 is a schematic cross-sectional view of a semiconductor device of a modified example of the second embodiment. Figure 9 is the FF' cross-section of Figure 10. Figure 10 is a schematic cross-sectional view of a semiconductor device of a modified example of the second embodiment. Figure 10 is the GG' cross-section of Figure 9.

[0132] Figure 9 is a diagram corresponding to Figure 8 of the second embodiment.

[0133] A modified semiconductor device of the second embodiment is a bidirectional switching device 210.

[0134] In the bidirectional switching device 210, the silicon carbide layer 10 is n - It includes a low-concentration region 38 (the 13th silicon carbide region) of the shape.

[0135] The low-concentration region 38 is provided between the first pillar region 32a and the second pillar region 32b in the second direction. For example, the first end E1 (E1 in Figure 9) of the first pillar region 32a on the side of the second element region 101b in the first direction, and the second end (E2 in Figure 9) of the second pillar region 32b on the side of the first element region 101a in the first direction, are provided within the low-concentration region 38.

[0136] The low-concentration region 38 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in the low-concentration region 38 is lower than the n-type impurity concentration in the drift region 31. The n-type impurity concentration in the low-concentration region 38 is, for example, 1 × 10⁻⁶ 15 cm -3 The above 5 x 10 17 cm -3 The following applies:

[0137] According to the bidirectional switching device 210, a modified version of the second embodiment, the presence of a low-concentration region 38 effectively reduces the electric field strength in the intermediate region 102. Therefore, the length of the intermediate region 102 in the first direction can be further shortened.

[0138] As described above, according to the second embodiment and its modifications, the length of the intermediate region 102 in the first direction can be shortened, and a miniaturized semiconductor device can be realized.

[0139] In the first and second embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type was described as an example, but it is also possible to have the first conductivity type be p-type and the second conductivity type be n-type.

[0140] In the first and second embodiments, aluminum (Al) was exemplified as a p-type impurity, but boron (B) can also be used. Similarly, nitrogen (N) and phosphorus (P) were exemplified as n-type impurities, but arsenic (As), antimony (Sb), etc., can also be applied.

[0141] In the first and second embodiments, the example described was a case where the gate electrode has a stripe shape extending in a second direction within the element region. However, it is also possible to have a structure in which, for example, the gate electrode has a stripe shape extending in a first direction. Furthermore, it is also possible to have a structure in which the gate electrode has a mesh shape.

[0142] In the first and second embodiments, the case where the widths of the p-type pillar region and the n-type drift region in the second direction are the same was described as an example, but the widths of the p-type pillar region and the n-type drift region in the second direction may be different.

[0143] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0144] 10 Semiconductor layer 12a First source electrode (first electrode) 12b Second source electrode (second electrode) 16a First gate insulating layer 16b Second gate insulating layer 18a First gate electrode 18b Second gate electrode 30 n + The back surface region of the shape (the first silicon carbide region) 31 n-type drift region (second silicon carbide region) 32a p-type first pillar region (third silicon carbide region) 32b p-type second pillar region (seventh silicon carbide region) 33a n-type first JFET region (fourth silicon carbide region) 33b n-type second JFET region (eighth silicon carbide region) 34a p-type first base region (fifth silicon carbide region) 34b p-type second base region (ninth silicon carbide region) 35a n + The first source region of the type (the sixth silicon carbide region) 35b n + The second source region of the type (the tenth silicon carbide region) 36 n - Surface region of the shape (11th silicon carbide region) 37 p-type separation region (12th silicon carbide region) 38 n - Low concentration region of the shape (13th silicon carbide region) 100 Bidirectional switching devices (semiconductor devices) 101a First element region 101b Second element region 102 Intermediate area 200 Bidirectional switching devices (semiconductor devices) d1 shortest distance E1 First end E2 Second end F1 First Side F2 Second side P1 period

Claims

1. The first element region and The second element region, An intermediate region provided between the first element region and the second element region, Equipped with, The first element region is, A silicon carbide layer having a first surface and a second surface facing the first surface, A first silicon carbide region of the first conductive type in contact with the second surface, A second silicon carbide region having a first conductivity type, provided between the first silicon carbide region and the first surface, wherein the concentration of the first conductivity type impurity is lower than the concentration of the first conductivity type impurity in the first silicon carbide region, A plurality of third silicon carbide regions of a second conductivity type are provided between the first silicon carbide region and the first surface, extending in a first direction parallel to the first surface, and repeatedly arranged in a first period in a second direction parallel to the first surface and perpendicular to the first direction, with the second silicon carbide region in between. A fourth silicon carbide region of first conductivity type is provided between the second silicon carbide region and the first surface, and is in contact with the second silicon carbide region. A fifth silicon carbide region of a second conductivity type is provided between the third silicon carbide region and the first surface, and is in contact with the third silicon carbide region. A sixth silicon carbide region of the first conductivity type is provided between the third silicon carbide region and the first surface, A silicon carbide layer containing, A first gate electrode facing the fourth silicon carbide region and the fifth silicon carbide region, A first gate insulating layer is provided between the first gate electrode and the fourth silicon carbide region and between the first gate electrode and the fifth silicon carbide region, A first electrode is provided on the side of the first surface of the silicon carbide layer, is in contact with the fourth silicon carbide region and the sixth silicon carbide region, and is electrically connected to the fifth silicon carbide region. Includes, The aforementioned second element region is The first silicon carbide region and, The second silicon carbide region and, A plurality of seventh silicon carbide regions of second conductivity are provided between the first silicon carbide region and the first surface, extending in the first direction and repeatedly arranged in the second direction with the second silicon carbide region in between in the first period, An eighth silicon carbide region of first conductivity type is provided between the second silicon carbide region and the first surface, and is in contact with the second silicon carbide region, A ninth silicon carbide region of second conductivity is provided between the seventh silicon carbide region and the first surface, and is in contact with the seventh silicon carbide region. A 10th silicon carbide region of the first conductivity type is provided between the 9th silicon carbide region and the first surface, The silicon carbide layer containing, A second gate electrode facing the eighth silicon carbide region and the ninth silicon carbide region, A second gate insulating layer is provided between the second gate electrode and the eighth silicon carbide region and between the second gate electrode and the ninth silicon carbide region, A second electrode is provided on the side of the first surface of the silicon carbide layer, is in contact with the eighth silicon carbide region and the tenth silicon carbide region, is electrically connected to the ninth silicon carbide region, and is electrically separated from the first electrode. Includes, The aforementioned intermediate region is The first silicon carbide region and, The second silicon carbide region and, The third silicon carbide region and, The seventh silicon carbide region and, A first conductive eleventh silicon carbide region is provided between the third silicon carbide region and the first surface, and between the seventh silicon carbide region and the first surface, The silicon carbide layer includes the above, A semiconductor device wherein, in the intermediate region, the arrangement of the seventh silicon carbide region in the second direction is shifted by half a period of the first period with respect to the arrangement of the third silicon carbide region in the second direction.

2. The semiconductor device according to claim 1, wherein the concentration of the first conductive type impurity in the eleventh silicon carbide region is lower than the concentration of the first conductive type impurity in the second silicon carbide region.

3. The semiconductor device according to claim 1, wherein the concentration of the first conductive type impurity in the 11th silicon carbide region is lower than the concentration of the first conductive type impurity in the 4th silicon carbide region and the concentration of the first conductive type impurity in the 8th silicon carbide region.

4. The semiconductor device according to claim 1, wherein in the intermediate region, in a cross-section parallel to the first plane, the shortest distance between the third silicon carbide region and the seventh silicon carbide region is less than or equal to the first period.

5. The semiconductor device according to claim 1, wherein the silicon carbide layer in the intermediate region further includes, within the second silicon carbide region, a twelfth silicon carbide region of a second conductivity type that is separated from the third silicon carbide region and the seventh silicon carbide region in the first direction, extends in the second direction, and is provided between the third silicon carbide region and the seventh silicon carbide region.

6. The semiconductor device according to claim 5, wherein the twelfth silicon carbide region is separated from the first surface.

7. The semiconductor device according to claim 1, wherein in the intermediate region, the position of the first end of the third silicon carbide region in the first direction on the second element region side is closer to the second element region than the position of the second end of the seventh silicon carbide region in the first direction on the first element region side.

8. The semiconductor device according to claim 7, wherein the width of the third silicon carbide region in the second direction decreases toward the first end, and the width of the seventh silicon carbide region in the second direction decreases toward the second end.

9. The semiconductor device according to claim 7, wherein the silicon carbide layer in the intermediate region further includes a thirteenth silicon carbide region provided between the third silicon carbide region and the seventh silicon carbide region in the second direction, and having a first conductivity type impurity concentration lower than that of the second silicon carbide region.

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