Semiconductor wafer, semiconductor device, and method for manufacturing semiconductor wafers

Abstract

Improve recovery characteristics. [Solution] The semiconductor wafer WF comprises a silicon carbide substrate 1, an epitaxial layer 20 formed on the silicon carbide substrate 1 having a lower impurity concentration than the silicon carbide substrate 1, and a lifetime control layer 10 formed within the silicon carbide substrate 1, the lifetime control layer 10 being formed at a position away from the interface between the silicon carbide substrate 1 and the epitaxial layer 20.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor wafer, a semiconductor device, and a method for manufacturing a semiconductor wafer, using silicon carbide as a semiconductor material. [Background technology]

[0002] Japanese Patent Publication No. 2019-102493 (Patent Document 1) describes generating point defects in a silicon carbide semiconductor wafer on which a device is formed by injecting hydrogen from above the device, targeting the area near the interface between the silicon carbide substrate and the epitaxial layer. Furthermore, Patent Document 1 describes that the recovery characteristics can be improved by reducing the hole lifetime due to the generated point defects.

[0003] International Publication No. 2023 / 100454 (Patent Document 2) describes forming point defects by injecting hydrogen near the interface between the silicon carbide substrate and the epitaxial layer after forming an epitaxial layer on the silicon carbide substrate. Subsequently, Patent Document 2 describes improving the recovery characteristics without degrading the static characteristics of the device by performing annealing to recover the point defects to some extent. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2019-102493 [Patent Document 2] International Publication No. 2023 / 100454 [Overview of the project] [Problems that the invention aims to solve]

[0005] To achieve carbon neutrality, energy conservation in power electronics equipment is crucial. Currently, silicon (Si) is widely used as the semiconductor material for power devices, which are key to energy conservation.

[0006] For example, when using silicon-based power devices as switching elements in power converters such as inverters, IGBTs (Insulated Gate Bipolar Transistors) are used. In power converters, it is necessary to connect a freewheeling diode (recirculating diode) in antiparallel to the switching element. In this regard, since IGBTs do not have a body diode, an external Schottky diode that functions as a freewheeling diode is provided in antiparallel to the IGBT.

[0007] In recent years, development of power devices using silicon carbide (SiC), a wide-bandgap semiconductor material, has been progressing in order to further reduce energy consumption. For example, when using silicon carbide as a switching element in a power device, the use of SiC MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) is being considered. A parasitic body diode is formed in SiC MOSFETs. Therefore, since the body diode can be used as a freewheeling diode in SiC MOSFETs, an external diode is unnecessary. As a result, using SiC MOSFETs as switching elements makes it possible to realize low-cost and compact semiconductor devices.

[0008] However, the parasitic body diode present in the SiC MOSFET is a pn junction diode. Since a pn junction diode is a bipolar device, recovery losses occur due to recovery current. Therefore, reducing these recovery losses is desirable. In other words, improving the recovery characteristics is desirable. [Means for solving the problem]

[0009] A semiconductor wafer according to an embodiment includes a silicon carbide substrate, an epitaxial layer formed on the silicon carbide substrate and having an impurity concentration lower than that of the silicon carbide substrate, and a lifetime control layer formed in the silicon carbide substrate and located at a position away from the interface between the silicon carbide substrate and the epitaxial layer.

[0010] A semiconductor wafer according to an embodiment includes a silicon carbide substrate, an epitaxial layer formed on the silicon carbide substrate and having an impurity concentration lower than that of the silicon carbide substrate, and a lifetime control layer formed in the silicon carbide substrate and including point defects that function as recombination centers for electrons and holes. The full width at half maximum of the density profile of the point defects in the thickness direction of the semiconductor wafer is less than 3 μm.

[0011] A method for manufacturing a semiconductor wafer according to an embodiment includes: (a) a step of preparing a silicon carbide substrate; (b) a step of forming a lifetime control layer in the silicon carbide substrate; and (c) a step of forming an epitaxial layer on the silicon carbide substrate after the step (b) described above.

[0012] A semiconductor device according to an embodiment includes a SiC MOSFET, a drain electrode, a silicon carbide substrate of a first conductivity type located on the drain electrode, a first conductivity type epitaxial layer formed on the silicon carbide substrate and having an impurity concentration lower than that of the silicon carbide substrate, a lifetime control layer formed in the silicon carbide substrate and located at a position away from the interface between the silicon carbide substrate and the epitaxial layer, a well of a second conductivity type formed in the epitaxial layer, a source region of the first conductivity type formed in the well, a gate insulating film formed on the epitaxial layer, a gate electrode formed on the gate insulating film, and a source electrode electrically connected to the source region.

[0013] A semiconductor device according to an embodiment includes a SiC MOSFET, a drain electrode, a silicon carbide substrate of a first conductivity type located on the drain electrode, an epitaxial layer of the first conductivity type formed on the silicon carbide substrate and having an impurity concentration lower than that of the silicon carbide substrate, a lifetime control layer formed in the silicon carbide substrate and including point defects functioning as recombination centers of electrons and holes, a well of a second conductivity type formed in the epitaxial layer, a source region of the first conductivity type formed in the well, a gate insulating film formed on the epitaxial layer, a gate electrode formed on the gate insulating film, and a source electrode electrically connected to the source region. The full width at half maximum of the density profile of point defects in the thickness direction of the semiconductor device is less than 3 μm.

[0014] A semiconductor device according to an embodiment includes a SiC pn junction diode, a first electrode, a silicon carbide substrate of a first conductivity type located on the first electrode, an epitaxial layer of the first conductivity type formed on the silicon carbide substrate and having an impurity concentration lower than that of the silicon carbide substrate, a lifetime control layer formed in the silicon carbide substrate and located at a position away from the interface between the silicon carbide substrate and the epitaxial layer, a semiconductor region of a second conductivity type formed in the epitaxial layer, and a second electrode electrically connected to the semiconductor region.

[0015] A semiconductor device according to an embodiment includes a SiC pn junction diode, a first electrode, a silicon carbide substrate of a first conductivity type located on the first electrode, an epitaxial layer of the first conductivity type formed on the silicon carbide substrate and having an impurity concentration lower than that of the silicon carbide substrate, a lifetime control layer formed in the silicon carbide substrate and including point defects functioning as recombination centers of electrons and holes, a semiconductor region of a second conductivity type formed in the epitaxial layer, and a second electrode electrically connected to the semiconductor region. The full width at half maximum of the density profile of point defects in the thickness direction of the semiconductor device is less than 3 μm.

Advantages of the Invention

[0016] According to one embodiment, recovery characteristics can be improved. [Brief explanation of the drawing]

[0017] [Figure 1] This is a cross-sectional view showing a semiconductor wafer in Embodiment 1. [Figure 2] This figure shows the density profile of point defects. [Figure 3] This is a diagram showing the lifetime. [Figure 4] This graph shows the relationship between the full width at half maximum and the reduction rate of recovery loss in the concentration profile of point defects. [Figure 5] This figure shows the semiconductor wafer manufacturing process in Embodiment 1. [Figure 6] This figure shows the semiconductor wafer manufacturing process, following Figure 5. [Figure 7] This figure shows the semiconductor wafer manufacturing process, following Figure 6. [Figure 8] This is a cross-sectional view showing a semiconductor device in Embodiment 2. [Figure 9] This figure shows the manufacturing process of a semiconductor device in Embodiment 2. [Figure 10] This is a cross-sectional view showing a semiconductor device in Embodiment 3. [Figure 11] This is a cross-sectional view showing the semiconductor device in Embodiment 4. [Modes for carrying out the invention]

[0018] In all the drawings illustrating the embodiments, the same reference numeral is used for identical components, and repeated explanations of them are omitted. Hatching may be used even in plan views to improve clarity.

[0019] <Consideration of improvements> For example, as a technology to improve recovery characteristics, there are Patent Documents 1 and 2, which are listed in the background technology section.

[0020] However, in the technology described in Patent Document 1, hydrogen is injected into the gate insulating film and epitaxial layer of the device, resulting in degradation of the gate insulating film and crystal degradation of the epitaxial layer. As a result, the static properties of the device may deteriorate in the technology described in Patent Document 1. Specifically, deterioration of the static properties of the device means an increase in on-resistance. Furthermore, since silicon carbide has poorer crystal quality than silicon, if crystal degradation occurs due to hydrogen injection, a synergistic increase in on-resistance may occur.

[0021] In the technology described in Patent Document 2, hydrogen is injected through the epitaxial layer, targeting the interface between the silicon carbide substrate and the epitaxial layer. As a result, a certain amount of point defects remain within the epitaxial layer. Also, the peak concentration of point defects is reduced. If the amount of hydrogen injected is increased to increase the peak concentration of point defects, the number of point defects remaining in the epitaxial layer increases, thus degrading the static characteristics of the device.

[0022] Based on the above, Patent Documents 1 and 2 have room for improvement in terms of improving recovery characteristics without degrading the static characteristics of the device. Therefore, the embodiment incorporates measures to overcome the aforementioned areas for improvement. The technical concept of the embodiment incorporating these measures will be explained below.

[0023] <Embodiment 1> <<Semiconductor Wafer Configuration>> Figure 1 is a cross-sectional view showing a semiconductor wafer (WF) in Embodiment 1.

[0024] In Figure 1, the semiconductor wafer WF has a silicon carbide substrate 1, a lifetime control layer 10, and an epitaxial layer 20. The silicon carbide substrate 1 contains, for example, nitrogen (N), which is an n-type impurity. That is, in Embodiment 1, the silicon carbide substrate 1 is an n-type silicon carbide substrate. However, the technical concept of this disclosure is not limited to this, and can also be applied to semiconductor devices using a p-type silicon carbide substrate 1. In other words, the technical concept of this disclosure can be broadly applied to semiconductor devices with opposite conductivity types. In this regard, this specification will describe the invention assuming that the silicon carbide substrate 1 is an n-type silicon carbide substrate.

[0025] The nitrogen concentration introduced into the silicon carbide substrate 1 is 1 × 10⁻⁶. 18 / cm 3 The thickness of the silicon carbide substrate 1 is, for example, between 50 μm and 500 μm. A typical example of the thickness of the silicon carbide substrate 1 is about 150 μm.

[0026] The epitaxial layer 20 is formed on the silicon carbide substrate 1. The epitaxial layer 20 is a layer using silicon carbide as a semiconductor material. In Embodiment 1, the epitaxial layer 20 is an n-type semiconductor layer into which n-type impurities such as nitrogen have been introduced.

[0027] The epitaxial layer 20 has a lower impurity concentration than the silicon carbide substrate 1. The impurity concentration of the epitaxial layer 20 is, for example, 1 × 10⁻⁶ 14 / cm 3 The above 1 x 10 17 / cm 3 The following is a typical example of the impurity concentration in the epitaxial layer 20: 3 × 10⁻⁶ 15 / cm 3 The thickness of the epitaxial layer 20 is, for example, between 10 μm and 150 μm. A typical example of the epitaxial layer 20 thickness is about 30 μm. The epitaxial layer 20 determines the breakdown voltage of the semiconductor device in the off state. A typical specification for a semiconductor device is a breakdown voltage of 3.3 kV.

[0028] The epitaxial layer 20 is composed of, for example, a buffer layer 2 and a drift layer 3. The buffer layer 2 is formed on the silicon carbide substrate 1. The drift layer 3 is formed on the buffer layer 2. The drift layer 3 has a lower impurity concentration than the buffer layer 2.

[0029] The lifetime control layer 10 is formed within the silicon carbide substrate 1. The lifetime control layer 10 is formed at a location away from the interface between the silicon carbide substrate 1 and the epitaxial layer 20. This allows for the formation of a lifetime control layer 10 within the silicon carbide substrate 1 to shorten the carrier lifetime, while suppressing an increase in the point defect density within the epitaxial layer 20. This is because, as will be described later, the lifetime control layer 10 is a layer that forms many point defects that function as recombination centers for electrons and holes, and by forming this lifetime control layer 10 at a location away from the interface between the silicon carbide substrate 1 and the epitaxial layer 20, the formation of many point defects within the epitaxial layer 20 can be suppressed.

[0030] The lifetime control layer 10 contains point defects that function as electron-hole recombination centers.

[0031] Figure 2 shows the density profile of point defects.

[0032] Figure 3 shows the lifetime.

[0033] In Figures 2 and 3, the area between A and B represents the drift layer 3. The area between B and C represents the buffer layer 2. The area between A and C represents the epitaxial layer 20. The area between C and F represents the silicon carbide substrate 1. The area between D and E represents the lifetime control layer 10. C represents the interface between the epitaxial layer 20 and the silicon carbide substrate 1.

[0034] As shown in Figure 2, the concentration peak of point defects is located within the lifetime control layer 10. In this specification, the lifetime control layer 10 is defined as a region that includes the range from the concentration peak of point defects to half the concentration of the concentration peak.

[0035] The lifetime control layer 10 contains point defects that function as electron-hole recombination centers. The epitaxial layer 20 contains point defects that function as electron-hole recombination centers at a background density. In Embodiment 1, the point defect density in the lifetime control layer 10 is 10 times or more that of the point defect density in the epitaxial layer 20.

[0036] Therefore, as shown in Figure 3, the lifetime of carriers within the lifetime control layer 10 is shortened. As a result, the semiconductor device manufactured using the semiconductor wafer of Embodiment 1 can improve recovery characteristics. This is because a shorter carrier lifetime means that the number of carriers that become recovery current is reduced, thereby reducing the recovery loss caused by the recovery current.

[0037] On the other hand, in the semiconductor wafer WF of Embodiment 1, the density of point defects in the epitaxial layer 20 is low. That is, in the epitaxial layer 20, which greatly affects the on-resistance of the semiconductor device, the density of point defects that cause an increase in on-resistance is low. Therefore, with a semiconductor device manufactured using the semiconductor wafer of Embodiment 1, the increase in on-resistance can be suppressed. In other words, according to Embodiment 1, the deterioration of static characteristics can be suppressed.

[0038] From the above, it can be concluded that a semiconductor device manufactured using the semiconductor wafer of Embodiment 1 can improve recovery characteristics without degrading the static characteristics of the device.

[0039] As shown in Figure 2, the lifetime control layer 10 is formed, for example, at a position 500 nm or more deeper than the interface between the silicon carbide substrate 1 and the epitaxial layer 20. This allows for a concentration peak of point defects to be located within the silicon carbide substrate 1 while reducing the density of point defects within the epitaxial layer 20. In a semiconductor wafer WF configured in this way, the full width at half maximum of the point defect density profile in the thickness direction of the semiconductor wafer WF is less than 3 μm.

[0040] According to this, according to Embodiment 1, the effect of improving the recovery characteristics can be increased significantly.

[0041] This point will be described below.

[0042] FIG. 4 is a graph showing the relationship between the full width at half maximum in the concentration profile of point defects and the reduction rate of recovery loss. As shown in FIG. 4, when the full width at half maximum is less than 3 μm, the reduction rate of recovery loss increases significantly. On the other hand, when the full width at half maximum is 3 μm or more, the effect of reducing the recovery loss is small. That is, from the graph shown in FIG. 4, it can be seen that the reduction effect of recovery loss changes significantly with the value at which the full width at half maximum becomes 3 μm as a boundary value. That is, from the graph shown in FIG. 4, it can be seen that the value at which the full width at half maximum becomes 3 μm has critical significance.

[0043] <<Method for manufacturing a semiconductor wafer>> Next, the method for manufacturing the semiconductor wafer WF in Embodiment 1 will be described.

[0044] First, as shown in FIG. 5, a silicon carbide substrate 1 is prepared. The silicon carbide substrate 1 is, for example, an n-type 4H-SiC substrate. The silicon carbide substrate 1 is doped with n-type impurities. The n-type impurities are, for example, nitrogen. The impurity concentration of nitrogen is, for example, 1×10 18 / cm 3 or more and 1×10 21 / cm 3 or less. The silicon carbide substrate 1 has a silicon surface (Si surface) and a carbon surface (C surface), and the upper surface of the silicon carbide substrate 1 may be either the silicon surface or the carbon surface.

[0045] Next, as shown in FIG. 6, a lifetime control layer 10 is formed in the silicon carbide substrate 1. Specifically, the lifetime control layer 10 is formed by injecting ions into the silicon carbide substrate 1 by using the ion implantation method. The ions are, for example, hydrogen (protons) or helium. When hydrogen is used, the dose amount of hydrogen is 1×10 12 / cm 2 or more and 1×10 15 / cm2 The following is the case: When hydrogen or helium is injected into the silicon carbide substrate 1, numerous point defects that function as electron-hole recombination centers are formed within the silicon carbide substrate 1. The layer in which these numerous point defects are formed is the lifetime control layer 10.

[0046] In Embodiment 1, since ions are directly implanted into the silicon carbide substrate 1, the full width at half maximum of the density profile of point defects formed by ion implantation can be controlled to less than 3 μm. Furthermore, in Embodiment 1, by adjusting the ion implantation energy, the lifetime control layer 10 is formed, for example, at a position 500 nm or more deeper than the upper surface of the silicon carbide substrate 1.

[0047] In Embodiment 1, an example is shown in which ions are implanted over the entire upper surface of the silicon carbide substrate 1. However, the technical concept of this disclosure is not limited to this, and for example, a mask may be formed on the silicon carbide substrate 1, and then ions may be implanted through the mask to partially form the lifetime control layer 10.

[0048] Next, as shown in Figure 7, an epitaxial layer 20 is formed on the silicon carbide substrate 1. The epitaxial layer 20 consists of, for example, a buffer layer 2 formed on the silicon carbide substrate 1 and a drift layer 3 formed on the buffer layer 2. The buffer layer 2 and the drift layer 3 can be formed, for example, by using an epitaxial growth method. Nitrogen, which is an n-type impurity, is introduced into each of the buffer layer 2 and the drift layer 3. The impurity concentration of nitrogen introduced into the drift layer 3 is lower than the impurity concentration of nitrogen introduced into the buffer layer 2. The impurity concentration of the drift layer 3 depends on the device rating. For example, the impurity concentration of the drift layer 3 is 1 × 10⁻⁶. 14 ( / cm 3 ) 1 x 10 17 ( / cm 3 The thickness of the drift layer 3 is, for example, approximately 10 μm to 150 μm.

[0049] As described above, the semiconductor wafer WF in Embodiment 1 can be manufactured.

[0050] A key feature of the manufacturing process in Embodiment 1 is the formation of a lifetime control layer 10 within the silicon carbide substrate 1 before forming the epitaxial layer 20 on the silicon carbide substrate 1. In particular, in Embodiment 1, the lifetime control layer 10 is formed within the silicon carbide substrate 1 by ion implanting hydrogen or helium into the silicon carbide substrate 1 before forming the epitaxial layer 20 on the silicon carbide substrate 1.

[0051] As a result, according to Embodiment 1, ions are not implanted into the silicon carbide substrate 1 via the epitaxial layer 20. That is, the implanted ions do not pass through the epitaxial layer 20. Therefore, the lifetime control layer 10 can be formed in the silicon carbide substrate 1 without damaging the epitaxial layer 20, which is the operating region of the semiconductor device. In other words, a large number of point defects can be generated in the silicon carbide substrate 1 without generating new point defects in the epitaxial layer 20. Therefore, the recovery characteristics can be improved without causing deterioration of the static characteristics of the semiconductor device due to point defects.

[0052] As described above, in Embodiment 1, point defects are formed in the silicon carbide substrate 1 by implanting ions such as hydrogen or helium into the silicon carbide substrate 1 without going through the epitaxial layer 20. Therefore, the total width at half maximum in the density profile of the point defects can be narrowed. Specifically, according to Embodiment 1, the total width at half maximum in the density profile of the point defects can be made to less than 3 μm. As a result, the recovery characteristics are greatly improved (see Figure 4).

[0053] <Embodiment 2> <<Configuration of semiconductor device>> Embodiment 2 describes an example of a semiconductor device manufactured using the semiconductor wafer WF in Embodiment 1. The semiconductor device 100 in Embodiment 2 is a semiconductor device that includes a SiC MOSFET.

[0054] Figure 8 is a cross-sectional view showing the semiconductor device 100.

[0055] In Figure 8, the semiconductor device 100 includes a silicon carbide substrate 1, a buffer layer 2, a drift layer 3, a drain electrode 4, p-type wells 5A and 5B, a source region 6A and 6B, a body contact region 7A and 7B, a gate insulating film 8, a gate electrode 9, a lifetime control layer 10, an interlayer insulating film 11, a source electrode 12, an epitaxial layer 20, a channel formation region CH1, and a channel formation region CH2.

[0056] The silicon carbide substrate 1 is 1 × 10 18 ( / cm 3 It contains approximately 50 μm to 500 μm of nitrogen. The thickness of the silicon carbide substrate 1 is approximately 50 μm to 500 μm. In a typical example, the thickness of the silicon carbide substrate 1 is approximately 150 μm.

[0057] The silicon carbide substrate 1 has an upper surface and a lower surface. A drain electrode 4 is formed on the lower surface of the silicon carbide substrate 1. On the other hand, a buffer layer 2 is formed on the upper surface of the silicon carbide substrate 1. A lifetime control layer 10 is formed within the silicon carbide substrate 1. The lifetime control layer 10 contains a number of point defects that function as electron-hole recombination centers.

[0058] A drift layer 3 is formed on buffer layer 2. The buffer layer 2 and drift layer 3 constitute the epitaxial layer 20. The epitaxial layer 20 is 1 × 10 14 ( / cm 3 ) 1 x 10 17 ( / cm 3 It contains nitrogen at a level below 250. The thickness of the epitaxial layer 20 is between 10 μm and 150 μm. In a typical example, the thickness of the epitaxial layer 20 is 30 μm. The epitaxial layer 20 determines the breakdown voltage of the SiC MOSFET in the off state. In a typical example, the breakdown voltage specification is 3.3 kV.

[0059] Within the epitaxial layer 20, p-type wells 5A and 5B are formed. For example, p-type impurities such as aluminum (Al) are introduced into p-type wells 5A and 5B. The depth of each p-type well 5A and p-type well 5B is approximately 1 μm. The impurity concentration in each p-type well 5A and p-type well 5B is, for example, 1 × 10⁻⁶ 18 ( / cm 3 It is about that level.

[0060] Within the p-type well 5A, a source region 6A and a body contact region 7A are formed. The source region 6A is an n-type semiconductor region. The depth of the source region 6A is approximately 0.4 μm. The impurity concentration in the source region 6A is 1 × 10⁻⁶. 20 ( / cm 3 ) is the extent of the impurity. On the other hand, the body contact region 7A is a p-type semiconductor region. The body contact region 7A has a higher impurity concentration than the p-type well 5A. The source region 6A and the body contact region 7A are formed to be in contact with each other.

[0061] Source region 6B is an n-type semiconductor region. The depth of source region 6B is approximately 0.4 μm. The impurity concentration in source region 6B is 1 × 10⁻⁶. 20 ( / cm 3 ) is of a certain degree. On the other hand, the body contact region 7B is a p-type semiconductor region. The body contact region 7B has a higher impurity concentration than the p-type well 5B. The source region 6B and the body contact region 7B are formed to be in contact with each other.

[0062] A gate insulating film 8 is formed on a portion of the source region 6B, on the channel formation region CH2, on a portion of the drift layer 3, on the channel formation region CH1, and on a portion of the source region 6A. The gate insulating film 8 is, for example, a film mainly composed of silicon oxide. The thickness of the gate insulating film 8 is, for example, about 50 nm. Nitrogen is introduced near the interface between the gate insulating film and the drift layer 3 to improve the interface properties.

[0063] A gate electrode 9 is formed on the gate insulating film 8. The gate electrode 9 is composed of, for example, a polysilicon film containing a high concentration of n-type impurities.

[0064] In the gate length direction of the gate electrode 9, a channel formation region CH1 is formed within the p-type well 5A between the end of the p-type well 5A and the source region 6A. The channel formation region CH1 is a p-type semiconductor region, but when a gate voltage greater than or equal to a threshold voltage is applied to the gate electrode 9, it inverts to an n-type semiconductor region and becomes a channel.

[0065] In the gate length direction of the gate electrode 9, a channel formation region CH2 is formed within the p-type well 5B between the end of the p-type well 5B and the source region 6B. The channel formation region CH2 is a p-type semiconductor region, but when a gate voltage of a threshold voltage or higher is applied to the gate electrode 9, it becomes a channel consisting of an inversion layer, which is an n-type semiconductor region.

[0066] An interlayer insulating film 11 is formed to cover the gate electrode 9. Source electrodes 12 are formed on the body contact region 7B, a portion of the source region 6B, the interlayer insulating film 11, a portion of the source region 6A, and the body contact region 7A. As a result, the source region 6A and the body contact region 7A are electrically connected via the source electrodes 12. Therefore, the same potential is supplied to the source region 6A and the body contact region 7A. The source region 6B and the body contact region 7B are electrically connected via the source electrodes 12. Therefore, the same potential is supplied to the source region 6B and the body contact region 7B.

[0067] The semiconductor device 100 is configured as described above.

[0068] Next, we will briefly explain the operation of a SiC MOSFET.

[0069] First, in Figure 8, when a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode 9, channels consisting of inversion layers are formed in the channel formation regions CH1 and CH2. As a result, electrons flow through the path source electrode 12 → source region 6A → channel formation region CH1 (inversion layer) → drift layer 3 → buffer layer 2 → silicon carbide substrate 1 → drain electrode 4. Similarly, electrons flow through the path source electrode 12 → source region 6B → channel formation region CH2 (inversion layer) → drift layer 3 → buffer layer 2 → silicon carbide substrate 1 → drain electrode 4. In this way, the SiC MOSFET turns on. In this state, when a gate voltage less than the threshold voltage is applied to the gate electrode 9, the channels consisting of inversion layers disappear and the flow of electrons is interrupted. As a result, the SiC MOSFET turns off. In this way, the SiC MOSFET operates.

[0070] For example, the semiconductor device 100 is used in an inverter device. The inverter device is used, for example, for motor drive control. In motor drive control, there is a mode in which a back electromotive force is generated due to the inductance contained in the motor. In this case, a positive potential is applied to the source electrode 12 of the SiC MOSFET constituting the semiconductor device 100, while a negative potential is applied to the drain electrode 4. As shown in Figure 8, a body diode BD consisting of a pn junction diode exists parasitically between the p-type well 5B (p-type semiconductor layer) and the drift layer 3 (n-type semiconductor layer) of the SiC MOSFET. Similarly, although not shown in the figure, a body diode consisting of a pn junction diode exists parasitically between the p-type well 5A (p-type semiconductor layer) and the drift layer 3 (n-type semiconductor layer).

[0071] Therefore, when a positive potential is applied to the source electrode 12 by the back electromotive force, a positive potential is applied to the anode (p-type well 5B) of the body diode via an electrically connected path from the source electrode 12 to the body contact region 7B and then to the p-type well 5B. Conversely, when a negative potential is applied to the drain electrode 4 by the back electromotive force, a negative potential is applied to the cathode (drift layer 3) of the body diode via an electrically connected path from the drain electrode 4 to the silicon carbide substrate 1, then to the buffer layer 2 and then to the drift layer 3. This means that the body diode BD is forward-biased. Therefore, when a back electromotive force is generated, a freewheeling current flows through the forward-biased body diode BD. In other words, the body diode BD functions as a freewheeling diode.

[0072] Subsequently, when the back electromotive force disappears, 0V is supplied to the source electrode 12, while a positive potential is supplied to the drain electrode 4. In this state, 0V is applied to the anode (p-type well 5B) of the body diode BD, while a positive potential is applied to the cathode (drift layer 3) of the body diode BD. This means that the body diode BD is reverse-biased. Therefore, electrons that were injected under forward bias are swept out toward the drain electrode 4. On the other hand, holes that were injected under forward bias are swept out toward the source electrode 12. This sweeping out of electrons and holes generates a recovery current. A large recovery current results in a large recovery loss.

[0073] In this regard, in Embodiment 2, a lifetime control layer 10 is formed within the silicon carbide substrate 1. The lifetime control layer 10 contains numerous point defects that function as electron-hole recombination centers. As a result, electron-hole recombination is promoted during carrier sweeping, reducing the recovery current. Therefore, recovery losses can be reduced. In other words, according to Embodiment 2, recovery characteristics can be improved. In particular, the full width at half maximum in the point defect density profile is narrow. Specifically, according to Embodiment 2, the full width at half maximum in the point defect density profile can be reduced to less than 3 μm. Therefore, the effect of improving recovery characteristics is significant.

[0074] The semiconductor device 100 in Embodiment 2 is manufactured using the semiconductor wafer WF in Embodiment 1. Therefore, the density of point defects in the epitaxial layer 20 is low (background level). In other words, the density of point defects that increase the on-resistance is low in the epitaxial layer 20, which greatly affects the on-resistance of the semiconductor device 100.

[0075] Therefore, according to the semiconductor device 100, the increase in on-resistance can be suppressed. In other words, according to Embodiment 2, the deterioration of the static characteristics of the semiconductor device 100 can be suppressed.

[0076] Based on the above, the semiconductor device 100 in Embodiment 2 can improve the recovery characteristics without degrading the static characteristics of the SiC MOSFET (device).

[0077] <<Manufacturing Method for Semiconductor Devices>> Next, the manufacturing method for the semiconductor device 100 in Embodiment 2 will be described.

[0078] First, prepare the semiconductor wafer WF manufactured in Embodiment 1.

[0079] Next, as shown in Figure 9, p-type wells 5A and 5B, source region 6A and 6B, body contact region 7A and 7B are formed within the drift layer 3, for example, by using photolithography and ion implantation. The thickness of the mask used in photolithography is, for example, about 0.5 μm to 5 μm. The mask material can be a silicon oxide film (hard mask) or a photoresist film.

[0080] Then, after removing the mask using ashing technology, a carbon film is formed on the upper surface of the epitaxial layer 20 and on the lower surface of the silicon carbide substrate 1, respectively. The carbon film can be formed, for example, by using plasma CVD (Chemical Vapor Deposition). The thickness of the carbon film is, for example, about 0.03 μm to 0.05 μm.

[0081] Next, the upper surface of the epitaxial layer 20 and the lower surface of the silicon carbide substrate 1 are covered with a carbon film, and then heat treatment is performed at a temperature of 1500 degrees Celsius or higher for 2 to 3 minutes. This activates the conductive impurities introduced into each layer (each region) within the epitaxial layer 20. After that, the carbon film is removed, for example, by plasma treatment.

[0082] Next, as shown in Figure 8, a gate insulating film 8 and an n-type polysilicon film are sequentially formed on the drift layer 3, and then a mask is formed on the n-type polysilicon film. The gate insulating film 8 can be formed, for example, using a thermal oxidation method. The n-type polysilicon film can be formed, for example, using a CVD method. Next, the n-type polysilicon film is processed by a dry etching method using the mask to form the gate electrode 9. The thickness of the gate insulating film 8 is, for example, about 0.05 μm to 0.15 μm. The thickness of the gate electrode 9 is, for example, about 0.2 μm to 0.5 μm.

[0083] Subsequently, an interlayer insulating film 11 is formed on the drift layer 3 so as to cover the gate electrode 9. The interlayer insulating film 11 can be formed, for example, by using a plasma CVD method.

[0084] Then, by using photolithography and dry etching techniques, a first through-hole and a second through-hole are formed in the interlayer insulating film 11. This exposes the source region 6A and the body contact region 7A from the bottom of the first through-hole, and exposes the source region 6B and the body contact region 7B from the bottom of the second through-hole.

[0085] Next, a silicide layer is formed at the bottom of the first through-hole and the bottom of the second through-hole. Then, a metal film is formed to fill the interior of the first through-hole and the interior of the second through-hole, for example, by sputtering. The metal film is composed of a laminated film made by sequentially stacking a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film. Then, a source electrode 12 made of the metal film is formed by using photolithography and etching techniques. The source electrode 12 is electrically connected to the source region 6A and the body contact region 7A. The source electrode 12 is electrically connected to the source region 6B and the body contact region 7B.

[0086] Next, for example, by using a sputtering method, a metal film is formed on the underside of the silicon carbide substrate 1. Then, a laser silicide treatment (heat treatment) is performed to react the metal film with the silicon carbide substrate 1 and form a silicide layer (not shown). After that, a drain electrode 4 is formed on the underside of the silicide layer. The drain electrode 4 can be formed, for example, by a sputtering method. The drain electrode 4 is composed of a laminated film in which a titanium film, a nickel film, and a gold film are stacked in that order from the silicide layer side. The thickness of the drain electrode 4 is, for example, about 0.5 μm to 1 μm.

[0087] As described above, the semiconductor device 100 can be manufactured.

[0088] <Embodiment 3> Embodiment 3 describes an example of a semiconductor device manufactured using the semiconductor wafer WF in Embodiment 1. The semiconductor device 200 in Embodiment 3 is a semiconductor device that includes a SiC pn junction diode.

[0089] Figure 10 is a cross-sectional view showing the semiconductor device 200.

[0090] In Figure 10, the semiconductor device 200 includes a silicon carbide substrate 1, a buffer layer 2, a drift layer 3, a lifetime control layer 10, an epitaxial layer 20, a cathode electrode 21, an anode region 22, and an anode electrode 23. In this case, the anode region 22 may be formed by ion implantation or by the epitaxial layer.

[0091] The anode region 22 is a p-type semiconductor region, and for example, aluminum, a p-type impurity, is introduced there. The depth of the anode region 22 is approximately 2 μm. The impurity concentration in the anode region 22 is, for example, 1 × 10⁻⁶ 19 ( / cm 3 ) 1 x 10 20 ( / cm 3 The size is approximately less than or equal to the size of the anode region 22. The anode region 22 is in contact with the drift layer 3, which is an n-type semiconductor layer. As a result, a pn junction is formed at the interface between the anode region 22 and the drift layer 3. Thus, the semiconductor device 200 includes a SiC pn junction diode.

[0092] The anode region 22 is electrically connected to the anode electrode 23 formed on the anode region 22. Meanwhile, a cathode electrode 21 is formed on the lower surface of the silicon carbide substrate 1. The cathode electrode 21 is electrically connected to the drift layer 3 via the silicon carbide substrate 1 and the buffer layer 2. In other words, in the SiC pn junction diode formed by the anode region 22 and the drift layer 3, the anode region 22, which functions as an anode, is electrically connected to the anode electrode 23, while the drift layer 3, which functions as a cathode, is electrically connected to the cathode electrode 21.

[0093] Since SiC pn junction diodes are bipolar devices, recovery losses occur. In this regard, in Embodiment 3, as shown in Figure 10, a lifetime control layer 10 is formed in the silicon carbide substrate 1. The lifetime control layer 10 has many point defects that function as electron-hole recombination centers. As a result, electron-hole recombination is promoted during carrier sweeping, which reduces the recovery current. Therefore, recovery losses can be reduced. In other words, according to Embodiment 3, recovery characteristics can be improved.

[0094] In particular, the full width at half maximum (FMAX) in the point defect density profile is narrow. Specifically, according to Embodiment 3, the FMAX in the point defect density profile can be reduced to less than 3 μm. Therefore, the improvement in recovery characteristics is significant.

[0095] The semiconductor device 200 in Embodiment 3 is manufactured using the semiconductor wafer WF in Embodiment 1. Therefore, the density of point defects in the epitaxial layer 20 is low (background level). In other words, the density of point defects that increase the on-resistance is low in the epitaxial layer 20, which greatly affects the on-resistance of the semiconductor device 200.

[0096] Therefore, according to the semiconductor device 200, the increase in on-resistance can be suppressed. In other words, according to Embodiment 3, the deterioration of the static characteristics of the semiconductor device 200 can be suppressed.

[0097] Based on the above, the semiconductor device 200 in Embodiment 3 can improve the recovery characteristics without degrading the static characteristics of the SiC pn junction diode (device).

[0098] <Embodiment 4> Embodiment 4 describes an example of a semiconductor device manufactured using the semiconductor wafer WF in Embodiment 1. The semiconductor device 300 in Embodiment 4 is a semiconductor device including a SiC IGBT.

[0099] Figure 11 is a cross-sectional view showing the semiconductor device 300.

[0100] In Figure 11, the semiconductor device 300 includes a silicon carbide substrate 1P, a buffer layer 2, a drift layer 3, p-type wells 5A and 5B, a body contact region 7A and 7B, a gate insulating film 8, a gate electrode 9, a lifetime control layer 10, an interlayer insulating film 11, an epitaxial layer 20, a collector electrode 31, an emitter region 32A, an emitter region 32B, and an emitter electrode 33.

[0101] The silicon carbide substrate 1P is a p-type semiconductor substrate. That is, for example, aluminum, a p-type impurity, is introduced into the silicon carbide substrate 1P. An epitaxial layer 20 is formed on the upper surface of the silicon carbide substrate 1P. Since the epitaxial layer 20 is an n-type semiconductor layer, a pn junction is formed between the silicon carbide substrate 1P and the epitaxial layer 20. A collector electrode 31 is formed on the lower surface of the silicon carbide substrate 1P.

[0102] Within the epitaxial layer 20, p-type wells 5A and 5B are formed. Within p-type well 5A, an emitter region 32A and a body contact region 7A are formed. The emitter region 32A is an n-type semiconductor region, while the body contact region 7A is a p-type semiconductor region. The emitter region 32A and the body contact region 7A are in contact with each other. Within p-type well 5B, an emitter region 32B and a body contact region 7B are formed. The emitter region 32B is an n-type semiconductor region, while the body contact region 7B is a p-type semiconductor region. The emitter region 32B and the body contact region 7B are in contact with each other. The emitter region 32A and the body contact region 7A are electrically connected to the emitter electrode 33. Therefore, the emitter region 32A and the body contact region 7A are electrically connected via the emitter electrode 33. The emitter region 32B and the body contact region 7B are electrically connected to the emitter electrode 33. Therefore, the emitter region 32B and the body contact region 7B are electrically connected via the emitter electrode 33.

[0103] A SiC IGBT turns on when a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode 9, with 0V applied to the emitter electrode 33 and a positive voltage applied to the collector electrode 31. Specifically, when a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode 9, a channel is formed and the emitter region 32A and the drift layer 3 are electrically connected. Similarly, a channel is formed and the emitter region 32B and the drift layer 3 are electrically connected.

[0104] Therefore, considering that the emitter electrode 33, emitter region 32A, emitter region 32B, and drift layer 3 are electrically connected, when 0V is applied to the emitter electrode 33, 0V is also applied to the drift layer 3. On the other hand, since the silicon carbide substrate 1P is electrically connected to the collector electrode 31, when a positive voltage is applied to the collector electrode 31, a positive voltage is also applied to the silicon carbide substrate 1P. As a result, the pn junction formed by the silicon carbide substrate 1P and the epitaxial layer 20 is forward biased.

[0105] As a result, holes are injected from the collector electrode 31 into the epitaxial layer 20 via the silicon carbide substrate 1P. Then, electrons are injected into the epitaxial layer 20 via the path from the emitter electrode 33 → emitter region 32A and emitter region 32B → channel → into the drift layer 3, as if attracted by the injected holes. This causes a conductivity modulation phenomenon, reducing the resistance within the epitaxial layer 20. In other words, in SiC IGBTs, the on-resistance can be reduced by the conductivity modulation phenomenon.

[0106] Subsequently, when a gate voltage smaller than the threshold voltage is applied to the gate electrode 9, the SiC IGBT turns off. More specifically, the SiC IGBT turns off when the sweeping of holes injected into the epitaxial layer 20 to the emitter electrode 33 and the sweeping of electrons injected into the epitaxial layer 20 to the collector electrode 31 are complete. In other words, the SiC IGBT turns off when the tail current, which flows due to the sweeping of holes and electrons, stops flowing. Therefore, it is desirable to reduce the tail current in order to shorten the time required to transition the SiC IGBT to off (in order to achieve high-speed switching).

[0107] In this regard, in Embodiment 4, as shown in Figure 11, a lifetime control layer 10 is formed within the silicon carbide substrate 1P. The lifetime control layer 10 has numerous point defects that function as electron-hole recombination centers. As a result, recombination of electrons and holes is promoted during carrier sweeping, which reduces the tail current.

[0108] In particular, the full width at half maximum (FMAX) in the point defect density profile is narrow. Specifically, according to Embodiment 4, the FMAX in the point defect density profile can be reduced to less than 3 μm. Therefore, the tail current reduction effect is significant.

[0109] The semiconductor device 300 in Embodiment 4 is manufactured using the semiconductor wafer WF in Embodiment 1. Therefore, the density of point defects in the epitaxial layer 20 is low (background level). In other words, the density of point defects that increase the on-resistance is low in the epitaxial layer 20, which greatly affects the on-resistance of the semiconductor device 300.

[0110] Therefore, according to the semiconductor device 300, the increase in on-resistance can be suppressed. In other words, according to Embodiment 4, the deterioration of the static characteristics of the semiconductor device 300 can be suppressed.

[0111] Based on the above, the semiconductor device 300 in Embodiment 4 can improve the switching characteristics without degrading the static characteristics of the SiC IGBT (device).

[0112] The present invention has been described in detail above based on its embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of symbols]

[0113] 1. Silicon carbide substrate 1P Silicon Carbide Substrate 2 buffer layers 3 Drift Layer 4 Drain electrodes 5A p-type well 5B p-type well 6A Source Area 6B Source Area 7A Body contact area 7B Body Contact Area 8 gate insulating film 9. Postal Service 10 Lifetime control layer 11 Interlayer insulating film 12 Source electrodes 20 Epitaxial Layer 21 Cathode electrode 22 Anode Region 23 Anode electrode 31 Collector electrode 32A Emitter region 32B Emitter region 33. Emitter electrode 100 Semiconductor Equipment 200 Semiconductor Equipment 300 semiconductor equipment BD Body Diode WF Semiconductor wafer

Claims

1. Silicon carbide substrate and An epitaxial layer formed on the silicon carbide substrate, wherein the epitaxial layer has a lower impurity concentration than the silicon carbide substrate, A lifetime control layer formed within the silicon carbide substrate, wherein the lifetime control layer is formed at a position away from the interface between the silicon carbide substrate and the epitaxial layer, A semiconductor wafer equipped with the following features.

2. In the semiconductor wafer according to claim 1, The lifetime control layer includes point defects that function as electron-hole recombination centers.

3. In the semiconductor wafer according to claim 2, The epitaxial layer contains point defects that function as electron-hole recombination centers, The point defect density in the lifetime control layer is 10 times or more the point defect density in the epitaxial layer.

4. In the semiconductor wafer according to claim 2, The full width at half maximum of the density profile of the point defects in the thickness direction of the semiconductor wafer is less than 3 μm.

5. In the semiconductor wafer according to claim 1, The lifetime control layer is formed at a position 500 nm or more deeper than the interface.

6. Silicon carbide substrate and An epitaxial layer formed on the silicon carbide substrate, wherein the epitaxial layer has a lower impurity concentration than the silicon carbide substrate, A lifetime control layer formed in the silicon carbide substrate, the lifetime control layer including point defects that function as electron-hole recombination centers, A semiconductor wafer comprising, A semiconductor wafer in which the full width at half maximum of the density profile of the point defects in the thickness direction of the semiconductor wafer is less than 3 μm.

7. In the semiconductor wafer according to claim 6, The peak position of the density profile of the point defect is located within the silicon carbide substrate.

8. In the semiconductor wafer according to claim 7, In the thickness direction of the semiconductor wafer, the lifetime control layer is formed at a position 500 nm or more deep from the interface between the silicon carbide substrate and the epitaxial layer.

9. (a) Steps to prepare a silicon carbide substrate, (b) A step of forming a lifetime control layer in the silicon carbide substrate, (c) After step (b), a step of forming an epitaxial layer on the silicon carbide substrate, A method for manufacturing semiconductor wafers, comprising:

10. In the method for manufacturing a semiconductor wafer according to claim 9, In step (b) above, ions are implanted into the silicon carbide substrate.

11. In the method for manufacturing a semiconductor wafer according to claim 10, The aforementioned ion is either hydrogen or helium.

12. In the method for manufacturing a semiconductor wafer according to claim 10, The aforementioned ion is hydrogen, The dose of hydrogen is 1 × 10 １２ / cm ２ The above 1 x 10 １５ / cm ２ The following applies:

13. In the method for manufacturing a semiconductor wafer according to claim 10, In step (b) above, the ions are injected into the silicon carbide substrate via a mask.

14. A semiconductor device including a SiC MOSFET, Drain electrode and A first-conductivity silicon carbide substrate located on the drain electrode, The first conductive type epitaxial layer formed on the silicon carbide substrate, the epitaxial layer having a lower impurity concentration than the silicon carbide substrate, A lifetime control layer formed within the silicon carbide substrate, wherein the lifetime control layer is formed at a position away from the interface between the silicon carbide substrate and the epitaxial layer, A second conductive well formed within the epitaxial layer, The first conductivity type source region formed in the well, A gate insulating film formed on the epitaxial layer, A gate electrode formed on the gate insulating film, A source electrode electrically connected to the source region, A semiconductor device equipped with the following features.

15. A semiconductor device including a SiC MOSFET, Drain electrode and A first-conductivity silicon carbide substrate located on the drain electrode, The first conductive type epitaxial layer formed on the silicon carbide substrate, the epitaxial layer having a lower impurity concentration than the silicon carbide substrate, A lifetime control layer formed in the silicon carbide substrate, the lifetime control layer including point defects that function as electron-hole recombination centers, A second conductive well formed within the epitaxial layer, The first conductivity type source region formed in the well, A gate insulating film formed on the epitaxial layer, A gate electrode formed on the gate insulating film, A source electrode electrically connected to the source region, Equipped with, A semiconductor device wherein the full width at half maximum of the density profile of the point defects in the thickness direction of the semiconductor device is less than 3 μm.

16. A semiconductor device including a SiC pn junction diode, First electrode and, A silicon carbide substrate of the first conductivity type located on the first electrode, The first conductive type epitaxial layer formed on the silicon carbide substrate, the epitaxial layer having a lower impurity concentration than the silicon carbide substrate, A lifetime control layer formed within the silicon carbide substrate, wherein the lifetime control layer is formed at a position away from the interface between the silicon carbide substrate and the epitaxial layer, A second conductivity type semiconductor region formed within the epitaxial layer, A second electrode electrically connected to the semiconductor region, A semiconductor device equipped with the following features.

17. A semiconductor device including a SiC pn junction diode, First electrode and, A silicon carbide substrate of the first conductivity type located on the first electrode, The first conductive type epitaxial layer formed on the silicon carbide substrate, the epitaxial layer having a lower impurity concentration than the silicon carbide substrate, A lifetime control layer formed in the silicon carbide substrate, the lifetime control layer including point defects that function as electron-hole recombination centers, A second conductivity type semiconductor region formed within the epitaxial layer, A second electrode electrically connected to the semiconductor region, Equipped with, A semiconductor device wherein the full width at half maximum of the density profile of the point defects in the thickness direction of the semiconductor device is less than 3 μm.

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