Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device that can suppress the increase in turn-on loss and improve reliability. [Solution] The semiconductor device according to the present disclosure has a first trench electrode and a second trench electrode, the first trench electrode has a two-stage structure having a lower electrode provided on the lower side which is the second main electrode side, an upper electrode provided on the upper side which is the first main electrode side, a first trench insulating film covering the inner surface of the trench, and a partition insulating film provided between the lower electrode and the upper electrode, the upper electrode has a recess in the portion corresponding to the upper part of the lower electrode, the side wall of the recess has a pointed portion that protrudes toward the bottom of the trench, the partition insulating film is provided so as to cover the inside of the recess and the pointed portion, the second trench electrode has a second trench insulating film covering the inner surface of the trench, a trench electrode filled in the trench covered by the second trench insulating film, and a visible member embedded in the upper region of the second trench insulating film.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and particularly to a semiconductor device having a two-stage trench electrode structure.

Background Art

[0002] Recently, as disclosed in FIG. 4 of Patent Document 1, a semiconductor device has been developed that includes a two-stage trench electrode having an upper-stage trench electrode and a lower-stage trench electrode in the thickness direction of a semiconductor substrate, and a single-stage trench electrode having a single trench electrode.

[0003] In Patent Document 1, the lower electrode of the two-stage trench electrode is given a source potential instead of a gate potential and functions as a field plate electrode. Also, the trench electrode of the single-stage trench electrode is given a source potential.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the semiconductor device as described above, since all the lower electrodes and the trench electrodes of the single-stage trench electrode are connected to the source potential, the collector-gate capacitance (Cgc) becomes small, and the ratio of Cgc to the emitter-gate capacitance (Cge) (Cgc / Cge) becomes small, increasing the gate resistance of the semiconductor element. When the recovery dv / dt at turn-on is set to a predetermined value, there is a problem that the turn-on loss increases.

[0006] This disclosure is made to solve the above-mentioned problems and aims to provide a semiconductor device having a two-stage trench electrode that can suppress an increase in turn-on loss and improve reliability. [Means for solving the problem]

[0007] The semiconductor device according to this disclosure comprises a semiconductor substrate having at least a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type on the first semiconductor layer, and a third semiconductor layer of a first conductivity type provided on the upper part of the second semiconductor layer; a first trench electrode and a second trench electrode provided inside a trench that penetrates the third semiconductor layer and the second semiconductor layer in the thickness direction of the semiconductor substrate and reaches into the first semiconductor layer; an interlayer insulating film covering the first and second trench electrodes; a first main electrode in contact with the third semiconductor layer; and a second main electrode provided on the opposite side of the semiconductor substrate in the thickness direction from the first main electrode, wherein the first trench electrode includes a lower electrode provided on the lower side facing the second main electrode and an upper electrode provided on the upper side facing the first main electrode The device has a two-stage structure comprising an upper electrode, a first trench insulating film covering the inner surface of the trench, and a partition insulating film provided between the lower electrode and the upper electrode, wherein the upper electrode has a recessed portion corresponding to the upper portion of the lower electrode, and the side wall of the recess has a pointed portion protruding toward the bottom of the trench, and the partition insulating film is provided to cover the inside of the recess and the pointed portion, and the second trench electrode has a second trench insulating film covering the inner surface of the trench, a trench electrode filled in the trench covered by the second trench insulating film, and a viewing member embedded in the upper region of the second trench insulating film, the upper electrode is connected to the potential of the first main electrode, and the lower electrode and the trench electrode are connected to the gate potential. [Effects of the Invention]

[0008] According to the semiconductor device described herein, in a semiconductor device having a two-stage trench electrode, it is possible to obtain a semiconductor device that can suppress an increase in turn-on loss and improve reliability. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic plan view showing the top surface configuration of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 2] This is a plan view of a subregion within the active region. [Figure 3] This is a cross-sectional view of a subregion within the active area. [Figure 4] This diagram shows the thickness of each part of the two-stage trench electrode and the single-stage trench electrode. [Figure 5] This is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 6] This is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 7] This is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 8] This is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 9] This is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 10] This is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 11] This is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 12] This is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 13] This is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 14] This is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 15]This is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 16] This is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 17] This is a plan view showing the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 18] This is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of this disclosure. [Figure 19] This is a cross-sectional view showing the configuration of a semiconductor device of a modified example 1 of Embodiment 1 relating to this disclosure. [Figure 20] This is a plan view showing the configuration of the semiconductor device of Embodiment 2 according to the present disclosure. [Figure 21] This is a cross-sectional view of a partial region within the active area, shown in the direction of the arrow. [Figure 22] This is a cross-sectional view of a partial region within the active area, shown in the direction of the arrow. [Figure 23] This is a cross-sectional view of a partial region within the active area, shown in the direction of the arrow. [Figure 24] This is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 3 of this disclosure. [Figure 25] This is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 4 of this disclosure. [Figure 26] This is a schematic plan view showing the top surface configuration of the semiconductor device according to Embodiment 5 of the present disclosure. [Figure 27] This is a plan view of a subregion within the active area. [Figure 28] This is a cross-sectional view of a subregion within the active area. [Modes for carrying out the invention]

[0010] <Introduction> Embodiments relating to this disclosure will be described below with reference to the attached drawings. Note that the drawings are schematic representations, and the relative sizes and positions of images shown in different drawings are not necessarily accurately represented and may be modified as appropriate. Furthermore, in the following description, similar components will be denoted by the same reference numerals, and their names and functions will also be the same. Therefore, detailed descriptions of them may be omitted.

[0011] Furthermore, in the following description, terms such as "top," "bottom," "side," "bottom," "front," and "back" may be used to indicate specific positions and directions. These terms are used for convenience to facilitate understanding of the embodiments and are not related to the actual directions in which they are implemented. In the following, "outside" refers to the direction toward the outer periphery of the semiconductor device, and "inside" refers to the direction opposite to "outside."

[0012] Furthermore, in the following description, the conductivity types of impurities are generally defined as n-type as the "first conductivity type" and p-type as the "second conductivity type," but the reverse definition is also acceptable.

[0013] Also, n - The n type indicates that the impurity concentration is lower than that of the n type. + The type indicates that the impurity concentration is higher than that of the n type. Similarly, p - The p-type indicates that the impurity concentration is lower than that of the p-type. + The type indicates that the impurity concentration is higher than that of the p-type.

[0014] <Embodiment 1> <Device configuration> FIG. 1 is a plan view schematically showing the upper surface configuration of an insulated gate bipolar transistor (IGBT) 100 according to Embodiment 1 of the present disclosure. The IGBT 100 shown in FIG. 1 has a rectangular outer shape, and most of it is an active region AR where a plurality of minimum unit structures (IGBT cells) called “unit cells” of the IGBT are arranged and the main current flows. The outside of the active region AR is a termination region 5. A plurality of trench electrodes (not shown) are provided in parallel in the active region AR at intervals from each other. The plurality of trench electrodes are connected to a gate wiring 3 provided in the active region AR, and the gate wiring 3 is connected to a gate pad 2. A dicing line 4 is provided outside the termination region 5. Note that the shapes and arrangements of the gate wiring 3 and the gate pad 2 are not limited to those shown in FIG. 1.

[0015] FIG. 2 shows a plan view of a partial region 50 surrounded by a broken line in the active region AR of FIG. 1. FIG. 2 is a partial plan view in which the upper structure such as an emitter electrode in the active region AR is omitted.

[0016] As shown in FIG. 2, in the active region AR, strip-shaped two-stage trench electrodes 30 (first trench electrodes) and single-stage trench electrodes 40 (second trench electrodes) are provided such that their longitudinal directions are parallel. The two-stage trench electrodes 30 and the single-stage trench electrodes 40 are provided so as to extend in a direction (left-right direction on the paper surface) intersecting the extending direction of the gate wiring 3 provided in the central portion of the active region AR. Note that the extending directions of the two-stage trench electrodes 30 and the single-stage trench electrodes 40 are not limited to this, and the extending direction may be the up-down direction on the paper surface.

[0017] FIG. 3 shows a cross-sectional view taken along the line A-A in FIG. 2 in the direction of the arrow. As shown in FIG. 3, the IGBT 100 has an n - -type drift layer 9 (first semiconductor layer) made of a semiconductor substrate. The n - -type drift layer 9 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 12 / cm 3 ~1.0×10 15 / cm 3 In Figure 3, the semiconductor substrate is n + This range extends from the p-type source layer 6 to the p-type collector layer 12. In Figure 3, n + The upper edge of the paper over the p-type source layer 6 is called the first main surface of the semiconductor substrate, and the lower edge of the paper over the p-type collector layer 12 is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the IGBT 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the IGBT 100.

[0018] As shown in Figure 3, n - On the first main surface side of the type drift layer 9, n - n-type impurities have a higher concentration in the drift layer 9. + A carrier storage layer 8 is provided. + The n-type carrier storage layer 8 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0 × 10⁻⁶. 13 / cm 3 ~1.0×10 17 / cm 3 n + By providing a carrier storage layer 8, the current loss when current flows through the IGBT 100 can be reduced, but n + It is not necessary to provide a carrier storage layer 8. + Type carrier storage layer 8 and n - The drift layer 9 and this layer together can be called the drift layer.

[0019] n + A p-type base layer 7 (second semiconductor layer) is provided on the first main surface side of the p-type carrier storage layer 8. The p-type base layer 7 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 19 / cm 3 The p-type base layer 7 is in contact with the trench insulating film 10 (first trench insulating film) of the two-stage trench electrode 30 and the trench insulating film 18 (second trench insulating film) of the one-stage trench electrode 40.

[0020] On the first main surface side of the p-type base layer 7, in contact with the trench insulating films 10 and 18, n + A type source layer 6 (third semiconductor layer) is provided. + The type source layer 6 constitutes the first main surface of the semiconductor substrate. + The n-type source layer 6 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0 × 10⁻⁶. 17 / cm 3 ~1.0×10 20 / cm 3 That is the case.

[0021] Also, n - On the second main surface side of the type drift layer 9, n - n-type impurities have a higher concentration in the drift layer 9. + A type buffer layer 11 is provided. + The p-type buffer layer 11 is provided to suppress punch-through of the depletion layer extending from the p-type base layer 7 towards the second main surface when the IGBT 100 is in the off state. + The buffer layer 11 contains, for example, phosphorus (P) or protons (H). + ) may be injected to form phosphorus (P) and protons (H + Both of the above may be injected to form the layer. The concentration of n-type impurities in the n-type buffer layer 11 is 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 18 / cm 3 That is the case.

[0022] Furthermore, a p+ type collector layer 12 is provided on the second main surface side of the n-type buffer layer 11. That is, the p+ type collector layer 12 is provided between the n-type drift layer 9 and the second main surface. The p+ type collector layer 12 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0 × 10¹⁶ / cm³ to 1.0 × 10²⁰ / cm³.

[0023] The two-stage trench electrode 30 penetrates the p-type base layer 7 from the first main surface of the semiconductor substrate, n -It is provided within a trench formed to reach the mold drift layer 9. Specifically, the two-stage trench electrode 30 has a trench insulating film 10 on the bottom and side walls, i.e., the inner surface, of the trench, and a lower electrode 19 is provided below the trench surrounded by the trench insulating film 10, and an upper electrode 14 is provided above the lower electrode 19. The lower electrode 19 and the upper electrode 14 are insulated from each other by a partition insulating film 20, and the upper electrode 14 is connected to the emitter potential and the lower electrode 19 is connected to the gate potential.

[0024] The upper electrode 14 has a recessed portion corresponding to the area above the lower electrode 19, and the side wall of the recess forms a pointed portion 15 that protrudes toward the bottom of the trench. The partition insulating film 20 is provided so as to cover the inside of the recess and the pointed portion 15.

[0025] The single-stage trench electrode 40 penetrates the p-type base layer 7 from the first main surface of the semiconductor substrate, n - It is provided within a trench formed to reach the mold drift layer 9. Specifically, the first-stage trench electrode 40 has a trench insulating film 18 on the bottom and side walls, i.e., the inner surface, of the trench, and a trench electrode 17 that extends from the bottom of the trench to the first main surface, and a visible member 16 made of a conductor is embedded in the upper region of the trench insulating film 18 on the side wall.

[0026] The trench insulating film 18 of the single-stage trench electrode 40 consists of a p-type base layer 7 and n + It is in contact with the p-type source layer 6. When a gate drive voltage is applied to the trench electrode 17, a channel is formed in the p-type base layer 7 in contact with the trench insulating film 18.

[0027] Here, the trench insulating films 10, 18 and the partition insulating film 20 are composed of, for example, a silicon oxide film. The upper electrode 14, lower electrode 19, trench electrode 17, and visibility member 16 are composed of, for example, polysilicon, amorphous silicon, and metal. Furthermore, a trench refers to an opening provided in a semiconductor substrate, but it can also refer to a structure formed in the opening.

[0028] Furthermore, as shown in Figure 3, an interlayer insulating film IS is provided on the two-stage trench electrode 30 and the one-stage trench electrode 40, and an emitter electrode 1 (first main electrode) is provided on the first main surface of the semiconductor substrate including the interlayer insulating film IS. A collector electrode 13 (second main electrode) is provided on the second main surface of the semiconductor substrate, on the side opposite in the thickness direction from the side on which the emitter electrode 1 is provided.

[0029] The emitter electrode 1 may be formed from an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or it may be an electrode consisting of multiple layers of metal films formed on an electrode made of an aluminum alloy by electroless plating or electrolytic plating.

[0030] The collector electrode 13 may be composed of an aluminum alloy or an aluminum alloy with a plating film, similar to the emitter electrode 1. Alternatively, the collector electrode 13 may have a different configuration from the emitter electrode 1. The collector electrode 13 is in ohmic contact with the p-type collector layer 12 and is electrically connected to the p-type collector layer 12.

[0031] Figure 4 shows the horizontal length, or thickness, of each part of the two-stage trench electrode 30 and the single-stage trench electrode 40. In Figure 4, the thickness of the trench insulating film 10 between the trench sidewall and the pointed portion 15 of the two-stage trench electrode 30 is X1, the thickness of the pointed portion 15 is X2, and the thickness of the partition insulating film 20 between the pointed portion 15 and the lower electrode 19 is X3. Also, the thickness of the trench insulating film 18 between the trench sidewall and the viewing member 16 of the single-stage trench electrode 40 is X11, the thickness of the viewing member 16 is X12, and the thickness of the trench insulating film 18 between the viewing member 16 and the trench electrode 17 is X13. The relationships between the thicknesses are X1=X11, X2=X12, and X3=X13.

[0032] By using the above relationship to control the thicknesses X1, X2, and X3 of the two-stage trench electrode 30, a highly durable pointed portion 15 can be formed, thereby improving the reliability of the IGBT 100 gate.

[0033] In other words, when the IGBT 100 is turned off, a negative bias is applied between the gate and emitter. In this case, holes concentrate near the emitter electrode 1. An electric field is applied to the emitter electrode 1 due to the negative bias and the holes, and the electric field concentrates at the pointed portion 15, especially when the distance between the pointed portion 15 formed on the upper electrode 14 and the lower electrode 19, i.e., the thickness X3, becomes narrower. As described above, the electric field strength concentrated at the pointed portion 15 depends on the thickness X3 of the insulating film 20 partition between the pointed portion 15 and the lower electrode 19, so the reliability of the IGBT 100 can be improved by controlling variations caused by the manufacturing process.

[0034] As shown in the manufacturing method described later, the thickness X12 of the visible member 16 embedded near the first main surface within the trench insulating film 18 can be seen from the wafer surface during the manufacturing process. Therefore, from the relationship X2=X12, the thickness X3 of the partition insulating film 20 between the pointed portion 15 and the lower electrode 19 can be controlled, thereby improving the reliability of the IGBT 100.

[0035] Furthermore, in the IGBT100, the upper electrode 14 is connected to the emitter potential and the lower electrode 19 is connected to the gate potential, which allows for a larger Cgc / Cge ratio and reduces turn-on losses.

[0036] Furthermore, when the upper electrode 14 is connected to the emitter potential and the lower electrode 19 is connected to the gate potential, the electric field near the pointed portion 15 of the upper electrode 14 near the mesa becomes high during turn-off. However, by controlling the thickness X12 of the visibility member 16 embedded in the single-stage trench electrode 40 and the thickness X2 of the partition insulating film 20 between the pointed portion 15 and the lower electrode 19, the durability against damage to the pointed portion 15 can be improved, thereby improving the reliability of the IGBT 100.

[0037] <Manufacturing method> Next, the manufacturing method of the IGBT100 will be explained using Figures 5 to 18, which sequentially show the manufacturing process. Note that only the manufacturing methods for the two-stage trench electrode 30 and the single-stage trench electrode 40 will be shown below; the manufacturing methods for the other parts can be done using well-known methods, so their explanation will be omitted.

[0038] First, an n-type semiconductor substrate 300 is prepared, and in the process shown in Figure 5, a trench TR is formed in the region of the semiconductor substrate 300 where the two-stage trench electrode 30 and the one-stage trench electrode 40 are to be formed, extending from the first main surface 301 of the semiconductor substrate 300 to a predetermined depth and in the direction of the depth of the paper.

[0039] Next, in the process shown in Figure 6, an insulating film 303 (first insulating film) is formed in the region where the two-stage trench electrode 30 is formed (first region) so as to cover the inner surface of the trench TR, and an insulating film 304 (second insulating film) is formed in the region where the one-stage trench electrode 40 is formed (second region).

[0040] Next, in the process shown in Figure 7, a conductive material CD is embedded in the trench TR via insulating films 303 and 304. In the region where the two-stage trench electrode 30 is formed, the lower electrode 319 is formed, and in the region where the single-stage trench electrode 40 is formed, the trench electrode 317 is formed. For example, polysilicon, amorphous silicon, and metal can be used as the conductive material CD.

[0041] Next, in the process shown in Figure 8, the conductive CD formed above the insulating films 303 and 304 on the first main surface 301 is recessed, for example by etching, to expose the upper surfaces of the insulating films 303 and 304.

[0042] Next, in the process shown in Figure 9, a photoresist is applied to the first main surface 301, and a resist mask 350 is formed by patterning using photoengraving or the like.

[0043] Next, in the process shown in Figure 10, the resist mask 350 is used as an etching mask, and the lower electrode 319 is etched into the trench TR while the trench electrode 317 remains.

[0044] Next, in the process shown in Figure 11, after removing the resist mask 350, in the process shown in Figure 12, the insulating films 303 and 304 are recessed by etching so that their upper ends are lower than the upper ends of the lower electrode 319 and trench electrode 317.

[0045] Next, in the process shown in Figure 13, in the region where the two-stage trench electrode 30 is formed, an insulating film 320 (third insulating film) is formed on the trench sidewall and the upper part of the lower electrode 319, and in the region where the one-stage trench electrode 40 is formed, an insulating film 330 (fourth insulating film) is formed on the trench sidewall and the upper part of the trench electrode 317. The amount of insulating film formed per unit time differs for the insulating films 320 and 330 formed on the trench sidewall, on the electrodes, and on the retracted insulating films 303 and 304.

[0046] In other words, on the recessed insulating films 303 and 304 shown by the arrows in Figure 13, almost no insulating films 320 and 330 are formed, while insulating films 320 and 330 are formed on the trench sidewalls, the upper end of the lower electrode 319, and the upper end of the trench electrode 317. As a result, a gap GP is formed to embed the pointed portion 315 and the visibility member 316, as shown in Figure 14.

[0047] Next, in the process shown in Figure 15, a conductive material CD is embedded in the trench TR where insulating films 320 and 330 are formed. In the region where the two-stage trench electrode 30 is formed, an upper electrode 314 including a pointed portion 315 is formed, and in the region where the single-stage trench electrode 40 is formed, a visibility member 316 is embedded.

[0048] Next, in the process shown in Figure 16, the conductive CD and insulating films 320 and 330 formed above the first main surface 301 are retracted to the height of the first main surface 301.

[0049] Next, in the process shown in Figure 17, the first trench electrode 40 is observed from the first main surface 301 side, the positional relationship between the trench electrode 317, the viewing member 316, and the insulating film 304 is obtained, and the width and shape of the pointed portion 315 formed at the bottom of the upper electrode 314 of the second trench electrode 30 are estimated and managed.

[0050] If the estimated width and shape of the pointed portion 315 are within the design range, an insulating film 340 is formed on the upper part of the two-stage trench electrode 30 and the one-stage trench electrode 40 in the process shown in Figure 18 to form an interlayer insulating film. Through the above process, the two-stage trench electrode 30 and the one-stage trench electrode 40 can be obtained, and the width and shape of the pointed portion 315 of the two-stage trench electrode 30 can be controlled using the visual indicator 316 of the one-stage trench electrode 40.

[0051] <Example 1> Figure 19 is a cross-sectional view showing the configuration of IGBT101 in Modification 1 of Embodiment 1, and corresponds to the cross-sectional view in the direction indicated by the arrow along line AA of the subregion 50 enclosed by the dashed line in the active region AR of Figure 1.

[0052] In the IGBT100 of Embodiment 1 shown in Figure 3, a two-stage trench electrode 30 and a single-stage trench electrode 40 were provided in the active region AR. However, the IGBT101 shown in Figure 19 is equipped with a two-stage trench electrode 70 in addition to the two-stage trench electrode 30 and the single-stage trench electrode 40.

[0053] The structure of the two-stage trench electrode 70 is basically the same as that of the two-stage trench electrode 30, with a lower electrode 19 provided below the trench surrounded by the trench insulating film 10, and an upper electrode 24 provided above the lower electrode 19. The lower electrode 19 and the upper electrode 24 are insulated from each other by a partition insulating film 20, and the only difference from the two-stage trench electrode 30 is that the upper electrode 24 is connected to the gate potential.

[0054] The upper electrode 24 has a recessed portion corresponding to the area above the lower electrode 19, and the side wall of the recess forms a pointed portion 25 that protrudes toward the bottom of the trench. The partition insulating film 20 is provided so as to cover the inside of the recess and the pointed portion 25.

[0055] In Figure 19, an example is shown in which the same number of two-stage trench electrodes 30, one-stage trench electrodes 40, and two-stage trench electrodes 70 are provided. However, the number is not limited to equal numbers; the total number in the active region AR can be increased by one number and decreased by another.

[0056] By providing a two-stage trench electrode 70 in which the upper electrode 24 is connected to the gate potential, the number of lower electrodes 19 connected to the emitter potential can be adjusted, similar to the two-stage trench electrode 30, to adjust the Cgc / Cge ratio to a desired value. In other words, the more electrodes connected to the emitter potential, the lower the Cge decreases, so by adjusting the number of electrodes connected to the emitter potential, the Cge can be adjusted, and thus the Cgc / Cge ratio can be adjusted.

[0057] Here, the two-stage trench electrode 30 and the two-stage trench electrode 70 are used to adjust the Cgc / Cge ratio, and can therefore be called the first adjustment trench electrode and the second adjustment trench electrode, respectively.

[0058] <Modification 2> In the IGBT 100 of Embodiment 1 shown in Figure 3, the potential of the viewing member 16 embedded in the upper region of the trench insulating film 18 of the single-stage trench electrode 40 was not limited. The viewing member 16 may be connected to either the gate potential or the emitter potential, or it may be at a floating potential. This is because the viewing member 16 does not function as an electrode and is used only for controlling the width and shape of the pointed portion 15 of the two-stage trench electrode 30. Not limiting the potential of the viewing member 16 increases the design flexibility.

[0059] <Embodiment 2> Figure 20 is a diagram illustrating the semiconductor device of Embodiment 2, and shows the plan view shape of the partial region 60 enclosed by the dashed line in the active region AR of Figure 1. Figure 20 is a partial plan view in which the upper structure such as the emitter electrode near the gate wiring 3 is omitted, and is a top view of the wiring lead-out region.

[0060] The wiring exit area is the region where the lower electrode 19 of the two-stage trench electrode 30 is connected to the gate potential, and the lower electrode 19 is exposed at the end of the two-stage trench electrode 30.

[0061] Figure 21 shows a cross-sectional view along line BB in Figure 20, Figure 22 shows a cross-sectional view along line CC in the direction indicated by the arrow, and Figure 23 shows a cross-sectional view along line DD in the direction indicated by the arrow.

[0062] As shown in Figures 21 and 22, the two-stage trench electrode 30 has a structure similar to that of the single-stage trench electrode 40 at its end, with the lower electrode 19 extending upward so as to contact the interlayer insulating film IS, and is electrically connected to the gate wiring 3 provided on the interlayer insulating film IS via a contact hole 62.

[0063] Furthermore, as shown in Figure 23, the two-stage trench electrode 30 has the structure of a two-stage trench electrode 30 in portions other than the ends, with the upper electrode 14 in contact with the interlayer insulating film IS and electrically connected to the emitter wiring 64 provided on the interlayer insulating film IS via a contact hole 63.

[0064] As shown in Figure 21, a p-type termination well region 61 is provided on the termination region 5 side, which is outside the end of the two-stage trench electrode 30.

[0065] Thus, in the wiring outlet area, the end of the two-stage trench electrode 30 has the same structure as the single-stage trench electrode 40. Therefore, as shown in Figure 22, the width and shape of the pointed portion 15 of the two-stage trench electrode 30 can be controlled using the visual indicator 16 of the single-stage trench electrode 40.

[0066] <Embodiment 3> Figure 24 is a diagram illustrating the semiconductor device of Embodiment 3, and is a cross-sectional view in the direction indicated by the arrow along the EE line of the partial region 80 enclosed by the dashed line in the active region AR of Figure 1. The partial region 80 is the outer terminal region 5 of the active region AR, and the single-stage trench electrode 81 formed in the terminal region has the same structure as the single-stage trench electrode 40, and is provided with a trench insulating film 88 on the bottom and side walls of the trench, i.e., on the inner surface, and a trench electrode 89 that extends from the bottom of the trench to the first main surface, and a visibility member 82 made of a conductor is embedded in the upper region of the trench insulating film 88 on the side wall. Therefore, the width and shape of the pointed portion 15 of the two-stage trench electrode 30 can be controlled using the visibility member 82.

[0067] Furthermore, a p-type termination well region 61 is provided outside the first-stage trench electrode 81, and an interlayer insulating film IS is provided on the p-type termination well region 61. Although no structures are shown on the region where the first-stage trench electrode 81 is provided, an emitter electrode or an interlayer insulating film may be provided there. The width and shape of the pointed portion 15 of the second-stage trench electrode 30 are controlled by the visibility member 82, so any potential may be applied to the first-stage trench electrode 81, including a floating potential.

[0068] <Embodiment 4> Figure 25 is a diagram illustrating the semiconductor device of Embodiment 4, and is a cross-sectional view in the direction indicated by the arrow along the FF line of the subregion 90 enclosed by the dashed line in the area where the dicing line 4 in Figure 1 is formed. As shown in Figure 25, a single-stage trench electrode 91 is formed in the subregion 90. The single-stage trench electrode 91 has the same structure as the single-stage trench electrode 40, and is provided with a trench insulating film 98 on the bottom and side walls of the trench, i.e., on the inner surface, and a trench electrode 99 that extends from the bottom of the trench to the first main surface, and a visibility member 92 made of a conductor is embedded in the upper region of the trench insulating film 98 on the side wall. Therefore, the width and shape of the pointed portion 15 of the two-stage trench electrode 30 can be controlled using the visibility member 92.

[0069] <Embodiment 5> Figure 26 is a schematic plan view showing the overall top configuration of the RC-IGBT (Reverse Conducting IGBT) 200 of Embodiment 2 according to this disclosure. The RC-IGBT 200 comprises an IGBT region 250 and a diode region 260 within a single semiconductor substrate.

[0070] Multiple diode regions 260 are arranged in both the vertical and horizontal directions within the RC-IGBT 200, and each diode region 260 is surrounded by an IGBT region 250. In other words, multiple diode regions 260 are provided in an island-like configuration within the IGBT region 250. Note that the number of diode regions 260 is not limited to the number shown in Figure 26.

[0071] Similar to the IGBT100 shown in Figure 1, the RC-IGBT200 has a termination region 205 outside the active region AR. Multiple trench electrodes (not shown) are provided in parallel with spacing between them in the active region AR. These multiple trench electrodes are connected to gate wiring 203 provided within the active region AR, and the gate wiring 203 is connected to gate pad 202. Dicing lines 204 are provided outside the termination region 205. Note that the shape and arrangement of the gate wiring 203 and gate pad 202 are not limited to those shown in Figure 1.

[0072] Figure 27 shows the plan view shape of the sub-region 51 enclosed by the dashed line in the active region AR of Figure 26. Figure 27 is a partial plan view of the active region AR with the superstructure, such as the emitter electrode, omitted.

[0073] As shown in Figure 27, the active region AR is provided with a striped two-stage trench electrode 230 and a single-stage trench electrode 240 arranged in parallel. The two-stage trench electrode 230 and the single-stage trench electrode 240 are provided so as to extend parallel to the arrangement direction of the multiple diode regions 260 in the left-right direction of the paper. However, the direction of extension of the two-stage trench electrode 230 and the single-stage trench electrode 240 is not limited to this, and they can also extend in the up-down direction of the paper.

[0074] Figure 28 shows a cross-sectional view in the direction indicated by the arrow along the GG line in Figure 27. As shown in Figure 28, the IGBT region 250 of RC-IGBT200 is made of n semiconductor substrate. - It has a type drift layer 209 (first semiconductor layer). - The drift layer 209 is n of IGBT100 - This is the same as drift layer 9.

[0075] In Figure 28, the semiconductor substrate is n + This range extends from the p-type source layer 206 to the p-type collector layer 212. In Figure 28, n + The upper edge of the paper over the p-type source layer 206 is called the first main surface of the semiconductor substrate, and the lower edge of the paper over the p-type collector layer 212 is called the second main surface of the semiconductor substrate.

[0076] As shown in Figure 28, n - On the first main surface side of the type drift layer 209, n - n-type impurities have a higher concentration in the n-type drift layer 209. + A carrier storage layer 208 is provided. + The carrier storage layer 208 is n of IGBT100 + This is the same as the carrier storage layer 208.

[0077] n + A p-type base layer 207 (second semiconductor layer) is provided on the first main surface side of the type carrier storage layer 208. The p-type base layer 207 is the same as the p-type base layer 207 of the IGBT 100.

[0078] The p-type base layer 207 is in contact with the trench insulating film 210 (first trench insulating film) of the two-stage trench electrode 230 and the trench insulating film 218 (second trench insulating film) of the single-stage trench electrode 240.

[0079] On the first main surface side of the p-type base layer 207, in contact with the trench insulating film 210, n + A type source layer 206 (third semiconductor layer) is provided. + The source layer 206 is n of IGBT100 +This is the same as source layer 6.

[0080] Also, n - On the second main surface side of the type drift layer 209, n - n-type impurities have a higher concentration in the n-type drift layer 209. + A type buffer layer 211 (the fourth semiconductor layer) is provided. + The type buffer layer 211 is n of IGBT100 + This is the same as the type buffer layer 11.

[0081] Furthermore, a p+ type collector layer 212 is provided on the second main surface side of the n type buffer layer 211. The p+ type collector layer 212 is the same as the p+ type collector layer 12 of the IGBT 100.

[0082] In the diode region 260 of the RC-IGBT200 shown in Figure 28, components common to both the IGBT region 250 and the diode region 260 are given the same reference numerals, and redundant explanations are omitted.

[0083] As shown in Figure 28, in the diode region 260, n + Instead of a p-type source layer 206, it has a p-type anode layer 221 (the fifth semiconductor layer), and p + Instead of the collector layer 212, n + It has a cathode layer 222 (sixth semiconductor layer).

[0084] The p-type anode layer 221 is a semiconductor layer having p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 19 / cm 3 n + The n-type cathode layer 222 is a semiconductor layer having n-type impurities such as arsenic or phosphorus, and the concentration of the n-type impurities is 1.0 × 10⁻⁶. 16 / cm 3 ~1.0×10 21 / cm 3 That is the case.

[0085] The two-stage trench electrode 230 penetrates the p-type base layer 207 from the first main surface of the semiconductor substrate, n - It is provided within a trench formed to reach the mold drift layer 209. Specifically, the two-stage trench electrode 230 has a trench insulating film 210 on the bottom and side walls, i.e., the inner surface, of the trench, and a lower electrode 219 is provided below the trench surrounded by the trench insulating film 210, and an upper electrode 214 is provided above the lower electrode 219. The lower electrode 219 and the upper electrode 214 are insulated from each other by a partition insulating film 220, and the upper electrode 214 is connected to the emitter potential and the lower electrode 219 is connected to the gate potential.

[0086] The upper electrode 214 has a recessed portion corresponding to the area above the lower electrode 219, and the side wall of the recess forms a pointed portion 215 that protrudes toward the bottom of the trench. The partition insulating film 220 is provided to cover the inside of the recess and the pointed portion 15.

[0087] The single-stage trench electrode 240 penetrates the p-type base layer 207 from the first main surface of the semiconductor substrate, n - It is provided within a trench formed to reach the mold drift layer 209. Specifically, the first-stage trench electrode 240 has a trench insulating film 218 on the bottom and side walls, i.e., the inner surface, of the trench, and a trench electrode 217 that extends from the bottom of the trench to the first main surface, and a visible member 216 made of a conductor is embedded in the upper region of the trench insulating film 218 on the side wall.

[0088] The two-stage trench electrode 230 and the single-stage trench electrode 240 are the same as the two-stage trench electrode 30 and the single-stage trench electrode 40 of the IGBT 100.

[0089] Furthermore, as shown in Figure 28, an interlayer insulating film IS is provided on the two-stage trench electrode 230 and the one-stage trench electrode 240, and an emitter electrode 201 (first main electrode) is provided on the first main surface of the semiconductor substrate including the interlayer insulating film IS. A collector electrode 213 (second main electrode), which also functions as a cathode electrode, is provided on the second main surface of the semiconductor substrate, on the side opposite in the thickness direction from the side on which the emitter electrode 201 is provided.

[0090] Since the visibility member 216 of the single-stage trench electrode 240 and the pointed portion 215 of the double-stage trench electrode 230 are made of the same material, the formation conditions are the same. By using the visibility member 216 to control the width and shape of the pointed portion 215 of the double-stage trench electrode 230, the durability against damage to the pointed portion 215 can be improved, thereby improving the reliability of the RC-IGBT200.

[0091] Within the scope of this disclosure, it is possible to freely combine the embodiments, or modify or omit the embodiments as appropriate.

[0092] The above-described disclosure is summarized below as an appendix.

[0093] (Note 1) First semiconductor layer of the first conductivity type, A second semiconductor layer of a second conductivity type on the first semiconductor layer, and a semiconductor substrate having at least a third semiconductor layer of a first conductivity type provided on the upper part of the second semiconductor layer, A first trench electrode and a second trench electrode are provided inside a trench that penetrates the third semiconductor layer and the second semiconductor layer of the semiconductor substrate in the thickness direction and reaches into the first semiconductor layer, An interlayer insulating film covering the first and second trench electrodes, The first main electrode in contact with the third semiconductor layer, The first main electrode is provided with a second main electrode located on the opposite side of the semiconductor substrate in the thickness direction, The first trench electrode is, The lower electrode is provided on the lower side, which is the second main electrode side, The upper electrode provided on the upper side which is the first main electrode, A first trench insulating film covering the inner surface of the trench, A two-stage structure is formed, comprising a partition insulating film provided between the lower electrode and the upper electrode. The upper electrode has a recessed portion corresponding to the upper part of the lower electrode, and the side wall of the recess has a pointed portion that protrudes toward the bottom of the trench. The partition insulating film is provided so as to cover the inside of the recess and the pointed portion. The second trench electrode is, A second trench insulating film covering the inner surface of the trench, A trench electrode filled in the trench covered with the second trench insulating film, The present invention comprises a viewing member embedded in the upper region of the second trench insulating film, The upper electrode is connected to the potential of the first main electrode, A semiconductor device in which the lower electrode and the trench electrode are connected to the gate potential.

[0094] (Note 2) First semiconductor layer of the first conductivity type, A second semiconductor layer of a second conductivity type on the first semiconductor layer, A third semiconductor layer of the first conductivity type is provided on the upper part of the second semiconductor layer. and a first region having at least a fourth semiconductor layer of a second conductivity type provided on the opposite side in the thickness direction from the third semiconductor layer of the first semiconductor layer, The first semiconductor layer, The aforementioned second semiconductor layer, A fifth semiconductor layer of the first conductivity type is provided on the upper part of the third semiconductor layer, A semiconductor substrate comprising a second region having at least a sixth semiconductor layer of a second conductivity type provided on the opposite side in the thickness direction from the fifth semiconductor layer of the first semiconductor layer, A first trench electrode is provided inside a first trench that penetrates the third semiconductor layer and the second semiconductor layer in the thickness direction in the first region and reaches into the first semiconductor layer, The second region comprises the fifth semiconductor layer, a second trench electrode provided inside the second trench that penetrates the second semiconductor layer in the thickness direction and reaches into the first semiconductor layer, An interlayer insulating film covering the first and second trench electrodes, A first main electrode in contact with the third semiconductor layer and the fifth semiconductor layer, The first main electrode is provided with a second main electrode located on the opposite side of the semiconductor substrate in the thickness direction. The first trench electrode is, The lower electrode is provided on the lower side, which is the second main electrode side, The upper electrode provided on the upper side which is the first main electrode, A first trench insulating film covering the inner surface of the first trench, A two-stage structure is formed, comprising a partition insulating film provided between the lower electrode and the upper electrode. The upper electrode has a recessed portion corresponding to the upper part of the lower electrode, and the side wall of the recess has a pointed portion that protrudes toward the bottom of the trench. The partition insulating film is provided so as to cover the inside of the recess and the pointed portion. The second trench electrode is, A second trench insulating film covering the inner surface of the second trench, A trench electrode filled in the trench covered with the second trench insulating film, The present invention comprises a viewing member embedded in the upper region of the second trench insulating film, The upper electrode is connected to the potential of the first main electrode, A semiconductor device in which the lower electrode and the trench electrode are connected to the gate potential.

[0095] (Note 3) The thickness of the first trench insulating film between the side wall of the trench and the pointed portion of the first trench electrode is X1. The thickness of the pointed part is X2, Let X3 be the thickness of the insulating film of the partition between the pointed portion and the lower electrode. The thickness of the second trench insulating film between the side wall of the trench of the second trench electrode and the viewing member is X11. The thickness of the aforementioned viewing member is X12, When the thickness of the second trench insulating film between the viewing member and the trench electrode is X13, A semiconductor device as described in Appendix 1 or Appendix 2, having the relationships X1=X11, X2=X12, and X3=X13.

[0096] (Note 4) The first trench electrode is, The upper electrode is connected to the potential of the first main electrode, The lower electrode is connected to the gate potential and includes a first adjustment trench electrode, The semiconductor device according to Appendix 3, wherein the upper electrode and the lower electrode include a second adjustment trench electrode connected to the gate potential.

[0097] (Note 5) The aforementioned viewing member is, A semiconductor device as described in Appendix 3, connected to the potential of the first main electrode, the gate potential, or the floating potential.

[0098] (Note 6) The first and second trench electrodes are, They are arranged with gaps between them so that their longitudinal direction is parallel to the active region through which the main current flows. The first trench electrode is, At the longitudinal end, it has the same structure as the second trench electrode, The semiconductor device according to Appendix 4 or Appendix 5, wherein the lower electrode is connected to the trench electrode of the structural part and electrically connected via the trench electrode to gate wiring provided along the outer circumference of the active region.

[0099] (Note 7) The first and second trench electrodes are, They are arranged with gaps between them so that their longitudinal direction is parallel to the active region through which the main current flows. The second trench electrode is, The semiconductor device described in Appendix 4 or Appendix 5, which is also located in the terminal region outside the active region.

[0100] (Note 8) The first and second trench electrodes are, They are arranged with gaps between them so that their longitudinal direction is parallel to the active region through which the main current flows. The second trench electrode is, The semiconductor device described in Appendix 4 or Appendix 5, which is also positioned on the outermost dicing line of the active region.

[0101] (Note 9) A semiconductor device according to any one of the appendices 1 to 8, wherein the visibility member and the upper electrode are made of the same conductor.

[0102] (Note 10) (a) A step of forming first and second trenches that reach a predetermined depth from the main surface of the semiconductor substrate, (b) The steps of forming a first insulating film on the inner surface of the first trench and forming a second insulating film on the inner surface of the second trench, (c) The steps of embedding a conductor through the first and second insulating films, forming a lower electrode in the first trench, and forming a trench electrode in the first trench, (d) A step of removing the conductor above the first and second insulating films on the main surface, (e) A step of selectively forming a resist mask so as to cover the second trench, (f) Using the resist mask as an etching mask, the lower electrode is etched so that it retracts into the first trench and the trench electrode remains in place. (g) After removing the resist mask, the first and second insulating films are removed by etching such that the upper ends of the first and second insulating films are lower than the upper ends of the lower electrode and the trench electrode. (h) A step of forming a third insulating film on the side wall of the first trench and on the upper part of the lower electrode, and forming a fourth insulating film on the trench side wall of the second trench and on the upper part of the trench electrode, (i) The steps of embedding the conductor in the first and second trenches in which the third and fourth insulating films have been formed, forming an upper electrode including a pointed portion in the first trench, and embedding a visible member in the second trench, (j) A step of removing the conductor and the third and fourth insulating films from the main surface, (k) A step of observing the trench electrode from the main surface side, obtaining the positional relationship between the trench electrode, the viewing member and the second insulating film, and estimating and managing the width and shape of the pointed portion of the first trench, (l) If the estimated width and shape of the pointed portion are within the design range, a step of forming an interlayer insulating film on the upper part of the first and second trenches, a method for manufacturing a semiconductor device. [Explanation of Symbols]

[0103] 1 gate wiring, 4 dicing lines, 5 termination regions, 6,206 n + Type source layer, 7,207 p-type base layer, 9,209 n - Type drift layer, 10, 18, 210, 218 Trench insulating film, 14, 214, 314 Upper electrode, 15, 215 Pointed part, 16, 216 Visibility member, 17, 217 Trench electrode, 19, 219 Lower electrode, 20, 220, 319 Partition insulating film, 30, 230 Two-stage trench electrode, 40, 240 One-stage trench electrode, 250 IGBT region, 260 Diode region, 300 Semiconductor substrate, 301 First main surface, 302 Second main surface, 303, 304, 320 Insulating film, 350 Photoresist.

Claims

1. First semiconductor layer of the first conductivity type, A second semiconductor layer of a second conductivity type on the first semiconductor layer, and a semiconductor substrate having at least a third semiconductor layer of a first conductivity type provided on the upper part of the second semiconductor layer, A first trench electrode and a second trench electrode are provided inside a trench that penetrates the third semiconductor layer and the second semiconductor layer of the semiconductor substrate in the thickness direction and reaches into the first semiconductor layer, An interlayer insulating film covering the first and second trench electrodes, The first main electrode in contact with the third semiconductor layer, The first main electrode is provided with a second main electrode located on the opposite side of the semiconductor substrate in the thickness direction, The first trench electrode is, The lower electrode, which is located on the lower side of the second main electrode, The upper electrode provided on the upper side which is the first main electrode, A first trench insulating film covering the inner surface of the trench, A two-stage structure is formed, comprising a partition insulating film provided between the lower electrode and the upper electrode. The upper electrode has a recessed portion corresponding to the upper part of the lower electrode, and the side wall of the recess has a pointed portion that protrudes toward the bottom of the trench. The partition insulating film is provided so as to cover the inside of the recess and the pointed portion. The second trench electrode is A second trench insulating film covering the inner surface of the trench, A trench electrode filled in the trench covered with the second trench insulating film, The present invention comprises a viewing member embedded in the upper region of the second trench insulating film, The upper electrode is connected to the potential of the first main electrode, A semiconductor device in which the lower electrode and the trench electrode are connected to the gate potential.

2. First semiconductor layer of the first conductivity type, A second semiconductor layer of a second conductivity type on the first semiconductor layer, A third semiconductor layer of the first conductivity type is provided on the upper part of the second semiconductor layer. and a first region having at least a fourth semiconductor layer of a second conductivity type provided on the opposite side in the thickness direction from the third semiconductor layer of the first semiconductor layer, The first semiconductor layer, The aforementioned second semiconductor layer, A fifth semiconductor layer of the first conductivity type is provided on the upper part of the third semiconductor layer, A semiconductor substrate comprising a second region having at least a sixth semiconductor layer of a second conductivity type provided on the opposite side in the thickness direction from the fifth semiconductor layer of the first semiconductor layer, A first trench electrode is provided inside a first trench that penetrates the third semiconductor layer and the second semiconductor layer in the thickness direction in the first region and reaches into the first semiconductor layer, The second region includes the fifth semiconductor layer, the second trench electrode provided inside the second trench that penetrates the second semiconductor layer in the thickness direction and reaches into the first semiconductor layer, An interlayer insulating film covering the first and second trench electrodes, A first main electrode in contact with the third semiconductor layer and the fifth semiconductor layer, The first main electrode is provided with a second main electrode located on the opposite side of the semiconductor substrate in the thickness direction. The first trench electrode is, The lower electrode, which is located on the lower side of the second main electrode, The upper electrode provided on the upper side which is the first main electrode, A first trench insulating film covering the inner surface of the first trench, A two-stage structure is formed, comprising a partition insulating film provided between the lower electrode and the upper electrode. The upper electrode has a recessed portion corresponding to the upper part of the lower electrode, and the side wall of the recess has a pointed portion that protrudes toward the bottom of the trench. The partition insulating film is provided so as to cover the inside of the recess and the pointed portion. The second trench electrode is A second trench insulating film covering the inner surface of the second trench, A trench electrode filled in the trench covered with the second trench insulating film, The present invention comprises a viewing member embedded in the upper region of the second trench insulating film, The upper electrode is connected to the potential of the first main electrode, A semiconductor device in which the lower electrode and the trench electrode are connected to the gate potential.

3. The thickness of the first trench insulating film between the side wall of the trench and the pointed portion of the first trench electrode is X1. The thickness of the pointed part is X2, Let X3 be the thickness of the insulating film of the partition between the pointed portion and the lower electrode. The thickness of the second trench insulating film between the side wall of the trench of the second trench electrode and the viewing member is X11. The thickness of the aforementioned viewing member is X12, When the thickness of the second trench insulating film between the viewing member and the trench electrode is X13, A semiconductor device according to claim 1 or claim 2, having the relationships X1 = X11, X2 = X12, and X3 = X13.

4. The first trench electrode is, The upper electrode is connected to the potential of the first main electrode, The lower electrode is connected to the gate potential and includes a first adjustment trench electrode, The semiconductor device according to claim 3, wherein the upper electrode and the lower electrode include a second adjustment trench electrode connected to the gate potential.

5. The aforementioned viewing member is, The semiconductor device according to claim 3, which is connected to any of the potential of the first main electrode, the gate potential, and the floating potential.

6. The first and second trench electrodes are, They are arranged with gaps between them so that their longitudinal direction is parallel to the active region through which the main current flows. The first trench electrode is, The longitudinal end portion has the same structure as the second trench electrode, The semiconductor device according to claim 4 or 5, wherein the lower electrode is connected to the trench electrode of the structural part and electrically connected via the trench electrode to gate wiring provided along the outer circumference of the active region.

7. The first and second trench electrodes are, They are arranged with gaps between them so that their longitudinal direction is parallel to the active region through which the main current flows. The second trench electrode is The semiconductor device according to claim 4 or claim 5, which is also arranged in a terminal region outside the active region.

8. The first and second trench electrodes are, They are arranged with gaps between them so that their longitudinal direction is parallel to the active region through which the main current flows. The second trench electrode is The semiconductor device according to claim 4 or 5, which is also positioned on the outermost dicing line of the active region.

9. The semiconductor device according to claim 1, wherein the viewing member and the upper electrode are made of the same conductor.

10. (a) A step of forming first and second trenches that reach a predetermined depth from the main surface of the semiconductor substrate, (b) The steps of forming a first insulating film on the inner surface of the first trench and forming a second insulating film on the inner surface of the second trench, (c) The steps of embedding a conductor through the first and second insulating films, forming a lower electrode in the first trench, and forming a trench electrode in the first trench, (d) A step of removing the conductor above the first and second insulating films on the main surface, (e) A step of selectively forming a resist mask so as to cover the second trench, (f) Using the resist mask as an etching mask, the lower electrode is etched so that it retracts into the first trench and the trench electrode remains in place. (g) After removing the resist mask, the first and second insulating films are removed by etching such that the upper ends of the first and second insulating films are lower than the upper ends of the lower electrode and the trench electrode. (h) A step of forming a third insulating film on the side wall of the first trench and the upper part of the lower electrode, and forming a fourth insulating film on the trench side wall of the second trench and the upper part of the trench electrode, (i) The steps of embedding the conductor in the first and second trenches in which the third and fourth insulating films have been formed, forming an upper electrode including a pointed portion in the first trench, and embedding a visibility member in the second trench, (j) A step of removing the conductor and the third and fourth insulating films from the main surface, (k) A step of observing the trench electrode from the main surface side, obtaining the positional relationship between the trench electrode, the viewing member and the second insulating film, and estimating and managing the width and shape of the pointed portion of the first trench, (l) If the estimated width and shape of the pointed portion are within the design range, a step of forming an interlayer insulating film on the upper part of the first and second trenches, a method for manufacturing a semiconductor device.

Images