Manufacturing method for nitride semiconductor devices

Abstract

The present invention provides a method for manufacturing a nitride semiconductor device that suppresses the increase in vacancy defects while improving the activation of dopant elements. [Solution] A method for manufacturing a nitride semiconductor device comprises the steps of: channeling an inert element into a predetermined region from the surface side of the nitride semiconductor; randomly implanting a dopant element into a predetermined region from the surface side; and heat-treating the nitride semiconductor into which the inert element and the dopant element have been implanted to activate the dopant element.

Description

[Technical Field]

[0001] This disclosure relates to a method for manufacturing nitride semiconductor devices. [Background technology]

[0002] In nitride semiconductor devices, p-type conductivity control is possible by using magnesium (Mg) as a dopant. Patent document 1 discloses a technique for forming a p-type diffusion layer by ion-implanting Mg and nitrogen (N) into a GaN substrate and then performing heat treatment. Ion-implanting N into the GaN substrate promotes the activation of Mg, making it easier to increase the effective acceptor concentration of the p-type diffusion layer. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-60765 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] While nitrogen (N) ion implantation into GaN substrates is effective in improving Mg activation, the implantation of N itself creates new vacancy defects in the GaN substrate. If vacancy defects remain after heat treatment to activate Mg, the electrical properties and reliability of the semiconductor device may deteriorate. This disclosure aims to provide a method for manufacturing a nitride semiconductor device that enables improved activation of the dopant element while suppressing the increase in vacancy defects. [Means for solving the problem]

[0005] In order to solve the above problems, a method for manufacturing a nitride semiconductor device according to an aspect of the present disclosure includes a step of channeling and implanting an inert element into a preset region from the side of the surface of the nitride semiconductor, a step of randomly implanting a dopant element into the preset region from the side of the surface, and a step of performing heat treatment on the nitride semiconductor into which the inert element and the dopant element are implanted to activate the dopant element.

Effect of the Invention

[0006] According to an aspect of the present disclosure, it is possible to provide a method for manufacturing a nitride semiconductor device that can improve the activation of dopant elements while suppressing an increase in vacancy defects.

Brief Description of the Drawings

[0007] [Figure 1A] FIG. 1A is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to an embodiment of the present disclosure in the order of steps. [Figure 1B] FIG. 1B is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to an embodiment of the present disclosure in the order of steps. [Figure 1C] FIG. 1C is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to an embodiment of the present disclosure in the order of steps. [Figure 1D] FIG. 1D is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to an embodiment of the present disclosure in the order of steps. [Figure 1E] FIG. 1E is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to an embodiment of the present disclosure in the order of steps. [Figure 1F] FIG. 1F is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to an embodiment of the present disclosure in the order of steps. [Figure 2] FIG. 2 is a diagram schematically showing the tilt angle with respect to the C axis. [Figure 3] FIG. 3 is a cross-sectional view schematically showing the configuration of a sample used in the experiment of the present disclosure. [Figure 4] FIG. 4 is a graph showing the experimental results of the present disclosure.

Best Mode for Carrying Out the Invention

[0008] Embodiments of the present disclosure will be described below. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of each device and each member, etc. are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Also, it is a matter of course that the relationship between the dimensions and the ratio thereof are different between the drawings.

[0009] In the following description, the directions may be described using the terms in the X-axis direction, the Y-axis direction, and the Z-axis direction. For example, the X-axis direction and the Y-axis direction are directions parallel to the surface 10a of the GaN substrate 10 described later. The Z-axis direction is a direction perpendicular to the surface 10a of the GaN substrate 10. The X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other.

[0010] In the following description, the positive direction of the Z-axis may be referred to as "up", and the negative direction of the Z-axis may be referred to as "down". "Up" and "down" do not necessarily mean the vertical direction with respect to the ground. That is, the directions of "up" and "down" are not limited to the gravitational direction. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship in a region, a layer, a film, a substrate, etc., and do not limit the technical idea of the present disclosure. For example, if the paper surface is rotated 180 degrees, it is a matter of course that "up" becomes "down" and "down" becomes "up".

[0011] In the following description, + and - attached to p and n indicating the conductivity type mean semiconductor regions having a relatively high or low impurity concentration, respectively, compared to the semiconductor regions to which + and - are not appended. However, even for semiconductor regions with the same p and p (or n and n) attached, it does not mean that the impurity concentrations of the respective semiconductor regions are exactly the same.

[0012] <Embodiment> (Manufacturing Method) A method for manufacturing a vertical MOSFET 1 according to an embodiment of this disclosure will now be described. Figures 1A to 1F are cross-sectional views showing the manufacturing method of a vertical MOSFET 1 according to an embodiment of this disclosure in order of steps. The vertical MOSFET 1 is manufactured using various devices such as a film deposition apparatus, an exposure apparatus, an ion implantation apparatus, an etching apparatus, and a heat treatment apparatus. Hereinafter, these devices will be collectively referred to as manufacturing apparatus.

[0013] The GaN substrate 10 shown in Figure 1A (an example of a "nitride semiconductor" in this disclosure) is a GaN single crystal substrate. The GaN substrate 10 is, for example, an n-type substrate. The GaN substrate 10 has a surface 10a and a back surface 10b located on the opposite side of surface 10a. For example, the GaN substrate 10 has a threading dislocation density of 1 × 10⁻¹⁶ 7 cm -2 This is a low-dislocation self-supporting GaN substrate. Because the GaN substrate 10 is a low-dislocation self-supporting GaN substrate, even when a large-area power device is formed on the GaN substrate 10, the leakage current in the power device can be reduced. This makes it possible to manufacture power devices with a high yield rate. In addition, in the heat treatment included in the manufacturing process of the vertical MOSFET 1, it is possible to prevent ion-implanted impurities from diffusing deeply along the dislocations.

[0014] The GaN substrate 10 may include a GaN single crystal substrate and a single crystal GaN layer epitaxially grown on the GaN single crystal substrate. In this case, the GaN single crystal substrate may be n+ type or n type, and the GaN layer may be n type or n- type. In the n-type or n-type GaN layer, the region where, for example, the well region 23 or JFET region 29 described later is not formed becomes the drift region 22. The surface 10a of the GaN substrate 10 is, for example, the C plane (Ga plane).

[0015] As shown in Figure 1A, the manufacturing apparatus channel-implants nitrogen (N) and randomly implants magnesium (Mg) into the region 23' in the GaN substrate 10 where the well region 23 (see Figure 1F described later) is to be formed (hereinafter referred to as the well-forming region). The well-forming region 23' is an example of a "pre-set region" in this disclosure, N is an example of an "inert element" in this disclosure, and Mg is an example of a p-type "dopant element" in this disclosure.

[0016] For example, the manufacturing apparatus forms a mask M1 on the surface 10a of the GaN substrate 10. The mask M1 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M1 has a shape that opens above the well-forming region 23' and covers above other regions. The manufacturing apparatus channel-injects N and randomly injects Mg from the side of the surface 10a of the GaN substrate 10 on which the mask M1 is formed, in the depth direction.

[0017] Channeling implantation and random implantation will be explained. Figure 2 is a schematic diagram showing the tilt angle θ with respect to the C axis. As described above, the surface 10a of the GaN substrate 10 is, for example, the C plane (Ga plane). Channeling implantation is the ion implantation of an element (e.g., N) along the C axis, which is the normal direction of the C plane. That is, channeling implantation is the ion implantation of an element (e.g., N) parallel or nearly parallel to the C axis. The tilt angle θ for channeling implantation is preferably -1° to 1° with respect to the C axis, and more preferably -0.5° to 0.5° with respect to the C axis. This makes it possible to implant an element (e.g., N) to a deep position from the surface 10a of the GaN substrate 10 so as to pass through the crystal lattice.

[0018] Random implantation is the ion implantation of an element (e.g., Mg) at an angle tilted with respect to the C-axis. The tilt angle θ of random implantation is preferably 4° to 10° with respect to the C-axis, and more preferably 6° to 8° with respect to the C-axis. The in-plane rotation angle (hereinafter referred to as the twist angle) of random implantation is preferably 10° to 20°, and more preferably 14° to 16°.

[0019] In Figure 1A, the order in which N channeling injection and Mg random injection are performed is not particularly limited, but it is preferable to perform N channeling injection before Mg random injection because the crystal structure of the GaN substrate 10 is less disordered before random injection than after Mg random injection. By performing N channeling injection before Mg random injection (i.e., performing N channeling injection first, followed by Mg random injection), it becomes easier to inject N into a deep location from the surface 10a of the GaN substrate 10, so as to pass through the less disordered crystal lattice.

[0020] The dose of N is preferably set to 1 to 10 times the dose of Mg, and more preferably to 2 to 5 times. This makes it easier to suppress Mg diffusion from the surface 10a of the GaN substrate 10 in the depth direction during the heat treatment for activating Mg described later. Even when using inert elements other than N, the dose of the inert element is preferably 1 to 10 times the dose of the dopant element.

[0021] In the GaN substrate 10 shown in Figure 1A, the layer into which N is injected is defined as the N injection layer L11 (an example of the "first injection layer" in this disclosure), and the layer into which Mg is injected is defined as the Mg injection layer L12 (an example of the "second injection layer" in this disclosure). For example, the injection energy (acceleration voltage) for N is set such that the depth d11 from the surface 10a of the GaN substrate 10 to the bottom surface of the N injection layer L11 is the same depth d12 from the surface 10a of the GaN substrate 10 to the bottom surface of the Mg injection layer L12, or is deeper than the depth d12. That is, the injection energy for N is set such that the injection depth d11 for N is the same depth as the injection depth d12 for Mg, or is deeper than the injection depth d12 for Mg.

[0022] The depth d11 from the surface 10a to the bottom surface of the N implantation layer L11 is preferably 1 to 5 times, more preferably 1 to 4 times, the depth d12 from the surface 10a to the bottom surface of the Mg implantation layer L12. Thereby, it becomes easy to suppress the Mg diffusion in the depth direction from the surface 10a of the GaN substrate 10 in the heat treatment for activating Mg described later. Note that the bottom surface of the N implantation layer L11 is a position where the N concentration becomes 1 / 10 from the N implantation peak position where the N concentration is maximum in the N implantation layer L11. The bottom surface of the Mg implantation layer L12 is a position where a pn junction surface between the p-type well region 23 shown in FIG. 1F described later and the n-type drift region 22 located therebelow is formed.

[0023] In the random implantation process of Mg in FIG. 1A, the Mg concentration at the Mg implantation peak position where the Mg concentration is maximum in the Mg implantation layer L12 is 1×10 16 cm -3 or more and 3×10 18 cm -3 or less, the implantation energy (acceleration voltage) and the dose amount of Mg are set. The Mg implantation peak position is, for example, a position at a depth of 200 nm or more and 1500 nm or less from the surface 10a of the GaN substrate 10, and as an example, it is a position at a depth of 500 nm from the surface 10a. <{

[0024] Alternatively, in the random implantation process of Mg in FIG. 1A, the Mg concentration in the entire Mg implantation layer L12 is 1×10 16 cm -3 or more and 3×10 18 cm -3 or less, the implantation energy and the dose amount of Mg may be set. The ion implantation process of Mg in FIG. 1A may be performed by single-stage ion implantation where the implantation energy is one condition, or may be performed by multi-stage ion implantation where there are a plurality of implantation energy conditions.

[0025] In the random Mg implantation step shown in Figure 1A, the Mg implantation depth d12 is preferably 200 nm or more and 2000 nm or less, and more preferably 300 nm or more and 1500 nm or less. The Mg implantation depth d12 may also be 300 nm or more and 1000 nm or less. In Figure 1A, after performing N channeling implantation and Mg random implantation, the manufacturing apparatus removes the mask M1 from the GaN substrate 10.

[0026] Next, as shown in Figure 1B, the manufacturing apparatus channel-implants nitrogen (N) and randomly implants oxygen (O) into the region 29' of the GaN substrate 10 where the JFET region 29 (see Figure 1F described later) is to be formed (hereinafter referred to as the JFET formation region). The JFET formation region 29' is an example of a "pre-set region" in this disclosure, N is an example of an "inert element" in this disclosure, and O is an example of an n-type "dopant element" in this disclosure.

[0027] For example, the manufacturing apparatus forms a mask M2 on the surface 10a of the GaN substrate 10. The mask M2 is a selectively removable SiO2 film or photoresist from the GaN substrate 10. The mask M2 has a shape that opens above the JFET formation region 29' and covers above other regions. The manufacturing apparatus channel-injects N and randomly injects O from the side of the surface 10a of the GaN substrate 10 on which the mask M2 is formed, in the depth direction.

[0028] In Figure 1B, the tilt angle θ for channeling injection is preferably -1° to 1° relative to the C axis, and more preferably -0.5° to 0.5° relative to the C axis. The tilt angle θ for random injection is preferably 4° to 10° relative to the C axis, and more preferably 6° to 8° relative to the C axis. The in-plane rotation angle (hereinafter referred to as the twist angle) for random injection of O is preferably 10° to 20°, and more preferably 14° to 16°.

[0029] In Figure 1B, the order in which N channeling injection and O random injection are performed is not particularly limited, but it is preferable to perform N channeling injection before O random injection because the crystal structure of the GaN substrate 10 is less disordered before random injection than after O random injection. By performing N channeling injection before O random injection (i.e., performing N channeling injection first, followed by O random injection), it becomes easier to inject N into a deep location from the surface 10a of the GaN substrate 10, so as to pass through the less disordered crystal lattice.

[0030] The dose of N is preferably set to 1 to 10 times the dose of O, and more preferably to 2 to 5 times. This makes it easier to suppress the diffusion of O from the surface 10a of the GaN substrate 10 in the depth direction during the heat treatment for activating O described later.

[0031] In the GaN substrate 10 shown in Figure 1B, the layer into which N is injected is defined as the N injection layer L21 (an example of the "first injection layer" in this disclosure), and the layer into which O is injected is defined as the O injection layer L22 (an example of the "second injection layer" in this disclosure). For example, the injection energy (acceleration voltage) for N is set such that the depth d21 from the surface 10a of the GaN substrate 10 to the bottom surface of the N injection layer L21 is the same depth d22 from the surface 10a of the GaN substrate 10 to the bottom surface of the O injection layer L22, or is deeper than the depth d12. That is, the injection energy for N is set such that the injection depth d21 for N is the same depth as the injection depth d22 for O, or is deeper than the injection depth d22 for O.

[0032] The depth d21 from the surface 10a to the bottom of the N-injection layer L21 is preferably 1 to 5 times, and more preferably 1 to 4 times, the depth d22 from the surface 10a to the bottom of the O-injection layer L22. This makes it easier to suppress O diffusion in the depth direction from the surface 10a of the GaN substrate 10 during the heat treatment for activating O described later. The bottom of the N-injection layer L21 is the position where the N concentration becomes 1 / 10 of the N-injection peak position where the N concentration is maximum in the N-injection layer L21. The bottom of the O-injection layer L22 is the position where the O concentration becomes 1 / 10 of the O-injection peak position where the O concentration is maximum in the O-injection layer L22.

[0033] In the random oxygen injection process shown in Figure 1B, the oxygen concentration at the oxygen injection peak position where the oxygen concentration is maximum in the oxygen injection layer L22 is 5 × 10⁻¹⁰. 16 cm -3 The above 5 x 10 17 cm -3 The injection energy (acceleration voltage) and dose of O are set as follows.

[0034] Alternatively, in the random injection process of O shown in Figure 1B, the O concentration is 5 × 10¹⁰ not only near the surface 10a of the GaN substrate 10, but also throughout the entire JFET formation region 29'. 16 cm -3 The above 5 x 10 17 cm -3 The O implantation energy and dose may be set as follows. The O ion implantation process in Figure 1B may be performed as a single-stage ion implantation with one implantation energy condition, or as a multi-stage ion implantation with multiple implantation energy conditions.

[0035] In the random implantation process of O in FIG. 1B, the implantation depth d22 of O is preferably 200 nm or more and 2000 nm or less, more preferably 300 nm or more and 1500 nm or less. The implantation depth d22 of O may be 300 nm or more and 1000 nm or less. In the random implantation process of O in FIG. 1B, O may be implanted to a deeper position than Mg implanted in the Mg random implantation process of FIG. 1A. For example, d12 < d22 may be set. In FIG. 1B, after performing N channeling implantation and O random implantation, the manufacturing apparatus removes the mask M2 from above the GaN substrate 10.

[0036] Next, as shown in FIG. 1C, the manufacturing apparatus performs channeling implantation or random implantation of nitrogen (N) into a region (hereinafter referred to as a contact formation region) 25' where a contact region 25 (see FIG. 1F described later) is to be formed in the GaN substrate 10, and randomly implants magnesium (Mg) as a p-type dopant element. When N is randomly implanted into the contact formation region 25', the contact formation region 25' is an example of the "predetermined region" of the present disclosure.

[0037] For example, the manufacturing apparatus forms a mask M3 on the surface 10a of the GaN substrate 10. The mask M3 is a SiO2 film or a photoresist that can be selectively removed with respect to the GaN substrate 10. The mask M3 has a shape that opens above the contact formation region 25' and covers other regions. The manufacturing apparatus performs channeling implantation or random implantation of N in the depth direction from the side of the surface 10a of the GaN substrate 10 on which the mask M3 is formed, and randomly implants Mg.

[0038] The tilt angle θ of the channeling implantation of N in FIG. 1C is the same as the tilt angle θ of the channeling implantation of N into the well formation region 23' described with reference to FIG. 1A. The tilt angle θ of the random implantation of N or Mg in FIG. 1C is the same as the tilt angle θ of the random implantation of Mg into the well formation region 23' described with reference to FIG. 1A.

[0039] In Figure 1C, the order in which N channeling or random injection and Mg random injection are performed is not particularly limited, but it is preferable to perform N channeling or random injection before Mg random injection because the crystal structure of the GaN substrate 10 is less disordered before random injection than after Mg random injection.

[0040] In Figure 1C, the dose of N is preferably set to 1 to 10 times the dose of Mg, and more preferably to 2 to 5 times. Furthermore, it is preferable to set the injection energy of N such that the depth from the surface 10a to the bottom of the N injection layer L31 into which N is injected in Figure 1C (i.e., the injection depth of N) is the same as or greater than the depth from the surface 10a to the bottom of the Mg injection layer L32 into which Mg is injected in Figure 1C (i.e., the injection depth of Mg). The injection depth of N is preferably 1 to 5 times the injection depth of Mg, and more preferably 1 to 4 times.

[0041] The bottom of N-injection layer L31 is located at a position where the N concentration is 1 / 10 of the N injection peak position where the N concentration is maximum in N-injection layer L31. The bottom of Mg-injection layer L32 is located at a position where the Mg concentration is 1 / 10 of the Mg concentration from the Mg injection peak position where the Mg concentration is maximum in Mg-injection layer L32.

[0042] In the random Mg injection process shown in Figure 1C, the Mg concentration in the Mg injection layer L32 is 5 × 10⁻⁶. 18 cm -3 The above 2 x 10 20 cm -3 The Mg injection energy (acceleration voltage) and dose are set as follows. The Mg peak position where the Mg concentration is maximum in the Mg injection layer L32 is, for example, a position less than 50 nm deep from the surface 10a of the GaN substrate 10. The Mg injection depth in the Mg injection layer L32 is, for example, in the range of less than 80 nm from the surface 10a of the GaN substrate 10. In Figure 1C, after channeling or random injection of N and random injection of Mg, the manufacturing apparatus removes the mask M3 from the GaN substrate 10.

[0043] Next, as shown in Figure 1D, the manufacturing apparatus channel-implants or randomly implants nitrogen (N) into the region 27' of the GaN substrate 10 where the source region 27 (see Figure 1F described later) is to be formed (hereinafter referred to as the source formation region), and randomly implants silicon (Si) as an n-type dopant element. When N is randomly implanted into the source formation region 27', the source formation region 27' becomes an example of the "pre-set region" in this disclosure.

[0044] For example, the manufacturing apparatus forms a mask M4 on the surface 10a of the GaN substrate 10. The mask M4 is a selectively removable SiO2 film or photoresist from the GaN substrate 10. The mask M4 has a shape that opens above the source formation region 27' and covers above other regions. The manufacturing apparatus channel-implants or randomly implants N and randomly implants Si from the side of the surface 10a of the GaN substrate 10 on which the mask M4 is formed, in the depth direction.

[0045] The tilt angle θ for channeling injection of N in Figure 1D is the same as the tilt angle θ for channeling injection of N into the well-forming region 23', as explained with reference to Figure 1A. The tilt angle θ for random injection of N or Si in Figure 1D is the same as the tilt angle θ for random injection of Mg into the well-forming region 23', as explained with reference to Figure 1A.

[0046] In Figure 1D, the order in which N channeling or random implantation and Si random implantation are performed is not particularly limited, but it is preferable to perform N channeling or random implantation before Si random implantation because the crystal structure of the GaN substrate 10 is less disordered before random implantation than after Si random implantation.

[0047] In Figure 1D, the dose of N is preferably set to 1 to 10 times the dose of Si, and more preferably to 2 to 5 times. Also, in Figure 1D, N is It is preferable to set the N injection energy such that the depth from the surface 10a to the bottom of the N injection layer L41 (i.e., the N injection depth) is the same as, or deeper than, the depth from the surface 10a to the bottom of the Si injection layer L42 where Si is injected in Figure 1D (i.e., the Si injection depth). The N injection depth is preferably 1 to 5 times the Si injection depth, and more preferably 1 to 4 times. The bottom of the N injection layer L41 is the position where the N concentration in the N injection layer L41 becomes 1 / 10 of the N injection peak position where the N concentration is maximum. The bottom of the Si injection layer L42 is the position where the pn junction surface is formed between the n+ type source region 27 shown in Figure 1F below and the p type well region 23 located below it.

[0048] In the random Si implantation process shown in Figure 1D, the Si concentration in the Si implantation layer L42 is 1 × 10⁻¹⁶ 19 cm -3 The above 5 x 10 20 cm -3 The Si injection energy (acceleration voltage) and dose are set as follows. In the Si injection layer L42, the Si peak position where the Si concentration is maximum is, for example, a position less than 50 nm deep from the surface 10a of the GaN substrate 10. Also, the Si injection depth in the Si injection layer L42 is, for example, in the range of less than 80 nm from the surface 10a of the GaN substrate 10. In Figure 1D, after channeling or random injection of N and random injection of Si, the manufacturing apparatus removes the mask M4 from the GaN substrate 10.

[0049] Next, the manufacturing apparatus forms an insulating protective film 30 on the surface 10a of the GaN substrate 10. The protective film 30 has the function of suppressing the release of nitrogen atoms from the GaN substrate 10 during heat treatment. Nitrogen vacancies are formed at the locations where nitrogen atoms are released from the GaN substrate 10. Since nitrogen vacancies can function as donor-type defects, the expression of p-type properties may be inhibited. To prevent this, the manufacturing apparatus provides a protective film 30 on the GaN substrate 10.

[0050] The protective film 30 preferably has high heat resistance, good adhesion to the GaN substrate 10, prevents impurities from diffusing from the protective film 30 to the GaN substrate 10, and is selectively removable from the GaN substrate 10. The protective film 30 is an aluminum nitride (AlN) film, an SiO2 film, or a silicon nitride (SiN) film. The protective film 30 may be a laminated film containing at least one of the AlN film, SiO2 film, and SiN film. In addition, an insulating film serving as a base for the protective film 30 may be provided between the GaN substrate 10 and the protective film 30. An example of the base insulating film is an SiO2 film. Note that the formation of the protective film 30 is not essential and may be omitted.

[0051] Next, the manufacturing apparatus heat-treats the GaN substrate 10 covered with the protective film 30 under the conditions of a maximum temperature of 1200°C to 1500°C, a maximum pressure of 0.1 MPa to 1 GPa, and a heat treatment time of 5 minutes to 3 hours. For example, the GaN substrate 10 may be heat-treated under the conditions of a maximum temperature of 1300°C, a maximum pressure of 500 MPa, and a heat treatment time of 60 minutes at the maximum temperature and pressure. This heat treatment is, for example, a rapid heating treatment. This heat treatment activates the dopant elements introduced into the GaN substrate 10 (for example, Mg as a p-type dopant element, and O and Si as n-type dopant elements). As a result, as shown in Figure 1E, a p-type well region 23, a p+-type contact region 25, an n+-type source region 27, and an n-type JFET region 29 are formed in the GaN substrate 10, and a drift region 22 is defined. Furthermore, this heat treatment can, to some extent, restore defects in the GaN substrate 10 caused by ion implantation. After the heat treatment, the manufacturing apparatus removes the protective film 30 from the GaN substrate 10.

[0052] Next, as shown in Figure 1F, the manufacturing apparatus forms a gate insulating film 31 on the surface 10a of the GaN substrate 10. The material constituting the gate insulating film 31 is not particularly limited, but is, for example, an SiO2 film. Next, the manufacturing apparatus forms a gate electrode 33 on the gate insulating film 31 and forms source electrodes 35 on the p+ type contact region 25 and the n+ type source region 27. The gate electrode 33 and source electrodes 35 may be formed simultaneously in the same process. The material constituting the gate electrode 33 and source electrodes 35 is not particularly limited, but is, for example, an Al film or an Al-Si alloy film. Also, before or after the formation of the gate electrode 33 and source electrodes 35, the manufacturing apparatus forms a drain electrode 37 on the back surface 10b of the GaN substrate 10. The material constituting the drain electrode 37 is not particularly limited, but is, for example, an Al film or an Al-Si alloy film. Through the above steps, a planar vertical MOSFET 1 (for example, a vertical DMOS (Double diffused MOSFET)) is completed.

[0053] The vertical MOSFET 1 shown in Figure 1F is part of a nitride semiconductor device manufactured by the manufacturing method according to this embodiment. The nitride semiconductor device has a structure in which, for example, the vertical MOSFET 1 shown in Figure 1F is used as a single unit structure, and this unit structure is repeatedly provided in the X-axis direction.

[0054] (Evaluation experiment) The Discloser conducted an experiment to compare the conductivity of p-type regions in two cases: one in which N and Mg are randomly implanted into a GaN substrate to form p-type regions (hereinafter referred to as the Comparative Example), and another in which N is channel-implanted into a GaN substrate and Mg is randomly implanted to form p-type regions (hereinafter referred to as the Example).

[0055] (1) Sample Figure 3 is a schematic cross-sectional view showing the configuration of the sample used in the experiment of this disclosure. This sample has an n-type GaN layer 110, a p-type region 123 provided in the GaN layer 110, a plurality of p+-type regions 125 provided in the p-type region 123 and arranged at equal intervals in the X-axis direction, and electrodes 135 provided on each of the p+-type regions 125. Similar to the p+-type regions 125, the electrodes 135 are also arranged at equal intervals in the X-axis direction.

[0056] In the example, a p-type region 123 was formed by channeling N into the N-injection layer L101 from the surface 10a side of the GaN layer 110, randomly injecting Mg into the Mg-injection layer L102, and then performing heat treatment. In the comparative example, a p-type region 223 was formed by randomly injecting N into the N-injection layer L101 from the surface 10a side of the GaN layer 110, randomly injecting Mg into the Mg-injection layer L102, and then performing heat treatment.

[0057] (2) Processing conditions (2.1)N injection conditions In the examples and comparative examples, the N implantation conditions were the same except for the difference between random implantation and channeling implantation. Specifically, the N implantation depth from the surface 110a of the GaN layer 110 was 700 nm, and the N concentration in the entire N implantation layer L101 was 8.9 × 10⁻¹⁴. 13 cm -3 The above 9.05 × 10 13 cm -3 N was injected in multiple stages as follows: (2.2) Mg injection conditions In the examples and comparative examples, the Mg implantation conditions were the same for both. Specifically, random Mg implantation was performed, the Mg implantation depth from the surface 110a of the GaN layer 110 was 700 nm, and the Mg concentration in the entire Mg implantation layer L102 was 1 × 10⁻¹⁶. 18 cm -3 Mg was injected in multiple stages to achieve the desired result. (2.3) Heat treatment conditions In the examples and comparative examples, the heat treatment conditions were the same. Specifically, the GaN layer 110 was heat-treated under the conditions of a maximum temperature of 1300°C, a maximum pressure of 500 MPa, and a heat treatment time of 60 minutes at the maximum temperature and pressure.

[0058] (2.4) Experimental results Figure 4 is a graph showing the experimental results of this disclosure. The vertical axis of this graph shows the average resistance (Ω) between adjacent electrodes 135 in the X-axis direction. E+ indicated on the vertical axis represents a power of 10. The horizontal axis of this graph shows the spacing between electrodes 135 in the X-axis direction, i.e., the electrode spacing (μm). As shown in Figure 4, it was confirmed that the resistance between electrodes 135 in the example was lower than that of the comparative example in the entire range of electrode spacing from 10 μm to 30 μm. The sheet resistance of the example was 1.10E+05 (Ω / □), and the sheet resistance of the comparative example was 1.26E+05 (Ω / □). From these results, it was found that the sheet resistance of the p-type region 123 can be reduced by channeling injection of N. It was also found that the example can activate Mg more effectively even with the same Mg dose as the comparative example.

[0059] (Effects of the embodiment) As described above, the method for manufacturing a nitride semiconductor device according to the embodiment of this disclosure comprises the steps of: channeling an inert element (e.g., N) into a predetermined region (e.g., a well formation region 23', a JFET formation region 29', etc.) from the surface 10a side of the GaN substrate 10; randomly implanting dopant elements (e.g., Mg, O, Si) into a predetermined region from the surface 10a side; and heat-treating the GaN substrate 10 into which the inert element and dopant element have been implanted to activate the dopant elements.

[0060] According to this method, inert elements effective in activating dopant elements can be injected with low damage into pre-set regions of the GaN substrate 10. For example, N, which is effective in activating the p-type dopant Mg, can be injected with low damage into the well-forming region 23'. This makes it possible to improve Mg activation while suppressing the increase in vacancy defects caused by N injection. Also, N, which is effective in activating the n-type dopant O, can be injected with low damage into the JFET-forming region 29'. This makes it possible to improve O activation while suppressing the increase in vacancy defects caused by N injection.

[0061] Furthermore, by ion implanting N, the downward diffusion of Mg can be suppressed. This allows the thickness (depth) of the p-type region containing Mg to be reduced, thereby suppressing the decrease in Mg concentration in the p-type region. For example, the thickness (depth) of the p+-type contact region 25 can be reduced, thereby suppressing the decrease in Mg concentration in the contact region 25.

[0062] The effects of this embodiment will be further explained using the case where Mg is used as the dopant element as an example. To realize a GaN-vertical MOSFET, it is necessary to finely create regions with different concentrations and depths by ion implantation. When Mg is ion-implanted into a GaN substrate to create a p-type region, Ga vacancies and N vacancies are generated in the Mg-implanted region. These Ga vacancies and N vacancies combine (cluster) during subsequent heat treatment, forming large double-vacancy defects. Large double-vacancy defects impair the electrical characteristics of the vertical MOSFET. As a countermeasure, there is a method of compensating for N vacancies and reducing the size of double-vacancy defects by ion-implanting N, but even with this method, new vacancy defects may be formed by the ion implantation of N, and vacancy defects may remain even after heat treatment. The persistence of vacancy defects can cause a decrease in the reliability of the vertical MOSFET and is undesirable. Therefore, in the manufacturing method according to the embodiment of this disclosure, N is channeled and implanted into the GaN substrate 10. This allows for the injection of N into the GaN substrate 10 with minimal damage, thereby suppressing the formation of vacancy defects. It enables the injection of a sufficient amount of N while suppressing the increase of vacancy defects, and also allows for the formation of a desired Mg profile for structural control.

[0063] (modified version) (1) In the embodiments of this disclosure, the p-type dopant element is not limited to Mg. The p-type dopant element may be beryllium (Be). The conditions for Mg shown in the embodiments of this disclosure are also applicable when Be is used as the p-type dopant element. Furthermore, the n-type dopant element is not limited to O or Si. The n-type dopant element may be germanium (Ge). The conditions for O and Si shown in the embodiments of this disclosure are also applicable when Ge is used as the n-type dopant element. Even in such embodiments, the effects of the above embodiments are achieved.

[0064] (2) In the embodiments of this disclosure, the inert element is not limited to N. The inert element may be argon (Ar). That is, Ar may be channeled and implanted into the well-forming region 23', the JFET region 29', etc. Even in such an embodiment, the effects of the above embodiments will be achieved.

[0065] (3) In the above embodiment, N was channeled and injected into both the well-forming region 23' and the JFET region 29'. However, embodiments of the present disclosure are not limited thereto. N may be channeled and injected into either the well-forming region 23' or the JFET region 29', and N may be randomly injected into the other. Alternatively, N may be channeled and injected into either the well-forming region 23' or the JFET region 29', and N may not be injected into the other. Even in such embodiments, in the region in which N is channeled and injected, N effective for activating the dopant element can be injected with low damage, and the activation of the dopant element can be improved while suppressing the increase in vacancy defects due to N injection.

[0066] (4) In the embodiments of this disclosure, the injection of N into the contact formation region 25' and the injection of N into the source formation region 27' may be omitted. Even in such embodiments, the effects of the above embodiments can be achieved in either the well formation region 23' or the JFET region 29' by channeling and injecting N into that region.

[0067] (5) In the above embodiments, the channeling injection of N into the well-forming region 23' and the channeling injection of N into the JFET region 29' were described to be performed separately. However, embodiments of the present disclosure are not limited thereto. The channeling injection of N into the well-forming region 23' and the JFET region 29' may be performed simultaneously. For example, in the process shown in Figure 1A, without forming a mask M1, N may be simultaneously channeled into the well-forming region 23' and the JFET region 29' with the same injection energy and the same dose. In such an embodiment, it becomes unnecessary to channel N in the process shown in Figure 1B, which may contribute to shortening the process and reducing manufacturing costs.

[0068] (6) The manufacturing method according to the embodiments of this disclosure is not limited to a vertical MOSFET with a planar structure in which a gate electrode 33 is disposed on a flat surface 10a of a GaN substrate 10 via a gate insulating film 31. The manufacturing method according to the embodiments of this disclosure may also be applied to a vertical MOSFET with a trench gate structure in which a trench is provided on the surface 10a of the GaN substrate 10 and a gate electrode is disposed in this trench via a gate insulating film. Even in such an embodiment, the same effects as in the above embodiment will be achieved.

[0069] (7) The manufacturing method according to the embodiments of this disclosure is not limited to vertical MOSFETs. The manufacturing method according to the embodiments of this disclosure may also be applied to horizontal MOSFETs in which the source region and drain region are arranged on the surface 10a side of the GaN substrate 10. Even in such an embodiment, the same effects as in the above embodiments will be achieved.

[0070] <Other Embodiments> As described above, this disclosure is described by embodiments and modifications thereof, but the statements and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure. For example, the gate insulating film 31 is not limited to an SiO2 film, but may be other insulating films. Silicon oxynitride (SiON) films, strontium oxide (SrO) films, silicon nitride (Si3N4) films, and aluminum oxide (Al2O3) films can also be used for the gate insulating film 31. Furthermore, composite films, such as those made by stacking several single-layer insulating films, can also be used for the gate insulating film 31.

[0071] Thus, this technology naturally includes various embodiments and modifications not described herein. Within the scope of the embodiments and modifications described above, at least one of various omissions, substitutions, and modifications of the components can be made. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also exist.

[0072] Furthermore, this disclosure may also adopt the following structure. (1) A process of channeling and implanting an inert element into a predetermined region from the surface side of a nitride semiconductor, A step of randomly injecting dopant elements into the predetermined region from the surface side, A method for manufacturing a nitride semiconductor device, comprising the step of subjecting the nitride semiconductor, into which the inert element and the dopant element have been implanted, to heat treatment to activate the dopant element. (2) A method for manufacturing a nitride semiconductor device according to (1), comprising the step of channeling the inert element and then randomly implanting the dopant element. (3) The method for manufacturing a nitride semiconductor device according to (1) or (2), wherein the dopant element is magnesium (Mg) or beryllium (Be). (4) The method for manufacturing a nitride semiconductor device according to (1) or (2), wherein the dopant element is oxygen (O), silicon (Si), or germanium (Ge). method. (5) The method for manufacturing a nitride semiconductor device according to any one of (1) to (4), wherein the inert element is nitrogen (N) or argon (Ar). (6) The surface of the nitride semiconductor is a C-plane, In the aforementioned random injection process, A method for manufacturing a nitride semiconductor device according to any one of (1) to (5), wherein the dopant element is ion-implanted at an inclination angle of 4° to 10° with respect to the C axis, which is the normal direction of the C plane. (7) A method for manufacturing a nitride semiconductor device according to any one of (1) to (6) above, wherein the dose amount of the inert element is 1 to 10 times the dose amount of the dopant element. (8) In the nitride semiconductor, if the layer into which the inert element is implanted is designated as the first implantation layer, and the layer into which the dopant element is implanted is designated as the second implantation layer, A method for manufacturing a nitride semiconductor device according to any one of (1) to (7), wherein the depth from the surface of the nitride semiconductor to the bottom surface of the first injection layer is 1 to 5 times the depth from the surface to the bottom surface of the second injection layer. [Explanation of Symbols]

[0073] 1. Vertical MOSFET 10 GaN substrates 10a surface 10b back side 22 Drift region 23 well area 23' Well-forming region 25 Contact area 25' Contact formation area 27 Source Area 27' Source formation region 29 JFET area 29´ JFET formation area 30 Protective film 31 Gate insulating film 33 Potatoes 35 Source Electrode 37 Drain electrode 110 GaN layer 110a surface 123, 223 p-type region 125 p+ type region 135 Electrode L11, L21, L31, L41, L101 N injection layer L12, L32, L102 Mg injection layer L22 O injection layer L42 Si injection layer M1, M2, M3, M4 Masks θ Tilt angle (hereinafter referred to as tilt angle)

Claims

1. A process of channeling and implanting an inert element into a predetermined region from the surface side of a nitride semiconductor, A step of randomly injecting dopant elements into the predetermined region from the surface side, A method for manufacturing a nitride semiconductor device, comprising the step of subjecting the nitride semiconductor, into which the inert element and the dopant element have been implanted, to heat treatment to activate the dopant element.

2. A method for manufacturing a nitride semiconductor device according to claim 1, wherein after performing the step of channeling the inert element, the step of randomly implanting the dopant element is performed.

3. The method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein the dopant element is magnesium (Mg) or beryllium (Be).

4. The method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein the dopant element is oxygen (O), silicon (Si), or germanium (Ge). method.

5. The method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein the inert element is nitrogen (N) or argon (Ar).

6. The surface of the nitride semiconductor is a C-plane, In the aforementioned random injection process, A method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein the dopant element is ion-implanted at an inclination angle of 4° to 10° with respect to the C axis, which is the normal direction of the C plane.

7. The method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein the dose amount of the inert element is 1 to 10 times the dose amount of the dopant element.

8. In the nitride semiconductor, if the layer into which the inert element is implanted is designated as the first implantation layer, and the layer into which the dopant element is implanted is designated as the second implantation layer, The method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein the depth from the surface of the nitride semiconductor to the bottom of the first injection layer is 1 to 5 times the depth from the surface to the bottom of the second injection layer.

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