Silicon carbide semiconductor equipment

Abstract

To provide a silicon carbide semiconductor device that can suppress contact resistance. [Solution] The silicon carbide semiconductor device comprises a semiconductor substrate containing silicon carbide, an insulated gate type electrode structure embedded in a first trench 8 provided in the semiconductor substrate, a trench contact 12 embedded in a second trench 11 provided in the semiconductor substrate, a second conductivity type base region provided in contact with the side surface of the first trench and the side surface of the second trench on the semiconductor substrate, a first conductivity type main electrode region provided on the upper surface side of the base region in contact with the side surface of the first trench and the side surface of the second trench, and a second conductivity type base contact region provided in contact with the bottom surface of the second trench, wherein the region of the semiconductor substrate along the side surface and bottom surface of the second trench contains silicon carbide with a 3C structure.

Description

[Technical Field]

[0001] This disclosure relates to silicon carbide semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device in which an amorphous layer is formed by ion implanting phosphorus into a hexagonal single crystal silicon carbide substrate, the amorphous layer is recrystallized into cubic single crystal n-type silicon carbide by heat treatment, and electrodes are formed by depositing nickel onto the upper surface of the n-type silicon carbide.

[0003] Patent Document 2 describes n made of 4H-SiC + n formed on the first main surface of type SiC - Within the type epitaxial growth layer, n + Type source area and n + n formed within the source region of type + Type 3C-SiC region and p + It has a type potential fixed region and n + Type 3C-SiC region and p + A semiconductor device is disclosed in which a barrier metal film is formed in contact with a fixed potential region, and source wiring electrodes are formed on the barrier metal film. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2009-49198 [Patent Document 2] International Publication No. 2017 / 042963 [Overview of the project] [Problems that the invention aims to solve]

[0005] Reducing the pitch (cell pitch) of multiple active elements arranged in a row reduces the contact area between the main electrode and the semiconductor layer, increasing the contact resistance. Thus, contact resistance can sometimes affect the miniaturization of semiconductor devices.

[0006] The purpose of this disclosure is to provide a silicon carbide semiconductor device that can suppress contact resistance. [Means for solving the problem]

[0007] To achieve the above objective, one aspect of the present disclosure is a silicon carbide semiconductor device comprising: (a) a semiconductor substrate containing silicon carbide; (b) an insulated gate type electrode structure embedded in a first trench provided in the semiconductor substrate; (c) a trench contact embedded in a second trench provided in the semiconductor substrate; (d) a base region of a second conductivity type provided in contact with the side surface of the first trench and the side surface of the second trench on the semiconductor substrate; (e) a main electrode region of a first conductivity type provided on the upper surface side of the base region in contact with the side surface of the first trench and the side surface of the second trench; and (f) a base contact region of a second conductivity type provided in contact with the bottom surface of the second trench, wherein the region of the semiconductor substrate along the side surface and bottom surface of the second trench contains silicon carbide in a 3C structure. [Effects of the Invention]

[0008] According to this disclosure, a silicon carbide semiconductor device that can suppress contact resistance can be provided. [Brief explanation of the drawing]

[0009] [Figure 1] This is a vertical cross-sectional view showing an example of an active element in a SiC semiconductor device according to the first embodiment. [Figure 2] This is an enlarged cross-sectional view of region A in Figure 1. [Figure 3] This is an explanatory diagram showing the positional relationship in a plan view of the gate trench, contact trench, and interlayer insulating film according to the first embodiment. [Figure 4]It is a cross-sectional view of a process example of a method for manufacturing a SiC semiconductor device according to the first embodiment. [Figure 5] It is a cross-sectional view of a process example of a method for manufacturing a SiC semiconductor device according to the first embodiment. [Figure 6] It is a cross-sectional view of a process example of a method for manufacturing a SiC semiconductor device according to the first embodiment. [Figure 7] It is a cross-sectional view of a process example of a method for manufacturing a SiC semiconductor device according to the first embodiment. [Figure 8] It is a cross-sectional view of a process example of a method for manufacturing a SiC semiconductor device according to the first embodiment. [Figure 9] It is a cross-sectional view of a process example of a method for manufacturing a SiC semiconductor device according to the first embodiment. [Figure 10] It is a vertical cross-sectional view showing an example of a contact trench included in a SiC semiconductor device according to the first modification of the first embodiment.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and redundant descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual ones. Also, there may be portions where the dimensional relationships and ratios are different among the drawings. Further, the embodiments shown below are examples of devices and methods for embodying the technical idea of the present disclosure, and the technical idea of the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of the constituent parts as the following.

[0011] In this specification, "first main electrode region" means a semiconductor region that is either the source region or the drain region in field-effect transistors (FETs) and electrostatic induction transistors (SITs). In insulated-gate bipolar transistors (IGBTs), "first main electrode region" means a semiconductor region that is either the source region or the collector region. In electrostatic induction thyristors (SI thyristors) and gate turn-off thyristors (GTOs), "first main electrode region" means a semiconductor region that is either the anode region or the cathode region. "Second main electrode region" means a semiconductor region that is either the source region or the drain region in FETs and SITs. In IGBTs, "second main electrode region" means the region that is either the source region or the collector region. In SI thyristors and GTOs, "second main electrode region" means a semiconductor region that is either the anode region or the cathode region. Thus, if the "first main electrode region" is the source region, then the "second main electrode region" means the drain region. If the "first main electrode region" is the source region, then the "second main electrode region" means the collector region. If the "first main electrode region" is the anode region, then the "second main electrode region" is the cathode region. By changing the bias relationship, the functions of the "first main electrode region" and the "second main electrode region" can be swapped in FETs and the like. Furthermore, in this specification, when simply referred to as the "main electrode region," it comprehensively means either the first main electrode region or the second main electrode region.

[0012] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of this disclosure. For example, if an object is rotated 90° and observed, up and down will be converted to left and right, and if it is rotated 180° and observed, up and down will be inverted and read. Also, "top surface" may be read as "front surface," and "bottom surface" may be read as "back surface."

[0013] In the following description, the case where the first conductivity type is n-type and the second conductivity type is p-type will be exemplarily described. However, the conductivity types may be selected in the reverse relationship, i.e., the first conductivity type may be p-type and the second conductivity type may be n-type. Also, the “+” and “-” attached to “n” and “p” mean semiconductor regions with relatively higher or lower impurity densities, respectively, compared to the semiconductor regions without the attached “+” and “-”. However, even for semiconductor regions with the same “n” attached, it does not mean that the impurity densities of the respective semiconductor regions are exactly the same. Furthermore, in the following description, members and regions with the limitation of “the first conductivity type” and “the second conductivity type” added, even without specific explicit limitation, technically and logically self-evidently mean members and regions made of semiconductor materials.

[0014] In addition, SiC crystals have crystal polymorphs, and the main ones are cubic 3C, and hexagonal 4H and 6H. The reported values of the bandgap at room temperature are 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. In the following description, the cases mainly using 4H-SiC and 3C-SiC will be exemplified.

[0015] [First Embodiment] ≪Structure of SiC Semiconductor Device≫ As a silicon carbide semiconductor device (SiC semiconductor device) according to the first embodiment, a trench gate type MOSFET will be described as an example. FIG. 1 shows a vertical cross-section viewed from the B-B direction of FIG. 3.

[0016] As shown in FIG. 1, the SiC semiconductor device according to the first embodiment includes a semiconductor substrate 16. The semiconductor substrate 16 is, for example, composed of a silicon carbide (SiC) substrate.

[0017] The semiconductor substrate 16 includes a drift layer 2 of the first conductivity type (n - -type). On the upper surface side of the drift layer 2, base regions 6a and 6b of the second conductivity type (p - -type) are provided. The lower surfaces of the base regions 6a and 6b are in contact with the upper surface of the drift layer 2. On the upper surface side of the base regions 6a and 6b, regions of the first conductivity type (n +A first main electrode region (source region) 7a, 7b of type 6 is provided. The lower surfaces of the source regions 7a, 7b are in contact with the upper surfaces of the base regions 6a, 6b. The impurity concentration in the source regions 7a, 7b is higher than that of the drift layer 2.

[0018] Multiple trenches (gate trenches) 8 are provided in parallel and spaced apart from each other on the upper surface of the semiconductor substrate 16. The multiple gate trenches 8 have the same width and depth. The gate trenches 8 are first trenches provided from the upper surface of the semiconductor substrate 16 in the depth direction perpendicular to the upper surface of the semiconductor substrate 16. The gate trenches 8 penetrate the source regions 7a, 7b and the base regions 6a, 6b to reach the drift layer 2. As shown in Figures 1 and 2, the sides (side walls) of the gate trenches 8 are in contact with the sides of the source regions 7a, 7b, the base regions 6a, 6b and the drift layer 2. As shown in Figure 1, a gate bottom protection region 3 is provided at the bottom of the gate trench 8. The gate bottom protection region 3 has a higher impurity concentration than the base regions 6a, 6b, and is a second conductivity type (p + This is a semiconductor region of type (type) and is located inside the drift layer 2.

[0019] A gate insulating film 9 is provided so as to cover the bottom (underside) and sides of the gate trench 8. As the gate insulating film 9, a single layer film of any one of the following can be used: silicon dioxide film (SiO2 film), silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, or bismuth oxide (Bi2O3) film, or a multilayer film made by stacking multiple of these films.

[0020] A gate electrode 10 is embedded inside the gate trench 8, with a gate insulating film 9 interposed therebetween. The gate insulating film 9 and the gate electrode 10 constitute an insulated gate type electrode structure (9,10). As the material for the gate electrode 10, for example, a polysilicon film (doped polysilicon film) with high impurity concentrations of impurities such as phosphorus (P) or boron (B) can be used.

[0021] Furthermore, some of the multiple insulated gate electrode structures (9,10) may be gate trench sections connected to the gate runner, while the remaining insulated gate electrode structures (9,10) may be dummy trench sections not connected to the gate runner.

[0022] Between adjacent gate trenches 8, a mesa region is provided, which is formed from the upper part of the semiconductor substrate 16. The mesa region is the area of ​​the semiconductor substrate 16 sandwiched between adjacent gate trenches 8, and is the area above the deepest point of the gate trenches 8. The mesa regions between multiple gate trenches 8 have the same width. The mesa region includes the upper part of the drift layer 2, the embedded region 4, the base contact region 5, the base regions 6a and 6b, and the source regions 7a and 7b.

[0023] A trench (contact trench) 11 is provided in the mesa portion of the semiconductor substrate 16. The contact trench 11 is a second trench provided in the depth direction perpendicular to the upper surface of the mesa portion of the semiconductor substrate 16. As shown in Figure 2, the cross-sectional shape of the contact trench 11 is rectangular, and the angle θ formed by the side surface S2 and the bottom surface S3 is, for example, about 90°. Similarly, the angle formed by the side surface S1 and the bottom surface S3 is also about 90°. As shown in Figure 1, the depth of the contact trench 11 is shallower than the gate trench 8. The width of the contact trench 11 is about 0.1 μm or more and 2 μm or less.

[0024] The contact trench 11 penetrates the source regions 7a, 7b and the base regions 6a, 6b to reach the base contact region 5. The bottom surface S3 of the contact trench 11 may be at the same depth as or slightly deeper than the bottom surface of the base regions 6a, 6b. The base contact region 5 has a higher impurity concentration than the base regions 6a, 6b, and is of the second conductivity type (p + This is a semiconductor region of type 3C. As shown in Figure 2, the sides S1 and S2 (sidewalls) of the contact trench 11 are in contact with the sides of the source regions 7a and 7b and the base regions 6a and 6b. The bottom surface S3 (bottom surface) of the contact trench 11 is in contact with the base contact region 5. In the left-right direction of Figure 2, the width of the base contact region 5 is wider than the width of the bottom surface S3 of the contact trench 11, and the upper surface of the portion of the base contact region 5 that is not in contact with the bottom surface S3 is in contact with the lower surfaces of the base regions 6a and 6b. The region of the semiconductor substrate 16 along the sides S1 and S2 and the bottom surface S3 of the contact trench 11 contains silicon carbide in a 3C structure.

[0025] As shown in Figure 1, the lower surface of the base contact region 5 has a second conductivity type (p) with a lower impurity concentration than the base contact region 5. + An embedded area 4 of a specific type is provided. The upper surface of the embedded area 4 is in contact with the lower surface of the base contact area 5. The side surface of the base contact area 5, and the side surface and lower surface of the embedded area 4 are in contact with the drift layer 2.

[0026] The gate trenches 8 may have a planar pattern extending in a stripe-like manner in the depth and front directions of the plane of Figure 1, or they may have a dot-like planar pattern. The contact trenches 11 are provided between two adjacent gate trenches 8. Figure 3 shows the gate trenches 8 extending in a stripe-like manner. The contact trenches 11 are provided spaced apart from the gate trenches 8. The gate trenches 8 and contact trenches 11 are arranged alternately in a stripe-like manner in the left-right direction of Figure 3. Note that the number of gate trenches 8 and contact trenches 11 is not limited to that shown in Figure 3. The SiC semiconductor device according to the first embodiment can be made into a power semiconductor device (power device) that can carry a large current by arranging a plurality of unit cells including gate trenches 8 to form a multi-channel structure.

[0027] As shown in Figure 1, a conductive portion (trench contact) 12 is embedded in the contact trench 11. The conductive portion 12 is made of, for example, a metallic material. The conductive portion 12 mainly consists of, for example, tungsten (W) or aluminum (Al).

[0028] An interlayer insulating film 13 is selectively provided on the upper surface of the insulated gate electrode structure (9,10). The interlayer insulating film 13 is composed of single-layer films such as silicon oxide films doped with boron (B) and phosphorus (P) (BPSG films), silicon oxide films doped with phosphorus (P) (PSG films), undoped silicon oxide films that do not contain phosphorus (P) or boron (B) and are called "NSG", silicon oxide films doped with boron (B) (BSG films), silicon nitride films (Si3N4 films), or laminated films made by stacking multiple such films. As shown in Figure 3, the edges of the interlayer insulating film 13 have irregularities in a plan view. For example, the convex edges completely cover the source regions 7a and 7b, while the concave edges do not completely cover the source regions 7a and 7b, leaving a portion of the upper surface of the source regions 7a and 7b exposed.

[0029] As shown in Figure 1, a first main electrode (source electrode) 14 is provided so as to cover the source regions 7a, 7b and the upper surface of the conductor portion 12 that are exposed between the interlayer insulating films 13. The lower surface of the source electrode 14 is in contact with the upper surface of the source regions 7a, 7b and the conductor portion 12, and is electrically conductive. The source electrode 14 is provided separately from the gate wiring electrode (not shown) which is electrically connected to the gate electrode 10. The source electrode 14 may have a laminated structure of a lower barrier metal layer and an upper source wiring electrode. The barrier metal layer is made of a metal such as titanium nitride (TiN), titanium (Ti), or a TiN / Ti laminated structure with Ti as the lower layer. The source wiring electrode is made of a metal such as aluminum (Al), aluminum-silicon (Al-Si), aluminum-copper (Al-Cu), or copper (Cu). The conductor portion 12 and the source electrode 14 described above may be integrally constructed from the same material.

[0030] On the lower side of the drift layer 2, a first conductivity type (n) with a higher impurity concentration than the drift layer 2 is present. + A second main electrode region (drain region) 1 of type n is provided. The drain region 1 is made of a semiconductor substrate (SiC substrate) made of SiC. A dislocation conversion layer or a recombination promotion layer may be provided between the drift layer 2 and the drain region 1, which is an n-type buffer layer with a higher impurity concentration than the drift layer 2 and a lower impurity concentration than the drain region 1.

[0031] A second main electrode (drain electrode) 15 is provided on the lower side of the drain region 1. For the drain electrode 15, a single layer film made of gold (Au), or a metal film stacked in the order of titanium (Ti), nickel (Ni), and Au from the drain region 1 side can be used, and a metal film of molybdenum (Mo), tungsten (W), etc. may be stacked as the bottom layer. Furthermore, nickel silicide (NiSi) is provided between the drain region 1 and the drain electrode 15 for ohmic contact. x A drain contact layer such as a film may be provided. When simply referred to as "main electrode," it comprehensively means either the first main electrode (source electrode) 14 or the second main electrode (drain electrode) 15.

[0032] Figure 2 shows an enlarged view of the dashed-dotted region A surrounding the contact trench 11 in Figure 1. Of the source region 7a, the region along the side surface S1 of the contact trench 11 is called the first source region 71a, and the region other than the first source region 71a is called the second source region 72a. Of the source region 7b, the region along the side surface S2 of the contact trench 11 is called the first source region 71b, and the region other than the first source region 71b is called the second source region 72b. One side of the first source regions 71a and 71b is in contact with the sides S1 and S2 of the contact trench 11, and the other side is in contact with one side of the second source regions 72a and 72b. The other side of the second source regions 72a and 72b is in contact with the gate trench 8.

[0033] Of the base region 6a, the region along the side surface S1 of the contact trench 11 is called the first base region 61a, and the region other than the first base region 61a is called the second base region 62a. Of the base region 6b, the region along the side surface S2 of the contact trench 11 is called the first base region 61b, and the region other than the first base region 61b is called the second base region 62b. One side of the first base regions 61a and 61b is in contact with the sides S1 and S2 of the contact trench 11, and the other side is in contact with one side of the second base region 62a and 62b. The other side of the second base regions 62a and 62b is in contact with the gate trench 8.

[0034] Of the base contact region 5, the region along the bottom surface S3 of the contact trench 11 is called the first base contact region 51, and the region other than the first base contact region 51 is called the second base contact region 52. The upper surface of the first base contact region 51 is in contact with the bottom surface S3 of the contact trench 11, and the lower surface is in contact with the upper surface of the second base contact region 52.

[0035] The first source regions 71a, 71b, the first base regions 61a, 61b, and the first base contact region 51 are regions containing 3C-SiC (3C structure). The first source regions 71a, 71b, the first base regions 61a, 61b, and the first base contact region 51 may be a mixed crystal of 3C-SiC and 4H-SiC (4C structure). In addition to 3C-SiC, the first source regions 71a, 71b, the first base regions 61a, 61b, and the first base contact region 51 may also contain amorphous structures, 4H-SiC, etc. 3C-SiC has a narrower band gap than 4H-SiC. Therefore, by including 3C-SiC, the first source regions 71a, 71b, the first base regions 61a, 61b, and the first base contact region 51 can be made to make ohmic contact with the conductor portion 12. Furthermore, by including 3C-SiC, contact resistance can be suppressed even when the first source regions 71a, 71b, the first base regions 61a, 61b, and the first base contact region 51 are in direct contact with the conductor portion 12, thus eliminating the need to provide a silicide film. The inclusion of 3C-SiC in the first source regions 71a, 71b, the first base regions 61a, 61b, and the first base contact region 51 suppresses contact resistance with the conductor portion 12. The proportion of 3C-SiC included in the first source regions 71a, 71b, the first base regions 61a, 61b, and the first base contact region 51 is not limited to this, but may be, for example, 10% or more and 100% or less. For example, by setting the proportion of 3C-SiC included in the first source regions 71a, 71b, the first base regions 61a, 61b, and the first base contact region 51 to 10% or more, better ohmic contact with the conductor portion 12 can be achieved.

[0036] The thickness d1 between one side of the first source regions 71a, 71b and the other side, the thickness d2 between one side of the first base regions 61a, 61b and the other side, and the thickness d3 between the upper and lower surfaces of the first base contact region 51 are, for example, between 20 nm and 100 nm. Thicknesses d1, d2, and d3 may be the same or different.

[0037] The concentration of n-type impurities in the first source regions 71a and 71b is higher than the impurity concentration in the second source regions 72a and 72b. The impurity concentration in the first source regions 71a and 71b is, for example, 1 × 10⁻⁶. 18 cm -3 The above 7 x 10 19 cm -3 The following are some examples. The first source regions 71a and 71b contain, for example, phosphorus (P) or nitrogen (N) as n-type impurities. The first source regions 71a and 71b may also contain, for example, arsenic (As) as n-type impurities. The first source regions 71a and 71b may contain multiple types of known n-type impurities such as P, As, and N as n-type impurities.

[0038] The concentration of p-type impurities in the first base regions 61a and 61b is higher than the impurity concentration in the second base regions 62a and 62b. The impurity concentration in the first base regions 61a and 61b is, for example, 1 × 10⁻⁶. 18 cm -3 The above is 2 x 10 20 cm -3 The following are some examples. The first base regions 61a and 61b contain, for example, aluminum (Al) as a p-type impurity. The first base regions 61a and 61b may also contain, for example, boron (B) as a p-type impurity. The first base regions 61a and 61b may contain multiple types of known p-type impurities such as Al and B as p-type impurities.

[0039] The concentration of p-type impurities in the first base contact region 51 is higher than the impurity concentration in the second base contact region 52. The impurity concentration in the second base contact region 52 is, for example, 1 × 10⁻⁶. 18 cm -3 The above is 2 x 10 20 cm -3 The following are some examples. The first base contact region 51 contains, for example, aluminum (Al) as a p-type impurity. The first base contact region 51 may also contain, for example, boron (B) as a p-type impurity. The first base contact region 51 may contain multiple types of known p-type impurities such as Al and B as p-type impurities.

[0040] The second source regions 72a, 72b, the second base regions 62a, 62b, and the second base contact region 52 are mainly composed of 4H-SiC (4C structure). The proportion of 4H-SiC contained in the second source regions 72a, 72b, the second base regions 62a, 62b, and the second base contact region 52 is, for example, between 90% and 100%. In addition to 4H-SiC, the second source regions 72a, 72b, the second base regions 62a, 62b, and the second base contact region 52 may also contain small amounts of amorphous structure, 3C-SiC, etc.

[0041] The second source regions 72a and 72b may contain, for example, phosphorus (P) or nitrogen (N) as n-type impurities. The second source regions 72a and 72b may also contain arsenic (As) as an n-type impurity. The second base regions 62a and 62b and the second base contact region 52 may contain, for example, aluminum (Al) or boron (B) as p-type impurities.

[0042] When the SiC semiconductor device according to the first embodiment is in operation, the source electrode 14 is at ground potential, a positive voltage is applied to the drain electrode 15, and a positive voltage above the threshold is applied to the gate electrode 10. This causes an inversion layer (channel) to form on the side of the gate trench 8 in the base regions 6a and 6b, resulting in an ON state. In the ON state, current flows from the drain electrode 15 to the source electrode 14 via the drain region 1, the drift layer 2, the inversion layers in the base regions 6a and 6b, and the source regions 7a and 7b. On the other hand, if the voltage applied to the gate electrode 10 is below the threshold, no inversion layer is formed in the base regions 6a and 6b, resulting in an OFF state, and no current flows from the drain electrode 15 to the source electrode 14.

[0043] ≪Manufacturing Method for SiC Semiconductor Devices≫ Next, an example of a manufacturing method for a SiC semiconductor device according to the first embodiment will be described. More specifically, the method for forming the first source regions 71a, 71b, the first base regions 61a, 61b, and the first base contact region 51 will be mainly described. It should be noted that the manufacturing method for a SiC semiconductor device described below is just one example, and it is of course possible to realize it by various other manufacturing methods, including this modification, as long as it falls within the scope of the claims.

[0044] The formation of 4H-SiC and 3C-SiC can be achieved by changing the element to be ion-implanted, the temperature during ion implantation, the dose (impurity concentration), and the activation temperature for each region. The process cross-section shown in Figure 4 shows the drift layer 2, base regions 6a, 6b, source regions 7a, 7b, embedded region 4, and base contact region 5, which are mainly composed of 4H-SiC, before the formation of 3C-SiC. After forming these semiconductor regions, the contact trench 11 is formed. As for the formation of the base regions 6a, 6b, source regions 7a, 7b, embedded region 4, and base contact region 5, ion implantation of n-type or p-type impurities is performed on the 4H-SiC at a high temperature (e.g., around 500°C) at a concentration that does not disrupt the structure of the 4H-SiC. In this way, the base regions 6a, 6b, source regions 7a, 7b, embedded region 4, and base contact region 5 are formed while maintaining the 4H-SiC structure. The inside of the contact trench 11 shown in Figure 4 is hollow, representing the state before the conductor portion 12 is formed.

[0045] The conditions for the process shown in Figures 5 to 9 are described below. As a method for forming 3C-SiC, first, 3C-SiC is formed by ion implantation of n-type impurities (first conductivity type impurities) or p-type impurities (second conductivity type impurities) into 4H-SiC, thereby disrupting the structure of 4H-SiC and forming an amorphous structure. The temperature during ion implantation is set low in order to disrupt the structure of 4H-SiC. By performing ion implantation of high-concentration impurities at a low temperature, the structure of 4H-SiC can be disrupted. The temperature during ion implantation is set, for example, to room temperature (e.g., 20°C) or higher and 200°C or lower. The dose amounts (total dose amounts) of n-type and p-type impurities are, for example, 1 × 10⁻⁶. 15 cm -2 Set it to approximately the above.

[0046] Ion implantation of n-type and p-type impurities is selectively performed on the side surfaces S1, S2 and bottom surface S3 of the contact trench 11. n-type impurities are ion-implanted into the n-type semiconductor region, and p-type impurities are ion-implanted into the p-type semiconductor region. Ion implantation is mainly performed at shallow locations near the side surfaces S1, S2 and bottom surface S3. This allows for the formation of amorphous structures on and near the side surfaces S1, S2 and bottom surface S3 of the contact trench 11.

[0047] First, p-type impurities (e.g., Al) are ion-implanted into the base regions 6a, 6b, and base contact region 5. There are three methods for ion implantation, as shown in Examples 1 to 3 below.

[0048] <Example 1> As shown in Figure 5, Al is ion-implanted perpendicularly toward the bottom surface S3 of the contact trench 11.

[0049] <Example 2> As shown in Figure 6, Al is ion-implanted diagonally toward the lower side S1 of the contact trench 11. Then, as shown in Figure 7, Al is ion-implanted diagonally toward the lower side S2 of the contact trench 11. Alternatively, the ion implantation shown in Figure 7 may be performed first, followed by the ion implantation shown in Figure 6.

[0050] <Example 3> Perform all the ion implantation procedures shown in Figures 5, 6, and 7.

[0051] After performing ion implantation according to one of Examples 1, 2, or 3, n-type impurities (e.g., N) are ion-implanted into source regions 7a and 7b. For example, as shown in Figure 8, N is ion-implanted at an angle toward the upper side of side S1 of the contact trench 11. The angle of ion implantation with respect to the vertical is larger than that in Figure 6 of Example 2. Similarly, as shown in Figure 9, N is ion-implanted at an angle toward the upper side of side S2 of the contact trench 11. The angle of ion implantation with respect to the vertical is larger than that in Figure 7 of Example 2. Alternatively, the ion implantation shown in Figure 9 may be performed first, followed by the ion implantation shown in Figure 8.

[0052] Next, activation annealing is performed. The activation annealing temperature is, for example, between 1600°C and 1900°C. During activation annealing, the amorphous structure recrystallizes to become 3C-SiC. This allows the amorphous structure to be formed on the sides S1, S2 and bottom S3 of the contact trench 11 and in their vicinity. This allows the formation of the first source regions 71a, 71b, the first base regions 61a, 61b, and the first base contact region 51 containing 3C-SiC. Subsequently, the conductive portion 12 is formed inside the contact trench 11. The explanation of the subsequent steps is omitted.

[0053] The embedded region 4 and the base contact region 5 may be formed by ion implantation after the contact trench 11 has been formed. Alternatively, ion implantation of n-type impurities may be performed first, followed by ion implantation of p-type impurities.

[0054] <<Main effects of the first embodiment>> The following describes the main effects of the SiC semiconductor device according to the first embodiment, but first, an overview will be provided. In order to further miniaturize the unit cell, a technique for forming trench contacts by embedding electrode material in trenches provided in the SiC semiconductor substrate is being researched. By forming trench contacts, the contact area between the SiC semiconductor substrate and the source electrode can be secured even in the case of miniaturization. In addition, in order to achieve ohmic contact between the SiC semiconductor substrate and the electrode, nickel silicide (NiSi) is applied to the surface of the SiC semiconductor substrate. x It is necessary to form the electrodes after providing a silicide film such as ) ). The same applies to trench contacts; it is necessary to provide a silicide film on the inner surface of the trench before embedding the electrode material in the trench. However, providing a silicide film inside a trench is not easy.

[0055] For example, uniformly forming a silicide film on the vertical surface of a trench is not easy. There may be areas on the vertical surface where the silicide film is not formed. Also, the silicide film may not be formed at the corners of the trench. If there are areas on the inner surface of the trench where the silicide film is not formed, the contact resistance between the SiC semiconductor substrate and the trench contact will increase. Thus, simply providing a trench contact does not easily enable ohmic bonding between the trench contact and the SiC semiconductor substrate, making it difficult to reduce the cell pitch.

[0056] In contrast, according to the SiC semiconductor device of the first embodiment, the regions along the side surfaces S1, S2 and bottom surface S3 of the contact trench 11 in the semiconductor substrate 16 contain silicon carbide with a 3C structure. More specifically, the first source regions 71a, 71b, the first base regions 61a, 61b, and the first base contact region 51 contain silicon carbide with a 3C structure. Since 3C-SiC has lower contact resistance than 4H-SiC, the semiconductor substrate 16 can make ohmic contact with the conductor portion 12 with low resistance without the need for a silicide film. Therefore, contact resistance can be suppressed. This makes it possible to trench the contacts, reduce the cell pitch, and achieve further miniaturization. In addition, the reliability of the trench contacts can be improved.

[0057] According to the SiC semiconductor device of the first embodiment, 3C-SiC is formed by ion implanting n-type or p-type impurities into 4H-SiC exposed on the side surfaces S1, S2 and bottom surface S3 of the contact trench 11, and then amorphousizing it. Therefore, 3C-SiC can be formed simply and stably while keeping costs down.

[0058] According to the SiC semiconductor device of the first embodiment, by providing 3C-SiC, the unevenness of the bonding surface with the conductor portion 12 of the SiC semiconductor substrate can be reduced compared to when a silicide film is provided. This improves the adhesion between the SiC semiconductor substrate and the conductor portion 12.

[0059] <<First Modification of the First Embodiment>> The SiC semiconductor device according to the first modification of the first embodiment differs from the SiC semiconductor device according to the first embodiment in that the cross-sectional shape of the contact trench 11 is tapered (trapezoidal), as shown in Figure 10. The other components of the semiconductor device according to the first modification of the first embodiment are the same as those of the SiC semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0060] The sides of the contact trench 11 have a forward tapered shape, for example, narrowing from the opening towards the bottom surface S3. The angle θ formed by the side surface S2 and the bottom surface S3 of the contact trench 11 is, for example, greater than 90°. Similarly, the angle formed by the side surface S1 and the bottom surface S3 is also greater than 90°. By making the cross-sectional shape of the contact trench 11 tapered, it becomes easier to ion implant impurities into the side surfaces S1 and S2 of the contact trench 11. As a result, 3C-SiC can be stably formed in the side surfaces S1 and S2 and the bottom surface S3 of the contact trench 11. Furthermore, by making the cross-sectional shape of the contact trench 11 tapered, the contact area between the first source regions 71a and 71b and the first base regions 61a and 61b and the conductor portion 12 can be increased.

[0061] ≪Second Modification of the First Embodiment≫ The SiC semiconductor device according to the second modification of the first embodiment includes 3C-SiC on the upper surface S4 (Figures 2 and 3) of the source regions 7a and 7b and in their vicinity. As shown in Figure 3, a portion of the upper surface S4 of the source regions 7a and 7b is not covered by the interlayer insulating film 13 and is in direct contact with the source electrode 14, as shown in Figure 2, and is electrically conductive. By providing 3C-SiC on the upper surface S4 of the source regions 7a and 7b and in their vicinity, the source regions 7a and 7b can be electrically conductive with low resistance on both the side surface and the upper surface S4. The 3C-SiC is formed by ion implanting n-type impurities into the upper surface S4 of the source regions 7a and 7b during the process shown in Figures 8 and 9, when n-type impurities are ion implanted into the side surfaces S1 and S2.

[0062] ≪Third Modification of the First Embodiment≫ In the manufacturing method of the SiC semiconductor device according to the first embodiment, the structure of 4H-SiC was disrupted by ion implanting p-type impurities into the p-type semiconductor region and n-type impurities into the n-type semiconductor region; however, this technology is not limited to this. In the manufacturing method of the SiC semiconductor device according to the third modification of the first embodiment, in order to disrupt the structure of 4H-SiC, inert gases such as helium (He) and argon (Ar), silicon (Si), or carbon (C) are ion-implanted regardless of whether it is a p-type or n-type semiconductor region. The dose amount, temperature, and other conditions for ion implantation of the inert gas are the same as the dose amount, temperature, and other conditions for the n-type and p-type impurities shown in Figures 5 to 9. The first source regions 71a, 71b, the first base regions 61a, 61b, and the first base contact region 51 formed in this manner contain the inert gas element.

[0063] Inert gases, silicon, or carbon ions have little effect on the conductivity type of the semiconductor. Therefore, the same element can be ion-implanted regardless of whether it is a p-type or n-type semiconductor region. This eliminates the need to ion-implant different elements in the upper and lower parts of the contact trench 11's sides S1 and S2, simplifying the process.

[0064] [Other embodiments] Although the first embodiment and its variations have been described above, the discussions and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0065] For example, a MOSFET was given as an example of a semiconductor device according to the first embodiment and its modified form, n + Instead of drain region 1 of type p + This method is also applicable to insulated-gate bipolar transistors (IGBTs) with a collector region of a specific type. In addition to IGBTs alone, it is also applicable to reverse-conducting IGBTs (RC-IGBTs) and reverse-blocking insulated-gate bipolar transistors (RB-IGBTs).

[0066] Furthermore, when depositing a metallic material into a SiC semiconductor device, a barrier metal layer may be formed as appropriate. By providing a barrier metal layer, the adhesion between the metallic material and the substrate can be improved, and the diffusion of the metallic material into the semiconductor can be suppressed.

[0067] Furthermore, an n-type high-concentration layer may be provided on the upper surface of the drift layer 2, having a higher impurity concentration than the drift layer 2 and with its lower surface in contact with the upper surface of the drift layer 2. The high-concentration layer is, for example, a current diffusion layer or a storage layer. When a high-concentration layer is provided, the lower surfaces of the base regions 6a and 6b are in contact with the upper surface of the high-concentration layer. The gate trench 8 penetrates the source regions 7a and 7b and the base regions 6a and 6b to reach the high-concentration layer, and the side surface (side wall) of the gate trench 8 is in contact with the high-concentration layer. The gate bottom protection region 3 may be provided inside the high-concentration layer. The side surface of the base contact region 5 and the side surface and lower surface of the embedded region 4 may also be in contact with the high-concentration layer.

[0068] Furthermore, the configurations disclosed in the first embodiment and its variations can be combined as appropriate, within the bounds of consistency. Thus, this disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of this disclosure is determined solely by the inventive features relating to the claims that are reasonable given the above description. [Explanation of Symbols]

[0069] 1. Second main electrode region (drain region) 2 Drift Layers 3. Gate bottom protection area 4. Recessed area 5. Base contact area 6a,6b Base region 7a,7b 1st main electrode area (source area) 8. Gate trench (Trench 1) 9. Gate insulating film (insulated gate type electrode structure) 10. Grid gate (insulated gate electrode structure) 11. Contact trench (Second trench) 12 Conductor section (trench contact) 13 Interlayer insulating film 14. First main electrode (source electrode) 15. Second main electrode (drain electrode) 16 Semiconductor substrates 51. First base contact area 52 Second base contact area 61a, 61b First base region 62a, 62b Second base region 71a, 71b First source area 72a, 72b Second source area S1,S2 side S3 Bottom S4 top

Claims

1. A semiconductor substrate containing silicon carbide, An insulated gate type electrode structure embedded in a first trench provided in the semiconductor substrate, A trench contact embedded in a second trench provided in the semiconductor substrate, The semiconductor substrate is provided with a second conductive base region in contact with the side surface of the first trench and the side surface of the second trench, A first conductivity type main electrode region is provided on the upper surface of the base region, in contact with the side surface of the first trench and the side surface of the second trench, A second conductive base contact region provided in contact with the bottom surface of the second trench, Equipped with, The region along the side surface and the bottom surface of the second trench of the semiconductor substrate contains silicon carbide with a 3C structure. Silicon carbide semiconductor device.

2. The region along the side surface of the second trench, in each of the base region and the main electrode region, contains silicon carbide with a 3C structure. The region of the base contact area along the bottom surface of the second trench contains silicon carbide with a 3C structure. The silicon carbide semiconductor device according to claim 1.

3. The cross-sectional shape of the second trench is rectangular or trapezoidal. The silicon carbide semiconductor device according to claim 1 or 2.

4. The impurity concentration contained in the aforementioned main electrode region is 1 × 10 １８ cm －３ The above 7 x 10 １９ cm －３ The following: The impurity concentration in the aforementioned base region and the impurity concentration in the aforementioned base contact region are 1 × 10 １８ cm －３ The above is 2 x 10 ２０ cm －３ The following is: The silicon carbide semiconductor device according to claim 2.

5. The region along the side surface and bottom surface of the second trench in the semiconductor substrate includes silicon carbide with a 3C structure and silicon carbide with a 4H structure. The silicon carbide semiconductor device according to claim 1.

6. The base region and the main electrode region, respectively, and the base contact region contain an inert gas element. The silicon carbide semiconductor device according to claim 2.

7. The trench contact comprises aluminum or tungsten. The silicon carbide semiconductor device according to claim 1 or 2.

8. Silicon carbide with a 3C structure is formed by amorphous silicon carbide with a 4H structure. The silicon carbide semiconductor device according to claim 1 or 2.

9. The upper surface of the main electrode region contains silicon carbide with a 3C structure. The silicon carbide semiconductor device according to claim 1 or 2.

10. The system has multiple of the aforementioned first trenches, The second trench is located between two adjacent first trenches. The silicon carbide semiconductor device according to claim 1 or 2.

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