Information processing device and information processing method

Abstract

This allows for reduced processing time while maintaining the processing accuracy of analog-to-digital conversion. [Solution] According to the present disclosure, an information processing device is provided, comprising: a cell array having cells that output a calculated voltage to a signal line based on an input signal and a coefficient to be held; an analog-to-digital converter that outputs a digital value based on a ramp voltage and the voltage of the signal line; and a voltage control unit that controls the voltage range of the ramp voltage.

Description

Technical Field

[0001] The present disclosure relates to an information processing apparatus and an information processing method.

Background Art

[0002] In analog CIM (Computing in Memory) using a single-slope ADC (SS-ADC), a technique of changing the range of the single-slope ADC in two stages and repeating analog-to-digital conversion twice is generally known. In this technique, in the first stage, analog-to-digital conversion is performed at full scale with low resolution, and in the second stage, the processing range is limited and analog-to-digital conversion is performed at high resolution (see Patent Document 1 and Non-Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Non-Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, even when the input value can be detected in one stage, it is necessary to repeat analog-to-digital conversion twice, resulting in a long processing time. In addition, as the processing time becomes longer, the energy consumption associated with the comparator current and the leakage current increases. [[ID=四十七]]

[0006] Therefore, this disclosure provides an information processing device and an information processing method that can suppress processing time while maintaining the processing accuracy of analog-to-digital conversion processing. [Means for solving the problem]

[0007] To solve the above problems, according to this disclosure, A cell array having cells that output a calculated voltage to a signal line based on an input signal and a coefficient to be held, An analog-to-digital converter that outputs a digital value based on the lamp voltage and the voltage of the signal line, A voltage control unit that controls the voltage range of the lamp voltage, An information processing device is provided that includes the following features.

[0008] The system further includes a first storage unit that stores setting information regarding the voltage range, The voltage control unit may control the voltage range based on the setting information.

[0009] The aforementioned setting information may include at least information about the starting voltage of the lamp voltage.

[0010] The system may further include a setting unit that sets the setting information based on at least one of the coefficient and the voltage of the signal line input to the analog-to-digital converter.

[0011] A lamp voltage generator that generates the aforementioned lamp voltage may be further provided.

[0012] The system may further include a determination unit for determining the completion of the conversion of the signal line voltage to a digital value.

[0013] The lamp voltage generator may stop or suppress voltage generation based on the determination of the determination unit.

[0014] The analog-to-digital converter may further include a comparator that compares the lamp voltage with the voltage of the signal line and outputs a first signal having information indicating a match when they match.

[0015] The determination unit may execute the determination based on the first signal.

[0016] The analog-to-digital converter further includes a latch that inputs a counter value and stores the counter value based on the first signal. The determination unit may execute the determination based on the counter value held by the latch.

[0017] The determination unit may use, as a condition for the determination, that the counter value held by the latch does not change.

[0018] The setting unit may include, in the setting information, information regarding the counter value corresponding to the start voltage of the lamp voltage.

[0019] The analog-to-digital converter further includes a counter that stops changing the counter value based on the first signal. The determination unit may execute the determination based on the counter value of the counter.

[0020] The setting unit may include, in the setting information, information regarding the counter value corresponding to the start voltage of the lamp voltage.

[0021] In the cell array, a plurality of cells including the cell are arranged in n rows and m columns (n and m are natural numbers), and each of the plurality of cells outputs an arithmetic voltage to a signal line for each column based on an input signal and a coefficient to be held. The analog-to-digital converter has a plurality of comparators respectively connected to the signal lines for each column. Each of the plurality of comparators may compare the lamp voltage with the voltage of the corresponding signal line and output a first signal having information indicating a match when they match.

[0022] The determination unit may execute the determination based on the first signals output by each of the plurality of comparators.

[0023] The setting unit may set the range of the start voltage and the end voltage of the lamp voltage based on the plurality of coefficients stored in each of the plurality of cells and the input signal to be input to the plurality of cells.

[0024] The setting unit may set the range of the start voltage and the end voltage of the lamp voltage based on the voltage of the signal line for each column.

[0025] The start voltage may be set based on a predetermined offset voltage as well.

[0026] In order to solve the above problems, according to the present disclosure, a step of outputting an arithmetic voltage to a signal line based on an input signal and a coefficient to be held; an analog-to-digital conversion step of outputting a digital value based on a lamp voltage and the voltage of the signal line; a voltage control step of controlling the voltage range of the lamp voltage; An information processing method including these is provided.

Brief Description of Drawings

[0027] [Figure 1] A diagram showing a configuration example of an information processing apparatus. [Figure 2] A configuration diagram showing a connection example of an analog-to-digital converter and an ADC state determination circuit. [Figure 3] A diagram showing the distribution of output values when performing the product-sum operation process of NN. [Figure 4] A diagram schematically showing the voltage range generated by the schedule creation unit. [Figure 5]A time chart based on the schedule generated by the scheduling department. [Figure 6] A time chart showing an example of processing in an ADC state determination circuit. [Figure 7] This figure shows an example of the configuration of an ADC state determination circuit according to Modification 1 of the first embodiment. [Figure 8] A time chart showing an example of processing of an ADC state determination circuit according to Modification 1 of the First Embodiment. [Figure 9] A diagram showing the range of analog calculation output values ​​and the range of analog calculation output values ​​after actual calculation. [Figure 10] A time chart showing an example of how the voltage generation period of a lamp voltage generator can be changed. [Figure 11] A flowchart showing an example of processing by the information processing device 1 according to the second embodiment. [Figure 12] A diagram showing an example of the configuration of an information processing device according to Modification 1 of the second embodiment. [Figure 13] A diagram showing an example configuration of an information processing device according to the third embodiment. [Figure 14] A diagram showing an example of the connection between an analog-to-digital converter and an ADC state determination circuit. [Figure 15] This figure shows an example of the configuration of an ADC state determination circuit according to Modification 1 of the third embodiment. [Figure 16] A diagram showing an example configuration of an information processing device according to the fourth embodiment. [Modes for carrying out the invention]

[0028] Embodiments of the information processing apparatus and information processing method will be described below with reference to the drawings. The following description will focus on the main components of the information processing method, information processing apparatus, and information processing method, but there may be components and functions of the information processing apparatus and information processing method that are not shown or described. The following description does not exclude any components or functions not shown or described.

[0029] (First Embodiment) Figure 1 shows an example of the configuration of the information processing device 1 according to this embodiment. The information processing device 1 is a device capable of performing calculations using analog CIM (Computing in Memory), and is composed of, for example, a plurality of circuit blocks formed on a semiconductor substrate.

[0030] As shown in Figure 1, the information processing device 1 comprises a cell array 10, an analog-to-digital converter 20, a clock 22, a schedule creation unit 24, a schedule storage unit 26, an ADC setting change circuit 28, an input storage unit 30, a coefficient storage unit 32, a decoder 34, a shift adder 36, a control circuit 38, and an ADC state determination circuit 40. In this implementation configuration, the analog-to-digital converter (ADC) may be simply referred to as ADC.

[0031] The cell array 10 is an array capable of performing arithmetic processing using analog CIM. The cell array 10 has multiple cells 100 arranged in an N row and M column configuration. N and M are arbitrary natural numbers. In Figure 1, it is configured with 10 rows and 3 columns, but is not limited to this. Each row corresponds to a bit.

[0032] Cell 100 is a processing engine (PE) and includes, for example, a memory unit 102, a logic circuit 104, and a capacitor 106. Word lines L1 and input lines L2 are connected to cell 100 in the row direction, and bit lines L3 and ADC lines L4 are connected in the column direction. The cell array 10 is not limited to the configuration of cell 100 and only needs to be capable of arithmetic processing by analog CIM.

[0033] The memory unit 102 is, for example, a latch, and stores a coefficient set via the word line L1 based on the input of the bit line L3. The memory unit 102 is not limited to a latch, and can utilize other types of memory such as DRAM, RRAM, STT-MRAM, PCM, Flash, or FeFET.

[0034] The logic circuit 104 is, for example, a logical OR circuit, and multiplies the coefficient stored in the memory unit 102 by the input value included in the input signal input via the input line L2, and stores the result in the capacitor 106. As a result, the capacitor 106 outputs a calculated voltage, which is proportional to the product of the input value and the coefficient, as an output signal to the ADC line L4. In this way, the cell 100 outputs a calculated voltage to the signal line, the ADC line L4, based on the input signal and the stored coefficient.

[0035] The analog-to-digital converter 20 is, for example, a single-slope analog-to-digital converter (SS-ADC), which outputs a digital value based on the voltage input via each ADC line L4 and the ramp voltage. This analog-to-digital converter 20 includes a ramp voltage generator 202, a counter 204, a plurality of comparators 206, and a plurality of latches 208. Further details of the analog-to-digital converter 20 will be described later.

[0036] Clock 22 generates a clock signal and supplies it to the ramp voltage generator 202 and the counter 204. The ramp voltage generator 202 and the counter 204 operate in synchronization with the clock signal.

[0037] The schedule creation unit 24 generates the supply start time when the lamp voltage generator 202 begins supplying the lamp voltage, the lamp voltage at the supply start time, and the supply end time when the supply ends. Furthermore, the schedule creation unit 24 generates an offset count value corresponding to the supply start time. Details of the schedule creation unit 24 will be described later. The schedule creation unit 24 sets setting information based on at least one of the coefficients stored in the coefficient storage unit 32 (described later) and the voltage of each ADC line L4 input to the analog-to-digital converter 20. The schedule creation unit 24 may also generate a counter value corresponding to the supply start time and a counter value corresponding to the supply end time. In this embodiment, the schedule creation unit 24 corresponds to the setting unit.

[0038] The schedule storage unit 26 stores the schedule generated by the schedule creation unit 24. Specifically, the schedule storage unit 26 stores setting information regarding the range of the lamp voltage of the lamp voltage generator 202. This setting information includes at least the starting voltage information of the lamp voltage. The schedule storage unit 26 also supplies the stored schedule to the ADC setting change circuit 28. In this embodiment, the schedule storage unit 26 corresponds to the first storage unit.

[0039] The ADC setting change circuit 28 executes control on the lamp voltage generator 202 and counter 204 according to the schedule. Specifically, the ADC setting change circuit 28 controls the voltage range of the lamp voltage generator 202 based on the setting information regarding the voltage range of the lamp voltage stored in the schedule storage unit 26.

[0040] More specifically, the ADC setting change circuit 28 starts supplying a predetermined lamp voltage at the start of supply. In this case, the ADC setting change circuit 28 starts supplying the lamp voltage based on the start of supply and the lamp voltage at the start of supply. Alternatively, the ADC setting change circuit 28 may start supplying the lamp voltage based on a counter value corresponding to the start of supply. In this embodiment, the ADC setting change circuit 28 corresponds to the voltage control unit.

[0041] The input storage unit 30 stores the input values ​​for each cell 100. The coefficient storage unit 32 stores the coefficients to be stored in the storage unit 102 of each cell 100. In this way, the coefficients held in the storage unit 102 of cell 100 are rewritten based on the coefficients stored in the coefficient storage unit 32, and an input voltage related to the input value propagating through the neural network is supplied based on the data in the input storage unit 3.

[0042] The decoder 34 is connected to the word line L1 and input line L2 of each cell 100. The decoder 34 can apply any voltage to each cell 100 based on the data stored in the input storage unit 30 and the coefficient storage unit 32. That is, the decoder 34 applies a coefficient voltage to each cell 100 based on the coefficient value stored in the coefficient storage unit 32. As a result, the coefficient is stored in the storage unit 102 of each cell 100.

[0043] Furthermore, the decoder 34 applies an input voltage to each cell 100 based on the input value stored in the input memory unit 30. As a result, the product of the input and coefficient of each cell 100 is calculated, and the sum in the column direction is output as a signal voltage to the comparator 206 of the analog-to-digital converter 20 via the ADC line L4.

[0044] The shift adder 36 adds an offset count value corresponding to the start time of supply to the output of each latch 208 when the counter 204 starts from 0. Alternatively, when the counter 204 starts from an offset count value, it is possible to proceed with processing without adding the offset count value to the output of each latch 208.

[0045] Furthermore, the shift adder 36 performs processing such as shift addition and activation of the sum-of-products values ​​as needed. The shift adder 36 stores the calculation result in the input storage unit 30.

[0046] The control circuit 38 controls each circuit of the information processing device 1. The control circuit 38 is composed of, for example, a CPU (Central Processing Unit). The ADC state determination circuit 40 determines the processing state of the analog-to-digital converter 20.

[0047] Here, referring to Figure 2 and based on Figure 1, the details of the analog-to-digital converter 20 and the ADC state determination circuit 40 will be explained. Figure 2 is a configuration diagram showing an example of the connection between the analog-to-digital converter 20 and the ADC state determination circuit 40.

[0048] The ADC status determination circuit 40 determines the completion of the conversion of the voltage on the signal line, ADC line L4, to a digital value. In this embodiment, the ADC status determination circuit 40 corresponds to the determination unit.

[0049] The ramp voltage generator 202 of the analog-to-digital converter 20 is a circuit that generates a ramp signal, and its output terminal is connected to the inverting terminal of each comparator 206. Each ADC line L4 is connected to the non-inverting terminal of each comparator 206.

[0050] The output terminal of each comparator 206 is connected to the corresponding input terminal of each latch 208. The output terminal of each comparator 206 is also connected to the input terminal of the ADC state determination circuit 40. The input terminal of each latch 208 is connected to the output terminal of the counter 204. The output terminal of each latch 208 is connected to the shift adder 36.

[0051] The output terminal of clock 22 is connected to the input terminals of the lamp voltage generator 202 and counter 204. The output terminal of ADC setting change circuit 28 is also connected to the input terminals of the lamp voltage generator 202 and counter 204.

[0052] With this configuration, the lamp voltage generator 202 starts supplying a predetermined lamp voltage at the start of supply, in accordance with the control of the ADC setting change circuit 28. Also, the counter 204 starts supplying counter voltage at the start of supply.

[0053] The ramp voltage gradually increases from the ramp voltage at the start of supply. Comparator 206 outputs a first signal whose output inverts when the signal voltage, which is the analog calculation output supplied from ADC line L4, and the ramp voltage become the same voltage.

[0054] The output of comparator 206 is input to latch 208. Latch 208 receives a code value from counter 204 indicating the current count value, and holds the code value when the output of comparator 206 is inverted. After the analog-to-digital converter 20 has finished processing, latch 208 outputs the code value, which is the digital output, to shift adder 36.

[0055] The ADC status determination circuit 40 makes a determination based on the first signal output by each comparator 206. More specifically, the ADC status determination circuit 40 determines that the ADC has finished in all columns when the output values ​​of each comparator 206 are reversed.

[0056] For example, if the output value of each comparator 206 inverts from a high level to a low level, the ADC state determination circuit 40 outputs, for example, the negated OR of the output signals of each comparator 206 as a signal. As a result, the ADC state determination circuit 40 outputs a high-level signal when each comparator 206 holds a code value. Alternatively, if the output value of each comparator 206 inverts from a low level to a high level, the ADC state determination circuit 40 outputs, for example, the logical AND of the output signals of each comparator 206 as a signal.

[0057] The ADC status determination circuit 40 changes its output value when the ADC has finished in all columns. As a result, for example, the lamp voltage generator 202 stops generating voltage. More specifically, the ADC setting change circuit 28 stops or suppresses the voltage supply to the lamp voltage generator 202 when the output value of the ADC status determination circuit 40 is changed. This also suppresses the energy consumption associated with the comparator current and leakage current of the comparator 206. In this way, the power consumption of the analog-to-digital converter 20 can be suppressed by the status determination of the ADC status determination circuit 40.

[0058] Here, the details of the schedule creation unit 24 will be explained using Figures 3 to 5. The schedule generated by the schedule creation unit 24 can be created in any way. Figure 3 is a diagram showing the distribution of output values ​​in the cell array 10 when performing a multiply-accumulate operation in a neural network (NN). The horizontal axis shows the input value to the analog-to-digital converter 20, and the vertical axis shows the frequency of occurrence. The input value to the analog-to-digital converter 20 corresponds to the signal voltage from the ADC line L4. In this embodiment, a multiply-accumulate operation in a neural network (NN) is used as an example, but the invention is not limited to this.

[0059] As shown in Figure 3, in a multiply-accumulate operation in a neural network (NN) as an example, the input voltage to the analog-to-digital converter 20 is concentrated within the voltage range of the minimum value min and the maximum value max. Therefore, the schedule creation unit 24 sets the output range of the ramp voltage generator 202 as setting information, based on the voltage range of the minimum value min and the maximum value max. The schedule creation unit 24 predicts the voltage range in advance from the structure and coefficients of the NN. More specifically, the schedule creation unit 24 generates the voltage range of the minimum value min and the maximum value max based on the possible range of input values ​​stored in the input storage unit 30 and the possible range of coefficient values ​​stored in the coefficient storage unit 32.

[0060] Furthermore, the schedule creation unit 24 may add an offset to [min, max] to reduce distortion that is likely to occur in the analog-to-digital converter 20. This makes it possible to set the output range of the ramp voltage generator 202 to [min-offset, max]. The schedule creation unit 24 also generates an offset counter value corresponding to min-offset.

[0061] Figure 4 schematically shows the voltage range generated by the schedule creation unit 24. The horizontal axis represents time, and the vertical axis represents the ramp voltage. The ramp voltage generator 202 starts outputting the ramp voltage at the supply start time ts. This ramp voltage at the supply start time ts is the minimum value min minus the offset offset, and is proportional to the time from the origin to the supply start time ts.

[0062] On the other hand, the lamp voltage generator 202 terminates its lamp voltage output at the end of supply time te. The lamp voltage is proportional to the time from the origin to the end of supply time te, and the lamp voltage of the lamp voltage generator 202 at the end of supply time te is at its maximum value max.

[0063] Figure 5 is a time chart according to the schedule generated by the schedule creation unit 24. Here, the input and output to the comparator 206 in the first column are shown.

[0064] From top to bottom, the graph shows the period during which the ramp voltage is generated according to the schedule generated by the schedule creation unit 24, the input voltage of the first column of the ADC line L4 (analog calculation output), the ramp voltage of the ramp voltage generator 202, and the output of the comparator 206.

[0065] The ADC setting change circuit 28 outputs control signals indicating the duration of the ramp voltage generation to the ramp voltage generator 202 and the counter 204. The high level indicates the voltage range of the ramp voltage generation period. Time points t1, t5, and t9 correspond to the supply start time ts, and time points t3, t7, and t11 correspond to the supply end time te.

[0066] Furthermore, the input voltage and ramp voltage indicate the voltage based on the signal magnitude. The comparator output indicates the output period at high levels and the output stop period at low levels.

[0067] At time t0, the control circuit 38 inputs the output voltage of the first column ADC line L4 to the first column comparator 206. Subsequently, at time t1, the ramp voltage generator 202 begins supplying the ramp voltage to the first column comparator 206. Simultaneously, the counter 204 begins counting.

[0068] Next, at time t2, the ramp voltage and the output voltage of the first column ADC line L4 match, and the comparator 206 outputs an inverted low signal. Then, at time t3, the ramp voltage generator 202 stops supplying the ramp voltage to the comparator 206.

[0069] Similarly, at time t4, the control circuit 38 inputs the output voltage of the first column ADC line L4 to the first column comparator 206. Subsequently, at time t5, the ramp voltage generator 202 begins supplying the ramp voltage to the comparator 206.

[0070] Next, at time t6, the lamp voltage and the output voltage of ADC line L4 match, and comparator 206 outputs an inverted low signal. Then, at time t7, the lamp voltage generator 202 stops supplying the lamp voltage to comparator 206.

[0071] Similarly, at time t8, the control circuit 38 inputs the output voltage of the third column ADC line L4 to the first column comparator 206. Subsequently, at time t9, the ramp voltage generator 202 begins supplying the ramp voltage to the comparator 206.

[0072] Next, at time t10, the lamp voltage and the output voltage of ADC line L4 match, and comparator 206 outputs an inverted low signal. Then, at time t11, the lamp voltage generator 202 stops supplying the lamp voltage to comparator 206.

[0073] Figure 6 is a time chart showing an example of the processing of the ADC state determination circuit 40. For simplicity of explanation, the cell array 10 is described using an example with N=2 rows.

[0074] From top to bottom, the output shows the input voltage of the first column of ADC line L4 (analog calculation output), the input voltage of the second column of ADC line L4 (analog calculation output), the ramp voltage of ramp voltage generator 202, the output of comparator 206 in the first column, the output of comparator 206 in the second column, and the output of ADC state determination circuit 40.

[0075] The input voltage and ramp voltage indicate voltage based on signal magnitude. The comparator output indicates the output period at high levels and the output stop period at low levels. The output of the ADC status determination circuit 40 indicates termination at high levels.

[0076] At time t12, the control circuit 38 starts the control process. At time t13, it starts inputting the output voltage of the first column ADC line L4 to the first column comparator 206, and starts inputting the output voltage of the second column ADC line L4 to the second column comparator 206.

[0077] Next, at time t14, the lamp voltage and the output voltage of the first ADC line L4 match, and the comparator 206 of the first row inverts the low signal. Next, at time t15, the lamp voltage and the output voltage of the second ADC line L4 match, and the comparator 206 of the second row inverts the low signal. The ADC state determination circuit 40 outputs a high-level signal at time t15 because both the comparator 206 of the first row and the comparator 206 of the second row have inverted their signal outputs.

[0078] Next, at time t16, the ADC setting change circuit 28 stops the voltage rise with respect to the ramp voltage generator 202 and starts the next data processing. This suppresses the energy consumption associated with the comparator current and leakage current of the comparators 206 in the first and second columns.

[0079] Similarly, at time t17, the control circuit 38 begins inputting the output voltage of the first column ADC line L4 to the first column comparator 206, and begins inputting the output voltage of the second column ADC line L4 to the second column comparator 206.

[0080] Next, at time t18, the lamp voltage and the output voltage of the first ADC line L4 match, and the comparator 206 of the first column outputs a low signal inverted. Next, at time t19, the lamp voltage and the output voltage of the second ADC line L4 match, and the comparator 206 of the second column outputs a low signal inverted. The ADC state determination circuit 40 determines that both the comparator 206 of the first column and the comparator 206 of the second column have signal outputs, so at time t19, it outputs a high-level signal.

[0081] Next, at time t20, the ADC setting change circuit 28 stops the voltage rise with respect to the ramp voltage generator 202 and starts the next data processing. This suppresses the energy consumption associated with the comparator current and leakage current of the comparators 206 in the first and second columns.

[0082] Similarly, at time t21, the control circuit 38 begins inputting the output voltage of the first column ADC line L4 to the first column comparator 206, and begins inputting the output voltage of the second column ADC line L4 to the second column comparator 206.

[0083] Next, at time t22, the lamp voltage and the output voltage of the first ADC line L4 match, and the comparator 206 of the first column outputs a low signal inverted. Next, at time t23, the lamp voltage and the output voltage of the second ADC line L4 match, and the comparator 206 of the second column outputs a low signal inverted. The ADC state determination circuit 40 determines that both the comparator 206 of the first column and the comparator 206 of the second column have signal outputs, so at time t23, it outputs a high-level signal.

[0084] Next, at time t24, the ADC setting change circuit 28 stops the voltage rise with respect to the ramp voltage generator 202 and starts the next data processing. This suppresses the energy consumption associated with the comparator current and leakage current of the first and second column comparators 206. In this way, the ADC state determination circuit 40 ends the voltage rise period of the ramp voltage generator 202 when the processing of each comparator 206 is completed, thus suppressing the energy consumption associated with the comparator current and leakage current of the first and second column comparators 206.

[0085] As described above, according to this embodiment, the schedule creation unit 24 predicts the range of the output voltage (analog calculation output) of the ADC line L4 and schedules the start voltage and end voltage of the ramp voltage generator 202 based on the output voltage range. This makes it possible to suppress processing time while maintaining the processing accuracy of the analog-to-digital conversion process of the analog-to-digital converter 20.

[0086] (Modification 1 of the first embodiment) The information processing device 1 according to Modification 1 of the First Embodiment differs from the information processing device 1 according to the First Embodiment in that the ADC state determination circuit 40 determines the state of the analog-to-digital converter 20 based on the value maintained in the latch 208. The differences from the information processing device 1 according to the First Embodiment will be explained below.

[0087] Figure 7 shows an example of the configuration of the ADC status determination circuit 40 according to Modification 1 of the First Embodiment. As shown in Figure 7, the output value of the latch 208 is input to the ADC status determination circuit 40 according to Modification 1 of the First Embodiment. The ADC status determination circuit 40 determines that the ADC has finished in all columns when all latches 208 hold code values ​​indicating the count value from the counter 204.

[0088] For example, each latch 208 outputs a high-level signal to the ADC state determination circuit 40 when it holds a code value. The ADC state determination circuit 40 also outputs a signal that is, for example, the logical AND of the output signals of each latch 208. As a result, the ADC state determination circuit 40 outputs a high-level signal when each latch 208 holds a code value.

[0089] Figure 8 is a time chart showing an example of processing of the ADC state determination circuit 40 according to Modification 1 of the First Embodiment. Here, for the sake of simplicity, the cell array 10 will be described using an example with N=2 rows.

[0090] From top to bottom, the diagram shows the input voltage of the first column of ADC line L4 (analog calculation output), the input voltage of the second column of ADC line L4 (analog calculation output), the ramp voltage of ramp voltage generator 202, the input and holding code to latch 208 of the first column, the input and holding code to latch 208 of the second column, and the output of ADC state determination circuit 40.

[0091] The input voltage and ramp voltage indicate voltage based on the signal magnitude. The input to latch 208 and the hold code indicate numerical values ​​based on the signal magnitude. A high level output from the ADC status determination circuit 40 indicates termination.

[0092] At time t25, the control circuit 38 starts the control process. At time t26, the input of the output voltage of the first column ADC line L4 to the first column comparator 206 begins, and the input of the output voltage of the second column ADC line L4 to the second column comparator 206 begins. At the same time, the output of the counter 204 to the first column latch 208 and the second column latch 208 begins.

[0093] Next, at time t27, the first latch 208 holds the counter value. Then, at time t28, the second latch 208 holds the counter value. The ADC state determination circuit 40 outputs a high-level signal at time t28 because both the first and second latches 208 hold the counter values.

[0094] Next, at time t29, the ADC setting change circuit 28 stops the voltage rise of the ramp voltage generator 202 and starts the next data processing. This suppresses the energy consumption associated with the comparator current and leakage current of the comparators 206 in the first and second columns.

[0095] Similarly, at time t30, input of the output voltage of the first column ADC line L4 to the first column comparator 206 is started, and input of the output voltage of the second column ADC line L4 to the second column comparator 206 is started. At the same time, the output of the counter 204 to the first column latch 208 and the second column latch 208 is started.

[0096] Next, at time t31, the first latch 208 holds the counter value. Then, at time t32, the second latch 208 holds the counter value. The ADC state determination circuit 40 outputs a high-level signal at time t28 because both the first and second latches 208 hold the counter values.

[0097] Next, at time t33, the ADC setting change circuit 28 stops the voltage rise of the ramp voltage generator 202 and starts the next data processing. This suppresses the energy consumption associated with the comparator current and leakage current of the comparators 206 in the first and second columns.

[0098] Similarly, at time t34, at time t12, the input of the output voltage of the first column ADC line L4 to the first column comparator 206 is started, and the input of the output voltage of the second column ADC line L4 to the second column comparator 206 is started. At the same time, the output of the counter 204 to the first column latch 208 and the second column latch 208 is started.

[0099] Next, at time t35, the first latch 208 holds the counter value. Then, at time t36, the second latch 208 holds the counter value. The ADC state determination circuit 40 outputs a high-level signal at time t39 because both the first and second latches 208 hold the counter values.

[0100] Next, at time t37, the ADC setting change circuit 28 stops the voltage rise of the ramp voltage generator 202 and starts the next data processing. This suppresses the energy consumption associated with the comparator current and leakage current of the first and second column comparators 206. In this way, the ADC state determination circuit 40 ends the voltage rise period of the ramp voltage generator 202 when the processing of each comparator 206 is completed, thus suppressing the energy consumption associated with the comparator current and leakage current of the first and second column comparators 206.

[0101] (Second Embodiment) The schedule creation unit 24 of the information processing device 1 according to the second embodiment differs from the information processing device 1 according to the first embodiment in that it can reschedule the output range of the ramp voltage of the ramp voltage generator 202 according to the range of the output voltage (analog calculation output) of the ADC line L4. The differences between the information processing device 1 according to the first embodiment and its modified examples will be described below.

[0102] Figure 9 shows the range of analog calculation output values ​​predicted in advance by the schedule creation unit 24 and the range of analog calculation output values ​​after actual calculation. Figure 9(a) shows the range of analog calculation output values ​​predicted in advance, and Figure 9(b) shows the range of analog calculation output values ​​after actual calculation. The horizontal axis represents the output voltage (analog calculation output value) of the ADC line L4, and the vertical axis represents the frequency.

[0103] As shown in Figure 9(b), the range of the analog calculation output values ​​has a smaller maximum value than the previously predicted value, and the range of the analog calculation output value distribution has narrowed. Thus, there may be a discrepancy between the range of the analog calculation output values ​​predicted in advance and the range of the actual analog calculation output values ​​after calculation.

[0104] The schedule creation unit 24 in this operational meter configuration first generates a voltage range between the minimum value min and the maximum value max by referring to the analog calculation output value stored in the input storage unit 30 (see Figure 1). Next, the schedule creation unit 24 can generate a voltage range between the minimum value min and the maximum value max based on the actual analog calculation output value after calculation.

[0105] Furthermore, the schedule creation unit 24 may add an offset to [min, max] to reduce distortion that is likely to occur in the analog-to-digital converter 20. This makes it possible to set the output range of the ramp voltage generator 202 to [min-offset, max]. The schedule creation unit 24 also generates an offset counter value corresponding to the minimum value min-offset.

[0106] The schedule creation unit 24 stores the generated schedule in the schedule storage unit 26. Subsequent processing is carried out as shown in the example time chart in Figure 10.

[0107] Figure 10 is a time chart showing an example where the voltage generation period of the lamp voltage generator 202 is changed according to the schedule generated by the schedule creation unit 24. Here, the input and output to the comparator 206 in the first column are shown.

[0108] From top to bottom, the graph shows the lamp voltage generation period (set schedule) according to the schedule generated by the schedule creation unit 24, the input voltage of the first column of the ADC line L4 (analog calculation output), the lamp voltage of the lamp voltage generator 202, and the output of the comparator 206.

[0109] The ADC setting change circuit 28 outputs control signals indicating the duration of the lamp voltage generation to the lamp voltage generator 202 and the counter 204. The high level indicates the voltage range of the lamp voltage generation period. Time points t39, t43, and t47 correspond to the supply start time ts, and time points t41, t45, and t49 correspond to the supply end time te.

[0110] The range from time t39 to time t41 and the range from time t43 to time t45 represent the voltage generation period predicted in advance by the schedule creation unit 24. On the other hand, the range from time t47 to time t49 represents the voltage generation period set by the schedule creation unit 24 after the actual calculation.

[0111] Furthermore, the input voltage and ramp voltage indicate the voltage based on the signal magnitude. The comparator output indicates the output period at high levels and the output stop period at low levels.

[0112] At time t38, the control circuit 38 inputs the output voltage of the first column ADC line L4 to the first column comparator 206. Subsequently, at time t39, the ramp voltage generator 202 begins supplying the ramp voltage to the first column comparator 206. Simultaneously, the counter 204 begins counting.

[0113] Next, at time t40, the ramp voltage and the output voltage of the first row ADC line L4 match, and the comparator 206 outputs an inverted low signal. Then, at time t41, the ramp voltage generator 202 stops supplying the ramp voltage to the comparator 206.

[0114] Furthermore, the schedule creation unit 24 determines whether the output voltage range is within the previously scheduled output range. Since it is within the previously scheduled output range, the schedule creation unit 24 maintains the output voltage range without changing it.

[0115] Similarly, at time t42, the control circuit 38 inputs the output voltage of the first column ADC line L4 to the first column comparator 206. Subsequently, at time t43, the ramp voltage generator 202 begins supplying the ramp voltage to the comparator 206.

[0116] Next, at time t44, the lamp voltage and the output voltage of ADC line L4 match, and comparator 206 outputs an inverted low signal. Then, at time t45, the lamp voltage generator 202 stops supplying the lamp voltage to comparator 206.

[0117] Furthermore, the schedule creation unit 24 determines whether the output voltage range is within the previously scheduled output range. Since the output voltage range exceeds the previously scheduled output range, the schedule creation unit 24 stores the schedule with the changed output voltage range in the schedule storage unit 26. The ADC setting change circuit 28 controls the lamp voltage generator 202 and the counter 204 with the schedule with the changed output voltage range.

[0118] Similarly, at time t46, the control circuit 38 inputs the output voltage of the third column ADC line L4 to the first column comparator 206. Subsequently, at time t47, the ramp voltage generator 202 begins supplying the ramp voltage to the comparator 206.

[0119] Next, at time t48, the lamp voltage and the output voltage of ADC line L4 match, and comparator 206 outputs an inverted low signal. Then, at time t49, the lamp voltage generator 202 stops supplying the lamp voltage to comparator 206.

[0120] In this way, the scheduling unit 24 reschedules according to the actual output voltage range. This makes it possible to perform processing of the analog-to-digital converter 20 with higher precision while suppressing processing time.

[0121] Figure 11 is a flowchart showing an example of processing of the information processing device 1 according to the second embodiment. First, the control circuit 38 obtains, for example, the coefficients of a neural network (NN) from a higher-level processing unit and stores them in the coefficient storage unit 32 (step S100).

[0122] Next, the schedule creation unit 24 uses the coefficient information stored in the coefficient storage unit 32 to pre-schedule the output voltage range of the lamp voltage generator 202, the initial generated voltage, and the offset counter of the counter 204 (step S102). Subsequently, the schedule creation unit 24 receives the scheduled information, which is the output voltage range of the lamp voltage generator 202, the initial generated voltage, and the offset counter of the counter 204, and stores it in the schedule storage unit 26 (step S104).

[0123] Next, the ADC setting change circuit 28 sets the occurrence period (setting schedule) based on the schedule stored in the schedule storage unit 26 (step S106). Subsequently, the control circuit 38 inputs the output voltage of the ADC line L4 of each column to the comparator 206 of the first column, and the ramp voltage generator 202 and counter 204 perform their operations (step S108).

[0124] The ADC status determination circuit 40 determines whether the ramp voltage has been exceeded by the calculation output of each column (step S110). If the ramp voltage of all columns has not been exceeded (No. in step S110), the operation from step S108 is repeated.

[0125] On the other hand, if the ramp voltage of all rows exceeds the calculation output, the code value stored in each latch 208 is output to the shift adder 36 and stored in the input storage unit 30 (step S112). The control circuit 38 determines whether all data processing has been completed (step S114), and if it has not been completed (No. in step S114), the schedule creation unit 24 determines whether the range of the output voltage is within the previously scheduled output range based on the output voltage stored in the input storage unit 30 (step S116).

[0126] If the output is within the output range (Yes in step S116), the schedule creation unit 24 repeats the process from step S106. On the other hand, if the output is outside the output range (Yes in step S116), the schedule creation unit 24 reschedules the output voltage range, etc., based on the output voltage stored in the input storage unit 30 (step S118), and repeats the process from step S104.

[0127] On the other hand, if the process is finished (Yes in step S114), the entire process is terminated.

[0128] As described above, according to this embodiment, the schedule creation unit 24 reschedules the output range of the ramp voltage generator 202 according to the range of the output voltage (analog calculation output) of the ADC line L4. This makes it possible to perform processing of the analog-to-digital converter 20 with higher precision while suppressing processing time.

[0129] (Modification 1 of the second embodiment) The information processing device 1 according to Modification 1 of the Second Embodiment differs from the information processing device 1 according to the Second Embodiment in that it does not have an ADC state determination circuit 40. The differences from the information processing device 1 according to the Second Embodiment will be explained below.

[0130] Figure 12 shows an example of the configuration of the information processing device 1 according to Modification 1 of the second embodiment. As shown in Figure 12, the information processing device 1 according to Modification 1 of the second embodiment differs from the information processing device 1 according to the second embodiment in that it does not have an ADC state determination circuit 40. For example, when the fluctuation of the predicted maximum value max of the lamp voltage generator 202 is small, it is possible to suppress the processing time while maintaining the processing accuracy of the analog-to-digital conversion process of the analog-to-digital converter 20, and to reduce the size of the circuit.

[0131] (Third embodiment) The information processing device 1 according to the third embodiment differs from the information processing device 1 according to the second embodiment in that it has counters for each column. The differences from the information processing device 1 according to the second embodiment will be explained below.

[0132] Figure 13 shows an example of the configuration of the information processing device 1 according to the third embodiment. As shown in Figure 13, the information processing device 1 according to the third embodiment has counters 204 configured in columns. When the output of the comparator 206 is inverted, the counter 204 stops changing the counter value and outputs the counter value to the shift adder 38 and the input storage unit 30. This makes it possible to perform the same processing as the information processing device 1 according to the second embodiment without providing a latch 208.

[0133] Here, with reference to Figure 13 and based on Figure 14, the details of the analog-to-digital converter 20 and ADC state determination circuit 40 according to the third embodiment will be described. Figure 14 is a configuration diagram showing an example of the connection between the analog-to-digital converter 20 and ADC state determination circuit 40 according to the third embodiment. Here, the differences from the information processing device 1 according to the second embodiment will be explained.

[0134] The ramp voltage generator 202 of the analog-to-digital converter 20 is a circuit that generates a ramp signal, and its output terminal is connected to the inverting terminal of each comparator 206. Each ADC line L4 is connected to the non-inverting terminal of each comparator 206.

[0135] The output terminal of the ADC setting change circuit 28 is connected to the input terminals of the lamp voltage generator 202 and each counter 204.

[0136] With this configuration, the lamp voltage generator 202 starts supplying a predetermined lamp voltage at the start of supply, in accordance with the control of the ADC setting change circuit 28. Also, at the start of supply, each counter 204 starts supplying counter voltage.

[0137] The ramp voltage gradually increases from the ramp voltage at the start of supply. Comparator 206 inverts its output when the signal voltage, which is the analog calculation output supplied from ADC line L4, and the ramp voltage become the same voltage.

[0138] The output of comparator 206 is input to counter 204. Counter 204 stops its counter operation and outputs a digital output to shift adder 36 and input storage unit 30.

[0139] The ADC status determination circuit 40 determines that the ADC has finished in all columns when each counter 204 stops. For example, if the output value of each comparator 206 inverts from a high level to a low level, the ADC status determination circuit 40 outputs, for example, the negative OR of the output signals of each comparator 206 as a signal.

[0140] Furthermore, the ADC setting change circuit 28 stops the operation of the ramp voltage generator 202 when the output value of the ADC state determination circuit 40 is changed. In this way, the ADC state determination circuit 40 ends the voltage rise period of the ramp voltage generator 202 when the operation of each counter 204 is completed, so the energy consumption associated with the comparator current and leakage current of the comparator 206 of each column is suppressed. This makes it possible to suppress the power consumption of the analog-to-digital converter 20.

[0141] (Modification 1 of the third embodiment) The information processing device 1 according to Modification 1 of the Third Embodiment differs from the information processing device 1 according to the Third Embodiment in that the ADC state determination circuit 40 determines the state of the analog-to-digital converter 20 based on the value of the counter 204. The differences from the information processing device 1 according to the Third Embodiment will be explained below.

[0142] Figure 15 shows an example of the configuration of the ADC status determination circuit 40 according to Modification 1 of the third embodiment. As shown in Figure 15, the output value of the counter 204 is input to the ADC status determination circuit 40 according to Modification 1 of the embodiment of the counter 204. The ADC status determination circuit 40 determines that the ADC has finished in all columns when the change of values ​​of all counters 204 has stopped.

[0143] For example, the ADC state determination circuit 40 outputs a signal which is the logical AND of the output signals of each counter 204. As a result, the ADC state determination circuit 40 outputs a high-level signal when each latch 208 holds a code value. In this way, the ADC state determination circuit 40 terminates the voltage rise period of the ramp voltage generator 202 when the operation of each counter 204 is finished, thereby suppressing the energy consumption associated with the comparator current and leakage current of the comparator 206 in each column. This makes it possible to reduce the power consumption of the analog-to-digital converter 20.

[0144] (Fourth Embodiment) The information processing device 1 according to the fourth embodiment differs from the information processing device 1 according to the first to third embodiments and their modified versions, with the exception of the information processing device 1 according to modification 1 of the second embodiment, in that it does not have a schedule creation unit 24 and a schedule storage unit 26. The differences from the information processing device 1 according to the first embodiment will be explained below.

[0145] Figure 16 shows an example of the configuration of the information processing device 1 according to the fourth embodiment. As shown in Figure 16, the information processing device 1 according to the fourth embodiment differs from the information processing device 1 according to the first embodiment in that it does not have a schedule creation unit 24 and a schedule storage unit 26.

[0146] This allows the voltage rise period of the ramp voltage generator 202 to end in accordance with the completion of each column's comparator 206, thereby suppressing the energy consumption associated with the comparator current and leakage current of each column's comparator 206, and enabling a reduction in circuit size.

[0147] (Fifth embodiment) The ADC setting change circuit 28 in the information processing device 1 according to the fifth embodiment differs in that, in accordance with the control of the control circuit 38, it can change the control method of the information processing device 1 according to the first to fourth embodiments and their modified versions in a time series according to the control purpose. The differences from the information processing device 1 according to the first to fourth embodiments will be explained below.

[0148] The information processing device 1 according to this embodiment has a configuration equivalent to, for example, the first embodiment (see Figure 1), a modified version of the first embodiment (see Figure 7), the second embodiment, the third embodiment (see Figure 13), and a modified version of the third embodiment (see Figure 15). The ADC setting change circuit 28 can execute only one of the following processes a to c. Alternatively, it can execute a combination of at least two of processes a, b, and c. At the start of the control process, it is also possible to set initial settings (for example, an arbitrary start voltage and end voltage).

[0149] Process a modifies the setting information based on a pre-created plan for the lamp voltage generator 202 (for example, a process example according to the first embodiment). Process b modifies the setting information based on the output history of the lamp voltage generator 202 (for example, a process example according to the second embodiment). Process c stops the output of the lamp voltage generator 202 when the conversion of the voltage of each ADC line L4 to a digital value is completed (for example, a process example according to the first embodiment).

[0150] Thus, by changing the control method according to the purpose of the information processing device 1 according to the fifth embodiment, it becomes possible to further reduce the processing time while maintaining the processing accuracy of the analog-to-digital conversion process of the analog-to-digital converter 20.

[0151] At least a part of the information processing apparatus and information processing method described in the above-described embodiments may be configured as hardware or as software. In the case of software configuration, a program that implements at least a part of the functions of the information processing method and information processing apparatus may be stored on a recording medium such as a flexible disk or CD-ROM, and loaded into a computer for execution. The recording medium is not limited to removable ones such as magnetic disks or optical disks, but may also be a fixed recording medium such as a hard disk drive or memory.

[0152] Furthermore, programs that implement at least some of the functions of information processing methods and information processing devices may be distributed via communication lines such as the Internet (including wireless communication). In addition, such programs may be encrypted, modulated, or compressed and distributed via wired or wireless lines such as the Internet, or stored on a recording medium.

[0153] Furthermore, this technology can take the following configuration.

[0154] (1) A cell array having cells that output a calculated voltage to a signal line based on an input signal and a coefficient to be held, An analog-to-digital converter that outputs a digital value based on the lamp voltage and the voltage of the signal line, A voltage control unit that controls the voltage range of the lamp voltage, An information processing device equipped with the following features.

[0155] (2) The system further includes a first storage unit that stores setting information regarding the voltage range, The voltage control unit controls the voltage range based on the setting information, as described in (1).

[0156] (3) The information processing device according to (2), wherein the setting information includes at least information on the starting voltage of the lamp voltage.

[0157] (4) The information processing apparatus according to (2) or (3), further comprising a setting unit that sets the setting information based on at least one of the coefficient and the voltage of the signal line input to the analog-to-digital converter.

[0158] (5) An information processing device according to any one of (1) to (4), further comprising a lamp voltage generator for generating the aforementioned lamp voltage.

[0159] (6) The information processing device on (5) further comprises a determination unit for determining the completion of the conversion of the voltage of the signal line to a digital value.

[0160] (7) The lamp voltage generator stops or suppresses voltage generation based on the determination of the determination unit, as shown in (6) above.

[0161] (8) The information processing device (7) further includes a comparator that compares the lamp voltage and the signal line voltage and outputs a first signal containing information indicating a match when they match.

[0162] (9) The determination unit is an information processing device (8) which performs the determination based on the first signal.

[0163] (10) The aforementioned analog-to-digital converter is The system further includes a latch that takes a counter value as input and stores the counter value based on the first signal, The determination unit performs the determination based on the counter value held by the latch, as shown in (8).

[0164] (11) The determination unit is an information processing device as described in (10), wherein the determination is made based on the condition that the counter value held by the latch does not change.

[0165] (12) The setting unit includes information relating to a counter value corresponding to the starting voltage of the lamp voltage in the setting information, as shown in (11).

[0166] (13) The aforementioned analog-to-digital converter is The system further includes a counter that stops changing the counter value based on the first signal, The determination unit performs the determination based on the counter value of the counter, as shown in (8).

[0167] (14) The setting unit includes information relating to a counter value corresponding to the starting voltage of the lamp voltage in the setting information, as described in (13).

[0168] (15) The cell array contains multiple cells arranged in an n-row and m-column (n and m are natural numbers) configuration, and each of the multiple cells outputs a calculated voltage to the signal line for each column based on the input signal and the coefficients it holds. The aforementioned analog-to-digital converter is Each of the aforementioned rows has multiple comparators connected to its respective signal line, The information processing apparatus according to (8), wherein each of the plurality of comparators compares the lamp voltage with the voltage of the corresponding signal line and outputs a first signal having information indicating a match when they match.

[0169] (16) The information processing apparatus according to (15), wherein the determination unit performs the determination based on the first signal output by each of the plurality of comparators.

[0170] (17) The setting unit sets the range of the start voltage and end voltage of the ramp voltage based on a plurality of coefficients stored in each of the plurality of cells and input signals to be input to the plurality of cells, as described in (15).

[0171] (18) The setting unit sets the range of the start voltage and end voltage of the lamp voltage based on the voltage of the signal line for each row, as described in (15).

[0172] (19) The information processing apparatus according to any one of (3) to (18), wherein the starting voltage is set based on a predetermined offset voltage.

[0173] (20) A process of outputting a calculated voltage to a signal line based on the input signal and the coefficients to be held, An analog-to-digital conversion process that outputs a digital value based on the lamp voltage and the voltage of the signal line, A voltage control step for controlling the voltage range of the lamp voltage, An information processing method comprising:

[0174] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents. [Explanation of Symbols]

[0175] 1: Information processing unit, 10: Cell array, 20: Analog-to-digital converter, 24: Schedule creation unit (setting unit), 26: Schedule storage unit (first storage unit), 28: ADC setting change circuit (voltage control unit), 40: ADC status determination circuit (determination unit), 100: Cell, 202: Lamp voltage generator, 204: Counter, 208: Latch, L4: ADC line (signal line)

Claims

1. A cell array having cells that output a calculated voltage to a signal line based on an input signal and a coefficient to be held, An analog-to-digital converter that outputs a digital value based on the lamp voltage and the voltage of the signal line, A voltage control unit that controls the voltage range of the lamp voltage, An information processing device equipped with the following features.

2. The system further includes a first storage unit that stores setting information regarding the voltage range, The information processing apparatus according to claim 1, wherein the voltage control unit controls the voltage range based on the setting information.

3. The information processing apparatus according to claim 2, wherein the setting information includes at least information on the starting voltage of the lamp voltage.

4. The information processing apparatus according to claim 2, further comprising a setting unit that sets the setting information based on at least one of the coefficient and the voltage of the signal line input to the analog-to-digital converter.

5. The information processing apparatus according to claim 4, further comprising a lamp voltage generator that generates the aforementioned lamp voltage.

6. The information processing apparatus according to claim 5, further comprising a determination unit for determining the completion of the conversion of the voltage of the signal line to a digital value.

7. The information processing device according to claim 6, wherein the lamp voltage generator stops generating voltage based on the determination of the determination unit.

8. The information processing apparatus according to claim 7, further comprising a comparator that compares the lamp voltage and the signal line voltage and outputs a first signal having information indicating a match when they match.

9. The information processing apparatus according to claim 8, wherein the determination unit performs the determination based on the first signal.

10. The aforementioned analog-to-digital converter is The system further includes a latch that takes a counter value as input and stores the counter value based on the first signal, The information processing apparatus according to claim 8, wherein the determination unit performs the determination based on the counter value held by the latch.

11. The information processing apparatus according to claim 10, wherein the determination unit makes it a condition for the determination that the counter value held by the latch does not change.

12. The information processing device according to claim 11, wherein the setting unit includes information relating to a counter value corresponding to the starting voltage of the lamp voltage in the setting information.

13. The aforementioned analog-to-digital converter is The system further includes a counter that stops changing the counter value based on the first signal, The information processing apparatus according to claim 8, wherein the determination unit performs the determination based on the counter value of the counter.

14. The information processing apparatus according to claim 13, wherein the setting unit includes information relating to a counter value corresponding to the starting voltage of the lamp voltage in the setting information.

15. The cell array contains a plurality of cells, including the cell, arranged in an n x m (n, m are natural numbers) configuration, and each of the plurality of cells outputs a calculated voltage to the signal line for each column based on the input signal and the coefficients it holds. The aforementioned analog-to-digital converter is Each of the aforementioned rows has multiple comparators connected to its respective signal line, The information processing apparatus according to claim 8, wherein each of the plurality of comparators compares the lamp voltage with the voltage of the corresponding signal line and outputs a first signal having information indicating a match when they match.

16. The information processing apparatus according to claim 15, wherein the determination unit performs the determination based on the first signal output by each of the plurality of comparators.

17. The information processing apparatus according to claim 15, wherein the setting unit sets the range of the start voltage and end voltage of the ramp voltage based on a plurality of coefficients stored in each of the plurality of cells and input signals to be input to the plurality of cells.

18. The information processing apparatus according to claim 15, wherein the setting unit sets the range of the start voltage and end voltage of the lamp voltage based on the voltage of the signal line for each row.

19. The information processing apparatus according to claim 3, wherein the starting voltage is set based on a predetermined offset voltage.

20. A process of outputting a calculated voltage to a signal line based on the input signal and the coefficients to be held, An analog-to-digital conversion process that outputs a digital value based on the lamp voltage and the voltage of the signal line, A voltage control step for controlling the voltage range of the lamp voltage, An information processing method comprising:

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