SiGe epitaxial wafer and method for manufacturing the same

Abstract

The objective is to provide a SiGe epitaxial wafer, in which a SiGe layer is heteroepitaxially grown on a silicon substrate, and a method for manufacturing the same, which is suitable for semiconductor device fabrication, with reduced dislocation density and warpage. [Solution] A SiGe epitaxial wafer comprising a SiGe layer mainly composed of SiGe on a silicon substrate, wherein the SiGe epitaxial wafer has a first SiGe layer on the silicon substrate, a second SiGe layer on the first SiGe layer, and a third SiGe layer on the second SiGe layer, wherein the Ge composition ratio of the first SiGe layer increases from the silicon substrate side toward the second SiGe layer side, the Ge composition ratio of the second SiGe layer decreases from the first SiGe layer side toward the third SiGe layer side, and the Ge composition ratio of the third SiGe layer is constant in the thickness direction, and a method for manufacturing the same.

Description

Technical Field

[0001] The present invention relates to a SiGe epitaxial wafer and a method for manufacturing the same.

Background Art

[0002] SiGe and Ge are widely used in logic ICs, high-frequency devices, etc. For example, a semiconductor layer with applied strain has a higher carrier mobility compared to a semiconductor layer with relaxed strain, and a semiconductor circuit that operates at high speed can be fabricated. Therefore, by applying strain to the channel layer using the lattice constant difference between Si and the SiGe layer, a FET with a high operating speed has been fabricated. Also, it is known that a channel layer with high mobility can be obtained by using SiGe as the channel material of a FinFET.

[0003] Furthermore, for semiconductors after the next generation, GAA (Gate All Around) and CFET (Complementary Field Effect Transistor) have been proposed, and the usage area of SiGe is also expanding. To fabricate a FET with a GAA structure, it is necessary to selectively etch SiGe from a SiGe / Si multilayer structure to obtain a Si nanosheet, and the process of forming an epitaxial layer of SiGe becomes essential. Also, in a GAA structure or CFET, since the crystal orientation in which carriers move is different from that of conventional devices, the use of a SiGe layer is being considered to improve hole mobility.

[0004] The method for fabricating a SiGe layer is fabricated by epitaxial growth on a silicon substrate for semiconductor devices. Such a substrate with a SiGe layer formed on a silicon substrate is sometimes called a virtual SiGe substrate. In the heteroepitaxial growth of Ge and SiGe on a silicon substrate, the mismatch caused by the lattice constant difference between Si and Ge is relaxed by a buffer layer using a SiGe mixed crystal, and crystal growth is performed.

[0005] Various buffer layers using SiGe mixed crystals have been proposed. For example, there are forward-sloping buffer layers in which the Ge concentration is gradually increased from the silicon substrate up to a predetermined Ge concentration, and methods that apply stress using a Si / SiGe superlattice layer. Non-patent document 1, on the other hand, describes a reverse-sloping buffer in which a SiGe layer with a high Ge composition is placed at the bottom and the Ge composition is reduced towards the surface. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] VAShah,et.al.,J.Appl.Phys.,107,064304(2010). [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] Epitaxial structures using buffer layers with reverse-graded compositions are known to be very effective in reducing dislocation density by preventing the pile-up of dislocations generated in the lower layer by a high-concentration SiGe layer. However, there was a problem in that warping increased due to lattice constant differences caused by differences in Ge composition, making them unsuitable for use in device processing.

[0008] The present invention has been made to solve the above problems and aims to provide a SiGe epitaxial wafer (virtual SiGe substrate) in which a SiGe layer is heteroepitaxially grown on a silicon substrate, which is suitable for semiconductor device fabrication and has reduced dislocation density and warpage, and a method for manufacturing the same. [Means for solving the problem]

[0009] The present invention has been made to achieve the above objective, and provides a SiGe epitaxial wafer having a SiGe layer mainly composed of SiGe on a silicon substrate, wherein the SiGe epitaxial wafer has a first SiGe layer on the silicon substrate, a second SiGe layer on the first SiGe layer, and a third SiGe layer on the second SiGe layer, wherein the Ge composition ratio of the first SiGe layer increases from the silicon substrate side toward the second SiGe layer side, the Ge composition ratio of the second SiGe layer decreases from the first SiGe layer side toward the third SiGe layer side, and the Ge composition ratio of the third SiGe layer is constant in the thickness direction.

[0010] Such SiGe epitaxial wafers reduce the stress and dislocation density of the epitaxial layer, resulting in wafers with reduced dislocation density and warpage, making them suitable for semiconductor device fabrication.

[0011] In this case, the thickness of the first SiGe layer can be in the range of 10 to 10,000 nm.

[0012] With a film thickness within this range, the stress on the wafer can be reduced more effectively.

[0013] In this case, the thickness of the second SiGe layer can be in the range of 1 to 100 nm.

[0014] With a film thickness within this range, the dislocation density can be reduced more effectively.

[0015] At this time, the composition formula of the first SiGe layer is Si 1-x Ge x (0 <x≦0.3)であるものとすることができる。

[0016] Within this range of Ge composition ratios, it becomes possible to further effectively reduce the stress on the wafer.

[0017] At this time, the composition formula of the second SiGe layer is Si 1-y Ge y (0 <y≦0.3)であるものとすることができる。

[0018] Within this range of Ge composition ratios, the dislocation density can be reduced even more effectively.

[0019] At this time, the composition formula of the third SiGe layer is Si 1-z Ge z (0 <z≦0.3)であるものとすることができる。

[0020] This makes it possible to form a semiconductor device layer of stable quality on the third SiGe layer.

[0021] In this case, multiple second SiGe layers can be provided on the first SiGe layer.

[0022] This allows for a more reliable reduction in dislocation density.

[0023] The present invention has also been made to achieve the above objective, and provides a method for manufacturing a SiGe epitaxial wafer, comprising forming a SiGe layer mainly composed of SiGe on a silicon substrate by epitaxial growth, the method comprising the steps of: forming a first SiGe layer on a silicon substrate; forming a second SiGe layer on the first SiGe layer; and forming a third SiGe layer on the second SiGe layer, wherein in the step of forming the first SiGe layer, the Ge composition ratio is increased from the silicon substrate side toward the second SiGe layer side; in the step of forming the second SiGe layer, the Ge composition ratio is decreased from the first SiGe layer side toward the third SiGe layer side; and in the step of forming the third SiGe layer, the Ge composition ratio is kept constant in the thickness direction.

[0024] According to such a method for manufacturing a SiGe epitaxial wafer, the stress and dislocation density of the epitaxial layer can be reduced, and thereby, a SiGe epitaxial wafer with reduced dislocation density and warpage, which is suitable for manufacturing semiconductor devices, can be manufactured.

[0025] At this time, in the step of forming the first SiGe layer, the film thickness of the first SiGe layer can be in the range of 10 to 10000 nm.

[0026] If the film thickness is within this range, the stress applied to the wafer can be more effectively reduced.

[0027] At this time, in the step of forming the second SiGe layer, the film thickness of the second SiGe layer can be in the range of 1 to 100 nm.

[0028] If the film thickness is within this range, the dislocation density can be more effectively reduced.

[0029] At this time, in the step of forming the first SiGe layer, the composition formula of the first SiGe layer can be Si 1-x Ge x (0 < x ≤ 0.3).

[0030] If the Ge composition ratio is within this range, the stress applied to the wafer can be further effectively reduced.

[0031] At this time, in the step of forming the second SiGe layer, the composition formula of the second SiGe layer can be Si 1-y Ge y ((continued on next page)0 < y ≤ 0.3).

[0032] If the Ge composition ratio is within this range, the dislocation density can be further effectively reduced.

[0033] At this time, in the step of forming the third SiGe layer, the composition formula of the third SiGe layer can be Si 1-z Ge z(0 <z≦0.3)とすることができる。

[0034] This makes it possible to form a semiconductor device layer of stable quality on the third SiGe layer.

[0035] In this case, the step of forming the second SiGe layer can be performed multiple times after the step of forming the first SiGe layer.

[0036] This allows for a more reliable reduction in dislocation density. [Effects of the Invention]

[0037] As described above, the SiGe epitaxial wafer of the present invention reduces the stress and dislocation density of the epitaxial layer, resulting in a SiGe epitaxial wafer in which a SiGe layer is heteroepitaxially grown on a silicon substrate, which is suitable for semiconductor device fabrication due to reduced dislocation density and warpage.

[0038] Furthermore, the SiGe epitaxial wafer manufacturing method of the present invention makes it possible to reduce the stress and dislocation density of the epitaxial layer, thereby enabling the production of SiGe epitaxial wafers in which a SiGe layer is heteroepitaxially grown on a silicon substrate, which are suitable for semiconductor device fabrication, and have reduced dislocation density and warpage. [Brief explanation of the drawing]

[0039] [Figure 1] (a) A schematic cross-sectional view and (b) Ge composition ratio (concentration) of a SiGe epitaxial wafer according to the first embodiment of the present invention are shown. [Figure 2] (a) A schematic cross-sectional view and (b) Ge composition ratio (concentration) of a SiGe epitaxial wafer according to the second embodiment of the present invention are shown. [Modes for carrying out the invention]

[0040] The present invention will be described in detail below, but the present invention is not limited to these descriptions.

[0041] As described above, there was a need for a SiGe epitaxial wafer, in which a SiGe layer is heteroepitaxially grown on a silicon substrate, and a method for manufacturing the same, which is suitable for semiconductor device fabrication and has reduced dislocation density and warpage.

[0042] As a result of diligent study on the above problems, the present inventors have provided a SiGe epitaxial wafer having a SiGe layer mainly composed of SiGe on a silicon substrate, wherein the wafer has a first SiGe layer on the silicon substrate, a second SiGe layer on the first SiGe layer, and a third SiGe layer on the second SiGe layer, wherein the Ge composition ratio of the first SiGe layer increases from the silicon substrate side toward the second SiGe layer side, and the Ge composition ratio of the second SiGe layer is We have discovered that a SiGe epitaxial wafer in which the Ge composition ratio of the third SiGe layer decreases from the first SiGe layer side toward the third SiGe layer side, and the Ge composition ratio of the third SiGe layer is constant in the thickness direction, results in a SiGe epitaxial wafer in which the stress and dislocation density of the epitaxial layer are reduced, thereby providing a SiGe epitaxial wafer in which the SiGe layer is heteroepitaxially grown on a silicon substrate and has reduced dislocation density and warpage, making it suitable for semiconductor device fabrication, and thus we have completed the present invention.

[0043] The present inventors have also conducted extensive research on the above-mentioned problems and have come up with a method for manufacturing a SiGe epitaxial wafer, comprising the steps of: forming a first SiGe layer on a silicon substrate by epitaxial growth, forming a second SiGe layer on the first SiGe layer, and forming a third SiGe layer on the second SiGe layer, wherein in the step of forming the first SiGe layer, the Ge composition ratio is increased from the silicon substrate side toward the second SiGe layer side, and the second SiGe We have discovered that by manufacturing a SiGe epitaxial wafer in which the Ge composition ratio is reduced from the first SiGe layer side to the third SiGe layer side during the layer formation process, and the Ge composition ratio is kept constant in the thickness direction during the third SiGe layer formation process, the stress and dislocation density of the epitaxial layer can be reduced. This makes it possible to manufacture a SiGe epitaxial wafer in which a SiGe layer is heteroepitaxially grown on a silicon substrate, which is suitable for semiconductor device fabrication, with reduced dislocation density and warpage, and thus the present invention has been completed.

[0044] In this invention, "main component" refers to the component that is present in the largest amount relative to all components, preferably 50% by mass or more, more preferably 70% by mass or more, and even more preferably 90% by mass or more, and may also be 100% by mass.

[0045] (SiGe epitaxial wafer) The SiGe epitaxial wafer according to the first embodiment of the present invention will be described below with reference to Figure 1. Figure 1(a) shows a schematic cross-sectional view of the SiGe epitaxial wafer according to the first embodiment of the present invention, and Figure 1(b) shows the Ge composition ratio (concentration) of the SiGe epitaxial wafer in Figure 1(a).

[0046] The SiGe epitaxial wafer 1 shown in Fig. 1(a) is a SiGe epitaxial wafer having a SiGe layer mainly composed of SiGe on a silicon substrate 2, and includes a first SiGe layer 3 on the silicon substrate 2, a second SiGe layer 4 on the first SiGe layer 3, and a third SiGe layer 5 on the second SiGe layer 4. The SiGe epitaxial wafer 1 can include a SiGe buffer layer 6 similar to the third SiGe layer 5, having a constant Ge composition ratio and not exceeding that of the third SiGe layer 5, under the second SiGe layer 4.

[0047] The silicon substrate 2 is not particularly limited, but a substrate with a surface orientation of (100), P-type, and a resistivity of 10 Ωcm can be used.

[0048] The first SiGe layer 3 is made of a compound represented by the composition of Si 1-x Ge x (0 < x < 1), and has a structure in which the Ge composition on the silicon substrate 2 side is lower than that on the second SiGe layer 4 side in order to reduce stress due to the lattice constant difference from Si.

[0049] The film thickness of the first SiGe layer 3 is preferably in the range of 10 to 10000 nm. If the film thickness is within this range, the stress applied to the wafer can be more effectively reduced.

[0050] Also, the composition formula of the first SiGe layer 3 is preferably Si 1-x Ge x (0 < x ≤ 0.3). If the Ge composition ratio is within this range, the stress applied to the wafer can be further effectively reduced.

[0051] The second SiGe layer 4 is made of a compound represented by the composition of Si 1-y Ge y (0 < y < 1), and has a structure in which the Ge composition on the first SiGe layer 3 side is higher than that on the third SiGe layer 5 side. This can prevent the dislocations generated on the first SiGe layer 3 side from piling up to the third SiGe layer 5 side.

[0052] The film thickness of the second SiGe layer 4 is preferably in the range of 1 to 100 nm. If the film thickness is within this range, the dislocation density can be more effectively reduced.

[0053] Also, the composition formula of the second SiGe layer 4 is Si 1-y Ge y (0 < y ≦ 0.3), which is preferable. If the Ge composition ratio is within this range, the dislocation density can be further effectively reduced.

[0054] The gradient of the Ge composition ratio in the first SiGe layer 3 and the second SiGe layer 4 may be continuous, stepwise, or a combination thereof, as shown in FIG. 1(b).

[0055] The third SiGe layer 5 is made of a compound represented by the composition of Si 1-z Ge z (0 < z < 1), and the Ge composition ratio is constant in the thickness direction. Also, the Ge composition can be the highest among the first SiGe layer 3, the second SiGe layer 4, and the third SiGe layer 5.

[0056] The composition formula of the third SiGe layer 5 is Si 1-z Ge z (0 < z ≦ 0.3), which is preferable. Thereby, a semiconductor device layer with stable quality can be formed on the third SiGe layer 5.

[0057] Next, the SiGe epitaxial wafer according to the second embodiment of the present invention will be described with reference to FIG. 2. FIG. 2(a) shows a schematic cross-sectional view of the SiGe epitaxial wafer according to the second embodiment of the present invention, and FIG. 2(b) shows the Ge composition ratio (concentration) of the SiGe epitaxial wafer of FIG. 2(a).

[0058] Figure 2(a) shows an example of a SiGe epitaxial wafer 10 having multiple second SiGe layers 4 on the first SiGe layer 3. This allows for a more reliable reduction of dislocation density. Furthermore, as shown in the figure, multiple pairs of SiGe buffer layers 6 and second SiGe layers 4 can also be present on the first SiGe layer 3. These can be selected considering dislocation density and substrate warpage.

[0059] The SiGe epitaxial wafers 1 and 10 may further have a device layer 7 on top of the third SiGe layer 5.

[0060] Device layer 7 consists of Si, SiGe, and Si 28 From among these, the appropriate component is selected depending on the device to be fabricated and its intended use. The film thickness is not particularly limited, but can be arbitrarily selected within the range of 5 to 200 nm. The device layer 7 does not have to be a single layer; it may consist of multiple layers of different components. For example, although not limited to Si 28 Layers of 8nm and Si 0.7 Ge 0.3 A structure in which layers are stacked at a density of 20 nm is also acceptable.

[0061] According to the SiGe epitaxial wafer of the present invention as described above, the stress and dislocation density of the epitaxial layer are reduced, resulting in a SiGe epitaxial wafer in which a SiGe layer is heteroepitaxially grown on a silicon substrate, which is suitable for semiconductor device fabrication, as it has reduced dislocation density and warpage.

[0062] (Method for manufacturing SiGe epitaxial wafers) Next, the method for manufacturing a SiGe epitaxial wafer according to the present invention will be described with reference to Figures 1 and 2.

[0063] The manufacturing method of the SiGe epitaxial wafer according to the present invention is a method for manufacturing the SiGe epitaxial wafer 1 in which a SiGe layer mainly composed of SiGe is formed on the silicon substrate 2 by epitaxial growth, including a step of forming a first SiGe layer 3 on the silicon substrate 2, a step of forming a second SiGe layer 4 on the first SiGe layer 3, and a step of forming a third SiGe layer 5 on the second SiGe layer 4. Further, a step of forming a SiGe buffer layer 6 having a constant Ge composition ratio and equal to or less than the third SiGe layer 5, similar to the third SiGe layer 5, may be included under the second SiGe layer 4.

[0064] The first to third SiGe layers 3 to 5 are formed on the silicon substrate 2 by vapor phase growth. The growth method is not limited to the following conditions. For example, it can be grown at a pressure of 1 to 100 Torr and a growth temperature of 600 to 800 °C in a reduced pressure CVD apparatus compatible with 300 mm diameter wafers. As the Si source, monosilane (SiH4) or dichlorosilane (SiH2Cl2) can be used, and as the Ge source, monogermane (GeH4) or germanium tetrachloride (GeCl4) can be used. The flow rate of the precursor and the growth temperature can be selected according to the composition of the SiGe layer to be formed.

[0065] In the step of forming the first SiGe layer 3, in order to reduce the stress due to the lattice constant difference from Si, the Ge composition ratio is increased from the silicon substrate 2 side toward the second SiGe layer 4 side.

[0066] At this time, it is preferable that the film thickness of the first SiGe layer 3 is in the range of 10 to 10000 nm. With a film thickness within this range, the stress applied to the wafer can be more effectively reduced.

[0067] Also, the composition formula of the first SiGe layer 3 is preferably Si 1-x Ge x (0 < x ≦ 0.3). With a Ge composition ratio within this range, the stress applied to the wafer can be further effectively reduced.

[0068] In the step of forming the second SiGe layer 4, the Ge composition ratio is decreased from the side of the first SiGe layer 3 toward the side of the third SiGe layer 5. Thereby, it is possible to prevent the dislocations generated on the side of the first SiGe layer 3 from piling up to the side of the third SiGe layer 5. The method for forming the second SiGe layer 4 is not particularly limited. For example, it can be continuously formed in the same chamber as the first SiGe layer 3 by a reduced-pressure CVD method.

[0069] At this time, it is preferable that the film thickness of the second SiGe layer 4 is in the range of 1 to 100 nm. If the film thickness is within this range, the dislocation density can be more effectively reduced.

[0070] Also, the composition formula of the second SiGe layer 4 is preferably Si 1-y Ge y (0 < y ≤ 0.3). [[ID=第十七]] If the Ge composition ratio is within this range, the dislocation density can be further effectively reduced.

[0071] [[ID=二十二]]The increase and decrease of the Ge composition ratio in the step of forming the first SiGe layer 3 and the second SiGe layer 4 may be continuous, stepwise, or a combination thereof, as shown in FIG. 1(b).

[0072] In the step of forming the third SiGe layer 5, the Ge composition ratio is made constant in the thickness direction. Also, the composition formula of the third SiGe layer 5 is preferably Si 1-z Ge z (0 < z ≤ 0.3). Thereby, a semiconductor device layer with stable quality can be formed on the third SiGe layer 5.

[0073] Also, FIGURE 2(a) shows an example in which the second SiGe layer 4 is repeatedly formed. Thereby, the dislocation density can be more reliably reduced. Also, a combination of the SiGe buffer layer 6 and the second SiGe layer 4 can be repeatedly formed. These can be selected in consideration of the dislocation density and the warp of the substrate.

[0074] After growing the first to third SiGe layers, the device layer 7 can be grown. To improve the surface morphology, the third SiGe layer 5 may be grown first, then the surface may be planarized by CMP before growing the device layer 7. The method for growing the device layer 7 is not particularly limited, but it can be carried out using an atmospheric pressure CVD apparatus or a reduced pressure CVD apparatus.

[0075] Device layer 7 consists of Si, SiGe, and Si 28 From among these, the appropriate component is selected depending on the device to be fabricated and its intended use. The film thickness is not particularly limited, but can be arbitrarily selected within the range of 5 to 200 nm. The device layer 7 does not have to be a single layer; multiple layers may be fabricated with different components. For example, although not limited to Si 28 Layers of 8nm and Si 0.7 Ge 0.3 It can be fabricated using a structure in which layers are stacked at a density of 20 nm.

[0076] By using the SiGe epitaxial wafer manufacturing method of the present invention, the stress and dislocation density of the epitaxial layer can be reduced, thereby enabling the production of SiGe epitaxial wafers in which a SiGe layer is heteroepitaxially grown on a silicon substrate, which are suitable for semiconductor device fabrication, and have reduced dislocation density and warpage. [Examples]

[0077] The present invention will be described in detail below with reference to examples, but this is not intended to limit the present invention.

[0078] (Example 1) A silicon wafer with a (100) orientation, P-type, boron-doped, and resistivity of 10 Ωcm was prepared and placed in a vacuum CVD apparatus. Inside the vacuum CVD furnace, a SiGe layer was formed by introducing SiH2Cl2 gas (Si source) and GeH4 gas (Ge source) at predetermined temperatures and pressures.

[0079] Specifically, first, a first SiGe layer was grown on a silicon wafer with three different Ge composition ratios. At a growth temperature of 610°C and a furnace pressure of 1333 Pa, (1) SiH2Cl2 was supplied at a rate of 200 sccm and GeH4 at a rate of 40 sccm to grow a 600 nm Si layer. 0.9 Ge 0.1 (2) The layer is grown, and then SiH2Cl2 is supplied at a rate of 200 sccm and GeH4 at a rate of 88 sccm to form a 600 nm Si layer. 0.8 Ge 0.2 (3) Finally, SiH2Cl2 is supplied at 200 sccm and GeH4 at 150 sccm to grow a Si layer of 800 nm. 0.7 Ge 0.3 The layers grew.

[0080] Next, a second SiGe layer was formed on top of the first SiGe layer. At a growth temperature of 610°C and a furnace pressure of 1333 Pa, 200 sccm of SiH2Cl2 and 150 sccm of GeH4 were supplied to create a SiGe layer with a constant Ge composition ratio. 0.7 Ge 0.3 After growing a 20nm layer (SiGe buffer layer), the GeH4 flow rate was gradually reduced so that the Ge composition decreased towards the surface, and a second SiGe layer of 10nm was grown.

[0081] Next, a third SiGe layer was formed on top of the second SiGe layer. The third SiGe layer was formed at a growth temperature of 610°C and a furnace pressure of 1333 Pa, with SiH2Cl2 supplied at a rate of 200 sccm and GeH4 at a rate of 150 sccm. 0.7 Ge 0.3 The layer was grown to a thickness of 1 μm.

[0082] (Comparative Example 1) A silicon wafer equivalent to that of Example 1 was prepared and placed in a reduced-pressure CVD apparatus in the same manner as in Example 1, and a first SiGe layer with three stages of Ge composition ratio variation was grown on the silicon wafer. Specifically, at a growth temperature of 610°C and a furnace pressure of 1333 Pa, (1) SiH2Cl2 was supplied at a rate of 200 sccm and GeH4 at a rate of 40 sccm to grow a 600 nm Si layer. 0.9 Ge 0.1(2) The layer is grown, and then SiH2Cl2 is supplied at a rate of 200 sccm and GeH4 at a rate of 88 sccm to form a 600 nm Si layer. 0.8 Ge 0.2 (3) Finally, SiH2Cl2 is supplied at 200 sccm and GeH4 at 150 sccm to grow a Si layer of 800 nm. 0.7 Ge 0.3 The layers grew.

[0083] Next, a SiGe layer corresponding to a third SiGe layer, with a constant Ge composition ratio, was formed on top of the first SiGe layer. The third SiGe layer was grown at a growth temperature of 610°C and a furnace pressure of 1333 Pa, with 200 sccm of SiH2Cl2 and 150 sccm of GeH4 supplied to form a 1 μm Si layer. 0.7 Ge 0.3 The layers grew.

[0084] (Comparative Example 2) A silicon wafer equivalent to that of Example 1 was prepared and placed in a reduced-pressure CVD apparatus in the same manner as in Example 1. Without creating a gradient layer of Ge composition ratios on the silicon wafer, SiH2Cl2 was supplied at a growth temperature of 610°C and a furnace pressure of 1333 Pa at a rate of 200 sccm and GeH4 at a rate of 150 sccm, resulting in a silicon wafer with a constant Ge composition ratio. 0.7 Ge 0.3 The layer was grown to a thickness of 200 nm.

[0085] Next, a second SiGe layer was formed. At a growth temperature of 610°C and a furnace pressure of 1333 Pa, 200 sccm of SiH2Cl2 and 150 sccm of GeH4 were supplied to form a third SiGe layer with a constant Ge composition ratio. 0.7 Ge 0.3 After growing the first layer at 20 nm, the GeH4 flow rate was gradually reduced so that the Ge composition decreased towards the surface, and a second SiGe layer was grown at 10 nm.

[0086] Next, a SiGe layer corresponding to a third SiGe layer, with a constant Ge composition ratio, was formed on top of the second SiGe layer. The third SiGe layer was grown at a growth temperature of 610°C and a furnace pressure of 1333 Pa, with 200 sccm of SiH2Cl2 and 150 sccm of GeH4 supplied to form a 2.8 μm Si layer.0.7 Ge 0.3 The layers grew.

[0087] (Example 2) A SiGe epitaxial wafer according to the embodiment shown in Figure 2 was fabricated. First, the process up to the first SiGe layer was carried out in the same manner as in Example 1.

[0088] Next, a second SiGe layer was formed on top of the first SiGe layer. At a growth temperature of 610°C and a furnace pressure of 1333 Pa, 200 sccm of SiH2Cl2 and 150 sccm of GeH4 were supplied to create a SiGe layer with a constant Ge composition ratio. 0.7 Ge 0.3 After growing a 20nm layer (SiGe buffer layer), the GeH4 flow rate was gradually reduced so that the Ge composition decreased towards the surface, and a second SiGe layer of 10nm was grown.

[0089] Furthermore, a second SiGe layer was formed on top of the second SiGe layer. At a growth temperature of 610°C and a furnace pressure of 1333 Pa, 200 sccm of SiH2Cl2 and 150 sccm of GeH4 were supplied to create a SiGe layer with a constant Ge composition ratio. 0.7 Ge 0.3 After growing a 150 nm layer (SiGe buffer layer), the GeH4 flow rate was gradually reduced so that the Ge composition decreased towards the surface, and a second SiGe layer was grown to a depth of 10 nm.

[0090] Finally, a third SiGe layer was formed on top of the second SiGe layer. The third SiGe layer was formed at a growth temperature of 610°C and a furnace pressure of 1333 Pa, by supplying SiH2Cl2 at a rate of 200 sccm and GeH4 at a rate of 150 sccm. 0.7 Ge 0.3 The layer was grown to 840 nm.

[0091] For the wafers prepared in the above examples and comparative examples, the warpage (Bow) was measured using a laser displacement meter, and dislocations were spread by gas etching to form etch pits. The dislocation density was then measured using a scanning electron microscope. The measurement results for warpage (Bow) and dislocation density are shown in Table 1.

[0092] [Table 1]

[0093] As shown in Table 1, in Example 1, the bow was 34 μm and the dislocation density (TDD) was 2 × 10⁻⁶. 4 / cm 2 In Example 2, the bow was 40 μm and the dislocation density (TDD) was 1 × 10⁻⁶. 4 / cm 2 The results were favorable. The criteria were: Bow within ±45 μm, and TDD 1 × 10⁻⁶. 5 / cm 2 The following is preferable.

[0094] On the other hand, in Comparative Example 1, the bow was 30 μm, which was a relatively good result, but the dislocation density (TDD) was 7 × 10⁻⁶. 5 / cm 2 The reduction was not sufficient. In Comparative Example 2, the dislocation density (TDD) was 4 × 10⁻⁶. 4 / cm 2 While the results for the other parameters were sufficiently low, the Bow reading was a high -121 μm.

[0095] As described above, according to the embodiments of the present invention, it was possible to manufacture a SiGe epitaxial wafer in which a SiGe layer was heteroepitaxially grown on a silicon substrate, with reduced dislocation density and warpage.

[0096] This specification includes the following embodiments: [1]: A SiGe epitaxial wafer having a SiGe layer mainly composed of SiGe on a silicon substrate, comprising a first SiGe layer on the silicon substrate, a second SiGe layer on the first SiGe layer, and a third SiGe layer on the second SiGe layer, wherein the Ge composition ratio of the first SiGe layer increases from the silicon substrate side toward the second SiGe layer side, the Ge composition ratio of the second SiGe layer decreases from the first SiGe layer side toward the third SiGe layer side, and the Ge composition ratio of the third SiGe layer is constant in the thickness direction. [2]: The SiGe epitaxial wafer according to [1] above, wherein the film thickness of the first SiGe layer is in the range of 10 to 10000 nm. [3]: The SiGe epitaxial wafer according to [1] or [2] above, wherein the film thickness of the second SiGe layer is in the range of 1 to 100 nm. [4]: The SiGe epitaxial wafer according to [1], [2] or [3] above, wherein the composition formula of the first SiGe layer is Si 1-x Ge x (0 < x ≦ 0.3). [5]: The SiGe epitaxial wafer according to [1], [2], [3] or [4] above, wherein the composition formula of the second SiGe layer is Si 1-y Ge y (0 < y ≦ 0.3). [6]: The SiGe epitaxial wafer according to [1], [2], [3], [4] or [5] above, wherein the composition formula of the third SiGe layer is Si 1-z Ge z (0 < z ≦ 0.3). [7]: The SiGe epitaxial wafer according to [1], [2], [3], [4], [5] or [6] above, wherein a plurality of the second SiGe layers are provided on the first SiGe layer. [8]: A method for manufacturing a SiGe epitaxial wafer in which a SiGe layer mainly composed of SiGe is formed on a silicon substrate by epitaxial growth, the method including a step of forming a first SiGe layer on the silicon substrate, a step of forming a second SiGe layer on the first SiGe layer, and a step of forming a third SiGe layer on the second SiGe layer. In the step of forming the first SiGe layer, the Ge composition ratio is increased from the side of the silicon substrate toward the side of the second SiGe layer. In the step of forming the second SiGe layer, the Ge composition ratio is decreased from the side of the first SiGe layer toward the side of the third SiGe layer. In the step of forming the third SiGe layer, the Ge composition ratio is made constant in the thickness direction. [9]: The method for manufacturing a SiGe epitaxial wafer according to [8] above, including making the film thickness of the first SiGe layer in the range of 10 to 10,000 nm in the step of forming the first SiGe layer.

[10] : The method for manufacturing a SiGe epitaxial wafer according to [8] or [9] above, including making the film thickness of the second SiGe layer in the range of 1 to 100 nm in the step of forming the second SiGe layer.

[11] : In the step of forming the first SiGe layer, the composition formula of the first SiGe layer is Si 1-x Ge x (0 < x ≤ 0.3). The method for manufacturing a SiGe epitaxial wafer according to [8], [9], or

[10] above.

[12] : In the step of forming the second SiGe layer, the composition formula of the second SiGe layer is Si 1-y Ge y (0 < y ≤ 0.3). The method for manufacturing a SiGe epitaxial wafer according to [8], [9],

[10] , or

[11] above.

[13] : In the step of forming the third SiGe layer, the composition formula of the third SiGe layer is Si 1-z Ge z (0 < z ≤ 0.�). The method for manufacturing a SiGe epitaxial wafer according to [8], [9],

[10] ,

[11] , or

[12] above.

[14] : A method for manufacturing a SiGe epitaxial wafer according to [8], [9],

[10] ,

[11] ,

[12] or

[13] , comprising performing the step of forming the second SiGe layer multiple times after the step of forming the first SiGe layer.

[0097] It should be noted that the present invention is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that is substantially identical to the technical idea described in the claims of the present invention and achieves similar effects is included within the technical scope of the present invention. [Explanation of Symbols]

[0098] 1, 10…SiGe epitaxial wafer, 2…Silicon substrate, 3...First SiGe layer, 4...Second SiGe layer, 5...Third SiGe layer, 6…SiGe buffer layer, 7…Device layer.

Claims

1. A SiGe epitaxial wafer comprising a SiGe layer mainly composed of SiGe on a silicon substrate, A first SiGe layer on a silicon substrate, The second SiGe layer on the first SiGe layer, The second SiGe layer has a third SiGe layer on it, The Ge composition ratio of the first SiGe layer increases from the silicon substrate side toward the second SiGe layer side. The Ge composition ratio of the second SiGe layer decreases from the first SiGe layer side toward the third SiGe layer side. A SiGe epitaxial wafer characterized in that the Ge composition ratio of the third SiGe layer is constant in the thickness direction.

2. The SiGe epitaxial wafer according to claim 1, characterized in that the thickness of the first SiGe layer is in the range of 10 to 10,000 nm.

3. The SiGe epitaxial wafer according to claim 1, characterized in that the thickness of the second SiGe layer is in the range of 1 to 100 nm.

4. The composition formula of the first SiGe layer is Si １－ｘ Ge ｘ The SiGe epitaxial wafer according to claim 1, characterized in that (0 < x ≤ 0.3).

5. The composition formula of the second SiGe layer is Si １－ｙ Ge ｙ The SiGe epitaxial wafer according to claim 1, characterized in that (0 < y ≤ 0.3).

6. The composition formula of the third SiGe layer is Si １－ｚ Ge ｚ The SiGe epitaxial wafer according to claim 1, characterized in that (0 < z ≤ 0.3).

7. The SiGe epitaxial wafer according to any one of claims 1 to 6, characterized in that a plurality of the second SiGe layers are located on the first SiGe layer.

8. A method for manufacturing a SiGe epitaxial wafer, comprising forming a SiGe layer mainly composed of SiGe on a silicon substrate by epitaxial growth, A step of forming a first SiGe layer on a silicon substrate, The process involves forming a second SiGe layer on the first SiGe layer, The process includes the step of forming a third SiGe layer on the second SiGe layer, In the process of forming the first SiGe layer, the Ge composition ratio is increased from the silicon substrate side toward the second SiGe layer side. In the process of forming the second SiGe layer, the Ge composition ratio is reduced from the first SiGe layer side toward the third SiGe layer side. A method for manufacturing a SiGe epitaxial wafer, characterized in that the Ge composition ratio is kept constant in the thickness direction during the step of forming the third SiGe layer.

9. The method for manufacturing a SiGe epitaxial wafer according to claim 8, characterized in that, in the step of forming the first SiGe layer, the thickness of the first SiGe layer is in the range of 10 to 10,000 nm.

10. The method for manufacturing a SiGe epitaxial wafer according to claim 8, characterized in that, in the step of forming the second SiGe layer, the thickness of the second SiGe layer is in the range of 1 to 100 nm.

11. In the step of forming the first SiGe layer, the composition formula of the first SiGe layer is Si １－ｘ Ge ｘ The method for manufacturing a SiGe epitaxial wafer according to claim 8, characterized in that (0 < x ≤ 0.3).

12. In the step of forming the second SiGe layer, the composition formula of the second SiGe layer is Si １－ｙ Ge ｙ (0 < y ≤ 0.3), and the method for manufacturing a SiGe epitaxial wafer according to claim 8, characterized in that.

13. In the step of forming the third SiGe layer, the composition formula of the third SiGe layer is Si １－ｚ Ge ｚ The method for manufacturing a SiGe epitaxial wafer according to claim 8, characterized in that (0 < z ≤ 0.3).

14. A method for manufacturing a SiGe epitaxial wafer according to any one of claims 8 to 13, characterized in that the step of forming the second SiGe layer is performed multiple times after the step of forming the first SiGe layer.

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