Threshold voltage compensation circuit and CMOS inverter

Abstract

The threshold voltage variation is compensated for, the output voltage of the CMOS inverter is brought close to half of the CMOS inverter's power supply voltage, and the through-current value is controlled to approach the design value. [Solution] The circuit has a first threshold voltage compensation circuit and a second threshold voltage compensation circuit. The first threshold voltage compensation circuit detects the change from the design value of the drain-source current of the common-source amplifier circuit due to variations in the threshold voltage, and detects and outputs the compensation voltage of the back gate terminal of the MOSFET of one polarity by feedback-controlling the voltage of the back gate terminal so that the change becomes smaller.

Description

Technical Field

[0001] The present invention relates to a threshold voltage compensation circuit and a CMOS inverter.

Background Art

[0002] Due to its low power consumption characteristics, the CMOS process is expected to be applied to integrated circuits other than logic circuits. The conventional CMOS inverter 3, which is a basic configuration of a CMOS logic circuit, connects the gate terminals and drain terminals of an n-type MOSFET (hereinafter abbreviated as nMOS) 19 and a p-type MOSFET (similarly abbreviated as pMOS) 59 as shown in FIG. 11, uses the gate terminal as the input terminal 103 and the drain terminal as the output terminal 104, and connects the source terminal 309 of the nMOS to the ground and the source terminal 209 of the pMOS to the positive power supply (Vdd). When the input potential is 0 V (logical Lo) or Vdd V (logical Hi), either MOSFET is OFF, so there is no DC current consumption, and only dynamic power consumption occurs during logic switching. Therefore, compared with a "current switching type logic circuit" based on a differential amplifier circuit, which is often used in integrated circuits other than CMOS that manufacture only n-type transistors, a logic circuit with extremely low power consumption can be configured. Also, compared with a normal source-grounded type inverting amplifier circuit, in a CMOS inverter, the load resistance for the nMOS is the pMOS, and the load resistance for the pMOS is the nMOS, and each has a non-linear current characteristic. Therefore, extremely steep voltage switching characteristics can be obtained in the input-output characteristics.

[0003] If this steep voltage switching characteristic can be utilized as a high small-signal gain in an amplification circuit, the number of stages in the amplification circuit can be reduced, resulting in lower power consumption. However, this requires operation at a DC bias point where both the nMOS and pMOS are simultaneously ON (through-current is flowing) at an input potential of Vdd / 2. Generally, CMOS inverters are designed by adjusting the gate widths of the nMOS and pMOS so that the output voltage is Vdd / 2 when the input voltage is Vdd / 2. However, since CMOS processes generally have variations in threshold voltage, the current values ​​at the DC bias voltage conditions of the design fluctuate independently for both the nMOS and pMOS. This causes the output voltage to deviate significantly from Vdd / 2, leading to critical malfunctions in gain and linear operating range when operating as an analog small-signal amplification circuit. Furthermore, even if the output voltage is Vdd / 2, it is clear that if the current values ​​of both the nMOS and pMOS are low, it will similarly lead to critical malfunctions in gain and linear operating range. In other words, a "threshold voltage compensation circuit" is required to compensate for threshold voltage fluctuations in the CMOS process and simultaneously compensate for the inverter's output voltage and the amount of through-current flowing through the inverter.

[0004] For example, Non-Patent Documents 2 and 3 show the configuration of a logic circuit that corrects threshold voltage. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] “First single-fibre bi-directional XFP transceiver for optical metro / access networks.,” Tomoaki Yoshida, Shunji Kimura, Kiyomi Kumozaki, and Takamasa Imai, Paper We4.P.021, 2005 31st European Conference on Optical Communication, ECOC 2005. [Non-Patent Document 2] "Development of a technique for compensating for characteristic variations in low-voltage CMOS digital circuits," Yusuke Tsugita, Kenichi Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya, IEICE Technical Report, IST2008-51, Oct., 2008. [Non-Patent Document 3] “A 300 nW, 15 ppm / C, 20 ppm / V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs,” Ken Ueno, Tetsuya Hirose, Tetsuya Asai, and Yoshihito Amemiya, IEEE J. Solid-State Circuits, SC-44, No. 7, July 2009, pp.2047-2054. [Overview of the project] [Problems that the invention aims to solve]

[0006] However, in these logic circuits, when correcting the DC bias operating point voltage of the pMOS based on the current of the nMOS, the positive power supply voltage Vdd is changed simultaneously with the back gate voltage of the pMOS, which can cause the inverter output potential to deviate from the reference. The object of the present invention is to provide a threshold voltage compensation circuit that can compensate for variations in threshold voltage and simultaneously compensate the output potential and through-current value of the inverter to values ​​that allow it to operate as an amplification circuit. [Means for solving the problem]

[0007] One aspect of the present invention involves forming a common-source amplifier circuit using a MOSFET of either nMOS or pMOS polarity, applying a DC bias voltage to the input terminal of the common-source amplifier circuit to detect the change in the drain-source current of the common-source amplifier circuit from the design value due to variations in the threshold voltage, and feedback-controlling the voltage at the back gate terminal to reduce the change, thereby detecting and outputting a compensation voltage at the back gate terminal of the MOSFET of one polarity, and the compensation voltage output by the first threshold voltage compensation circuit being used by the first threshold voltage compensation circuit This threshold voltage compensation circuit includes a CMOS inverter circuit whose through-current value is compensated by applying a DC bias voltage to the back gate terminal of a MOSFET of the same polarity, and a second threshold voltage compensation circuit that compares the DC output voltage and the reference voltage when a DC bias voltage is applied to the input terminal of the CMOS inverter circuit using a differential amplifier circuit, and feeds back a compensation voltage to the back gate terminal of a MOSFET of the other polarity of the CMOS inverter so as to reduce the voltage difference, thereby detecting and outputting the compensation voltage at the back gate terminal of the MOSFET of the other polarity of the CMOS inverter. [Effects of the Invention]

[0008] According to the present invention, it is possible to simultaneously compensate for changes in the DC output voltage and through-current value of the inverter due to variations in threshold voltage. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows a first embodiment of the circuit configuration of a first threshold voltage compensation circuit that compensates for the drain-source current value due to variations in threshold voltage according to this embodiment. [Figure 2] This figure shows a second embodiment of the circuit configuration of the first threshold voltage compensation circuit that compensates for the drain-source current value due to variations in the threshold voltage according to this embodiment. [Figure 3]This figure shows a third embodiment of the circuit configuration of the first threshold voltage compensation circuit that compensates for the drain-source current value due to variations in the threshold voltage according to this embodiment. [Figure 4] This figure shows a fourth embodiment of the circuit configuration of the first threshold voltage compensation circuit that compensates for the drain-source current value due to variations in the threshold voltage according to this embodiment. [Figure 5] This figure shows a fifth embodiment of the circuit configuration of the first threshold voltage compensation circuit that compensates for the drain-source current value due to variations in the threshold voltage according to this embodiment. [Figure 6] This figure shows a first embodiment of the circuit configuration of a threshold voltage compensation circuit that compensates for threshold voltage variations according to this embodiment. [Figure 7] This figure shows a second embodiment of the circuit configuration of a threshold voltage compensation circuit that compensates for threshold voltage variations according to this embodiment. [Figure 8] This figure shows a third embodiment of the circuit configuration of a threshold voltage compensation circuit that compensates for threshold voltage variations according to this embodiment. [Figure 9] This figure shows a fourth embodiment of the circuit configuration of a threshold voltage compensation circuit that compensates for variations in threshold voltage according to this embodiment. [Figure 10] The calculation results are shown in the figure. [Figure 11] This diagram shows the circuit configuration of a conventional CMOS inverter. [Modes for carrying out the invention]

[0010] Embodiments of the present invention will be described in detail below with reference to the drawings. Figure 1 shows a first embodiment of the circuit configuration of the "first threshold voltage compensation circuit for compensating drain-source current values ​​due to threshold voltage variations" according to this embodiment. The first threshold voltage compensation circuit 1 has an input terminal 101, an output terminal 102, and terminals 201, 301 to 303.

[0011] The first threshold voltage compensation circuit 1 in FIG. 1 has four nMOSs 11 to 14 and a resistor 401. The drain of nMOS 11 is connected to the resistor 401 and the gate of nMOS 12. The gate of nMOS 11 is connected to the input terminal 101. The source of nMOS 11 is connected to a power supply or electrical ground via the terminal 301. The back gate of nMOS 11 is connected to the drain of nMOS 13, the output terminal 102, and the source of nMOS 12.

[0012] The drain of nMOS 12 is connected to the source of nMOS 14. The back gate of nMOS 12 is connected to the source of nMOS 12.

[0013] The gate of nMOS 13 is connected to a power supply or electrical ground via the terminal 302. The source of nMOS 13 is connected to a power supply or electrical ground via the terminal 303. The back gate of nMOS 13 is connected to the source of nMOS 13.

[0014] The drain of nMOS 14 is connected to a power supply or electrical ground via the terminal 201 and is connected to the gate of nMOS 14 and the resistor 401. The source of nMOS 14 is connected to the drain of nMOS 12 and the back gate of nMOS 14.

[0015] In the first threshold voltage compensation circuit 1, nMOS 11 and the resistor 401 function as a source-grounded inverting amplifier circuit, and nMOS 11 functions as a source-grounded transistor. In the first threshold voltage compensation circuit 1, nMOS 12 functions as a drain-grounded amplifier circuit. In the first threshold voltage compensation circuit 1, nMOS 13 functions as a constant current source transistor. In the first threshold voltage compensation circuit 1, nMOS 14 functions as a DC level shift diode.

[0016] The common-source amplifier circuit, consisting of an nMOS11 and a resistor 401, is designed so that when a DC potential of Vdd / 2 is applied to the input terminal 101, the voltage drop, which is determined by the product of the current Ids flowing between the drain and source of the nMOS11 and the resistor 401, is Vdd / 2. Due to variations in the threshold voltage of the nMOS11, if the amount of current changes from the drain-source current Ids at the time of design, this change will appear as a change in the voltage at the drain terminal of the nMOS11.

[0017] On the other hand, transistors such as MOSFETs have the characteristic that when a sufficient drain-source voltage (Vds) is applied, the drain-source current (Ids) saturates according to the value of the gate-source voltage (Vgs). By fixing Vgs in this saturation region, they function as a constant current source. nMOS13 (constant current source transistor) determines the current value (i.e., the gate-source voltage Vgs) of nMOS12 and 14. Since the only path for DC current to flow is vertically through the drain-source junctions of nMOS14, nMOS12, and nMOS13, if the Vgs of nMOS13 is applied between terminals 303 and 302 (assuming 0 V is applied to terminal 302 and -Vdd / 2 to terminal 303, and the power supply voltage applied to terminal 201 is Vdd), the same current as the drain-source current (Ids) of nMOS13 will flow through nMOS12 and nMOS14, and the Vgs of nMOS12~14 will all be Vdd / 2 (assuming the gate widths of the nMOS12~14 transistors are all the same). Since the Ids of nMOS12~14 cannot be changed, their Vgs cannot be changed either, and the voltage change at the drain terminal of nMOS11 caused by the threshold voltage variation of nMOS11 will directly appear as a potential change at the source terminal of nMOS12. Since the source terminal of nMOS12 is connected to the back gate terminal of nMOS11, the body bias effect causes the current value Ids of nMOS11 to change in a direction that reduces the voltage change. Therefore, negative feedback is applied to control the Ids of nMOS11 so that it approaches the design value.

[0018] The nMOS14 is a DC level-shift diode, and since Vgs is fixed at Vdd / 2, the voltage at the drain terminal (gate terminal) of the nMOS14 is Vdd / 2 higher than the voltage at the drain terminal (Vdd / 2) of the nMOS12. Therefore, the voltage at the drain terminal (gate terminal) of the nMOS14 is equal to the voltage Vdd on the terminal 201 side of resistor 401, and one end of the drain terminal (gate terminal) of the nMOS14 and the terminal 201 side of resistor 401 can be integrated into terminal 201. In other words, if there is no need to integrate terminal 201, the nMOS14 can be omitted (see Figure 2: Second embodiment of the first threshold voltage compensation circuit 1). In Figure 2, the separated terminals 201 are represented as terminals 201 and 202.

[0019] It is clear that a drain-grounded transistor (source follower) using a constant current load composed of nMOS12~14 can compensate for the threshold voltage of nMOS11, which has its source grounded, using the voltage at the source terminal of nMOS12, i.e., output terminal 102, thereby bringing Ids closer to the design value. Furthermore, since the source follower circuit is used only to feed back the voltage change, there is no need to compensate for the threshold voltage of nMOS12~14 that constitute this circuit. Also, the source terminal of nMOS13 in the circuit of Figure 1 is connected to a negative power supply via terminal 303, and each terminal is supplied with a voltage that is -Vdd / 2 lower than the DC bias voltage of nMOS11. Therefore, to compensate for the back gate terminal of nMOS13 in Figure 1, as shown in Figure 2, an nMOS15 that functions as a DC level shift diode can be inserted between output terminal 102 and nMOS12, and the cathode (source) terminal of nMOS15 can be used as output terminal 102. Here, we assume that the gate width of the nMOS15 is the same as that of the nMOS12-13.

[0020] Figure 3 shows a third embodiment of the first threshold voltage compensation circuit 1 of this embodiment, which consists of three cascaded common-source inverting amplifier circuits composed of nMOS 11 and resistor 401 from the first embodiment. Since the amount of voltage change to be fed back must be the output of the inverting amplifier, the number of common-source amplifier stages is odd. The first threshold voltage compensation circuit 1 shown in Figure 3 includes three nMOS 11-1 to 11-3 and three resistors 401-1 to 401-3, which function as common-source transistors. In the third embodiment of the first threshold voltage compensation circuit 1, sufficient loop gain can be obtained in the feedback loop, thereby improving the convergence of the feedback loop. Similar to the second embodiment, nMOS 14 is not required; by adding nMOS 15, which is a DC level-shift diode, between output terminal 102 and nMOS 13, the same effect as in the second embodiment can be obtained. Here, assuming the need to compensate for the threshold voltages of both the common-source transistors nMOS11-1 to 11-3 and the constant current source transistor nMOS13 in the circuit of Figure 1, two output terminals 102-1 and 102-2 are provided to allow output at both levels.

[0021] Figure 4 shows a fourth embodiment of the first threshold voltage compensation circuit 1 of this embodiment, in which a loop filter 501 is added to the feedback loop of the first embodiment to improve convergence. The fourth embodiment is mainly used when the input voltage is fluctuating but the average value is constant, and it is desired to feed back the response to that average value. The loop filter 501 is a low-pass filter that allows only frequency components below a specific frequency to pass through. When a signal is applied as the input voltage, the loop filter 501 uses a low-pass filter with an upper limit frequency lower than the lower limit of the frequency components of the signal. The loop filter 501 is provided at any point along the feedback loop path of the common-source inverting amplifier circuit, from the gate terminal of nMOS 11 to the back gate terminal. In the example shown in Figure 4, the loop filter 501 is provided between the drain terminal of nMOS 11 and the gate terminal of nMOS 12.

[0022] The loop filter 501 can be inserted between the input terminal 101 and the gate terminal of the nMOS 11 to achieve a similar effect. However, inserting the loop filter 501 between the input terminal 101 and the gate terminal of the nMOS 11 has the same effect as applying a DC potential equivalent to the average value to the input terminal 101. Similarly, inserting the loop filter 501 between the source terminal of the nMOS 12 and the back gate terminal of the nMOS 11 also has the same effect as adding a loop filter to the feedback loop path of the common-source inverting amplifier circuit. However, in this case, the output terminals 102-1 and 102-2 will output the inverted fluctuation of the input potential amplified by the nMOS 11. Therefore, it is necessary to insert a filter similar to the loop filter 501 between the output terminals 102-1 and 102-2 and the back gate terminal of the MOSFET whose threshold voltage is compensated by the first threshold voltage compensation circuit 1.

[0023] Figure 5 shows a fifth embodiment of the first threshold voltage compensation circuit 1 of this embodiment, which is an example of the fourth embodiment shown in Figure 4, but constructed with pMOS. pMOS 51, 52, 53, 54, and 55 correspond to nMOS 11, 12, 13, 14, and 15, respectively. In the fifth embodiment, only the polarity of the fourth embodiment is reversed, and the role of each element is the same, so it is clear that the change in Ids due to the threshold voltage variation of the pMOS is compensated for and the current value is controlled to approach the design value. For convenience, Figure 5 shows the fourth embodiment of Figure 4 implemented with pMOS, but it is clear that the embodiments from Figures 1 to 3 can also be implemented with pMOS in the same way.

[0024] Figure 6 shows a first embodiment of the threshold voltage compensation circuit of this embodiment. Figure 6 shows the first threshold voltage compensation circuit 1, the second threshold voltage compensation circuit 2, and the CMOS inverter 3. The CMOS inverter 3 is a conventional CMOS inverter as shown in Figure 11, and has pMOS 59, nMOS 19, input terminal 103, and output terminal 104. The CMOS inverter 3 also has terminals 209 and 309.

[0025] In Figure 6, the first threshold voltage compensation circuit 1, which compensates for the drain-source current value due to variations in the threshold voltage of the CMOS inverter 3, is shown using the circuit diagram shown in Figure 4. The first threshold voltage compensation circuit 1 shown in Figure 4 compensates for the drain-source current value of the nMOS, so its output terminal 102-1 is connected to the back gate terminal of the nMOS 19 of the CMOS inverter 3. However, if the threshold voltage of the other pMOS 59 constituting the CMOS inverter 3 varies, even if a positive power supply Vdd is applied to terminal 209 of the CMOS inverter 3 and terminal 309 is grounded, the DC output voltage of output terminal 104 of the CMOS inverter 3 will deviate from Vdd / 2.

[0026] Therefore, a second threshold voltage compensation circuit 2 is required to compensate the output DC voltage of the CMOS inverter 3 to Vdd / 2 (the midpoint potential between the positive power supply and ground) by feedback-controlling the voltage of the back gate terminal of the pMOS. In Figure 6, a differential amplifier circuit consisting of nMOS 16~18 and resistors 402 and 403, and a source follower consisting of pMOS 60~62 constitute the second threshold voltage compensation circuit 2.

[0027] The second threshold voltage compensation circuit 2 has terminals 105, 106, 206-208, and 306-308. Terminals 206-208 are normally connected to a positive power supply or electrical ground, and terminals 306-308 are connected to a negative power supply or electrical ground. As will be described later, Vdd / 2 is applied as a reference voltage to the reference voltage input terminal 105. Terminal 106 is the output terminal of the second threshold voltage compensation circuit and, together with the output terminal 102 of the first threshold voltage compensation circuit, is connected to the back gate terminals of the pMOS / nMOS of the CMOS inverter whose threshold voltage is to be compensated.

[0028] The source and back gate of nMOS16 are connected to the drain of nMOS18. The gate of nMOS16 is connected to output terminal 104 of CMOS inverter 3. The drain of nMOS16 is connected to resistor 402.

[0029] The source and back gate of nMOS17 are connected to the drain of nMOS18. The gate of nMOS17 is connected to the reference voltage input terminal 105. The drain of nMOS17 is connected to the gate of pMOS60 via resistor 403 and loop filter 502.

[0030] The source of the nMOS18 is connected to terminal 308. The gate of the nMOS18 is connected to terminal 306. The back gate of the nMOS18 is connected to output terminal 102-2.

[0031] Resistor 402 is connected to terminal 208 at one end and to the drain of nMOS16 at the other end. Resistor 403 is connected to terminal 208 at one end and to the drain of nMOS17 at the other end.

[0032] The source and back gate of pMOS60 are connected to the drain of pMOS61, the back gate of pMOS59, and output terminal 106. The drain of pMOS60 is connected to the source and back gate of pMOS62.

[0033] The source and back gate of the pMOS61 are connected to terminal 207. The gate of the pMOS61 is connected to terminal 206.

[0034] The source and back gate of pMOS62 are connected to the drain of pMOS60. The gate and drain of pMOS62 are connected to terminal 307.

[0035] The output terminal 104 of the CMOS inverter 3 is connected to the gate terminal of the nMOS 16. When Vdd / 2 is applied as a reference voltage to the gate terminal (reference voltage input terminal) 105 of the other differential input terminal, the nMOS 17, the differential amplifier circuit amplifies the difference between this value and the output voltage of the CMOS inverter 3, and feeds back its positive-sequence output to the back gate of the pMOS 59 via the common-drain transistor pMOS 60. This controls the output voltage so that the difference between the output voltage of the CMOS inverter 3 and Vdd / 2 decreases, allowing the output DC voltage to approach Vdd / 2. However, if the current flowing through the differential amplifier of nMOS 16-18 deviates from the design value, the voltage drop across resistors 402 and 403 will also deviate from the design value, making accurate feedback impossible. For this reason, threshold voltage compensation is required for the nMOS 18, which is a constant current source transistor that determines the current amount of the differential amplifier. Threshold voltage compensation can be supplied from the output terminal 102-2 of the first threshold voltage compensation circuit 1. The differential pair of nMOS16 and 17 are composed of transistors with half the gate width of nMOS23, as they each carry half of the current from nMOS23. However, even if the threshold voltage fluctuates, the current flowing is determined by nMOS23, and even if it changes, only the potential of the common source terminal changes, and the voltage on the drain side does not change, so there is no need to apply threshold voltage compensation.

[0036] In the first embodiment shown in Figure 6, a CMOS inverter 3 is incorporated into the diagram for explanation. However, since the threshold voltage compensation circuit of the present invention is a control circuit connected to the CMOS inverter 3, it can be implemented with only the parts excluding the pMOS 59 and nMOS 19. Of course, it is clear that the same effect can be obtained by considering a circuit that includes the CMOS inverter 3 and outputs the threshold voltage compensation voltage of the CMOS inverter 3 from output terminals 102-1 and 106. Also, for convenience, an example in the diagram shows the loop filter 502 implemented on the feedback loop of the differential amplifier circuit, but it can be omitted when operating with only DC voltage. The loop filter 502 is a filter that has the same function as the loop filter 501.

[0037] In other words, the first threshold voltage compensation circuit 1 controls the through-current of the CMOS inverter 3 by feedback-controlling the voltage at the back gate of the nMOS 11 so that the drain-source current of the nMOS 11 becomes the design current value, and by applying this compensation voltage to the back gate terminal of the nMOS 19 of the CMOS inverter 3. The second threshold voltage compensation circuit 2 detects the difference between the voltage output from the output terminal 104 of the CMOS inverter 3 and the reference voltage (Vdd / 2) applied to the reference voltage input terminal 105, and controls the output voltage of the CMOS inverter 3 to approach Vdd / 2 by feedback-controlling to reduce this difference.

[0038] Figure 7 shows a second embodiment of the threshold voltage compensation circuit of this embodiment, and the basic configuration is the same as the circuit of the first embodiment. This is an example in which the potential equivalent to Vdd / 2 applied to the input terminal 101 and the reference voltage input terminal 105 is supplied from the internal terminals of the circuit, and the power supply voltage is made common, thereby minimizing the number of terminals.

[0039] In Figure 6, terminals 206, 208, and 209 are integrated into a single terminal 201 in Figure 7. This eliminates the need to specify the number of terminals for the positive power supply. Furthermore, terminals 101 and 103 in Figure 6 are integrated into a single terminal 101 in Figure 7. This eliminates the need for an input terminal for the CMOS inverter 3. Furthermore, terminals 301, 306, 307, and 309 in Figure 6 are integrated into a single terminal 301 in Figure 7. This eliminates the need to specify the number of terminals for the negative power supply. Furthermore, terminals 304 and 308 in Figure 6 are integrated into 304 in Figure 7. This eliminates the need for a separate negative power supply terminal. Terminal 105 in Figure 6 is connected to the source and back gate of pMOS 62 and the drain of pMOS 60. This eliminates the need for terminal 105.

[0040] Figure 8 shows a third embodiment of the threshold voltage compensation circuit of this embodiment, which is an example constructed using transistors with the opposite polarity to those of the first embodiment shown in Figure 6. In the third embodiment, the first threshold voltage compensation circuit 1, which compensates for the drain-source current value due to variations in the threshold voltage, is constructed using pMOS transistors. The nMOS 11, 12, 13, 14, and 15 in the first embodiment correspond to the pMOS 51, 52, 53, 54, and 55 in the third embodiment. The nMOS 16, 17, 18 and pMOS 60, 61, 62 of the second threshold voltage compensation circuit 2 in the first embodiment correspond to the pMOS 56, 57, 58 and nMOS 20, 21, 22 of the second threshold voltage compensation circuit 2 in the third embodiment.

[0041] In the first embodiment, the first threshold voltage compensation circuit 1 provides a compensation voltage to the nMOS 19 of the CMOS inverter 3, whereas in the third embodiment, the first threshold voltage compensation circuit 1 provides a compensation voltage to the pMOS 59 of the CMOS inverter 3. Furthermore, in the first embodiment, terminal 106 of the second threshold voltage compensation circuit 2 is connected to the pMOS 59 of the CMOS inverter 3, whereas in the third embodiment, terminal 106 of the second threshold voltage compensation circuit 2 is connected to the nMOS 19 of the CMOS inverter 3. Therefore, it is clear that the third embodiment will achieve the same effects as the first embodiment.

[0042] Figure 9 shows a fourth embodiment of the threshold voltage compensation circuit of this embodiment, in which the differential amplifier in the second threshold voltage compensation circuit 2 of the first embodiment in Figure 6 is increased to two stages, improving the loop gain of the feedback loop. If the final stage differential amplifier can provide a positive-sequence output to the pMOS 60 with respect to the input of the nMOS 16-1 of the first stage differential amplifier, the number of stages of the differential amplifier can be increased to any number.

[0043] Although the first threshold voltage compensation circuit 1 in Figures 6-7 and 9 was explained using the first threshold voltage compensation circuit 1 shown in Figure 4, it is also possible to control the CMOS inverter 3 by using the first threshold voltage compensation circuit 1 shown in Figures 1-3 together with the second threshold voltage compensation circuit 2.

[0044] (calculation result) The calculations performed are explained below. In the calculations, the threshold voltages of pMOS59 and nMOS19 of the CMOS inverter 3 in Figure 6 were changed in the same direction, while the current change was in opposite directions, and the output voltage V of the CMOS inverter was calculated as time progressed. out The change was calculated. As a comparative example, the output voltage V was calculated for a CMOS inverter 3 without the first threshold voltage compensation circuit 1 and the second threshold voltage compensation circuit 2 shown in Figure 11, when the threshold voltages of pMOS 59 and nMOS 19 were changed in the same direction, but the current change was in the opposite direction. out The change was calculated.

[0045] Figure 10 shows the calculation results. In Figure 10, the vertical axis represents the voltage magnitude, and the horizontal axis represents time (change in threshold voltage). The red solid line represents the output voltage V out The magnitude is shown, and the yellow solid line indicates the magnitude of the threshold voltage. Figure 10(a) shows the calculation results in the comparative example, and Figure 10(b) shows the calculation results in the threshold voltage compensation circuit of Figure 6.

[0046] In the comparative example, the threshold voltage is not compensated, so the output voltage V out The voltage fluctuates by more than 1V. However, if compensation is applied, the output voltage V out The fluctuation of V dd The value is within ±5mV relative to / 2 = 0.9V. From this, it can be said that in this embodiment, fluctuations in the threshold voltage of the MOSFET of the CMOS inverter can be compensated for. [Explanation of symbols]

[0047] 1 First threshold voltage compensation circuit, 2 Second threshold voltage compensation circuit, 3 CMOS inverter, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 nMOS, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62 pMOS, 101 Input terminal of the first threshold voltage compensation circuit, 102 (102-1, 102-2) Output terminal of the first threshold voltage compensation circuit, 103 Inverter input terminal, 104 Inverter output terminal (input terminal of the second threshold voltage compensation circuit), 105 Reference voltage input terminal, 106 Output terminals of the second threshold voltage compensation circuit: 201, 202, 203, 204, 205, 206, 207, 208, 209, 301, 302, 303, 304, 305, 306, 307, 308, 309; terminals: 401, 402, 403; resistors: 501; loop filter of the first threshold voltage compensation circuit: 502; loop filter of the second threshold voltage compensation circuit

Claims

1. A threshold voltage compensation circuit for a CMOS inverter, A threshold voltage compensation circuit comprising: a first threshold voltage compensation circuit that forms a common-source amplifier circuit using a MOSFET of either nMOS or pMOS polarity, applies a DC bias voltage to the input terminal of the common-source amplifier circuit to detect a change in the drain-source current of the common-source amplifier circuit from a design value due to variations in threshold voltage, and detects and outputs a compensation voltage at the back gate terminal of the MOSFET of one polarity by feedback control of the voltage at the back gate terminal so as to reduce the change; a CMOS inverter circuit in which the through-current value is compensated by applying the compensation voltage output by the first threshold voltage compensation circuit to the back gate terminal of a MOSFET of the same polarity as the first threshold voltage compensation circuit; and a second threshold voltage compensation circuit that compares the DC output voltage when a DC bias voltage is applied to the input terminal of the CMOS inverter circuit with a reference voltage using a differential amplifier circuit, and detects and outputs a compensation voltage at the back gate terminal of the MOSFET of the other polarity of the CMOS inverter by feeding back the compensation voltage to the back gate terminal of the MOSFET of the other polarity of the CMOS inverter so as to reduce the voltage difference.

2. The first threshold voltage compensation circuit consists of a common-source amplifier circuit and a first source follower circuit having a constant current source load, the output voltage of the common-source amplifier circuit is input to the first source follower circuit, and the output voltage of the first source follower circuit is fed back to the back gate terminal of the common-source transistor of the common-source amplifier circuit. The threshold voltage compensation circuit according to claim 1.

3. The above-mentioned common-source amplifier circuit is connected in any odd number of stages in cascade. The threshold voltage compensation circuit according to claim 2.

4. The feedback loop path from the gate terminal to the back gate terminal of the common-source transistor has a loop filter consisting of a low-pass filter at any point along the path of the feedback loop, The threshold voltage compensation circuit according to claim 2 or claim 3.

5. The system has the first threshold voltage compensation circuit and the second threshold voltage compensation circuit, The aforementioned second threshold voltage compensation circuit has a differential amplifier circuit and a second source follower circuit. The differential amplifier circuit compares a voltage equal to half the power supply voltage applied to the CMOS inverter with the output voltage of the CMOS inverter. The constant current source transistor of the differential amplifier circuit is compensated by the first threshold voltage compensation circuit. The positive-sequence output of the differential amplifier circuit is input to the second source follower circuit, and the output of the second source follower circuit is fed back to the back gate terminal of a MOSFET of the CMOS inverter, which is compensated by the first threshold voltage compensation circuit, and which has the opposite polarity to the MOSFET. The threshold voltage compensation circuit according to claim 2 or 3.

6. The differential amplifier circuit can be connected in any number of stages. The threshold voltage compensation circuit according to claim 5.

7. A loop filter consisting of a low-pass filter is provided at any point along the path of the feedback loop, from the input terminal of the differential amplifier circuit that receives the output voltage of the CMOS inverter of the second threshold voltage compensation circuit, to the back gate terminal of the MOSFET of the opposite polarity of the MOSFET on the side compensated by the first threshold voltage compensation circuit of the CMOS inverter. The threshold voltage compensation circuit according to claim 5.

8. A threshold voltage compensation circuit for a CMOS inverter, A threshold voltage compensation circuit is formed using a MOSFET of either nMOS or pMOS polarity, and by applying a DC bias voltage to the input terminal of the common-source amplifier circuit, it detects the change in the drain-source current of the common-source amplifier circuit from its design value due to variations in threshold voltage, and by feedback-controlling the voltage at the back gate terminal to minimize this change, it detects and outputs the compensation voltage at the back gate terminal of the MOSFET of the one polarity.

9. The invention comprises the first threshold voltage compensation circuit and the second threshold voltage compensation circuit described in claim 1, CMOS inverter.

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