Capacitor and semiconductor device containing the same, and method for manufacturing the same

Abstract

The present invention provides a capacitor, a semiconductor device containing the same, and a method for manufacturing the same. [Solution] The capacitor of the present invention includes a first electrode, a second electrode provided opposite the first electrode, and a dielectric layer provided between the first electrode and the second electrode, which includes a rutile crystal phase. The first electrode includes a group 5B element, or a metal nitride containing a group 5B element and a group 4B element.

Description

[Technical Field]

[0001] The present invention relates to a capacitor, a semiconductor device including the same, and a method for manufacturing the same. [Background technology]

[0002] A memory cell, the basic unit of DRAM (Dynamic Random Access Memory), consists of one transistor that controls charge transfer and one capacitor that stores charge. The size of DRAM memory cells is continuously decreasing, and this miniaturization of DRAM reduces the charge storage capacity of the capacitor. Therefore, in order to improve the charge storage capacity while compensating for the decrease in capacitor size, it is necessary to improve the dielectric constant of the dielectric layer. [Overview of the project] [Problems that the invention aims to solve]

[0003] The problem that this invention aims to solve is to provide a capacitor, a semiconductor element including the same, and a method for manufacturing the same. [Means for solving the problem]

[0004] On one side, a capacitor is provided comprising a first electrode, a second electrode provided opposite to the first electrode, and a dielectric layer provided between the first electrode and the second electrode, which includes a rutile crystal phase, wherein the first electrode includes a metal nitride containing a group 5B element, or a group 5B element and a group 4B element.

[0005] The dielectric layer is provided so as to be in contact with the first electrode.

[0006] The dielectric layer may contain TiO2.

[0007] The dielectric layer may predominantly contain a rutile crystalline phase.

[0008] The dielectric layer may have a thickness of 100 Å or less.

[0009] The Group 5B element may include V, Nb, Ta, or Db.

[0010] The Group 4B element may include Ti, Zr, Hf, or Rf.

[0011] The first electrode may be MN or M

[0017] , M’ 1-x N (0 < x < 1, M is a Group 5B element, M’ is a Group 4B element, and N is nitrogen), and may include a nitride represented by this formula.

[0012] On the other hand, in a semiconductor device including a capacitor, the capacitor includes a first electrode, a second electrode provided to face the first electrode, and a dielectric layer provided between the first electrode and the second electrode and including a rutile crystal phase. The first electrode includes a Group 5B element or a metal nitride including a Group 5B element and a Group 4B element, and a semiconductor device is provided.

[0013] The dielectric layer is provided so as to contact the first electrode.

[0014] The dielectric layer may include TiO2.

[0015] The first electrode may be MN or M x M’ 1-x N (0 < x < 1, M is a Group 5B element, M’ is a Group 4B element, and N is nitrogen), and may include a nitride represented by this formula.

[0016] <0********>On yet another aspect, in a method for manufacturing a semiconductor device including a capacitor, the capacitor is manufactured by a method including steps of forming a first electrode including a metal nitride including a Group 5B element, forming a dielectric layer including a rutile crystal phase on the first electrode, and forming a second electrode on the dielectric layer. A method for manufacturing a semiconductor device is provided.

[0017] The Group 5B element may include V, Nb, Ta, or Db.

[0018] The first electrode may further include a Group 4B element.

[0019] The Group 4B element may include Ti, Zr, Hf, or Rf.

[0020] The dielectric layer may include TiO2.

[0021] The dielectric layer may be formed by directly depositing TiO2 on the first electrode using an atomic layer deposition (ALD) process.

[0022] The dielectric layer may be formed to predominantly contain a rutile crystal phase.

[0023] The dielectric layer may be formed with a thickness of 100 Å or less.

Brief Description of the Drawings

[0024] [Figure 1] It is a cross-sectional view schematically showing a capacitor according to an exemplary embodiment. [Figure 2A] It is a drawing for explaining a method of manufacturing a capacitor according to the exemplary embodiment shown in FIG. 1. [Figure 2B] It is a drawing for explaining a method of manufacturing a capacitor according to the exemplary embodiment shown in FIG. 1. [Figure 2C] It is a drawing for explaining a method of manufacturing a capacitor according to the exemplary embodiment shown in FIG. 1. [Figure 3] It is a TEM (Transmission Electron Microscope) photograph showing a state where a rutile TiO2 layer is deposited on a VN electrode according to an exemplary embodiment. [Figure 4] It is a simulation result showing the change in interfacial energy due to heat treatment for the oxynitride of Group 5B element M and the oxide of Group 5B element M. [Figure 5] This diagram shows the crystalline phases that appear when a TiO2 dielectric layer is grown on each oxide layer of a group 5B element M through an atomic layer deposition (ALD) process. [Figure 6] This figure shows the results of measuring the leakage current density J and the equivalent oxide film thickness Toxeq. in a comparative example capacitor and an exemplary embodiment capacitor. [Figure 7] This is a circuit diagram illustrating the schematic circuit configuration and operation of a semiconductor element employing a capacitor according to an exemplary embodiment. [Figure 8] This is a schematic diagram showing a semiconductor device according to an exemplary embodiment. [Figure 9] This is a schematic diagram showing a semiconductor device according to another exemplary embodiment. [Figure 10] This is a plan view showing a semiconductor device according to yet another exemplary embodiment. [Figure 11] This is a cross-sectional view along the line A-A' in Figure 10. [Figure 12] This is a cross-sectional view showing a semiconductor device according to another exemplary embodiment. [Figure 13] This is a conceptual diagram illustrating a schematic element architecture applied to an electronic device according to an exemplary embodiment. [Figure 14] This is a conceptual diagram illustrating a schematic element architecture applied to an electronic device according to an exemplary embodiment. [Modes for carrying out the invention]

[0025] The following exemplary embodiments will be described in detail with reference to the attached drawings. In the following drawings, similar reference numerals refer to similar components, and the size of each component in the drawings is exaggerated for clarity and convenience of explanation. On the other hand, the embodiments described below are merely illustrative, and various modifications are possible from these embodiments.

[0026] In the following, "top" or "above" may include not only things that are directly above, below, to the left, or to the right in contact, but also things that are above, below, to the left, or to the right without contact. A singular expression includes multiple expressions unless the context clearly indicates otherwise. Also, when a part "contains" a component, this means that it does not exclude other components, but rather includes other components, unless otherwise specified.

[0027] The term "the foregoing" and similar referential terms can be used in both singular and plural forms. Unless explicitly stated otherwise, the steps constituting a method may be performed in any order, and are not necessarily limited to the order stated.

[0028] Furthermore, terms such as "...part" and "module" as used in the specification refer to a unit that processes at least one function or operation, which may be embodied in hardware or software, or in a combination of hardware and software.

[0029] The connections between the components shown in the drawings, or the connecting members, are illustrative examples of functional and / or physical or circuit connections, and in actual devices, they may be represented by interchangeable or additional diverse functional, physical, or circuit connections.

[0030] Any use of examples or illustrative terms is solely for the purpose of illustrating a technical idea and, unless limited by the claims, such examples or illustrative terms do not limit the scope.

[0031] Figure 1 is a schematic cross-sectional view showing a capacitor 100 according to an exemplary embodiment.

[0032] Referring to FIG. 1, the capacitor 100 may include a first electrode 110, a second electrode 120 disposed opposite to the first electrode 110, and a dielectric layer 130 provided between the first electrode 110 and the second electrode 120. Here, the dielectric layer 130 may include a dielectric material having a rutile crystal phase which is a stable phase at high temperature and high pressure.

[0033] The first electrode 110, which is a bottom electrode, may be disposed on a substrate (not shown). The substrate may be part of a structure that supports the capacitor 100 or part of an element connected to the capacitor 100. The substrate may include a semiconductor material pattern, an insulating material pattern, and / or a conductive material pattern. The substrate may include, for example, a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), etc., and / or an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0034] The first electrode 110 may include a predetermined metal nitride. Specifically, the first electrode 110 may include a metal nitride containing a Group 5B element. In this case, the first electrode 110 may include a nitride represented by MN (where M is a Group 5B element and N is nitrogen). The Group 5B element may include, for example, vanadium (V), niobium (Nb), tantalum (Ta), or dubnium (Db). The first electrode 110 may include a metal nitride in which a Group 4B element is added to the Group 5B element. In this case, the first electrode 110 is M x M’ 1-x It may include a nitride represented by N (0 < x < 1, M is a Group 5B element, M’ is a Group 4B element, and N is nitrogen). The Group 4B element may include, for example, titanium (Ti), zirconium (Zr), hafnium (Hf), or rutherfordium (Rf).

[0035] The first electrode 110 can be formed on a substrate by, for example, depositing a predetermined nitride using an atomic layer deposition (ALD) process. By including a nitride of a group 5B element in the first electrode 110, a dielectric layer 130 having a rutile crystal phase can be formed on the first electrode 110 through the oxide interface region.

[0036] The upper electrode, the second electrode 120, may be positioned opposite the first electrode 110 at a distance from each other. The second electrode 120 may contain a variety of conductive materials. The second electrode 120 may contain metals, metal nitrides, metal oxides, or combinations thereof. For example, the second electrode 120 may contain at least one conductive metal from among titanium (Ti), nickel (Ni), aluminum (Al), tantalum (Ta), tungsten (W), platinum (Pt), lead (Pd), gold (Au), iridium (Ir), rhodium (Rh), molybdenum (Mo), vanadium (V), niobium (Nb), ruthenium (Ru), and cobalt (Co), or it may contain conductive metal oxides or conductive metal nitrides of these metals. Conductive metal oxides may include, for example, platinum oxide (PtO), iridium oxide (IrO2), ruthenium oxide (RuO2), strontium ruthenium oxide (SrRuO2), barium strontium ruthenium oxide ((Ba,Sr)RuO3), calcium ruthenium oxide (CaRuO3), lanthanum strontium cobalt oxide ((La,Sr)CoO3), and the like. Conductive metal nitrides may include, for example, titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), cobalt nitride (CoN), tungsten nitride (WN), and the like.

[0037] The second electrode 120 may contain a metal nitride represented as HH'N, where H is a metallic element, H' is an element different from H, and N is nitrogen. Here, H is one or more elements selected from, for example, Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U. H' is, for example, one or more elements selected from H, Li, As, Se, N, O, P, S, Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U.

[0038] A dielectric layer 130 is provided between the first electrode 110 and the second electrode 120. The dielectric layer 130 may include a dielectric material having a high dielectric constant. For example, the dielectric layer 130 has a high dielectric constant of about 100 or more, but is not limited thereto. The dielectric layer 130 includes TiO2 having a rutile crystal phase which is a stable phase at high temperature and high pressure. Here, the dielectric layer 130 may dominantly contain the rutile crystal phase. "The dielectric layer 130 dominantly contains the rutile crystal phase" means that when the dielectric layer 130 contains other crystal phases (for example, anatase crystal phase, brookite crystal phase, etc.) and / or an amorphous phase in addition to the rutile crystal phase, the dielectric layer 130 contains the most rutile crystal phase. Thus, by the dielectric layer 130 dominantly containing the rutile crystal phase, a high dielectric constant can be realized.

[0039] Such a dielectric layer 130 having a rutile crystal phase can be formed, for example, by depositing TiO2 on the first electrode 110 through an atomic layer deposition (ALD) process. Here, the dielectric layer 130 having a rutile crystal phase can be formed so as to contact the first electrode 110. The dielectric layer 130 may have a thickness of, for example, about 100 Å or less. For example, the dielectric layer 130 may have a thickness of about 50 Å or more and 100 Å or less, but is not limited thereto.

[0040] An oxide interface region may be further provided between the first electrode 110 and the dielectric layer 130. Such an oxide interface region can be formed in the process of depositing the dielectric layer 130 having a rutile crystal phase on the upper surface of the first electrode 110 as will be described later. The oxide interface region is provided on at least a part of the upper surface of the first electrode 110 facing the dielectric layer 130.

[0041] The oxide interface region may contain a predetermined oxide. Specifically, the oxide interface region may contain a metal oxide containing a Group 5B element. In this case, the oxide interface region is M n O 2n-1 or MO 2n-1It may include oxides represented as (n is a natural number, M is a Group 5B element, and O is oxygen). Group 5B elements may include, for example, vanadium (V), niobium (Nb), tantalum (Ta), or dubnium (Db).

[0042] Such oxide interface regions containing oxides of group 5B elements can be useful in inducing the rutile crystalline phase of the dielectric layer 130 during the atomic layer deposition (ALD) process for forming the dielectric layer 130, as will be described later. The oxide interface region may have a thin thickness of, for example, about 12 Å or less. For example, the oxide interface region may have a thickness of about 5 Å to 12 Å, but is not limited to this.

[0043] Figures 2A to 2C are diagrams illustrating a method for manufacturing a capacitor 100 according to an exemplary embodiment.

[0044] Referring to Figure 2A, the first electrode 110 is formed on a substrate (not shown). The substrate may include semiconductor material patterns, insulating material patterns, and / or conductive material patterns. The substrate may include semiconductor materials such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP), and / or insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0045] The first electrode 110 can be formed on a substrate, for example, through an atomic layer deposition (ALD) process. Specifically, the first electrode 110 can be formed by depositing a metal nitride containing a group 5B element onto a substrate through an atomic layer deposition (ALD) process. In this case, the first electrode 110 may contain a nitride represented as MN (where M is a group 5B element and N is nitrogen). The first electrode 110 may also be formed by depositing a metal nitride in which a group 4B element is added to the group 5B element onto a substrate. In this case, the first electrode 110 may contain M x M' 1-xIt may contain a nitride represented by N(0 < x < 1, M is a Group 5B element, M' is a Group 4B element, and N is nitrogen).

[0046] Referring to FIG. 2B, a dielectric layer 130 is formed on the first electrode 110 using an atomic layer deposition (ALD) process. In this process, a dielectric layer 130 having a rutile crystal phase may be formed on the first electrode 110 containing a nitride of a Group 5B element.

[0047] An oxide interface region may be formed between the first electrode 110 and the dielectric layer 130 during the process of forming the dielectric layer 130. Specifically, since the surface of the first electrode containing a nitride of a Group 5B element is exposed to air, a natural oxide film may be formed on the surface of the first electrode 110.

[0048] Thereafter, an atomic layer deposition (ALD) process is performed to form a dielectric layer 130 (e.g., a TiO2 layer) on the first electrode 110. First, in the initial process of forming the dielectric layer 130 (e.g., a TiO2 layer) on the natural oxide film (e.g., an M2O5 film) (where M is a Group 5B element and O is oxygen) naturally formed on the surface of the first electrode 100, an oxide interface region having a reductive phase such as, for example, M2O3 may be formed on at least a part of the surface of the first electrode 100 while oxygen escapes from the oxide film. Here, the oxide interface region may contain a metal oxide containing a Group 5B element. In this case, the oxide interface region is MnO 2n-1 or MO 2n-1 (n is a natural number, M is a Group 5B element, and O is oxygen). Such an oxide interface region may be formed, for example, with a thickness of about 12 Å or less. For example, the oxide interface region is formed with a thickness of about 5 Å or more and 12 Å or less, but is not limited thereto.

[0049] Next, an atomic layer deposition (ALD) process is carried out to form a dielectric layer 130 (e.g., a TiO2 layer), and a dielectric layer 130 (e.g., a TiO2 layer) having a rutile crystal phase can grow and form from the upper surface of the first electrode 110. Such a dielectric layer 130 (e.g., a TiO2 layer) can be formed with a thickness of about 100 Å or less. For example, the dielectric layer 130 can be formed with a thickness of about 50 Å to 100 Å, but is not limited to this. On the other hand, after the atomic layer deposition (ALD) process is completed, an even more robust dielectric layer 130 having a rutile crystal phase can be formed through additional heat treatment.

[0050] Referring to Figure 2C, the second electrode 120 is deposited on the dielectric layer 130. The second electrode 120 may contain a variety of conductive materials. The second electrode 120 may contain metals, metal nitrides, metal oxides, or combinations thereof. For example, the second electrode 120 may contain at least one conductive metal from among titanium (Ti), nickel (Ni), aluminum (Al), tantalum (Ta), tungsten (W), platinum (Pt), lead (Pd), gold (Au), iridium (Ir), rhodium (Rh), molybdenum (Mo), vanadium (V), niobium (Nb), ruthenium (Ru), and cobalt (Co), or it may contain conductive metal oxides or conductive metal nitrides of these metals. Conductive metal oxides may include, for example, platinum oxide (PtO), iridium oxide (IrO2), ruthenium oxide (RuO2), strontium ruthenium oxide (SrRuO2), barium strontium ruthenium oxide ((Ba,Sr)RuO3), calcium ruthenium oxide (CaRuO3), lanthanum strontium cobalt oxide ((La,Sr)CoO3), etc. Conductive metal nitrides may include, for example, titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), cobalt nitride (CoN), tungsten nitride (WN), etc. The second electrode 120 may contain a metal nitride represented as AA'N, where A is a metallic element, A' is an element different from A, and N is nitrogen.

[0051] As described above, in the atomic layer deposition (ALD) process for forming the dielectric layer 130 (e.g., TiO2 layer), a Group 5B element or a metal nitride of a Group 5B element and a Group 4B element (specifically, MN or M x M’ 1-x N (0 < x < 1, M is a Group 5B element, M’ is a Group 4B element, and N is nitrogen)), a dielectric layer 130 (e.g., TiO2 layer) containing a rutile crystal phase can be formed on the upper surface of the first electrode 110.

[0052] In the initial step of the atomic layer deposition (ALD) process for forming the dielectric layer 130 (e.g., TiO2 layer), a metal oxide of a Group 5B element (specifically, MnO 2n-1 or MO 2n-1 (n is a natural number, M is a Group 5B element, and O is oxygen)), an oxide interface region is formed on the upper surface of the first electrode 110. Then, while the atomic layer deposition (ALD) process continues, a dielectric layer 130 (e.g., TiO2 layer) containing a rutile crystal phase can grow and be formed from the oxide interface region.

[0053] When a capacitor having a MIM (Metal-Insulator-Metal) structure is configured by providing a TiO2 dielectric layer between general metal electrodes, the TiO2 dielectric layer does not have a rutile crystal phase, which is a stable phase at high temperature and high pressure, but has anatase crystal phase with a low dielectric constant. However, in the capacitor 100 according to an exemplary embodiment, as the material of the first electrode 110, a Group 5B element or a nitride of a Group 5B element and a Group 4B element (specifically, MN or M x M’ 1-xUsing a nitride represented by N (where 0 < x < 1, M is a Group 5B element, M' is a Group 4B element, and N is nitrogen), and further directly growing TiO2, a dielectric layer having a rutile crystal phase with a high dielectric constant can be formed. Thus, the capacitor 100 according to an exemplary embodiment includes a dielectric material (e.g., rutile phase TiO2) having a rutile crystal phase with a high dielectric constant, thereby improving capacitance and improving the charge storage ability of a semiconductor device (e.g., DRAM) including such a capacitor 100.

[0054] FIG. 3 shows a TEM photograph of a dielectric layer (rutile TiO2 layer) having a rutile crystal phase formed by depositing TiO2 on a first electrode (VN electrode) using an atomic layer deposition (ALD) process according to an exemplary embodiment. On the other hand, although not shown in FIG. 3, a V2O3 oxide interface region is formed with a very thin thickness between the VN electrode and the rutile TiO2 layer. FIG. 4 shows simulation results indicating the change in interfacial energy due to heat treatment for oxynitrides and oxides containing a Group 5B element M. In FIG. 4, MON represents an oxynitride of a Group 5B element, and M2O3, MO2, and M2O5 represent oxides of a Group 5B element. In FIG. 4, ■ indicates the interfacial energy before heat treatment, and ▲ indicates the interfacial energy after heat treatment. The above-described heat treatment is performed, for example, in an atomic layer deposition (ALD) process for forming a dielectric layer (TiO2 layer).

[0055] Referring to FIG. 4, among the oxides containing a Group 5B element M, MnO 2n-1 , or MO 2n-1 (where n is a natural number, M is a Group 5B element, and O is oxygen), that is, the M2O3 oxide, is found to have the most improved stability by performing heat treatment.

[0056] FIG. 5 is a drawing showing the crystal phases that appear when a TiO2 dielectric layer is grown through an atomic layer deposition (ALD) process on each of the oxide layers of a Group 5B element M.

[0057] Referring to Figure 5, among oxides containing the group 5B element M, MO 1.875 If TiO2 is grown on an oxide layer, a TiO2 layer having an anatase crystalline phase is formed, and MnO 2n-1 , or MO 2n-1 It can be seen that if TiO2 is grown on an oxide layer that satisfies the following conditions (where n is a natural number, M is a group 5B element, and O is oxygen), i.e., an M2O3 oxide layer, a TiO2 layer having a rutile crystalline phase may be formed.

[0058] Figure 6 shows the results of measuring the leakage current density J and equivalent oxide thickness (Toxeq.) in a comparative example capacitor and an exemplary embodiment capacitor. The leakage current density was measured under a voltage of 1V.

[0059] In Figure 6, "C1" represents a comparative example capacitor, and "C2" represents an exemplary embodiment capacitor. The comparative example capacitor used includes a TiO2 dielectric layer having an anatase crystal phase between metal electrodes, while the exemplary embodiment capacitor used is the capacitor shown in Figure 1, which includes a TiO2 dielectric layer having a rutile crystal phase.

[0060] Referring to Figure 6, it can be seen that the capacitor according to the exemplary embodiment, due to the rutile crystal phase having a high dielectric constant, has an equivalent oxide film thickness that is improved by approximately 37.8% and a leakage current density that is reduced by approximately 31% compared to the capacitor according to the comparative example.

[0061] As described above, the capacitor 100 according to the exemplary embodiment can improve capacitance by including a TiO2 dielectric layer 130 having a rutile crystal phase with a high dielectric constant, thereby improving the charge conservation capability of the semiconductor device (e.g., DRAM) including this capacitor 100.

[0062] The aforementioned capacitor 100 can be used in a variety of semiconductor devices. For example, the aforementioned capacitor 100 can be used together with a transistor to form a DRAM element. However, it is not limited to this; the aforementioned capacitor 100 can be used together with other semiconductor units to form a variety of semiconductor devices. Furthermore, the aforementioned capacitor 100 can be used together with other circuit elements to form part of an electronic circuit that constitutes an electronic device.

[0063] Figure 7 is a circuit diagram illustrating the schematic circuit configuration and operation of a semiconductor element 1000 employing a capacitor 100 according to an embodiment.

[0064] Referring to Figure 7, the circuit diagram of semiconductor element 1000 relates to a single memory cell of a DRAM (dynamic random access memory) element and includes one transistor TR, one capacitor CA, a word line WL, and a bit line BL. Capacitor CA is capacitor 100 according to the exemplary embodiment described above.

[0065] The method for writing data to DRAM is as follows: A gate voltage (high) is applied to the gate electrode of the transistor TR via the word line WL to turn it "ON," and then the data voltage value to be input, VDD (hereinafter referred to as "high voltage") or 0 (hereinafter referred to as "low voltage"), is applied to the bit line BL. If a high voltage is applied to both the word line and the bit line, the capacitor CA is charged and the data "1" is recorded. If a high voltage is applied to the word line and a low voltage is applied to the bit line, the capacitor CA is discharged and the data "0" is recorded.

[0066] When reading data, a high voltage is applied to the word line WL to turn on the DRAM transistor TR, and then a voltage of VDD / 2 is applied to the bit line BL. If the DRAM data is "1", that is, if the capacitor CA voltage is VDD, the charge in capacitor CA gradually moves to the bit line BL, and the voltage of the bit line BL becomes slightly higher than VDD / 2. Conversely, if the data in capacitor CA is "0", the charge in the bit line BL moves to capacitor CA, and the voltage of the bit line BL becomes slightly lower than VDD / 2. The potential difference across the bit line that occurs in this way is detected by a sense amplifier, and the value is amplified to determine whether the data is "0" or "1".

[0067] Figure 8 is a schematic diagram showing a semiconductor element 1001 according to an exemplary embodiment.

[0068] Referring to Figure 8, the semiconductor element 1001 may include a structure in which a capacitor CA1 and a transistor TR are electrically connected by a contact 20. The capacitor CA1 may include a first electrode 110, a second electrode 120 provided opposite the first electrode 110, and a dielectric layer 130 provided between the first electrode 110 and the second electrode 120. Capacitor CA1 is the same as the capacitor 100 described in Figure 1, and since this has been described above, a further explanation will be omitted.

[0069] A transistor TR is a field-effect transistor. A transistor TR includes a semiconductor substrate SU having a source region SR, a drain region DR, and a channel region CH, and a gate stack GS disposed on the semiconductor substrate SU opposite the channel region CH, and comprising a gate insulating layer GI and a gate electrode GA.

[0070] The channel region CH is the region between the source region SR and the drain region DR, and is electrically connected to both the source region SR and the drain region DR. The source region SR may be electrically connected to or in contact with one end of the channel region CH, and the drain region DR may be electrically connected to or in contact with the other end of the channel region CH. The channel region CH can be defined as the substrate region between the source region SR and the drain region DR within the semiconductor substrate SU.

[0071] The semiconductor substrate SU may contain semiconductor materials. For example, the semiconductor substrate SU may contain semiconductor materials such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate SU may also contain an SOI (silicon on insulator) substrate.

[0072] The source region SR, drain region DR, and channel region CH are each formed independently by implanting impurities into different regions of the semiconductor substrate SU. In this case, the source region SR, channel region CH, and drain region DR may contain the substrate material as a base material. The source region SR and drain region DR may be made of a conductive material, in which case they may include, for example, a metal, a metal compound, or a conductive polymer.

[0073] The channel region CH may be embodied in a separate material layer (thin film), contrary to the illustration. In this case, for example, the channel region CH may include at least one of Si, Ge, SiGe, III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional materials (2D materials), quantum dots, and organic semiconductors. For example, oxide semiconductors include InGaZnO, two-dimensional materials include TMD (transition metal dichalcogenide) or graphene, and quantum dots may include colloidal quantum dots (QDs) or nanocrystal structures.

[0074] The gate electrode GA may be positioned on a semiconductor substrate SU, separated from the semiconductor substrate SU, and facing the channel region CH. The gate electrode GA may contain at least one of metals, metal nitrides, metal carbides, and polysilicon. For example, the metal may contain at least one of aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and tantalum (Ta), and the metal nitride may contain at least one of titanium nitride and tantalum nitride. The metal carbide may contain at least one of aluminum or silicon-doped (or silicon-containing) metal carbides, and specific examples may include TiAlC, TaAlC, TiSiC, or TaSiC.

[0075] The gate electrode GA may have a structure in which multiple materials are stacked, for example, a stacked structure of metal nitride layer / metal layer such as TiN / Al, or a stacked structure of metal nitride layer / metal carbide layer / metal layer such as TiN / TiAlC / W. However, the materials mentioned above are merely examples.

[0076] A gate insulating layer GI may be further disposed between the semiconductor substrate SU and the gate electrode GA. The gate insulating layer GI comprises a paraelectric material or a high-k dielectric material and may have a dielectric constant of about 20 to 70.

[0077] The gate insulating layer GI may contain silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or a two-dimensional insulator such as h-BN (hexagonal boron nitride). For example, the gate insulating layer GI may contain silicon oxide (SiO2), silicon nitride (SiN x ) and others, including hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), hafnium zirconium oxide (HfZrO2), zirconium silicon oxide (ZrSiO4), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), red scandium tantalum oxide (PbSc 0.5 Ta 0.5 The gate insulating layer GI may also contain O3, red zinc niobate (PbZnNbO3), etc. Furthermore, the gate insulating layer GI may contain metal nitride oxides such as aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), yttrium oxynitride (YON), silicates such as ZrSiON, HfSiON, YSiON, LaSiON, or aluminates such as ZrAlON, HfAlON. The gate insulating layer GI can form a gate stack together with the gate electrode GA.

[0078] One of the electrodes 110 and 120 of capacitor CA1 may be electrically connected to one of the source region SR and drain region DR of transistor TR by a contact 20. Here, the contact 20 may include a suitable conductive material, such as tungsten, copper, aluminum, or polysilicon.

[0079] The arrangement of capacitor CA1 and transistor TR can be varied in many ways. For example, capacitor CA1 may be placed on a semiconductor substrate SU, or it may be embedded within the semiconductor substrate SU.

[0080] Figure 8 shows a semiconductor element 1001 that includes one capacitor CA1 and one transistor TR, but this is illustrative, and the semiconductor element 1001 may include multiple capacitors and multiple transistors.

[0081] Figure 9 is a drawing showing a semiconductor element 1002 according to another exemplary embodiment.

[0082] Referring to Figure 9, the semiconductor element 1002 may include a structure in which a capacitor CA2 and a transistor TR are electrically connected by a contact 21. The transistor TR includes a semiconductor substrate SU having a source region SR, a drain region DR, and a channel region CH, and a gate stack GS disposed on the semiconductor substrate SU facing the channel region CH, and comprising a gate insulating layer GI and a gate electrode GA.

[0083] The interlayer insulating film 25 is provided on the semiconductor substrate SU in a manner that covers the gate stack GS. The interlayer insulating film 25 may contain an insulating material. For example, the interlayer insulating film 25 may contain a Si oxide (e.g., SiO2), an Al oxide (e.g., Al2O3), or a high dielectric material (e.g., HfO2). The contact 21 penetrates the interlayer insulating film 25 and electrically connects the transistor TR and the capacitor CA1.

[0084] Capacitor CA1 may include a first electrode 110, a second electrode 120 facing the first electrode 110, and a dielectric layer 130 provided between the first electrode 110 and the second electrode 120. The first electrode 110 and the second electrode 120 are presented in a shape that maximizes the contact area with the dielectric layer 130. Capacitor CA2 is substantially identical to capacitor 100 as described in Figure 1, and since this has been explained above, a further explanation will be omitted.

[0085] Figure 10 is a plan view showing a semiconductor element 1003 according to yet another exemplary embodiment.

[0086] Referring to Figure 10, the semiconductor element 1003 may include a structure in which a plurality of capacitors and a plurality of field-effect transistors are arranged iteratively. The semiconductor element 1003 may further include a semiconductor substrate 11' including a source, drain, and channel, a field-effect transistor including a gate stack 12, a contact structure 20' positioned on the semiconductor substrate 11' so as not to overlap with the gate stack 12, and a capacitor CA3 positioned on the contact structure 20', and a bit line structure 13 that electrically connects the plurality of field-effect transistors.

[0087] Figure 10 illustrates, but is not limited to, a configuration in which both the contact structure 20' and the capacitor CA3 are arranged repeatedly along the X and Y directions. For example, the contact structure 20' may be arranged along the X and Y directions, and the capacitor CA3 may be arranged in a hexagonal shape, such as a honeycomb structure.

[0088] Figure 11 is a cross-sectional view along the line A-A' in Figure 10.

[0089] Referring to Figure 11, the semiconductor substrate 11' may have an STI (shallow trench isolation) structure including an element isolation film 14. The element isolation film 14 is a single layer made of one type of insulating film, or a multilayer made of a combination of two or more types of insulating films. The element isolation film 14 contains an element isolation trench 14T within the semiconductor substrate 11', and the element isolation trench 14T may be filled with an insulating material. The insulating material includes, but is not limited to, at least one of FSG (fluoride silicate glass), USG (undoped silicate glass), BPSG (boro-phospho-silicate glass), PSG (phospho-silicate glass), FOX (flowable oxide), PE-TEOS (plasma-enhanced tetra-ethyl-ortho-silicate), and TOSZ (tonen silazene).

[0090] The semiconductor substrate 11' may further include a channel region CH defined by an element isolation film 14 and gate line trenches 12T arranged parallel to the upper surface of the semiconductor substrate 11' and extending along the X direction. The channel region CH may have a relatively long island shape with a short axis and a long axis. The long axis of the channel region CH may be aligned along the D3 direction parallel to the upper surface of the semiconductor substrate 11', as illustrated in Figure 10.

[0091] The gate line trench 12T may be positioned so as to intersect the channel region CH at a predetermined depth from the upper surface of the semiconductor substrate 11', or within the channel region CH. The gate line trench 12T may also be positioned inside the element isolation trench 14T, and the gate line trench 12T inside the element isolation trench 14T may have a lower bottom surface than the gate line trench 12T of the channel region CH. The first source / drain 11'ab and the second source / drain 11"ab may be positioned in the upper portion of the channel region CH located on both sides of the gate line trench 12T.

[0092] A gate stack 12 may be arranged inside the gate line trench 12T. Specifically, a gate insulating layer 12a, a gate electrode 12b, and a gate capping layer 12c may be arranged sequentially inside the gate line trench 12T. The gate insulating layer 12a and the gate electrode 12b may be as described above, and the gate capping layer 12c may contain at least one of silicon oxide, silicon oxynitride, and silicon nitride. The gate capping layer 12c may be placed on the gate electrode 12b to fill the remaining portion of the gate line trench 12T.

[0093] A bit line structure 13 may be positioned on the first source / drain 11'ab. The bit line structure 13 may be positioned parallel to the upper surface of the semiconductor substrate 11' and extending along the Y direction. The bit line structure 13 may be electrically connected to the first source / drain 11'ab and may sequentially include a bit line contact 13a, a bit line 13b, and a bit line capping layer 13c on the substrate. For example, the bit line contact 13a may contain polysilicon, the bit line 13b may contain a metallic material, and the bit line capping layer 13c may contain an insulating material such as silicon nitride or silicon oxynitride.

[0094] Figure 11 shows a case where the bit line contact 13a has a bottom surface at the same level as the top surface of the semiconductor substrate 11', but this is illustrative and not limited thereto. For example, in another embodiment, a recess (indentation) formed to a predetermined depth from the top surface of the semiconductor substrate 11' may be further provided, and the bit line contact 13a may extend into the recess, with the bottom surface of the bit line contact 13a being formed lower than the top surface of the semiconductor substrate 11'.

[0095] The bit line structure 13 may further include a bit line intermediate layer (not shown) between the bit line contact 13a and the bit line 13b. The bit line intermediate layer may include a metal silicide such as tungsten silicide, or a metal nitride such as tungsten nitride. A bit line spacer (not shown) may also be further formed on the side wall of the bit line structure 13. The bit line spacer may have a single-layer or multi-layer structure and may include an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride. The bit line spacer may also further include an air space (not shown).

[0096] The contact structure 20' may be positioned on the second source / drain 11"ab. The contact structure 20' and the bit line structure 13 may be positioned on different sources / drains on the substrate. The contact structure 20' is a structure in which a lower contact pattern (not shown), a metal silicide layer (not shown), and an upper contact pattern (not shown) are sequentially stacked on the second source / drain 11"ab. The contact structure 20' may further include a barrier layer (not shown) surrounding the sides and bottom of the upper contact pattern. For example, the lower contact pattern may contain polysilicon, the upper contact pattern may contain a metallic material, and the barrier layer may contain a conductive metal nitride.

[0097] The capacitor CA3 may be electrically connected to the contact structure 20' and placed on the semiconductor substrate 11'. Specifically, the capacitor CA3 includes a first electrode 110 electrically connected to the contact structure 20', a second electrode 120 spaced apart from the first electrode 110, and a dielectric layer 130 placed between the first electrode 110 and the second electrode 120.

[0098] The first electrode 110 may have a cylindrical or cup-like shape with an internal space that is sealed on the lower side. The second electrode 120 may have a comb-like shape with a projection that extends into the internal space formed by the first electrode 110 and the region between adjacent first electrodes 110. The dielectric layer 130 may be arranged between the first electrode 110 and the second electrode 120, parallel to their surfaces. The capacitor CA3 is substantially the same as the capacitor 100 described in Figure 1, and since this has been described above, a further explanation will be omitted.

[0099] An interlayer insulating film 15 may be further placed between the capacitor CA3 and the semiconductor substrate 11'. The interlayer insulating film 15 may be placed in the space between the capacitor CA3 and the semiconductor substrate 11' where no other structures are placed. Specifically, the interlayer insulating film 15 may be placed to cover wiring and / or electrode structures such as the bit line structure 13, contact structure 20', and gate stack 12 on the substrate. For example, the interlayer insulating film 15 may surround the wall of the contact structure 20'. The interlayer insulating film 15 may include a first interlayer insulating film 15a surrounding the bit line contact 13a and a second interlayer insulating film 15b covering the sides and / or top surfaces of the bit line 13b and the bit line capping layer 13c.

[0100] The first electrode 100 of the capacitor CA3 may be placed on the interlayer insulating film 15, specifically on the second interlayer insulating film 15b. Furthermore, when multiple capacitors CA3 are arranged, the bottom surfaces of the multiple first electrodes 110 may be separated by an etching stop layer 16. In other words, the etching stop layer 16 includes an opening 16T, within which the bottom surfaces of the second electrodes 120 of the capacitor CA3 may be placed. The first electrode 110 may have a cylindrical or cup-like shape with a sealed internal space on the bottom, as shown in the figure. The capacitor CA3 further includes a support (not shown) to prevent the second electrode 120 from tilting or tipping over, and the support may be placed on the side wall of the second electrode 120.

[0101] Figure 12 is a cross-sectional view showing a semiconductor element 1004 according to yet another exemplary embodiment.

[0102] The semiconductor element 1004 of this embodiment is shown in a cross-sectional view corresponding to the A-A' cross-sectional view in Figure 10, with only the shape of the capacitor CA4 differing from that in Figure 11. The capacitor CA4 is electrically connected to the contact structure 20' and placed on the semiconductor substrate 11', and includes a first electrode 110 electrically connected to the contact structure 20', a second electrode 120 spaced apart from the first electrode 110, and a dielectric layer 130 placed between the first electrode 110 and the second electrode 120.

[0103] The first electrode 110 may have a pillar shape such as a cylinder, rectangular prism, or polygonal prism extending along the vertical direction (Z direction). The second electrode 120 may have a comb shape with a projection extending into the region between adjacent first electrodes 110. The dielectric layer 130 may be arranged between the first electrode 110 and the second electrode 120, parallel to their surfaces. The capacitor CA4 is substantially the same as the capacitor 100 described in Figure 1, and since this has been described above, a further explanation will be omitted.

[0104] The capacitors and semiconductor elements according to the embodiments described above can be applied to a variety of application fields. For example, the semiconductor elements according to the embodiments can be applied as logic elements or memory elements. The semiconductor elements according to the embodiments can be used in devices such as mobile devices, computers, notebooks, sensors, network devices, and neuromorphic devices for arithmetic operations, program execution, and temporary data storage. Furthermore, the semiconductor elements according to the embodiments are effective in electronic devices where the amount of data transmitted is large and data transmission is continuous.

[0105] Figures 13 and 14 are conceptual diagrams illustrating the element architecture applied to an electronic device according to an exemplary embodiment.

[0106] Referring to Figure 13, the electronic device architecture 1100 may include a memory unit 1010, an arithmetic logic unit (ALU) 1020, and a control unit 1030. The memory unit 1010, ALU 1020, and control unit 1030 may be electrically connected. For example, the electronic device architecture 1100 may be realized on a single chip including the memory unit 1010, ALU 1020, and control unit 1030.

[0107] The memory unit 1010, ALU 1020, and control unit 1030 are interconnected on-chip via metal lines and can communicate directly with each other. The memory unit 1010, ALU 1020, and control unit 1030 may be monolithically integrated on a single substrate to form a single chip. Input / output elements 2000 may be connected to the electronic element architecture (chip) 1100. The memory unit 1010 may include both main memory and cache memory. Such an electronic element architecture (chip) 1100 is an on-chip memory processing unit. The memory unit 1010 may include the aforementioned capacitors and semiconductor elements that utilize them. The ALU 1020 or control unit 1030 may also each include the aforementioned capacitors.

[0108] Referring to Figure 14, the cache memory 1510, ALU 1520, and control unit 1530 constitute the CPU (Central Processing Unit) 1500, and the cache memory 1510 consists of SRAM (static random access memory). In addition to the CPU 1500, a main memory 1600 and auxiliary storage 1700 may be provided. The main memory 1600 is DRAM (dynamic random access memory) and may include the capacitors mentioned above. Depending on the case, the electronic element architecture may be realized on a single chip in a form in which computing unit elements and memory unit elements are adjacent to each other, without the distinction of sub-units.

[0109] The capacitors and semiconductor elements and electronic devices containing them described above have been explained with reference to the embodiments shown in the drawings, but these are merely illustrative, and anyone with ordinary skill in the art will understand that a variety of modifications and equivalent other embodiments are possible.

Claims

1. First electrode and A second electrode is provided opposite to the first electrode, A dielectric layer comprising a rutile crystal phase is provided between the first electrode and the second electrode, A capacitor in which the first electrode comprises a group 5B element, or a metal nitride containing a group 5B element and a group 4B element.

2. The capacitor according to claim 1, wherein the dielectric layer is provided so as to be in contact with the first electrode.

3. The dielectric layer is TiO ２ The capacitor according to claim 1, including the following:

4. The capacitor according to claim 1, wherein the dielectric layer predominantly comprises a rutile crystalline phase.

5. The capacitor according to claim 1, wherein the dielectric layer has a thickness of 100 Å or less.

6. The capacitor according to claim 1, wherein the group 5B element includes V, Nb, Ta, or Db.

7. The capacitor according to claim 1, wherein the group 4B element includes Ti, Zr, Hf, or Rf.

8. The first electrode is made of MN or M ｘ M' 1－ｘ The capacitor according to claim 1, comprising a nitride represented as N (0 < x < 1, M is a group 5B element, M' is a group 4B element, and N is nitrogen).

9. A semiconductor device including a capacitor, The aforementioned capacitor is First electrode and A second electrode is provided opposite to the first electrode, A dielectric layer comprising a rutile crystal phase is provided between the first electrode and the second electrode, The first electrode is a semiconductor device comprising a group 5B element, or a metal nitride containing both a group 5B element and a group 4B element.

10. The semiconductor element according to claim 9, wherein the dielectric layer is provided so as to be in contact with the first electrode.

11. The dielectric layer is TiO ２ A semiconductor element according to claim 9, including the above.

12. The first electrode is made of MN or M ｘ M' 1－ｘ A semiconductor device according to claim 9, comprising a nitride represented as N (0 < x < 1, M is a group 5B element, M' is a group 4B element, and N is nitrogen).

13. A method for manufacturing a semiconductor device including a capacitor, The aforementioned capacitor is The steps include forming a first electrode containing a metal nitride containing a group 5B element, The first electrode is formed by the step of forming a dielectric layer containing a rutile crystal phase, A method for manufacturing a semiconductor device, comprising the step of forming a second electrode on the dielectric layer.

14. The method for manufacturing a semiconductor device according to claim 13, wherein the group 5B element includes V, Nb, Ta, or Db.

15. The method for manufacturing a semiconductor device according to claim 13, wherein the first electrode further comprises a group 4B element.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the Group 4B element includes Ti, Zr, Hf, or Rf.

17. The dielectric layer is TiO ２ A method for manufacturing a semiconductor device according to claim 13, including the method described in claim 13.

18. The dielectric layer is formed by using an atomic layer deposition (ALD) process to deposit TiO2 on the first electrode. ２ A method for manufacturing a semiconductor device according to claim 13, which is formed by directly depositing a material.

19. The method for manufacturing a semiconductor device according to claim 13, wherein the dielectric layer is formed to predominantly contain a rutile crystalline phase.

20. The method for manufacturing a semiconductor device according to claim 13, wherein the dielectric layer is formed with a thickness of 100 Å or less.

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