Semiconductor equipment

Abstract

The structure is designed to suppress wafer warping while constructing the semiconductor layer constituting the deep layer using an ion implantation layer. [Solution] The p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 are formed by ion implantation. Furthermore, not only the p-type deep layer 5 and p-type guard ring 21, but also the p-type deep layer 30 is constructed in a linear shape. By constructing the p-type deep layer 30 in a linear shape in this way, the total value TV of the occupancy rate of the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 within the chip is made to be 40% or less. This makes it possible to suppress wafer warping even while constructing the p-type deep layer 30 by ion implantation.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and is particularly suitable for application to silicon carbide (hereinafter referred to as SiC) semiconductor devices. [Background technology]

[0002] Conventionally, semiconductor switching elements such as MOSFETs have been designed with a trench gate structure to reduce on-resistance. However, to suppress the application of a high electric field to the gate insulating film, it is necessary to relax the electric field at the bottom of the trench in the trench gate structure. For this reason, for example, in Patent Document 1, deep layers are formed on both sides of the trench gate structure by high-acceleration ion implantation to relax the electric field at the bottom of the trench. These deep layers suppress the rise of equipotential lines and relax the electric field at the bottom of the trench, thereby suppressing the application of a high electric field to the gate insulating film. In addition, a guard ring is provided in the outer peripheral region surrounding the cell region, and a deep layer is provided throughout the junction located between the cell region and the guard ring. As a result, equipotential lines extend from the cell region to the junction and then to the guard ring, and are terminated at the guard ring, making it possible to achieve high voltage resistance. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2019-54087 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, when forming deep layers using high-acceleration ion implantation as described in Patent Document 1, wafer warping occurs during the process, depending on the dose and acceleration, leading to problems associated with wafer warping, such as transport errors, substrate adsorption errors, and reduced photoresolution.

[0005] In contrast, while wafer warping can be mitigated by performing activation annealing after each ion implantation, this mitigation process generates stacking faults in the ion implantation area, leading to increased drain leakage and an increase in the number of processes, thus increasing manufacturing costs.

[0006] Furthermore, while measures such as ion implantation on the back surface of the wafer can be used as a counterdose against wafer warping, these can lead to an increase in the number of processes and unexpected particle adhesion due to surface adsorption, resulting in a decrease in yield due to pattern distortion.

[0007] Furthermore, a deep layer can be formed by embedding a p-type epitaxial layer within the trench, but controlling the density of the deep layer and performing surface planarization treatment are difficult.

[0008] In view of the above, the present invention aims to provide a semiconductor device with a structure that can suppress wafer warping while the semiconductor layer constituting the deep layer is composed of an ion implantation layer. [Means for solving the problem]

[0009] To achieve the above objective, the invention described in claim 1 is a semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connecting portion (RJ) located between the guard ring portion and the cell region, wherein the semiconductor device has a first or second conductivity type substrate (1, 101), and a first conductivity type drift layer (2, 50, 60, 102) formed on the surface side of the substrate having a surface and a back surface, and having a lower impurity concentration than the substrate. The cell region includes a second conductivity type layer (5, 5a, 51, 103) formed in the drift layer and including a portion formed in a stripe shape with one direction as the longitudinal direction, a first electrode (9, 106) electrically connected to the second conductivity type layer, and a second electrode (11, 107) formed on the back side of the substrate, and is equipped with a vertical semiconductor element that conducts current between the first electrode and the second electrode. The connecting portion is also equipped with a second conductivity type layer (31, 33-35, 71) formed in a line shape in the drift layer. Furthermore, the guard ring portion and the connecting portion are equipped with a second conductivity type ring (21, 32, 72, 104, 105) formed in the drift layer and having a multiple line-shaped frame shape surrounding the cell region, with at least a portion located on the outer circumference constituting a guard ring (21, 104). Furthermore, the second conductivity layer and the second conductivity ring are composed of ion implantation layers, and the proportion of the second conductivity layer and the second conductivity ring to the total surface area of ​​the chip is set to 40% or less.

[0010] In this way, the second conductivity layer and second conductivity ring are formed by ion implantation, but not only the second conductivity layer in the cell region and the second conductivity ring in the guard ring portion, but also the second conductivity layer in the connecting portion is made to be formed in a linear shape. By forming the second conductivity layer in the connecting portion in a linear shape in this way, the total occupancy rate of the second conductivity layer and second conductivity ring within the chip is kept below 40%. This makes it possible to suppress wafer warping while forming the semiconductor layer constituting the second conductivity layer in the connecting portion, i.e., the deep layer, by ion implantation.

[0011] Specifically, the invention described in claim 1 includes a linear portion (31) whose longitudinal direction is the same as the longitudinal direction of the second conductive layer provided in the connecting portion, The aforementioned guard rings have a larger spacing between them (DA3, DB3) as you move from the inner circumference to the outer circumference. The spacing of the guard rings is set to the third spacing (DA3, DB3), The relationship is that the spacing of the widest part of the third interval located on the outermost circumference (DA3out, DB3out) > the spacing of the part of the third interval located on the inner circumference (DA3in, DB3in).

[0012] By setting this third interval, the combined occupancy rate of the second conductivity layer and the second conductivity ring within the chip is kept below 40%.

[0013] The symbols in parentheses for each of the above means indicate an example of the correspondence with the specific means described in the embodiments described later. [Brief explanation of the drawing]

[0014] [Figure 1] This is a top layout diagram of a SiC semiconductor device according to the first embodiment. [Figure 2] This is a cross-sectional view taken along line II-II in Figure 1. [Figure 3] This diagram shows the relationship between the ion implantation acceleration voltage and wafer warpage. [Figure 4] This figure shows the relationship between the cumulative dose of ion implantation and wafer warpage. [Figure 5A] This is a cross-sectional view showing the rise of equipotential lines. [Figure 5B] This diagram shows the relationship between the spacing of the p-type layers and the pressure resistance. [Figure 6A] This figure shows the change in the electric field strength near the bottom of the gate trench when the width of the linear portion in the p-type deep layer is changed in the cell region. [Figure 6B]This figure shows the change in the feedback capacitance Crss when the width of the linear portion in a p-type deep layer is varied. [Figure 7] This chart shows the results of investigating the area ratios occupied by cell regions, connecting regions, and guard ring regions within a chip, and the area ratio of the p-type layer within those regions. [Figure 8A] Figures 1 and 2 are perspective cross-sectional views showing the manufacturing process of SiC semiconductor devices. [Figure 8B] This is a cross-sectional view showing the manufacturing process of a SiC semiconductor device, following Figure 8A. [Figure 8C] This is a cross-sectional view showing the manufacturing process of a SiC semiconductor device, following Figure 8B. [Figure 8D] Figure 8C is a cross-sectional view showing the manufacturing process of a SiC semiconductor device. [Figure 8E] This is a cross-sectional view showing the manufacturing process of a SiC semiconductor device, following Figure 8D. [Figure 8F] This is a cross-sectional view showing the manufacturing process of a SiC semiconductor device, following Figure 8E. [Figure 8G] This is a cross-sectional view showing the manufacturing process of SiC semiconductor devices, following Figure 8F. [Figure 8H] This is a cross-sectional view showing the manufacturing process of a SiC semiconductor device, following Figure 8G. [Figure 9] This is a top view layout diagram of a SiC semiconductor device according to a modified example of the first embodiment. [Figure 10] This is a top view layout diagram of a SiC semiconductor device according to a modified example of the first embodiment. [Figure 11] This is a top view layout diagram of a SiC semiconductor device according to a modified example of the first embodiment. [Figure 12] This is a top view layout diagram of a SiC semiconductor device according to a modified example of the first embodiment. [Figure 13] This is a perspective cross-sectional view of a SiC semiconductor device according to a second embodiment. [Figure 14A] Figure 13 is a perspective cross-sectional view showing the manufacturing process of a SiC semiconductor device. [Figure 14B] This is a perspective cross-sectional view showing the manufacturing process of SiC semiconductor devices, following Figure 14A. [Figure 14C] Figure 14B is a perspective cross-sectional view showing the manufacturing process of SiC semiconductor devices. [Figure 15] This is a top layout diagram of a SiC semiconductor device according to the third embodiment. [Figure 16] This is a cross-sectional view taken from line XVI-XVI in Figure 15. [Modes for carrying out the invention]

[0015] The embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0016] (First Embodiment) A first embodiment will be described. Here, a SiC semiconductor device in which a trench gate structure inverted MOSFET is formed as a semiconductor element will be used as an example.

[0017] Figure 1 shows the top surface layout of a SiC semiconductor device chip CH on which a trench gate MOSFET 100 is formed. The SiC semiconductor device shown in Figure 1 has a configuration comprising a cell region RC on which the MOSFET 100 is formed, and an outer peripheral region RO surrounding this cell region RC. The outer peripheral region RO has a guard ring portion RG and a connecting portion RJ located inside the guard ring portion RG, i.e., between the cell region RC and the guard ring portion RG. Note that Figure 1 is not a cross-sectional view, but partial hatching is shown to improve the clarity of the diagram.

[0018] As shown in Figure 2, the SiC semiconductor device is made of n + It is formed using a molded substrate 1. + On the main surface of the substrate 1, there is a low-concentration layer made of SiC, corresponding to n - The mold layer 2 and the p-type base region 3 are formed by epitaxial growth, and furthermore, n is present in the surface layer of the p-type base region 3. + Type source region 4 is formed.

[0019] n + The n-type substrate 1 has, for example, an n-type impurity concentration of 1.0×10 19 / cm 3 , a surface of (0001)Si plane, and is an off-substrate with an off-direction of <11-20> direction. The n - -type layer 2 has a lower impurity concentration than the n + -type substrate 1, and for example, an n-type impurity concentration of 5.0×10 15 ~2.0×10 16 / cm 3 . In the case of this embodiment, this n - -type layer 2 constitutes a drift layer.

[0020] Also, the p-type base region 3 is a portion where a channel region is formed, and has a p-type impurity concentration of, for example, 2.0×10 17 / cm 3 or so, and is formed with a thickness of 300 nm. In the surface layer portion of the p-type base region 3, that is, in the place sandwiched by the n + -type source regions 4 of adjacent cells in the MOSFET 100, p-type contact regions 3a and p-type hole extraction layers 3b with a partially high concentration of p-type impurities are formed. The n + -type source region 4 has a higher impurity concentration than the n - -type layer 2, and the n-type impurity concentration in the surface layer portion is, for example, 2.5×10 18 ~1.0×10 19 / cm 3 , and is formed with a thickness of about 0.5 μm.

[0021] In the cell region RC, the p-type base region 3 and the n + -type source region 4 are left on the surface side of the n + -type substrate 1, and in the connection portion RJ, the p-type base region 3 including the p-type hole extraction layer 3b is left on the surface side of the n + -type substrate 1. Also, in the guard ring portion RG, it penetrates the p-type base region 3 and n -A recess 20 is formed so as to reach the mold layer 2. This structure creates a mesa portion RM in which the cell region RC and the connecting portion RJ protrude beyond the guard ring portion RG. In Figure 1, the area enclosed by the dashed line represents the mesa portion RM, and the area inside it, which is hatched with a dashed line, represents the connecting portion RJ.

[0022] Furthermore, in the cell region RC, n - A p-type deep layer 5 is formed on the surface of the mold layer 2, with a higher p-type impurity concentration than the p-type base region 3. The p-type deep layer 5 constitutes at least a part of the second conductive mold layer. The p-type deep layer 5 is n - It is formed from a predetermined depth position in the mold layer 2 to the surface, n - It is formed by ion implanting p-type impurities into the mold layer 2.

[0023] p-type deep layer 5, n - The mold layer 2 has multiple linear sections 5a arranged at equal intervals, and as shown in Figure 1, they are arranged in a striped pattern without intersecting each other. In this embodiment, the p-type deep layer 5 also has intersecting sections 5b that extend in a direction intersecting the linear sections 5a, and the two are connected by the placement of intersecting sections 5b at both ends of each linear section 5a. In other words, the p-type deep layer 5 forms a rectangular shape surrounding the outer perimeter of the cell region RC with the outermost part of the multiple linear sections 5a and the intersecting sections 5b, and the remaining multiple linear sections 5a are arranged in a striped pattern inside. The above-mentioned p-type base region 3 and n + The p-type source region 4 is formed on top of this p-type deep layer 5.

[0024] In this embodiment, the p-type deep layer 5 is formed with the same impurity concentration, the same width, and the same depth, for example, the p-type impurity concentration is 1.0 × 10⁻⁶. 17 ~1.0×10 19 / cm 3It is composed of a width of approximately 0.4 to 1.0 μm and a depth of approximately 2.0 μm. Furthermore, the spacing DA1 of the linear portions 5a of the p-type deep layer 5 is set to 0.6 to 1.5 μm. The linear portion 31 of the p-type deep layer 30 of the connecting portion RJ, which will be described later, is connected to the intersection portion 5b of the p-type deep layer 5.

[0025] The extension direction of the p-type deep layer 5 is arbitrary, but in this embodiment, it is set to the same direction as the off-direction, the <11-20> direction.

[0026] Note that the intersection 5b of the p-type deep layer 5 is not essential, and the p-type deep layer 30 at the connecting section RJ does not need to be connected to each linear section 5a of the p-type deep layer 5. Here, the spacing DA1 of each linear section 5a of the p-type deep layer 5 is different from the spacing DA2 of the linear sections 31 of the p-type deep layer 30, but it is also possible to have a structure where the spacing DA1 and spacing DA2 are the same, and each linear section 5a and each linear section 31 are connected to each other.

[0027] Also, p-type base region 3 and n + n through type source region 4 - Multiple gate trenches 6, for example, with a width of 0.8 μm and a depth of 1.0 μm, are formed so as to reach the mold layer 2 and be shallower than the p-type deep layer 5. The aforementioned p-type base region 3 and n are in contact with the sides of each of these multiple gate trenches 6. + A type source region 4 is positioned. Each gate trench 6 is formed in a linear layout with the width direction in the left-right direction of the paper in Figure 2, the length direction in the vertical direction of the paper, and the depth direction in the up-down direction of the paper. Also, as shown in Figure 1, multiple gate trenches 6 are arranged so as to be sandwiched between each linear portion 5a of the p-type deep layer 5, and are arranged in parallel at equal intervals to form a stripe pattern.

[0028] Furthermore, the portion of the p-type base region 3 located on the side of the gate trench 6 is subjected to n during operation of the MOSFET 100. + Type source area 4 and n -A gate insulating film 7 is formed on the inner wall surface of the gate trench 6, which includes the channel region, serving as a channel region connecting to the mold layer 2. A gate electrode 8 made of doped poly-Si is formed on the surface of the gate insulating film 7, and the gate trench 6 is completely filled with these gate insulating film 7 and gate electrode 8. This constitutes a trench gate structure with one direction as the longitudinal direction. The p-type deep layer 5 described above is formed on both sides of this trench gate structure, along the same direction as the longitudinal direction of the trench gate structure. Note that in Figure 1, the number of trench gate structures and p-type deep layers 5 is reduced for clarity, but in reality, many similar structures are arranged.

[0029] Also, n + n for type substrate 1 - On the opposite side of layer 2, specifically n + On the surfaces of the n-type source region 4, the p-type base region 3, and the gate electrode 8, a source electrode 9 corresponding to the first electrode and a gate wiring layer (not shown) are formed via an interlayer insulating film 10. The source electrode 9 and the gate wiring layer are composed of multiple metals, such as Ni / Al. Of these multiple metals, at least n-type SiC, specifically n + The portion in contact with the n-type source region 4 is made of a metal capable of ohmic contact with n-type SiC. Furthermore, at least the portions of the multiple metals in contact with p-type SiC, specifically the p-type contact region 3a and the p-type hole extraction layer 3b, are made of a metal capable of ohmic contact with p-type SiC. These source electrodes 9 and gate wiring layers are electrically insulated by being separated on the interlayer insulating film 10. The source electrode 9 is then connected to the n-type SiC through a contact hole formed in the interlayer insulating film 10. + The gate wiring layer is electrically connected to the gate electrode 8, while the source region 4 and the p-type contact region 3a are electrically connected to the gate electrode 8.

[0030] Furthermore, n + On the back side of the substrate 1 is n +A drain electrode 11, corresponding to a second electrode electrically connected to the substrate 1, is formed. This structure constitutes an n-channel type inverting trench gate MOSFET 100. A cell region RC is formed by arranging multiple such MOSFETs 100.

[0031] On the other hand, in the guard ring portion RG, as described above, n penetrates the p-type base region 3. - A recess 20 is formed so as to reach the mold layer 2. Therefore, at a position away from the cell region RC, n + Type source region 4 and type p base region 3 are removed, n - Mold layer 2 is exposed. And, n + In the thickness direction of the substrate 1, parts of the cell region RC and connecting portion RJ located inside the recess 20 form island-like protruding mesa portions RM.

[0032] Also, n located below the recess 20 - Multiple p-type guard rings 21 are provided on the surface of mold layer 2 so as to surround the cell region RC and the connecting portion RJ. The p-type guard rings 21 constitute at least a part of the second conductive mold ring. In this embodiment, as shown in Figure 1, the p-type guard rings 21 are made of a square shape with rounded corners, but they may be made of other frame shapes such as a circular shape. The p-type guard rings 21 are n - It is formed from the surface of mold layer 2 to a predetermined depth, but n - It may be formed away from the surface of mold layer 2. The p-type guard ring 21 is n - It is formed by ion implanting p-type impurities into the mold layer 2.

[0033] In this embodiment, the p-type guard ring 21 has the same configuration as the p-type deep layer 5 described above. The p-type guard ring 21 differs from the linearly formed p-type deep layer 5 in that its upper surface shape is a frame-shaped line surrounding the cell region RC and the connecting portion RJ, but otherwise it is the same. That is, the p-type guard ring 21 has the same impurity concentration and width as the p-type deep layer 5. The spacing DA3 between each p-type guard ring 21 may be equal, but in order to mitigate electric field concentration on the cell region RC side and cause equipotential lines to move further outward, the spacing DA3 between the p-type guard rings 21 is narrower on the cell region RC side and wider towards the outer edge. The spacing DA3in of the p-type guard ring 21 in the portion located within a predetermined range from the boundary position of the mesa portion RM is narrower than the spacing DA1 of the linear portion 5a of the p-type deep layer 5 and the spacing DA2 of the linear portion 31 of the p-type deep layer 30, which will be described later. Furthermore, the widest part of the outermost part of the spacing DA3, that is, the spacing DA3out between the outermost p-type guard ring 21 and the one next to it, is wider than the spacings DA1 and DA2.

[0034] Although not shown in the diagram, if necessary, an ECR structure can be provided on the outer circumference of the p-type guard ring 21, thereby forming a guard ring section RG with an outer pressure-resistant structure surrounding the cell region RC.

[0035] Furthermore, the section from the cell region RC to the guard ring section RG is designated as a connecting section RJ, and in the connecting section RJ, n - A p-type deep layer 30 is formed on the surface of the mold layer 2. The p-type deep layer 30 is in contact with the p-type base region 3 and is fixed at the source potential. In this embodiment, as shown by the dashed hatching in Figure 1, a connecting portion RJ is formed to surround the cell region RC, and furthermore, multiple square-shaped p-type guard rings 21 with rounded corners are formed to surround the outside of this connecting portion RJ.

[0036] The p-type deep layer 30 has a configuration that includes multiple linear portions 31 arranged in a stripe pattern parallel to the p-type deep layer 5 formed in the cell region RC, and one or more frame-shaped portions 32 arranged to surround the p-type deep layer 5 and the linear portions 31. The linear portions 31 of the p-type deep layer 30 constitute a part of the second conductive type layer, and the frame-shaped portions 32 constitute a part of the second conductive type ring.

[0037] The linear portion 31 is formed in the region between the cell region RC and the frame-shaped portion 32. - If a p-type layer is not formed within the mold layer 2, areas where equipotential lines rise excessively will occur; therefore, the layer is formed in a way that prevents such areas from occurring. In the direction perpendicular to the longitudinal direction of the linear portion 5a of the p-type deep layer 5, multiple linear portions 31 are arranged parallel to the linear portion 5a between the cell region RC and the frame-shaped portion 32. In the longitudinal direction of the linear portion 5a, multiple linear portions 31 are also formed extending in the same direction as the linear portion 5a between the cell region RC and the frame-shaped portion 32. The tip of each linear portion 5a is connected to the intersection 5b of the p-type deep layer 5 or to the innermost part of the frame-shaped portion 32. In this way, the linear portions 31 are arranged between the cell region RC and the frame-shaped portion 32. The tip of the linear portion 31 may be separate from the intersection portion 5b or the frame-shaped portion 32, but in that case, it is preferable that the distance between them be the same as or smaller than the spacing DA1 of the linear portions 5a in the p-type deep layer 5.

[0038] The frame-shaped portion 32 has a rectangular shape with rounded corners and surrounds the cell region RC and the linear portion 31. Specifically, the frame-shaped portion 32 is arranged concentrically with the p-type guard ring 21. In this embodiment, multiple frame-shaped portions 32 are provided.

[0039] Each p-type deep layer 30, composed of these linear portions 31 and frame-shaped portions 32, is located below the p-type base region 3. - It is formed by ion implantation from the surface of mold layer 2 to a predetermined depth.

[0040] In this embodiment, the width of the linear portion 31 of the p-type deep layer 30 is set to 0.4 to 1.0 μm, which is the same width as the p-type deep layer 5. The spacing DA2 of the linear portions 31 is set to 0.6 to 1.5 μm, which may be the same as the spacing DA1 of the linear portions 5a of the p-type deep layer 5, but here it is set to be narrower than the spacing DA1.

[0041] The frame-shaped portion 32 is formed from the inner circumference to the outer circumference of the mesa portion RM and has the same width as the p-type deep layer 5. The spacing DA4 of the frame-shaped portion 32 may all be the same width, or they may be different. Preferably, the spacing DA4 of the frame-shaped portion 32 is less than or equal to the spacing DA1 of the linear portion 5a of the p-type deep layer 5 in the cell region RC. More preferably, the spacing DA4out of the frame-shaped portion 32 in the portion located within a predetermined range from the boundary position of the mesa portion RM is narrower than the spacing DA2 of the linear portion 31 in the p-type deep layer 30.

[0042] Here, the spacing DA3in of the p-type guard rings 21 and the spacing DA4out of the frame-shaped portion 32, which are located within a predetermined range from the boundary position of the mesa portion RM, are made narrower than the spacing DA2 of the linear portion 31 in the p-type deep layer 30. This is to accommodate mask misalignment when forming the recess 20 for forming the mesa portion RM.

[0043] If mask misalignment occurs, the formation position of the inner circumferential end of the recess 20 will shift. For example, in the structure of Figure 1, suppose mask misalignment occurs and the formation position of the inner circumferential end of the recess 20 shifts to the right side of the paper. In this case, on the left side of the paper, a part of the frame-shaped portion 32 will be formed inside the recess 20, outside the mesa portion RM, and on the right side of the paper, a part of the p-type guard ring 21 will be formed inside the mesa portion RM instead of inside the recess 20. In such a structure, since a part of the frame-shaped portion 32 has a structure similar to the guard ring, it is preferable that it has the same width and spacing as the inner circumferential side of the p-type guard ring 21. Therefore, as in this embodiment, the spacing DA4out of the frame-shaped portion 32 and the spacing DA3in of the p-type guard ring 21 are made narrower than the spacing DA1 in the portion located within a predetermined range from the boundary position of the mesa portion RM. Preferably, the frame-shaped portion 32 and the p-type guard ring 21 have the same width and spacing. This allows for adaptation to mask misalignment.

[0044] Although the frame-shaped portion 32 has been described separately from the p-type guard ring 21, it can be said that the frame-shaped portion 32 and the p-type guard ring 21 constitute a plurality of concentrically arranged frame-shaped p-type rings. In other words, the portion of the p-type ring located on the inner circumference side of the recess 20 constitutes the frame-shaped portion 32, and the portion formed within the recess 20 constitutes the p-type guard ring 21.

[0045] Furthermore, a p-type base region 3 is also formed in the connecting portion RJ. A p-type hole extraction layer 3b is formed on top of the p-type base region 3. The source electrode 9 is formed up to the top of the p-type hole extraction layer 3b, and the p-type base region 3 and the p-type deep layer 30 are connected through the p-type hole extraction layer 3b. The p-type hole extraction layer 3b is formed in the connecting portion RJ so as to surround the cell region RC. Here, the p-type hole extraction layer 3b is formed to surround the entire perimeter of the cell region RC, but it may also be divided into multiple sections and arranged at equal intervals around the entire perimeter. By providing this p-type hole extraction layer 3b, if an avalanche breakdown occurs in the cell region RC, or if an avalanche breakdown occurs in the guard ring portion RG or the connecting portion RJ, holes generated in the outer region can be extracted to the source electrode 9. Therefore, it is possible to limit the flow of holes into the cell region RC and suppress device failure.

[0046] Furthermore, an interlayer insulating film 10 is formed on the surface of the p-type hole-drawn layer 3b. Although not shown in the figure, the gate pad connected to the gate wiring layer is formed in the junction RJ at a location in the interlayer insulating film 10 that is different from the location where the source electrode 9 is placed.

[0047] The SiC semiconductor device according to this embodiment is constructed with the structure described above. When the MOSFET 100 is turned on, the SiC semiconductor device configured in this way controls the voltage applied to the gate electrode 8 to form a channel region on the surface of the p-type base region 3 located on the side of the gate trench 6. As a result, n + Type source region 4, channel region and n - A current is passed between the source electrode 9 and the drain electrode 11 through the mold layer 2.

[0048] Furthermore, when the MOSFET 100 is off, even if a high voltage is applied, the p-type deep layer 5 and p-type deep layer 30, which are formed to a depth greater than the trench gate structure, suppress the penetration of the electric field into the bottom of the gate trench. As a result, electric field concentration at the bottom of the gate trench is mitigated. This prevents the destruction of the gate insulating film 7.

[0049] Furthermore, at the connecting section RJ, the upward movement of equipotential lines is suppressed, and the equipotential lines are directed toward the guard ring section RG. Then, at the guard ring section RG, the p-type guard ring 21 gradually terminates the equipotential lines toward the outer circumference, so that the desired withstand voltage can be obtained even at the guard ring section RG.

[0050] Here, the widths and spacings DA1 to DA4 of each part of the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 are as described above. As a result, the proportion of the p-type layers implanted deep by ion implantation, i.e., the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21, that occupy the total surface area of ​​the chip constituting the SiC semiconductor device is kept to 40% or less.

[0051] When forming a p-type layer by ion implantation, the wafer for forming the SiC semiconductor device warps during the process depending on the dose and acceleration, leading to problems associated with wafer warping, such as transport errors, substrate adsorption errors, and reduced photoresolution.

[0052] Therefore, it is necessary to minimize wafer warping while simultaneously achieving the effects of suppressing the penetration of electric fields into the bottom of the gate trench and obtaining the desired withstand voltage in the guard ring section RG.

[0053] Specifically, the relationship between the ion implantation acceleration voltage and wafer warpage is shown in Figure 3. Furthermore, the relationship between the integrated ion implantation dose and wafer warpage is shown in Figure 4. The relationship between the ion implantation acceleration voltage and wafer warpage was investigated using a 350 μm thick substrate, with Al as the p-type impurity to form a p-type layer of approximately the same depth as the p-type deep layer 5. The study examined both the front and back sides of the SiC substrate when ion implantation was performed. The dose in this case was 8 × 10⁻⁶. 14 cm -2 This was kept constant. Furthermore, regarding the relationship between the ion implantation dose and wafer warpage, a constant acceleration voltage of 150 keV was used, and a p-type layer of approximately the same depth as the p-type deep layer 5 was formed on the surface of the SiC substrate using Al as the p-type impurity. The difference in height between the outer edge and the center of the substrate was measured as the amount of warpage.

[0054] As can be seen in Figure 3, wafer warpage is proportional to the ion implantation acceleration voltage, with increased wafer warpage resulting from higher acceleration voltages. Furthermore, as can be seen in Figure 4, wafer warpage is also proportional to the ion implantation dose, with increased wafer warpage resulting from higher doses.

[0055] Therefore, if the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 are to be formed to a deep position using a high acceleration voltage, it is necessary to reduce the dose during ion implantation. To achieve this, it is not desirable to have a structure in which the deep layer is provided over the entire area of ​​the joint, as in Patent Document 1, and it is necessary to limit the formation range of the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21, as in this embodiment.

[0056] Therefore, in this embodiment, the p-type deep layer 30 formed in the connecting portion RJ is composed of linear portions 31 and frame-shaped portions 32, and is not formed over the entire area of ​​the connecting portion RJ. However, when the p-type deep layer 30 is not formed over the entire area of ​​the connecting portion RJ, if the spacing DA2 of the linear portions 31 is wide, equipotential lines may rise up as shown in Figure 5A, which can reduce the breakdown voltage. Specifically, when the relationship between the spacing DA2 and the breakdown voltage was investigated by arranging the p-type layers in a stripe pattern, the results were obtained in Figure 5B, and it was confirmed that in order to obtain a breakdown voltage of about 1800[V] with a spacing DA2, it is preferable that the spacing DA2 be 1.5 μm or less. For this reason, the spacing DA2 of the linear portions 31 in the p-type deep layer 30 is set to 1.5 μm or less.

[0057] On the other hand, from the perspective of pressure resistance, a spacing DA2 of 1.5 μm or less is acceptable. However, if the spacing DA2 is too narrow, the remaining width of the photomask used when ion implanting the p-type deep layer 30 becomes narrow, which may prevent proper patterning. For this reason, the spacing DA2 is set to 0.6 μm or more.

[0058] Here, we have described the spacing DA2 of the linear portion 31 in the p-type deep layer 30, but the same applies to the spacing DA1 of the p-type deep layer 5 in the cell region RC, and it is preferable to set the spacing DA1 to 0.6 to 1.5 μm. Furthermore, it is preferable to set the spacing DA3in and spacing DA4out to 0.6 to 1.5 μm, and it is even preferable to make them smaller than spacing DA1 and spacing DA2 in order to accommodate mask misalignment.

[0059] Furthermore, narrowing the spacing DA1 and DA2 improves the breakdown voltage, but this also increases the formation ratio of p-type deep layer 5 and p-type deep layer 30, resulting in a larger dose during ion implantation. Therefore, it is necessary to reduce the spacing DA1 and DA2 while ensuring that the dose during ion implantation does not become excessive. In addition, not only the spacing DA1 and DA2, but also the width of p-type deep layer 5 and p-type deep layer 30 affects the dose during ion implantation. The width of p-type deep layer 5 and p-type deep layer 30 can cause a decrease in breakdown voltage and an increase in feedback capacitance Crss, so it is necessary to set the ion implantation dose so that the breakdown voltage is maintained, the feedback capacitance Crss is suppressed, and wafer warping is suppressed.

[0060] Figure 6A shows the change in the intensity of the electric field applied near the bottom of the gate trench 6 when the width of the linear portion 31 in the p-type deep layer 5 is changed in the cell region RC. Similar results were obtained when the width of the linear portion 31 was kept constant and the spacing between the linear portions 31 was widened. Although the electric field in the cell region RC is shown here, the same applies to the connecting portion RJ. As shown in this figure, when the width of the p-type deep layer 5 or p-type deep layer 30 is narrowed, equipotential lines are more likely to enter the p-type deep layer 5 or p-type deep layer 30, as described above. As a result, the rise of equipotential lines between the p-type deep layer 5 or p-type deep layer 30 increases, leading to a decrease in breakdown voltage. In particular, in the cell region RC, a high electric field is applied to the bottom of the gate trench 6, which can cause dielectric breakdown of the gate insulating film 7.

[0061] Figure 6B shows the change in the feedback capacitance Crss when the spacing between the linear sections 31 in the p-type deep layer 30 is kept constant and the width of the linear sections 31 is changed. Specifically, the feedback capacitance Crss was measured when the width of the linear sections 31 was changed with n=3 and 450[V] was applied to the drain side, and the average value was approximated by a curve. Similar results were obtained when the width of the linear sections 31 was kept constant and the spacing between the linear sections 31 was widened.

[0062] As the feedback capacitance Crss increases, the switching loss increases, so it is necessary to limit the width of the p-type deep layer 30 to a certain extent. When the width of the p-type deep layer 30 is narrow, the p-type deep layer 30 and n - A depletion layer forms at the PN junction with the p-type layer 2, causing equipotential lines to enter the p-type deep layer 30. Therefore, if the width of the p-type deep layer 30 is too narrow, the feedback capacitance Crss will increase further.

[0063] Considering switching losses, the feedback capacitance Crss is preferably 60 [pF] or less, and considering breakdown voltage, the electric field strength applied between the p-type deep layer 5 and the p-type deep layer 30 is preferably 4 [MV / cm] or less. To satisfy these conditions, in this embodiment, the width of the p-type deep layer 5 and the p-type deep layer 30 is 0.4 μm or more.

[0064] Furthermore, while the above conditions can be met by increasing the width of the p-type deep layer 5 and p-type deep layer 30, beyond a certain width, increasing the width does not significantly improve the effect of suppressing the feedback capacitance Crss or ensuring the breakdown voltage. Conversely, increasing the width of the p-type deep layer 5 and p-type deep layer 30 increases the dose amount when ion implanting p-type impurities, which affects wafer warping. For this reason, it is better to limit the width of the p-type deep layer 5 and p-type deep layer 30 to a certain size. Therefore, the width of the p-type deep layer 5 and p-type deep layer 30 is set to 1.5 μm or less, preferably 1.0 μm or less, where the effect of suppressing the feedback capacitance Crss and ensuring the breakdown voltage almost plateaus.

[0065] Furthermore, when the width of the p-type deep layer 5 and the p-type deep layer 30 is set to 0.4 to 1.5 μm, it is necessary to set the spacing between the p-type deep layer 5 and the p-type deep layer 30 so that the dose during ion implantation can keep the wafer warpage below a predetermined value. For this reason, spacings DA1 and DA2 are set to 0.6 to 1.5 μm based on the results shown in Figure 4. As mentioned above, spacings DA1 and DA2 can be the same, but unlike spacing DA1, which has a trench gate structure in between, spacing DA2 does not have a trench gate structure in between, so it is preferable to make it smaller than spacing DA1.

[0066] Although the spacings DA1 and DA2 have been described here, the same can be said for the spacings DA4 and DA4out of the frame-shaped portion 32 and the spacing DA3in of the p-type guard ring 21 located within a predetermined range from the boundary of the mesa portion RM. Furthermore, the same can be said for the width of the p-type guard ring 21 as for the p-type deep layer 5 and p-type deep layer 30. In addition, due to the structure, equipotential lines become densely packed near the mesa portion RM, so it is preferable to make the spacings DA4out and DA3in within a predetermined range from the boundary of the mesa portion RM smaller than the spacings DA1 and DA2 in order to suppress the rise of equipotential lines in the mesa portion RM.

[0067] In this way, the spacing DA1 to DA4 and the widths of the p-type deep layers 5 and 30 are defined. Figure 7 shows the results of investigating the area ratios of the cell region RC, the connecting portion RJ, and the guard ring portion RG within a 5 mm square chip on which a SiC semiconductor device is formed, and the occupancy rates of the p-type deep layers 5 and 30 and the p-type guard ring 21 within those areas. Here, as an example, the case where the cell region RC occupies 60% of the chip area, the connecting portion RJ 30% occupies 30% occupies 1 The width of the p-type guard ring 21 is set to 1.0 μm, and the spacing DA4 is set to 0.6 to 1.5 μm, with the spacing increasing as it moves away from the cell region RC.

[0068] As shown in this figure, in the comparative example where the p-type deep layer 30 is formed over the entire RJ joint, the proportion of the p-type deep layer 30 within the RJ joint becomes 100%. Therefore, the proportion of the p-type deep layer 30 within the chip is 30%, the same as the area ratio of the RJ joint within the chip. In the cell region RC, the proportion of the p-type deep layer 5 within the chip was 24%, and in the guard ring region RG, the proportion of the p-type guard ring 21 within the chip was 3%. Thus, the total occupancy rate of the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 within the chip was 57%.

[0069] In contrast, when the p-type deep layer 30 is constructed with a linear portion 31 and a frame-shaped portion 32, as in this embodiment, the proportion of the p-type deep layer 30 within the connecting portion RJ becomes 40%. Therefore, the proportion of the p-type deep layer 30 within the chip becomes 12%. Also, in the cell region RC, the proportion of the p-type deep layer 5 within the chip remains at 24%, and in the guard ring portion RG, the proportion of the p-type guard ring 21 within the chip remains at 3%. Therefore, the total occupancy rate TV of the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 within the chip becomes 39%.

[0070] In this way, by making the p-type deep layer 30 into a linear shape such as the linear portion 31 and the frame-shaped portion 32, the occupancy rate of the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 within the chip can be reduced. Here, the width of the p-type deep layer 5 and p-type deep layer 30 is set to 1.0 μm, and the spacing DA1 to DA3 is set to 0.6 μm. Therefore, compared to the case where the width is narrower and the spacing DA1 to DA3 is wider, the occupancy rate of the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 within the chip is higher. If the width of the p-type deep layer 30 is made smaller than 1.0 μm, or the spacing DA1 to DA3 is made larger than 0.6 μm, the total value TV can be made even smaller, at least to 40% or less. This makes it possible to suppress the total value TV of the occupancy rate of the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 within the chip, that is, to reduce the dose amount during ion implantation, and thus suppress wafer warping.

[0071] As described above, in this embodiment, by configuring the p-type deep layer 30 in a linear shape, the total occupancy rate TV of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 within the chip is set to 40% or less. This makes it possible to suppress wafer warping even while constructing the p-type deep layer 30 by ion implantation.

[0072] Furthermore, this embodiment can also achieve the following effects.

[0073] (1) As described above, the widths of the p-type deep layers 5 and 30 are set to 0.4 to 1.0 μm, and the spacing DA1 of the p-type deep layers 5, the spacing DA2 of the linear portion 31, and the spacing DA4 of the frame portion 32 are set to 0.6 to 1.5 μm. This suppresses the increase in the feedback capacitance Crss. Furthermore, it suppresses the rise of equipotential lines between the p-type deep layers 5 and 30, and also suppresses the application of a high electric field to the bottom of the gate trench 6, thereby ensuring the breakdown voltage of the SiC semiconductor device. In addition, by setting the widths and spacings DA1, DA2, and DA4 of the p-type deep layers 5 and 30 in this way, the occupied area of ​​the p-type deep layers 5 and 30 within the chip can be reduced, further reducing the dose during ion implantation. Therefore, further reduction of wafer warping becomes possible.

[0074] In this case, it is preferable to make the spacing DA1 to DA4 greater than or equal to the width of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21. By doing so, it is possible to achieve a total TV of 40% or less in the area occupied by the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 within the chip without degrading functions such as voltage resistance.

[0075] (2) Furthermore, if the size of each interval is set to interval DA3out > interval DA1 > interval DA2 > interval DA3in and interval DA4out, a break can be made to occur throughout the entire cell region RC. This prevents device failure even if a high voltage due to load surges or the like is applied to the SiC semiconductor device.

[0076] (3) Furthermore, in this embodiment, the p-type deep layer 5 of the cell region RC is provided with an intersection 5b, which connects to the linear portion 5a and the linear portion 31 in the p-type deep layer 30 of the connecting portion RJ. In addition, the innermost portion of the frame-shaped portion 32 is connected to the linear portion 31.

[0077] This structure allows for a reduction in the gaps between the p-type deep layers 5 and 30, i.e., the areas where the p-type deep layers 5 and 30 are not present, as seen in the top view in Figure 1. This further suppresses the rise of equipotential lines, enabling the securing of high voltage resistance.

[0078] Furthermore, instead of constructing the p-type deep layer 5 and p-type deep layer 30 with an ion implantation layer, n - It is also conceivable to form the layers by creating trenches on the surface of mold layer 2 and filling those trenches with p-type layers. However, filling the trenches with p-type layers is difficult in itself, and indentations occur in the p-type layers at the locations where linear sections intersect or connect. In contrast, when p-type deep layer 5 and p-type deep layer 30 are constructed using ion implantation layers, indentations do not occur in the p-type layers even at the locations where linear sections intersect or connect. Therefore, the flatness of the wafer surface can be ensured.

[0079] Next, the method for manufacturing a SiC semiconductor device according to this embodiment will be described with reference to Figures 8A to 8H.

[0080] [Process shown in Figure 8A] First, as a semiconductor substrate, n + n made of SiC on the main surface of the mold substrate 1 - Prepare a structure in which the second layer has been epitaxially grown. At this time, n + n - Alternatively, the semiconductor substrate can be prepared by epitaxially growing layer 2, or by pre-forming n + n - A so-called epitaxial substrate, in which mold layer 2 has been epitaxially grown, may be prepared as the semiconductor substrate.

[0081] [Process shown in Figure 8B] Next, n -A mask (not shown) is placed on the mold layer 2, and the mask is opened in the areas where the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 are to be formed. Then, p-type impurities are ion-implanted using the mask. At this time, the ion implantation range is adjusted so that the p-type impurities are n - The material is injected from the surface of mold layer 2 to a predetermined depth. This forms the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21. After that, the mask is removed.

[0082] In this example, the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 are formed at once, but they may be formed in multiple stages. In that case, for example, the p-type deep layer 5 and p-type deep layer 30 may be formed in upper and lower sections, with the lower section being wider than the upper section, or having different widths.

[0083] [Process shown in Figure 8C] Including the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21, n - On top of the type layer 2 are the p-type base region 3 and n + The type source region 4 is epitaxially grown sequentially.

[0084] [Process shown in Figure 8D] n + A mask (not shown) is placed on the type source region 4, and the areas of the mask intended for the formation of the p-type contact region 3a and the p-type hole extraction layer 3b are opened. Then, the p-type contact region 3a and the p-type hole extraction layer 3b are formed by ion implantation of p-type impurities using the mask. After that, the mask is removed.

[0085] Note that here n + The p-type source region 4 is epitaxially grown, and the p-type contact region 3a and p-type hole extraction layer 3b are formed by ion implantation, but this is not limited to this. For example, n +The p-type source region 4, the p-type contact region 3a, and the p-type hole extraction layer 3b may all be formed by ion implantation into the p-type base region 3. Alternatively, the p-type contact region 3a and the p-type hole extraction layer 3b may be formed by epitaxial growth to increase the impurity concentration in the surface layer of the p-type base region 3, and then n-type impurities may be ion implanted into the p-type base region 3. + It is also possible to form a type source region 4.

[0086] [Process shown in Figure 8E] n + After forming a mask (not shown) on the type source region 4 and the p-type base region 3, the areas of the mask intended for the formation of gate trenches 6 and recesses 20 are opened. Then, anisotropic etching such as RIE (Reactive Ion Etching) is performed using the mask, - A gate trench 6 and a recess 20 are simultaneously formed, with a depth greater than the upper surface of the mold layer 2.

[0087] In this example, the gate trench 6 and recess 20 are formed simultaneously, but they can also be formed separately. In that case, the gate trench 6 and recess 20 can be made to different depths, making it possible to design each to an optimal depth.

[0088] [Process shown in Figure 8F] After removing the mask, a gate insulating film 7 is formed, for example by depositing an oxide film, and the gate insulating film 7 is applied to the inner wall surface of the gate trench 6 and n + The surface of the type source region 4 is covered. Then, Poly-Si doped with p-type or n-type impurities is deposited, and this is etched back, leaving Poly-Si in at least the gate trench 6 to form the gate electrode 8. This constitutes a trench gate structure.

[0089] [Process shown in Figure 8G] An interlayer insulating film 10, made of, for example, an oxide film, is formed to cover the surfaces of the gate electrode 8 and the gate insulating film 7. Then, a mask (not shown) is formed on the surface of the interlayer insulating film 10, and the portion of the mask located between each gate electrode 8, that is, the portion corresponding to the p-type contact region 3a and its vicinity, is opened. At the same time, the portion of the mask corresponding to the p-type hole extraction layer 3b is also opened. After this, the interlayer insulating film 10 is patterned using the mask to create p-type contact regions 3a and n + Contact holes are formed to expose the type source region 4 and the p-type hole drawing layer 3b.

[0090] [Process shown in Figure 8H] An electrode material, for example, composed of a laminated structure of multiple metals, is formed on the surface of the interlayer insulating film 10. Then, by patterning the electrode material, a source electrode 9 and gate wiring (not shown) are formed.

[0091] The subsequent steps are not shown in the diagram, n + The SiC semiconductor device according to this embodiment is completed by performing steps such as forming a drain electrode 11 on the back side of the mold substrate 1.

[0092] As explained above, the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 are formed by ion implantation. Not only the p-type deep layer 5 and p-type guard ring 21, but also the p-type deep layer 30 is constructed in a linear fashion. By constructing the p-type deep layer 30 in a linear fashion, the total occupancy rate (TV) of the p-type deep layer 5, p-type deep layer 30, and p-type guard ring 21 within the chip is kept below 40%. This makes it possible to suppress wafer warping while constructing the p-type deep layer 30 by ion implantation.

[0093] (Modified version of the first embodiment) The layout of the p-type deep layer 5 and the p-type deep layer 30 may be changed compared to the first embodiment.

[0094] For example, as shown in Figure 9, the p-type deep layer 5 may be composed only of stripe-shaped portions made up of linear portions 5a. Alternatively, as shown in Figure 10, the inner portion of the frame-shaped portion 32 of the p-type deep layer 30 may be a grid-shaped portion 33 composed of stripes extending in two directions perpendicular to each other. Specifically, the grid-shaped portion 33 can be constructed with one stripe parallel to the linear portion 5a of the p-type deep layer 5 and the other stripe perpendicular to the linear portion 5a. Furthermore, as shown in Figure 11, the inner portion of the frame-shaped portion 32 of the p-type deep layer 30 may be a mesh-shaped portion 34 composed of stripes extending in two different directions that intersect each other and are inclined with respect to the linear portion 5a. In addition, as shown in Figure 12, the inner portion of the frame-shaped portion 32 of the p-type deep layer 30 may be a dot-shaped portion 35 in which multiple dots are arranged linearly with the same longitudinal direction as the linear portion 5a of the p-type deep layer 5. Here, the diagram shows a case where oval-shaped dots, whose longitudinal direction is the same as the direction in which the dot-shaped portions 35 are arranged in a straight line, are arranged in a dot line. However, each dot may be composed of other shapes such as circles or squares. In the structures shown in Figures 10 to 12, the grid-like portion 33, the mesh-like portion 34, and the dot-shaped portion 35 each constitute a part of the second conductive layer.

[0095] In these cases as well, it is preferable to set the interval DA2 of the p-type deep layer 30 in the connecting section RJ so that the relationship DA3out > DA1 > DA2 > DA3in, DA4out holds true. In the structures of Figures 10 and 11, the interval between each stripe extending in two directions that constitutes the grid-like section 33 or the mesh-like section 34 corresponds to the interval DA2. In the structure of Figure 12, the interval between adjacent dot lines or the interval between adjacent dots on the same dot line corresponds to the interval DA2.

[0096] (Second Embodiment) Next, we will describe the second embodiment. This embodiment is a modification of the first embodiment in which the pressure-resistant structure is changed to a p-type layer. Since the other aspects are the same as the first embodiment, we will mainly describe the parts that differ from the first embodiment.

[0097] As shown in Figure 13, in this embodiment, the cell region RC is provided with an n-type first current dispersion layer 50 and a p-type deep layer 51 below the p-type deep layer 5, and a second current dispersion layer 60 between the p-type deep layers 5. The p-type deep layer 51 corresponds to the first deep layer and constitutes at least a part of the second conductivity layer. The p-type deep layer 5 placed on top of the p-type deep layer 51 corresponds to the second deep layer.

[0098] Specifically, n - A first current dispersion layer 50 and a p-type deep layer 51 are formed on top of the mold layer 2. The first current dispersion layer 50 has a depth of 0.3 to 1.5 μm. The p-type deep layer 51 is shallower than the first current dispersion layer 50 but has approximately the same depth of 0.3 to 1.4 μm. In other words, the p-type deep layer 51 is formed so that its bottom is located within the first current dispersion layer 50, and n - The first current distribution layer 50 is formed to a depth such that it is located between the mold layer 2 and the first current distribution layer 50. In this example, a portion of the first current distribution layer 50 is positioned at the bottom of the p-type deep layer 51, but the first current distribution layer 50 and the p-type deep layer 51 may be of the same depth.

[0099] The first current dispersion layer 50 and the p-type deep layer 51 are each extended in one direction to form a stripe pattern with multiple lines arranged alternately, and are arranged at equal intervals along the vertical direction. In this embodiment, the stripe-shaped portion of the first current dispersion layer 50 and the p-type deep layer 51 are extended with their longitudinal direction intersecting the longitudinal direction of the trench gate structure.

[0100] The spacing between each line in the striped portion of the first current dispersion layer 50 is, for example, 0.6 to 1.5 μm, and the n-type impurity concentration is, for example, 5.0 × 10⁻⁶16 ~2.0×10 18 / cm 3 are set as follows. The width of each p-type deep layer 51 is, for example, 0.4 to 1.0 μm, and the p-type impurity concentration is, for example, 3.0×10 17 ~1.0×10 18 / cm 3 are set as follows. The interval DB1 between each p-type deep layer 51, that is, the width of each line of the striped portion in the first current dispersion layer 50, is made different from the interval DB2 of the linear portion 71 of the p-type deep layer 70 provided in the connection portion RJ described later, but they may be the same. Here, the interval DB1 is set to be greater than or equal to the interval DB2.

[0101] Regarding the first current dispersion layer 50, a concave portion is formed in the surface layer portion of the n - -type layer 2, and after epitaxial growth of the n-type layer, it is flattened, or it is formed by ion-implanting n-type impurities into the surface layer portion of the n - -type layer 2. When the first current dispersion layer 50 is formed by ion implantation, since n-type impurities are to be implanted into the n - -type layer 2, the dose amount becomes sufficiently less than that when p-type impurities are ion-implanted for the formation of the p-type deep layer 5 or the like. Therefore, wafer warping hardly occurs. Also, the p-type deep layer 51 is formed by ion-implanting p-type impurities. Therefore, for the p-type deep layer 51, the width and the dose amount are set in consideration of wafer warping. Also, for the p-type deep layer 51, the interval is set to 0.6 μm or more so that the remaining width of the photomask during ion implantation does not become too narrow.

[0102] ​​​​​​​It is preferably made higher than the type layer 2. Here, the n-type impurity concentration of the second current dispersion layer 60 is, for example, 1.0×10 16 ~5.0×10 17 / cm 3 and so on. Also, the thickness of the second current dispersion layer 60 is, for example, 0.5 to 2 μm. By ion-implanting p-type impurities into this second current dispersion layer 60, a p-type deep layer 5 is formed. And the p-type deep layer 5 is formed at a depth greater than or equal to the depth of the second current dispersion layer 60 and is connected to the p-type deep layer 51.

[0103] In addition, in this embodiment, in addition to the n - type layer 2, the first current dispersion layer 50 and the second current dispersion layer 60 form a part of the drift layer. The second current dispersion layer 60 is formed at a position corresponding to the trench gate structure and extends in a direction orthogonal to the first current dispersion layer 50, that is, in the same direction as the longitudinal direction of the trench gate structure.

[0104] In the guard ring portion RG, the second current dispersion layer 60 formed in the cell region RC on the surface of the n - type layer 2 remains. Also, a recess 20 is formed so as to penetrate the p-type base region 3 and reach the second current dispersion layer 60. And a p-type guard ring 21 is formed on the surface layer portion of the n - type layer 2. Here, the p-type guard ring 21 is arranged away from the bottom surface of the recess 20, but it may also be formed in contact with the bottom surface of the recess 20.

[0105] The p-type guard rings 21 are formed to surround the cell region RC and the connecting portion RJ, with multiple rings arranged concentrically, as in the layout of the first embodiment. The p-type guard rings 21 have the same width and impurity concentration as the p-type deep layer 51 described above. The spacing DB3 between each p-type guard ring 21 may be equal, but to mitigate electric field concentration on the cell region RC side and cause equipotential lines to move further outward, the spacing DB3 between the p-type guard rings 21 is narrower on the cell region RC side and wider towards the outer edge. The spacing DB3in of the p-type guard rings 21 in the portion located within a predetermined range from the boundary position of the mesa portion RM is narrower than the spacing DB1 of each p-type deep layer 51 in the cell region RC and the spacing DB2 of the linear portion 71 of the p-type deep layer 70 in the connecting portion RJ. Furthermore, the widest part of the spacing DB3, that is, the spacing DB3out between the outermost p-type guard ring 21 and the one next to it, is wider than the spacing DB1 and spacing DB2.

[0106] Also, at the RJ connection, n - A p-type deep layer 5 and a second current dispersion layer 60 are formed on the surface of the mold layer 2, and a p-type base region 3 is also formed on top of that. - A p-type deep layer 70 is formed on the surface of mold layer 2.

[0107] Although only a cross-section is shown in Figure 13, the p-type deep layer 70 has a configuration comprising a linear portion 71 and a frame-shaped portion 72. The linear portion 71 of the p-type deep layer 70 constitutes part of the second conductivity type layer, and the frame-shaped portion 72 constitutes part of the second conductivity type ring. When the SiC semiconductor device is viewed from above, the linear portion 71 is arranged parallel to the p-type deep layer 51 and is provided as one or more portions. When multiple linear portions 71 are provided, they are laid out so that the spacing DB2 between each linear portion 71 is less than or equal to the spacing DB1 between the p-type deep layers 51. Also, when the SiC semiconductor device is viewed from above, the frame-shaped portion 72 is arranged to surround the cell region RC and the linear portion 71 and is composed of a rectangular frame with rounded corners. The frame-shaped portion 72 is arranged concentrically with the p-type guard ring 21 and is provided as multiple portions in this embodiment.

[0108] The width of the p-type deep layer 70 is the same as that of the p-type deep layer 51. The spacing DB2 of the linear sections 71 may be the same as the spacing DB1 of the linear sections 5a of the p-type deep layer 5, but here it is narrower than spacing DB1. The spacing DB4 of the frame-shaped sections 72 may all be the same width, or they may be different. It is preferable that the spacing DB4 of the frame-shaped sections 72 be less than or equal to the spacing DB1 of the p-type deep layer 51 in the cell region RC. In particular, it is more preferable that the spacing DB4out of the spacing DB4 of the frame-shaped sections 72 located within a predetermined range from the boundary position of the mesa section RM be narrower than the spacing DB2 of the linear sections 71 in the p-type deep layer 70.

[0109] Furthermore, the spacing DB3in of the p-type guard rings 21 and DB4out of the frame-shaped portions 72, which are located within a predetermined range from the boundary position of the mesa portion RM, are made narrower than the spacing DB2 of the linear portions 71 in the p-type deep layer 70. This makes it possible to accommodate mask misalignment when forming the recesses 20 for forming the mesa portion RM, similar to the first embodiment.

[0110] In this example, the p-type deep layer 70 is provided with linear sections 71 and frame-shaped sections 72, but it may be composed of only one of them. The number of linear sections 71 and frame-shaped sections 72 can also be arbitrarily set. Furthermore, the inner portion of the frame-shaped section 72 may be arranged as a grid-like section 33, a mesh-like section 34, or even a dot-shaped section 35, as shown in the modified example of the first embodiment.

[0111] The SiC semiconductor device of this embodiment is configured as described above. In this SiC semiconductor device, the proportion of the p-type layer, i.e., the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21, that are implanted deeply by ion implantation, relative to the total area of ​​the chip constituting the SiC semiconductor device is set to 40% or less. This makes it possible to reduce the dose amount during ion implantation and suppress wafer warping.

[0112] Furthermore, the width of the p-type deep layer 5 is set to 0.4 to 1.0 μm, similar to the first embodiment. In this way, even for the p-type deep layer 5 which is placed above the p-type deep layer 51, wafer warping can be further suppressed by limiting the injection range.

[0113] Next, the manufacturing method of the SiC semiconductor device according to this embodiment will be described. The manufacturing method of the SiC semiconductor device according to this embodiment is generally the same as that of the first embodiment, except that the formation process of the first current dispersion layer 50, p-type deep layer 51, p-type deep layer 70, p-type guard ring 21, second current dispersion layer 60, and p-type deep layer 5 is different. For this reason, the manufacturing processes other than these will be described by referring to the manufacturing processes described in the first embodiment.

[0114] First, as in the process shown in Figure 8A described in the first embodiment, n is used as the semiconductor substrate. + n made of SiC on the main surface of the mold substrate 1 - Prepare a mold layer 2 that has been epitaxially grown. Then, perform the steps shown in Figures 14A to 14C.

[0115] [Process shown in Figure 14A] n - A mask (not shown) with an opening in the region where the first current dispersion layer 50 is to be formed is placed on the mold layer 2, and then the first current dispersion layer 50 is formed by ion implantation of n-type impurities. Note that the first current dispersion layer 50 may also be formed by selective epitaxial growth instead of ion implantation. For example, n - Alternatively, the mold layer 2 may be partially etched to form trenches at the planned locations for the formation of the first current dispersion layer 50, then the n-type layer may be epitaxially grown and planarized to form the first current dispersion layer 50.

[0116] [Process shown in Figure 14B] Next, n including the first current dispersion layer 50 - A mask (not shown) with openings for the planned formation positions of the p-type deep layer 51, p-type deep layer 70, and p-type guard ring 21 is placed on top of the mold layer 2, and then p-type impurities are ion-implanted. This forms the p-type deep layer 51, p-type deep layer 70, and p-type guard ring 21.

[0117] [Process shown in Figure 14C] Furthermore, n including p-type deep layer 51, p-type deep layer 70 and p-type guard ring 21 - A second current-dispersed layer 60 is epitaxially grown on the mold layer 2. Then, a mask (not shown) with an opening for the planned formation location of the p-type deep layer 5 is placed, and p-type impurities are ion-implanted. This forms the p-type deep layer 5 that penetrates the second current-dispersed layer 60 and connects to the p-type deep layer 51 and the p-type deep layer 70.

[0118] Although the subsequent steps are not shown in the diagram, the SiC semiconductor device of this embodiment can be manufactured by performing the same manufacturing steps as those described in Figure 8D and later in the first embodiment.

[0119] Thus, in this embodiment, the cell region RC has a p-type deep layer 51, the connecting portion RJ has a p-type deep layer 70, and the guard ring portion RG has a p-type guard ring 21, each being n -These are provided on the surface layer of mold layer 2 and are formed simultaneously by ion implantation. Furthermore, the proportion of the p-type layer, i.e., the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21, that are implanted deeply by ion implantation, is kept below 40% of the total surface area of ​​the chip constituting the SiC semiconductor device. This makes it possible to reduce the dose during ion implantation and suppress wafer warping.

[0120] (Third embodiment) A third embodiment will now be described. In this embodiment, a junction barrier Schottky diode (hereinafter referred to as JBS) is provided as a power element instead of a vertical MOSFET compared to the first embodiment. Since the other aspects are the same as the first embodiment, only the differences from the first embodiment will be described.

[0121] As shown in Figures 15 and 16, n + n - A type drift layer 102 is formed. And in the cell region RC, n - A striped p-type deep layer 103 is formed on the mold drift layer 102, and a p-type guard ring 104 is formed on the guard ring portion RG surrounding it. In addition, a p-type connecting layer 105 is formed in the connecting portion RJ between the cell region RC and the guard ring portion RG.

[0122] The p-type deep layer 103 constitutes at least a part of the second conductive layer, and n -Multiple lines are arranged at equal intervals on the type drift layer 102 to form a stripe pattern. The p-type guard ring 104 constitutes at least a part of the second conductive type ring and is composed of multiple square-shaped rings with rounded corners arranged concentrically. The p-type bridging layer 105 is composed of multiple frame-shaped elements arranged around the p-type deep layer 103 formed in the cell region. Here, the p-type bridging layer 105 is composed entirely of frame-shaped parts, but linear parts may also be provided inside the frame-shaped parts. The linear parts of the p-type bridging layer 105 constitute a part of the second conductive type layer, and the frame-shaped parts constitute a part of the second conductive type ring. These p-type deep layer 103, p-type guard ring 104, and p-type bridging layer 105 are n - It is formed by ion implanting p-type impurities into the type drift layer 102.

[0123] Furthermore, in the cell region RC and the connecting portion RJ, n - A Schottky electrode 106, which corresponds to the first electrode, is formed in contact with the surface of the p-type drift layer 102, the p-type deep layer 103, and the p-type bridging layer 105. In other words, in this embodiment, there are multiple p-type rings consisting of line-shaped frame-shaped p-type layers surrounding the cell region RC, and the Schottky electrode 106 is arranged to cover a part of the inner circumference of these rings. The part of these multiple p-type rings that is in contact with the Schottky electrode 106 is called the p-type bridging layer 105. In addition, among the multiple p-type layers, there are n-type rings that are not in contact with the Schottky electrode 106 and are located on the outside. - The part positioned where the type drift layer 102 is exposed is called the p-type guard ring 104. The part where the Schottky electrode 106 is formed is the Schottky electrode part RS, which consists of the cell region RC and the connecting part RJ.

[0124] Furthermore, n + An ohmic electrode 107, corresponding to the second electrode, is formed on the back side of the substrate 101. In this way, the SiC semiconductor device of this embodiment is constructed.

[0125] In this configuration, the p-type deep layer 103, the p-type guard ring 104, and the p-type bridging layer 105 have, for example, a width of 0.4 to 1 μm. These may be formed with the same width or with different widths. Furthermore, they have a depth of, for example, about 2 μm. These depths may be different, but here they are the same. In addition, the spacing DC1 to DC4 is, for example, 0.6 to 1.5 μm. These spacings DC1 to DC4 may be the same, but here they are different. Specifically, the spacing DC2 of the p-type bridging layer 105 in the bridging section RJ is narrower than the spacing DC1 of the p-type deep layer 103 in the cell region RC. In this embodiment, the p-type bridging layer 105 is composed only of frame-shaped portions. If the space between the frame-shaped portions of the spacing DC2 is defined as spacing DC4, then the spacing DC4out, which is located within a predetermined range from the boundary position of the Schottky electrode portion RS, is made the narrowest. Furthermore, the spacing DC3 of the p-type guard ring 104 may be equally spaced, but to mitigate electric field concentration on the cell region RC side and cause equipotential lines to move more toward the outer circumference, the spacing is made narrower on the cell region RC side and wider toward the outer circumference. The spacing DC3in of the p-type guard ring 104, which is located within a predetermined range from the boundary position of the Schottky electrode portion RS, is narrower than the spacing DC1 of the p-type deep layer 103 in the cell region RC and is about the same as spacing DC4out. In addition, the widest part of spacing DC3, that is, the spacing DC3out between the outermost p-type guard ring 104 and the one inward, is wider than spacing DC1 and spacing DC2.

[0126] Thus, in the SiC semiconductor device equipped with JBS as a power element, the width and spacing of the p-type junction layer 105 and the p-type guard ring 104 are the same as in the first embodiment.

[0127] Specifically, the spacing DC2 of the p-type bridging layer 105 is basically set to be less than or equal to the spacing DC1 of the p-type deep layer 103, and the spacing DC2 is made even smaller on the outer edge side of the Schottky electrode RS. In addition, the spacing DC3 between the p-type guard rings 104 is gradually increased towards the outer circumference. At the outermost edge, the spacing DC3out between the p-type guard rings 104 is larger than the spacing DC1 between the p-type deep layers 103. As a result, the proportion of the p-type layers implanted deep by ion implantation, i.e., the p-type deep layer 103, p-type bridging layer 105, and p-type guard ring 104, that constitute the total surface area of ​​the SiC semiconductor device is kept below 40%.

[0128] A SiC semiconductor device with such a structure is formed, for example, as follows: First, n + n - After epitaxial growth of the drift layer 102, n - A mask (not shown) is placed on the surface of the p-type drift layer 102. Then, a p-type deep layer 103, a p-type guard ring 104, and a p-type binding layer 105 are formed by ion implantation of p-type impurities from above the mask. Subsequently, an n-type layer containing the p-type deep layer 103, the p-type guard ring 104, and the p-type binding layer 105 is formed. - After depositing the electrode material on the mold drift layer 102, it is patterned to form the Schottky electrode 106. Finally, n + The SiC semiconductor device of this embodiment is completed by forming the ohmic electrode 107 on the back side of the mold substrate 101.

[0129] In the manufacturing of such SiC semiconductor devices, the p-type deep layer 103, the p-type guard ring 104, and the p-type bridging layer 105 are formed by ion implantation. However, since the p-type deep layer 103, the p-type guard ring 104, and the p-type bridging layer 105 are configured as described above, the same effects as in the first embodiment can be obtained in the SiC semiconductor device of this embodiment as well.

[0130] (Other embodiments) The present invention is not limited to the embodiments described above, and can be modified as appropriate within the scope of the claims.

[0131] For example, in each of the above embodiments, n - p-type impurities were ion-implanted from the surface of mold layer 2 to form a p-type deep layer 5, etc., but the surface of the p-type base region 3 or n + P-type impurities may be ion-implanted from the surface of the source region 4, etc. However, in that case, a higher acceleration voltage will be used for high-frequency ion implantation, and the effect of wafer warping will be greater. For this reason, considering the effect of wafer warping, the allowable range of dose and width of the p-type deep layer 5, etc., should be n - The gap may be narrower than when p-type impurities are ion-implanted from the surface of mold layer 2 to form a p-type deep layer 5, etc.

[0132] Furthermore, in each of the above embodiments, MOSFETs 100 and JBSs are given as examples of semiconductor elements provided in the cell region RC of the SiC semiconductor device. However, other semiconductor elements can be formed as long as they comprise a cell region RC and an outer region RO, and a p-type deep layer is formed in the junction RJ of the outer region RO. Examples of such semiconductor elements include IGBTs. In addition, in each of the above embodiments, an n-channel type MOSFET 100 with a first conductivity type of n-type and a second conductivity type of p-type was used as an example, but a p-channel type MOSFET 100 with the conductivity types of each component reversed may also be used. Furthermore, the elements are not limited to trench gate structures, but may also be planar type elements. Note that for IGBTs, n + The only difference is that the conductivity type of the substrate 1 is changed from n-type to p-type; the other structures and manufacturing methods are the same as in the embodiments described above.

[0133] Furthermore, in the first embodiment, the widths of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are the same, but they may be of different widths. In the second embodiment, the widths of the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21 are the same, but they may be of different widths. In the third embodiment, the widths of the p-type deep layer 103, the p-type guard ring 104, and the p-type connecting layer 105 are the same, but they may be of different widths. Moreover, in the first to third embodiments, the widths of each p-type guard ring 21 and p-type guard ring 104 are the same, but the width of each p-type guard ring 21 may be structured so that it widens towards the outer edge.

[0134] Furthermore, although the above embodiments described the case in which SiC is used as the semiconductor material, the present invention can also be applied to semiconductor devices that use other semiconductor materials such as Si.

[0135] In addition, when indicating the orientation of a crystal, a bar (-) should ideally be placed above the desired number. However, due to the limitations on expression imposed by electronic filing, in this specification, a bar will be placed before the desired number. [Explanation of Symbols]

[0136] 1 n + substrate type 2 n - mold layer 3 p-type base region 4 n + Type source area 5. 30 p-type deep layer 8 gates 9 Source electrodes 10 Interlayer insulating film 21 p-type guard ring

Claims

1. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connecting portion (RJ) located between the guard ring portion and the cell region, A substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, The aforementioned cell region includes: A second conductive type layer (5, 5a, 51, 103) is formed in the drift layer and includes portions that are formed in a stripe shape with one direction as the longitudinal direction, The first electrode (9, 106) is electrically connected to the second conductivity layer, The substrate has a second electrode (11, 107) formed on the back side, A vertical semiconductor element is provided between the first electrode and the second electrode for conducting current, The aforementioned connecting section also, The drift layer is provided with a second conductive layer (31, 33-35, 71) formed in a line shape. The guard ring portion and the connecting portion are: The drift layer is formed and has a plurality of line-shaped frame structures surrounding the cell region, and a second conductive ring (21, 32, 72, 104, 105) is provided, with at least a portion of the outer circumference constituting a guard ring (21, 104). The second conductive layer and the second conductive ring are composed of an ion implantation layer, and the proportion of the second conductive layer and the second conductive ring to the total surface area of ​​the chip is 40% or less. The second conductive layer provided in the connecting portion includes a linear portion (31) whose longitudinal direction is the same as the longitudinal direction of the second conductive layer provided in the cell region, The guard rings are arranged such that the spacing between them (DA3, DB3) increases from the inner circumference to the outer circumference. The spacing of the guard rings is set to the third spacing (DA3, DB3), A semiconductor device having the relationship that the spacing of the widest part of the third spacing located on the outermost circumference (DA3out, DB3out) > the spacing of the part of the third spacing located on the inner circumference (DA3in, DB3in).

2. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connecting portion (RJ) located between the guard ring portion and the cell region, A substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, The aforementioned cell region includes: A second conductive type layer (5, 5a, 51, 103) is formed in the drift layer and includes portions that are formed in a stripe shape with one direction as the longitudinal direction, The first electrode (9, 106) is electrically connected to the second conductivity layer, The substrate has a second electrode (11, 107) formed on the back side, A vertical semiconductor element is provided between the first electrode and the second electrode for conducting current, The aforementioned connecting section also, The drift layer is provided with a second conductive layer (31, 33-35, 71) formed in a line shape. The guard ring portion and the connecting portion are: The drift layer is formed and has a plurality of line-shaped frame structures surrounding the cell region, and a second conductive ring (21, 32, 72, 104, 105) is provided, with at least a portion of the outer circumference constituting a guard ring (21, 104). The second conductive layer and the second conductive ring are composed of an ion implantation layer, and the proportion of the second conductive layer and the second conductive ring to the total surface area of ​​the chip is 40% or less. The second conductive layer provided in the connecting portion includes a grid-like portion (33) having a structure in which stripes extending in a direction along the longitudinal direction of the second conductive layer provided in the cell region and in a direction intersecting the longitudinal direction are perpendicular to each other. The guard rings are arranged such that the spacing between them (DA3, DB3) increases from the inner circumference to the outer circumference. The spacing of the guard rings is set to the third spacing (DA3, DB3), A semiconductor device having the relationship that the spacing of the widest part of the third spacing located on the outermost circumference (DA3out, DB3out) > the spacing of the part of the third spacing located on the inner circumference (DA3in, DB3in).

3. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connecting portion (RJ) located between the guard ring portion and the cell region, A substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, The aforementioned cell region includes: A second conductive type layer (5, 5a, 51, 103) is formed in the drift layer and includes portions that are formed in a stripe shape with one direction as the longitudinal direction, The first electrode (9, 106) is electrically connected to the second conductivity layer, The substrate has a second electrode (11, 107) formed on the back side, A vertical semiconductor element is provided between the first electrode and the second electrode for conducting current, The aforementioned connecting section also, The drift layer is provided with a second conductive layer (31, 33-35, 71) formed in a line shape. The guard ring portion and the connecting portion are: The drift layer is formed and has a plurality of line-shaped frame structures surrounding the cell region, and a second conductive ring (21, 32, 72, 104, 105) is provided, with at least a portion of the outer circumference constituting a guard ring (21, 104). The second conductive layer and the second conductive ring are composed of an ion implantation layer, and the proportion of the second conductive layer and the second conductive ring to the total surface area of ​​the chip is 40% or less. The second conductive layer provided in the connecting portion includes a mesh-like portion (34) having stripes extending in two different directions that intersect with each other and having a structure that is inclined with respect to the second conductive layer provided in the cell region. The guard rings are arranged such that the spacing between them (DA3, DB3) increases from the inner circumference to the outer circumference. The spacing of the guard rings is set to the third spacing (DA3, DB3), A semiconductor device having the relationship that the spacing of the widest part of the third spacing located on the outermost circumference (DA3out, DB3out) > the spacing of the part of the third spacing located on the inner circumference (DA3in, DB3in).

4. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connecting portion (RJ) located between the guard ring portion and the cell region, A substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, The aforementioned cell region includes: A second conductive type layer (5, 5a, 51, 103) is formed in the drift layer and includes portions that are formed in a stripe shape with one direction as the longitudinal direction, The first electrode (9, 106) is electrically connected to the second conductivity layer, The substrate has a second electrode (11, 107) formed on the back side, A vertical semiconductor element is provided between the first electrode and the second electrode for conducting current, The aforementioned connecting section also, The drift layer is provided with a second conductive layer (31, 33-35, 71) formed in a line shape. The guard ring portion and the connecting portion are: The drift layer is formed and has a plurality of line-shaped frame structures surrounding the cell region, and a second conductive ring (21, 32, 72, 104, 105) is provided, with at least a portion of the outer circumference constituting a guard ring (21, 104). The second conductive layer and the second conductive ring are composed of an ion implantation layer, and the proportion of the second conductive layer and the second conductive ring to the total surface area of ​​the chip is 40% or less. The second conductive layer provided in the connecting portion includes a dot-shaped portion (35) having a dot-line structure in which a plurality of dots are arranged in a straight line with the same longitudinal direction as the longitudinal direction of the second conductive layer provided in the cell region, The guard rings are arranged such that the spacing between them (DA3, DB3) increases from the inner circumference to the outer circumference. The spacing of the guard rings is set to the third spacing (DA3, DB3), A semiconductor device having the relationship that the spacing of the widest part of the third spacing located on the outermost circumference (DA3out, DB3out) > the spacing of the part of the third spacing located on the inner circumference (DA3in, DB3in).

5. The cell region and the connecting portion are configured as a mesa portion (RM) that protrudes more than the guard ring portion. The semiconductor device according to any one of claims 1 to 4, wherein the portion of the third interval located on the inner circumference side is the portion of the third interval located within a predetermined range from the boundary position of the mesa portion.

6. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connecting portion (RJ) located between the guard ring portion and the cell region, A substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, The aforementioned cell region includes: A second conductive type layer (5, 5a, 51, 103) is formed in the drift layer and includes portions that are formed in a stripe shape with one direction as the longitudinal direction, The first electrode (9, 106) is electrically connected to the second conductivity layer, The substrate has a second electrode (11, 107) formed on the back side, A vertical semiconductor element is provided between the first electrode and the second electrode for conducting current, The aforementioned connecting section also, The drift layer is provided with a second conductive layer (31, 33-35, 71) formed in a line shape. The guard ring portion and the connecting portion are: The drift layer is formed and has a plurality of line-shaped frame structures surrounding the cell region, and a second conductive ring (21, 32, 72, 104, 105) is provided, with at least a portion of the outer circumference constituting a guard ring (21, 104). The second conductive layer and the second conductive ring are composed of an ion implantation layer, and the proportion of the second conductive layer and the second conductive ring to the total surface area of ​​the chip is 40% or less. The second conductive layer provided in the connecting portion includes a linear portion (31) whose longitudinal direction is the same as the longitudinal direction of the second conductive layer provided in the cell region, The distance between the second conductive rings located at the connecting portion is set to the fourth distance (DA4, DB4), A semiconductor device wherein the interval (DA4out, DB4out) of the fourth interval located within a predetermined range from the boundary between the connecting portion and the guard ring portion is less than the first interval (DA1, DB1), which is the interval of the second conductivity type layer arranged in the cell region.

7. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connecting portion (RJ) located between the guard ring portion and the cell region, A substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, The aforementioned cell region includes: A second conductive type layer (5, 5a, 51, 103) is formed in the drift layer and includes portions that are formed in a stripe shape with one direction as the longitudinal direction, The first electrode (9, 106) is electrically connected to the second conductivity layer, The substrate has a second electrode (11, 107) formed on the back side, A vertical semiconductor element is provided between the first electrode and the second electrode for conducting current, The aforementioned connecting section also, The drift layer is provided with a second conductive layer (31, 33-35, 71) formed in a line shape. The guard ring portion and the connecting portion are: The drift layer is formed and has a plurality of line-shaped frame structures surrounding the cell region, and a second conductive ring (21, 32, 72, 104, 105) is provided, with at least a portion of the outer circumference constituting a guard ring (21, 104). The second conductive layer and the second conductive ring are composed of an ion implantation layer, and the proportion of the second conductive layer and the second conductive ring to the total surface area of ​​the chip is 40% or less. The second conductive layer provided in the connecting portion includes a grid-like portion (33) having a structure in which stripes extending in a direction along the longitudinal direction of the second conductive layer provided in the cell region and in a direction intersecting the longitudinal direction are perpendicular to each other. The distance between the second conductive rings located at the connecting portion is set to the fourth distance (DA4, DB4), A semiconductor device wherein the interval (DA4out, DB4out) of the fourth interval located within a predetermined range from the boundary between the connecting portion and the guard ring portion is less than the first interval (DA1, DB1), which is the interval of the second conductivity type layer arranged in the cell region.

8. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connecting portion (RJ) located between the guard ring portion and the cell region, A substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, The aforementioned cell region includes: A second conductive type layer (5, 5a, 51, 103) is formed in the drift layer and includes portions that are formed in a stripe shape with one direction as the longitudinal direction, The first electrode (9, 106) is electrically connected to the second conductivity layer, The substrate has a second electrode (11, 107) formed on the back side, A vertical semiconductor element is provided between the first electrode and the second electrode for conducting current, The aforementioned connecting section also, The drift layer is provided with a second conductive layer (31, 33-35, 71) formed in a line shape. The guard ring portion and the connecting portion are: The drift layer is formed and has a plurality of line-shaped frame structures surrounding the cell region, and a second conductive ring (21, 32, 72, 104, 105) is provided, with at least a portion of the outer circumference constituting a guard ring (21, 104). The second conductive layer and the second conductive ring are composed of an ion implantation layer, and the proportion of the second conductive layer and the second conductive ring to the total surface area of ​​the chip is 40% or less. The second conductive layer provided in the connecting portion includes a mesh-like portion (34) having stripes extending in two different directions that intersect with each other and having a structure that is inclined with respect to the second conductive layer provided in the cell region. The distance between the second conductive rings located at the connecting portion is set to the fourth distance (DA4, DB4), A semiconductor device wherein the interval (DA4out, DB4out) of the fourth interval located within a predetermined range from the boundary between the connecting portion and the guard ring portion is less than the first interval (DA1, DB1), which is the interval of the second conductivity type layer arranged in the cell region.

9. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connecting portion (RJ) located between the guard ring portion and the cell region, A substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, The aforementioned cell region includes: A second conductive type layer (5, 5a, 51, 103) is formed in the drift layer and includes portions that are formed in a stripe shape with one direction as the longitudinal direction, The first electrode (9, 106) is electrically connected to the second conductivity layer, The substrate has a second electrode (11, 107) formed on the back side, A vertical semiconductor element is provided between the first electrode and the second electrode for conducting current, The aforementioned connecting section also, The drift layer is provided with a second conductive layer (31, 33-35, 71) formed in a line shape. The guard ring portion and the connecting portion are: The drift layer is formed and has a plurality of line-shaped frame structures surrounding the cell region, and a second conductive ring (21, 32, 72, 104, 105) is provided, with at least a portion of the outer circumference constituting a guard ring (21, 104). The second conductive layer and the second conductive ring are composed of an ion implantation layer, and the proportion of the second conductive layer and the second conductive ring to the total surface area of ​​the chip is 40% or less. The second conductive layer provided in the connecting portion includes a dot-shaped portion (35) having a dot-line structure in which a plurality of dots are arranged in a straight line with the same longitudinal direction as the longitudinal direction of the second conductive layer provided in the cell region, The distance between the second conductive rings located at the connecting portion is set to the fourth distance (DA4, DB4), A semiconductor device wherein the interval (DA4out, DB4out) of the fourth interval located within a predetermined range from the boundary between the connecting portion and the guard ring portion is less than the first interval (DA1, DB1), which is the interval of the second conductivity type layer arranged in the cell region.

10. The cell region and the connecting portion are configured as a mesa portion (RM) that protrudes more than the guard ring portion. The semiconductor device according to any one of claims 6 to 9, wherein the portion of the fourth interval located within a predetermined range from the boundary between the connecting portion and the guard ring portion is the portion located within a predetermined range from the boundary of the mesa portion.

11. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connecting portion (RJ) located between the guard ring portion and the cell region, A substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, The aforementioned cell region includes: A second conductive type layer (5, 5a, 51, 103) is formed in the drift layer and includes portions that are formed in a stripe shape with one direction as the longitudinal direction, The first electrode (9, 106) is electrically connected to the second conductivity layer, The substrate has a second electrode (11, 107) formed on the back side, A vertical semiconductor element is provided between the first electrode and the second electrode for conducting current, The aforementioned connecting section also, The drift layer is provided with a second conductive layer (31, 33-35, 71) formed in a line shape. The guard ring portion and the connecting portion are: The drift layer is formed and has a plurality of line-shaped frame structures surrounding the cell region, and a second conductive ring (21, 32, 72, 104, 105) is provided, with at least a portion of the outer circumference constituting a guard ring (21, 104). The second conductive layer and the second conductive ring are composed of an ion implantation layer, and the proportion of the second conductive layer and the second conductive ring to the total surface area of ​​the chip is 40% or less. The second conductive layer provided in the connecting portion includes a linear portion (31) whose longitudinal direction is the same as the longitudinal direction of the second conductive layer provided in the cell region, The guard rings are arranged such that the spacing between them (DA3, DB3) increases from the inner circumference to the outer circumference. The spacing of the guard rings is defined as the third spacing (DA3, DB3), and the spacing of the second conductive rings located at the connecting portion is defined as the fourth spacing (DA4, DB4). A semiconductor device having the following relationship: the spacing of the widest part of the third spacing located on the outermost periphery (DA3out, DB3out) > the spacing of the part of the fourth spacing located within a predetermined range from the boundary between the connecting part and the guard ring part (DA4out, DB4out).

12. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connecting portion (RJ) located between the guard ring portion and the cell region, A substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, The aforementioned cell region includes: A second conductive type layer (5, 5a, 51, 103) is formed in the drift layer and includes portions that are formed in a stripe shape with one direction as the longitudinal direction, The first electrode (9, 106) is electrically connected to the second conductivity layer, The substrate has a second electrode (11, 107) formed on the back side, A vertical semiconductor element is provided between the first electrode and the second electrode for conducting current, The aforementioned connecting section also, The drift layer is provided with a second conductive layer (31, 33-35, 71) formed in a line shape. The guard ring portion and the connecting portion are: The drift layer is formed and has a plurality of line-shaped frame structures surrounding the cell region, and a second conductive ring (21, 32, 72, 104, 105) is provided, with at least a portion of the outer circumference constituting a guard ring (21, 104). The second conductive layer and the second conductive ring are composed of an ion implantation layer, and the proportion of the second conductive layer and the second conductive ring to the total surface area of ​​the chip is 40% or less. The second conductive layer provided in the connecting portion includes a grid-like portion (33) having a structure in which stripes extending in a direction along the longitudinal direction of the second conductive layer provided in the cell region and in a direction intersecting the longitudinal direction are perpendicular to each other. The guard rings are arranged such that the spacing between them (DA3, DB3) increases from the inner circumference to the outer circumference. The spacing of the guard rings is defined as the third spacing (DA3, DB3), and the spacing of the second conductive rings located at the connecting portion is defined as the fourth spacing (DA4, DB4). A semiconductor device having the following relationship: the spacing of the widest part of the third spacing located on the outermost periphery (DA3out, DB3out) > the spacing of the part of the fourth spacing located within a predetermined range from the boundary between the connecting part and the guard ring part (DA4out, DB4out).

13. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connecting portion (RJ) located between the guard ring portion and the cell region, A substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, The aforementioned cell region includes: A second conductive type layer (5, 5a, 51, 103) is formed in the drift layer and includes portions that are formed in a stripe shape with one direction as the longitudinal direction, The first electrode (9, 106) is electrically connected to the second conductivity layer, The substrate has a second electrode (11, 107) formed on the back side, A vertical semiconductor element is provided between the first electrode and the second electrode for conducting current, The aforementioned connecting section also, The drift layer is provided with a second conductive layer (31, 33-35, 71) formed in a line shape. The guard ring portion and the connecting portion are: The drift layer is formed and has a plurality of line-shaped frame structures surrounding the cell region, and a second conductive ring (21, 32, 72, 104, 105) is provided, with at least a portion of the outer circumference constituting a guard ring (21, 104). The second conductive layer and the second conductive ring are composed of an ion implantation layer, and the proportion of the second conductive layer and the second conductive ring to the total surface area of ​​the chip is 40% or less. The second conductive layer provided in the connecting portion includes a mesh-like portion (34) having stripes extending in two different directions that intersect with each other and having a structure that is inclined with respect to the second conductive layer provided in the cell region. The guard rings are arranged such that the spacing between them (DA3, DB3) increases from the inner circumference to the outer circumference. The spacing of the guard rings is defined as the third spacing (DA3, DB3), and the spacing of the second conductive rings located at the connecting portion is defined as the fourth spacing (DA4, DB4). A semiconductor device having the following relationship: the spacing of the widest part of the third spacing located on the outermost periphery (DA3out, DB3out) > the spacing of the part of the fourth spacing located within a predetermined range from the boundary between the connecting part and the guard ring part (DA4out, DB4out).

14. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connecting portion (RJ) located between the guard ring portion and the cell region, A substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, The aforementioned cell region includes: A second conductive type layer (5, 5a, 51, 103) is formed in the drift layer and includes portions that are formed in a stripe shape with one direction as the longitudinal direction, The first electrode (9, 106) is electrically connected to the second conductivity layer, The substrate has a second electrode (11, 107) formed on the back side, A vertical semiconductor element is provided between the first electrode and the second electrode for conducting current, The aforementioned connecting section also, The drift layer is provided with a second conductive layer (31, 33-35, 71) formed in a line shape. The guard ring portion and the connecting portion are: The drift layer is formed and has a plurality of line-shaped frame structures surrounding the cell region, and a second conductive ring (21, 32, 72, 104, 105) is provided, with at least a portion of the outer circumference constituting a guard ring (21, 104). The second conductive layer and the second conductive ring are composed of an ion implantation layer, and the proportion of the second conductive layer and the second conductive ring to the total surface area of ​​the chip is 40% or less. The second conductive layer provided in the connecting portion includes a dot-shaped portion (35) having a dot-line structure in which a plurality of dots are arranged in a straight line with the same longitudinal direction as the longitudinal direction of the second conductive layer provided in the cell region, The guard rings are arranged such that the spacing between them (DA3, DB3) increases from the inner circumference to the outer circumference. The spacing of the guard rings is defined as the third spacing (DA3, DB3), and the spacing of the second conductive rings located at the connecting portion is defined as the fourth spacing (DA4, DB4). A semiconductor device having the following relationship: the spacing of the widest part of the third spacing located on the outermost periphery (DA3out, DB3out) > the spacing of the part of the fourth spacing located within a predetermined range from the boundary between the connecting part and the guard ring part (DA4out, DB4out).

15. The cell region and the connecting portion are configured as a mesa portion (RM) that protrudes more than the guard ring portion. The semiconductor device according to any one of claims 11 to 14, wherein the portion of the fourth interval located within a predetermined range from the boundary between the connecting portion and the guard ring portion is the portion located within a predetermined range from the boundary of the mesa portion.

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