CMOS-compatible graphene structure, interconnect, and method for manufacturing the same

Abstract

This invention provides a method for forming MLG (multilayer graphene) device layer structures at CMOS (complementary metal-oxide-semiconductor) compatible process temperatures. [Solution] The MLG (multilayer graphene) device layer structure is connected using vias 58. This structure includes an M1 MLG interconnect device layer on top of dielectric layers 44, 46. The interlayer dielectric insulates the M1 MLG interconnect device layer. The M2 MLG interconnect device layer is on top of the interlayer dielectric. Metal vias penetrate the M2 MLG interconnect device layer, the interlayer dielectric, and the M1 MLG interconnect device layer, making edge contact across the thickness of both the M1 MLG layer 40 and the M2 MLG layer 42. Carbon is diffused from a solid-phase graphene precursor through a catalyst layer, and MLG is deposited on a dielectric or metal layer by applying mechanical pressure at the diffusion temperature to form the MLG layer.

Description

Technical Field

[0001] (Statement of Government Interests) This invention was made with government support under Contract No. W911NF-18-1-0366 awarded by the U.S. Army Research Office. The U.S. government has certain rights in this invention.

[0002] (Claims of Priority and Cross-Reference to Related Applications) This application claims priority under 35 U.S.C. Section 119 and all applicable statutes and treaties based on U.S. Provisional Application No. 63 / 123,587, filed on December 10, 2020.

[0003] (Technical Field) The field of the present invention is semiconductor devices and manufacturing methods. The present invention relates particularly to interconnects and the formation of interconnects in integrated circuits (ICs).

Background Art

[0004] Interconnects are an important component in all ICs. Interconnects are conductive paths that connect a large number of transistors in digital, analog, or radio frequency (RF) ICs, and are an important factor in determining their performance (speed), switching energy (power), and reliability (lifetime). Currently, in the semiconductor industry, copper (Cu) is adopted as the main interconnect metal in most ICs, including various microprocessors. However, when the size of Cu becomes large, its resistivity significantly increases due to the size effect (increase in grain boundary and surface scattering, and the effect of a high-resistance barrier layer that is difficult to thin), self-heating becomes large, and the capacitance (or reliability) during energization decreases. Non-Patent Document 1. Therefore, the industry has been seeking a solution to replace Cu with another type of interconnect that scales with better performance attributes than Cu.

[0005] Cobalt (Co) has recently been introduced as a potential substitute for the narrowest Cu wiring due to its higher melting point compared to Cu. As wiring dimensions approach less than 20 nm, conventional (i.e., bulk or 3D) conductors such as Cu and Co, and noble metals such as ruthenium (Ru), suffer from significant size effects, leading to a nonlinear increase in resistivity, increased RC delay and self-heating (SH), and reduced electromigration (EM) reliability, thereby limiting performance, current transfer capability, and energy efficiency.

[0006] Graphene, particularly multilayer graphene (MLG) and doped multilayer graphene (DMLG), is a promising alternative to copper due to its lower resistivity (for doped MLG) and significantly higher melting points than conventional metals, including Cu and Co. Graphene belongs to a broader family known as two-dimensional (2D) van der Waals materials. (Non-patent Literature 2) Graphene also excels as a barrier material, preventing the diffusion of Cu and other metals. Graphene can also be used as a seed layer for growing other electronic materials, including gallium nitride (GaN), enabling the fabrication of various material heterostructures, including 2D-2D or 3D-2D structures, for a wide range of micro / nanoelectronic applications. However, compatibility with back-end-of-line (BEOL) CMOS processes is essential for employing any form of graphene (including single-layer (1L), multi-layer (FLG), MLG, and DMLG) in interconnects and other BEOL structures in CMOS integrated circuits, including barrier / cap layers for Cu (or other conventional metal) interconnects (Non-Patent Literature 3), on-chip inductors (Non-Patent Literature 4), or monolithic 3D integration (Non-Patent Literature 5). Single-layer or FLG can also be used as a canvas layer for region-selective fabrication of low-contact-resistance lateral heterojunction transistors (graphene-2D-semiconductor-graphene) and other active devices. Non-Patent Literature 6. FLG can also be used to construct highly transparent electrodes for solar cells and other optical devices. Non-Patent Literature 7. Previous efforts have attempted to adapt graphene to CMOS structures, but have encountered various obstacles, as described below.

[0007] Two prior publications disclose simulations showing that graphene nanoribbons can outperform Cu interconnects through intercalation doping. The proposed doping methods are impractical for CMOS manufacturing because they rely on impractical (toxic) AsF5 doping. These publications are Non-Patent Literature 8 and Non-Patent Literature 9.

[0008] Another publication discloses doped graphene interconnects from transferred graphene grown by CVD at 900°C to 1100°C. High-temperature CVD and transfer are incompatible with state-of-the-art IC manufacturing processes. This publication is Non-Patent Literature 10.

[0009] Elsewhere, it has been proposed to form graphene nanoribbon interconnects by inducing mechanical exfoliation. Exfoliation is not suitable for large-scale manufacturing. In addition, the nanoribbons are undoped and provide low conductivity that is not comparable to current Cu interconnects. This exfoliation method is disclosed in Non-Patent Document 11.

[0010] Patent Document 1 discloses a wound graphene ribbon supported around a conductive interconnect member. The carrier is a metal. This is a hybrid structure that requires a metal component, and its conductivity is limited by the contact resistance between graphene and the metal, and therefore rarely matches that of Cu. Furthermore, the relatively low melting point of the metal component limits the current-carrying capacity of such a hybrid structure.

[0011] Patent document 2 also discloses a hybrid metal-graphene interconnect structure. This interconnect also requires a barrier layer within the trench. The barrier material is selected from the group consisting of tantalum, tantalum nitride, and graphene seed material selected from the group consisting of ruthenium, nickel, palladium, iridium, and copper. The same drawbacks described in the previous paragraph apply.

[0012] Patent Document 3 discloses a graphene interconnect requiring a substrate catalyst film and an interconnect trench. The disclosed manufacturing method includes a high-temperature (>800°C) graphene growth process that is incompatible with CMOS BEOL processes.

[0013] Patent Document 4 discloses a graphene connector in a trench lined with a Ru or Ta liner, using a filler metal that is an elemental form or alloy containing one or more of copper, aluminum, silver, gold, calcium, platinum, tin, lithium, zinc, nickel, and tungsten. The graphene formation process is low-temperature CVD, which is known to produce poor-quality graphene.

[0014] Patent Document 5 discloses a hybrid metal / graphene interconnect. Graphene is formed on a metal such as copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), or palladium (Pd). High temperatures (incompatible with CMOS BEOL) are required to grow graphene on a metal surface.

[0015] Patent document 6 also discloses a hybrid metal-graphene interconnect structure. The hybrid structure includes an interfacial bonding layer between a nonmetallic material layer and a graphene layer, or between a metal layer and a graphene layer. The disclosed process is a high-temperature graphene growth process (>700°C) and is limited to only a few memory device applications. The same drawbacks described above apply to the hybrid approach.

[0016] Patent Document 7 discloses a method for manufacturing a graphene film. In this method, a catalytic metal film is formed on a substrate. The graphene film is formed on the catalytic metal film. The catalytic metal film is removed via an oxidizing agent. Subsequently, the graphene film is transferred to the substrate. Such a transfer process is incompatible with CMOS manufacturing and can increase the defect density of the film, thereby increasing the overall manufacturing cost.

[0017] Non-patent document 12 describes a method for forming an MLG graphene interconnect in a single device layer. This method involves diffusing carbon from graphite powder through a nickel catalyst layer. This paper does not disclose any techniques for forming multiple device layers or for connecting MLGs to each other in different device layers. Because it uses graphite powder, it is difficult to integrate the process into commercial CMOS manufacturing plants where extremely small particle counts are critical requirements. Furthermore, it is difficult to bring the powder into fully automated equipment.

[0018] Figure 1 shows a conventional dual damascene (DD) process for forming a metal (wiring)-via-metal (wiring) structure. This process has been scaled down to wiring widths of less than 20 nm. This structure suffers from the aforementioned "size effect," resulting in increased self-heating (SH), reduced reliability of electromigration (EM), and thereby limited interconnect current capacity. Figures 3A and 3B show that in the case of via wiring where the bottom contacts the M1 layer and the top contacts the M2 layer, current concentration and the SH effect occur, mainly due to current redistribution by edge contact resistance between the via and the metal wiring. Furthermore, voids occur when filling high-scale trenches and via holes with metal during the DD process, exacerbating reliability and variability issues. It should be noted that MLG wiring cannot follow the flow of the DD process. As will be discussed in subsequent sections, MLG wiring requires the use of a subtractive etching (SE) process scheme.

[0019] Representative papers that have attempted to use graphene ([1] to [3]) and other materials ([4] to [6]) for monolayer interconnects include the following: [1] Non-Patent Document 13, [2] Non-Patent Document 14, [3] Non-Patent Document 15, [4] Non-Patent Document 16, [5] Non-Patent Document 17, [6] Non-Patent Document 18. Although these processes ([4] to [6]) have made limited improvements in reducing resistivity and improving current-carrying capacity, a practical process for fabricating multilayer MLG connected by vias that is CMOS-compatible is still needed.

[0020] One publication discusses multi-level MLG with carbon nanotube (CNT) vias. [8] Non-Patent Document 19. In this structure, a very high temperature that is not compatible with CMOS is required for the entire process to create carbon nanotube vias.

Prior Art Documents

Patent Documents

[0021]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Non-Patent Documents

[0022]

Non-Patent Document 1

Outdoor Tool2

Outdoor Tools3

Outdoor Tools 4

Direct Environment 5

Outdoor Configuration 6

Direct Environment 7

Outdoor Tools 8

Outdoor Tools9

[0023] A preferred embodiment provides a multilayer graphene (MLG) device layer structure connected using vias. This structure includes an M1 MLG interconnect device layer on top of a dielectric layer. An interlayer dielectric isolates the M1 MLG interconnect device layer. The M2 MLG interconnect device layer lies on top of the interlayer dielectric. Metal vias penetrate the M2 MLG interconnect device layer, the interlayer dielectric, and the M1 MLG interconnect device layer, making edge contact across the thickness of both the M1 and M2 MLG layers. This method involves diffusing carbon from a solid-phase graphene precursor through a catalyst layer and applying mechanical pressure at the diffusion temperature to grow MLG directly onto a dielectric or metal layer, forming multiple MLG layers. [Brief explanation of the drawing]

[0024] [Figure 1] Figure 1 (Prior Art) illustrates the dual damascene (DD) method for conventional metal wiring as vias. [Figure 2A] Figure 2A shows a preferred method for forming MLG-metal wiring via-MLG structures in CMOS circuit fabrication using a subtractive etching process scheme. [Figure 2B]Figure 2B shows a preferred method for forming MLG-metal wiring via-MLG structures in CMOS circuit fabrication using a subtractive etching process scheme. [Figure 2C] Figure 2C shows a preferred method for forming MLG-metal wiring via-MLG structures in CMOS circuit fabrication using a subtractive etching process scheme. [Figure 3] Figures 3A and 3B (prior art) show the via layout and current density profile for an M1-via-M2 cross section manufactured by a conventional dual damascene (DD) method. Figures 3C and 3D (prior art) show the via layout and current density profile for an MLG-via-MLG cross section manufactured by a preferred subtractive etching (SE) process. [Figure 4] Figures 4A and 4B illustrate this method for growing MLG directly on a metal substrate (such as Cu). [Modes for carrying out the invention]

[0025] The present invention provides multilayer graphene (MLG) and doped multilayer graphene (DMG) structures, interconnects, and methods for forming MLG and DMG structure interconnects. In a preferred embodiment, the MLG is directly grown in a practical multilayer configuration on a dielectric (SiO2) substrate at a CMOS-compatible temperature (e.g., 350°C) by a pressure-assisted solid-phase precursor synthesis method, connected using metal vias, and edge contact between the MLG and wiring vias is achieved in a process that satisfies all IC processing thermal budget requirements.

[0026] This invention provides a method for joining two MLGs in an "edge contact" configuration, which is the most preferred method for connecting two MLGs to minimize interfacial contact resistance and, consequently, overall via resistance. This enables faster signal propagation and clock distribution within the chip, and a significant reduction in resistive losses (IR-drop) during on-chip power distribution.

[0027] In the preferred manufacturing method, there is no diffusion of carbon through any metal or dielectric, and unlike Cu wiring that must be completely encapsulated by a high-resistance, heat-resistant metal, which increases process complexity, cost, and the effective resistivity of the Cu wiring, neither the wiring (MLG or doped MLG) nor the metal vias require any diffusion barrier layer.

[0028] The preferred growth technique is currently around 10mm. 2 It exhibits a uniform, wide coverage area and can be easily scaled up to 8-inch or 12-inch wafers / substrates. This indicates that this process method has great potential for direct integration into current CMOS processes.

[0029] A preferred method can also be used to grow MLG directly on a metal substrate such as Cu (as demonstrated after several modifications), which can be employed to explore the potential benefits of using MLG as a barrier / capping layer against Cu (and other metals), eliminating the need for high-temperature metals that increase the effective resistivity of Cu interconnects, along with cost and process complexity.

[0030] A preferred multilevel MLG interconnect having a metal via structure exhibits a conductivity decrease of less than 2% over 1000 hours at room temperature without encapsulation or a barrier layer, and 200 MA / cm² above 100°C. 2 Under current density stress (approximately 50 times greater than the value that nanoscale Cu can safely withstand), it exhibits negligible electromigration (EM) (a typical reliability problem for interconnects). This makes this via method the most reliable process for transistor contacts among all currently available materials and process methods.

[0031] The significantly high current-carrying capacity of the preferred multi-level MLG interconnect structure allows for a substantial reduction in MLG thickness compared to conventional dual damascene process methods, leading to lower wiring volume, significantly improving IC speed, greatly reducing noise coupling, and significantly reducing switching energy or power consumption. This potential for power reduction by MLG interconnects is particularly important, as up to two-thirds of power consumption in modern microprocessors is attributable to interconnect capacity. The preferred interconnect structure of the present invention can result in faster, smaller, lighter, more flexible, more reliable, more energy-efficient, and more cost-effective ICs.

[0032] In a preferred method, the MLG is directly grown in a multilayer configuration on a dielectric (SiO2) substrate at 350°C by pressure-assisted solid-phase diffusion, and connected using metal vias, while meeting the thermal history requirements of all IC processes.

[0033] A preferred method is to join the MLGs in an "edge contact" configuration, which is the most preferred method of connecting to the MLGs in order to minimize interfacial contact resistance and, consequently, overall via resistance. This leads to faster signal propagation and clock distribution within the chip, as well as a significant reduction in resistive losses (IR-drop) during on-chip power distribution.

[0034] A preferred method avoids the diffusion of carbon through any metal or dielectric, and unlike Cu wiring (MLG or doped MLG) and metal vias, which require no diffusion barrier layer and must be completely encapsulated by a high-resistance, heat-resistant metal, thus reducing process complexity, cost, and the effective resistivity of the Cu wiring.

[0035] A preferred method is approximately 10 mm 2 The uniform and large coverage area was demonstrated experimentally, and this can be easily scaled up to 8-inch or 12-inch wafers / substrates. This demonstrates that the method can be directly integrated into current state-of-the-art CMOS processes.

[0036] A preferred method (experimentally demonstrated) is to grow MLG directly on a metal substrate such as Cu. One application of this method is to use MLG as a capping layer for Cu, eliminating the need for a high-temperature metal that increases the effective resistivity of the Cu interconnect, along with cost and process complexity.

[0037] A preferred device structure for a multilevel MLG interconnect using a metal via method exhibits a conductivity reduction of less than 2% over 1000 hours at room temperature and 200 MA / cm² above 100°C, without encapsulation or a barrier layer. 2 Under current density stress (approximately 50 times greater than the value that nanoscale Cu can safely withstand), it exhibits negligible electromigration (EM) (a typical reliability problem for interconnects). Such via structures far exceed the most reliable current processes for contacting transistors among all currently available materials and process schemes.

[0038] The preferred multi-level MLG interconnect via structure offers significantly higher current capacity compared to conventional structures, thereby allowing for a substantial reduction in MLG thickness compared to conventional dual damascene processes. This results in reduced wiring volume, significantly improved IC speed, reduced noise coupling, and lower power consumption. In particular, since two-thirds of the power consumption of recent microprocessors is due to wiring capacitance, this multi-level MLG interconnect via structure can reduce power consumption.

[0039] In preferred embodiments, different solid-phase graphene precursors are used. One solid-phase precursor is graphite powder. Another solid-phase precursor is graphite slurry. An additional solid-phase graphite precursor is an amorphous carbon (α-carbon) layer. The method employing a deposited α-carbon layer can offer significant advantages compared to graphite powder and graphite slurry for high-volume CMOS manufacturing.

[0040] In the experiment, MLG was deposited on SiO2, a preferred and widely used dielectric. However, the present invention's method for forming MLG allows MLG to be formed on any dielectric that can withstand the thermal requirements of the process (approximately 350-400°C).

[0041] Next, preferred embodiments of the present invention will be described with reference to experiments and drawings. In view of the general knowledge in the art and the description of the experiments described below, broader aspects of the present invention will be understood by those skilled in the art.

[0042] Figures 2A and 2B show a preferred method for growing graphene directly on a dielectric at CMOS processing temperatures, and Figure 2C shows a preferred method for forming an MLG-via-MLG structure having edge contacts between metal vias and two connected MLG layers. The processes in Figures 2A and 2B can reliably grow large-area, uniform, and high-quality MLG in multiple layers, while the processes in Figures 2C and 2D connect multiple layers with metal vias at edge contacts. The uniform MLG can be patterned into an interconnect pattern by conventional mask etching techniques. For example, in one experiment, the MLG layer was patterned by oxygen ICP etching using a metal mask and then removed by wet etching.

[0043] In Figure 2A, the first step 20 involves cleaning the silicon dioxide layer on the silicon substrate. For example, 200 nm thick SiO2 acts as an interlayer dielectric in the resulting MLG-via-MLG structure. In step 22, a metal or alloy catalyst is deposited, for example, nickel. Other metals and alloys such as Co, Fe, Cu, and Co-Ni alloys can also be used for graphene growth. However, the resulting graphene thickness, quality, and coverage area are important factors in the selection of the metal catalyst. Ni is the most likely and preferred choice. In one experiment, approximately 3 × 10⁻⁶ layers were obtained. -6Ni to a thickness of 100 nm was deposited by electron beam deposition under Torr chamber pressure. Thicknesses in the range of approximately 50 nm to 200 nm can also be applied. Generally, a thicker metal catalyst reduces the thickness of the resulting MLG layer, while a thinner metal catalyst increases the thickness of the resulting MLG layer (for the same growth time) because carbon atoms need to diffuse through the metal catalyst grains and grain boundaries and nucleate at the Ni / SiO2 interface. Low-temperature annealing below 450°C, for example, annealing at approximately 350°C for 2 hours in an H2 / Ar environment, improves the quality of the deposited metal catalyst (Ni). Annealing can be performed in vacuum, Ar, H2, N2, O2, or a forming gas, but the H2 / Ar combination is preferred because the presence of H2 with inert Ar as a background significantly improves the quality of the metal (by increasing the grain size of the metal). Performing annealing immediately before the actual growth step significantly improves coverage and growth quality. Annealing is preferably performed at the same temperature used in other steps, not only to reduce the overall process complexity but also to meet the thermal history requirements of CMOS BEOL. In the next step 24, a solid-phase graphene precursor is deposited, with three options as shown in Figure 2A: specifically, an amorphous carbon option, a graphene slurry option, and a graphene powder option. The powder can be sprinkled uniformly across the wafer to a thickness of about 100 μm. Amorphous carbon (thickness about 10-15 nm) was experimentally deposited using electron beam deposition, the same technique as for depositing Ni metal catalysts. Generally, the relationship between the thickness of the amorphous carbon precursor and the thickness of the resulting MLG thin film is a function of the supersaturated concentration of carbon in the selected catalyst. A ratio of 1:1 between the thickness of the amorphous carbon thin film and the thickness of the resulting MLG is a reasonable guideline. The slurry is a solution of organic solvent containing graphite powder, which can be spread uniformly on the wafer and heated to volatilize the organic solvent. The resulting thin film has a thickness of about 10-20 nm.

[0044] The process continues from step 26 in Figure 2B, where the formed graphene precursor is subjected to sufficient pressure and temperature to diffuse carbon through the Ni catalyst and form a graphene layer on SiO2. As an example, approximately 20 nm multilayer graphene (MLG) is formed by applying a mechanical pressure of approximately 65-80 psi at a temperature of at least approximately 350°C for approximately 60 minutes. The mechanical pressure can be further increased to optimize graphene growth. The minimum temperature for diffusion can be lowered to approximately 200°C. The maximum temperature for achieving diffusion can be raised to approximately 1000°C. However, for CMOS compatibility, the maximum temperature is required to be below 500°C. Subsequently, excess graphene precursor is removed by oxygen washing in step 28, and the metal catalyst is removed by etching in step 30, leaving a high-quality graphene layer on SiO2. In step 32, subtractive etching is performed to pattern the MLG interconnect.

[0045] The process in Figure 2C can be used to manufacture the lower MLG layer 40 and the upper 42 MLG layer (which can be called M1 and M2), and the lower MLG layer 40 and the upper 42 MLG layer can also be patterned by conventional mask etching techniques. The M1 and M2 layers 40 and 42 are formed directly on dielectric layers, for example, SiO2 layers 44 and 46, according to the process in Figures 2A and 2B. Plasma chemical vapor deposition (PECVD) was used in experiments to deposit SiO2, but the dielectric can be formed by any other technique. While dielectrics with uniform coverage and thickness are typical, the method of the present invention is versatile enough to form MLG on surfaces of any shape. An additional dielectric layer 48 can form part of the interconnect pattern of the M2 MLG layer 42. In step 50, the dielectric layer 46 is formed as an interlayer dielectric layer and prepared as in Figures 2A and 2B for the formation of the upper MLG M2 layer 42, after which the additional dielectric 48 is formed. In step 52, the hole 54 is opened through the layers up to the dielectric layer 44. In step 56, metal is deposited in the hole 54 to form a via 58, which advantageously forms edge contacts through the entire thickness of the lower 40 and upper 42 MLG M1 and M2 layers, respectively.

[0046] Various metals can be used for via 58. Density functional theory (DFT) simulations performed between Co, Ru, and W revealed that they have nearly identical edge contact resistances for MLG. However, Co has a higher activation energy and lower resistivity compared to Ru and W, resulting in higher resistance to electromigration (EM) and self-heating (SH), making it a more suitable and preferred metal for via 58 in multi-level MLG wiring via structures.

[0047] This edge contact avoids current concentration at the top and bottom contacts (Figures 3A and 3B), as shown in Figures 3C and 3D. This edge contact structure, as shown in Figures 3B and 3D, exhibits a significant reduction in current concentration and SH effects compared to conventional DD processes, primarily due to current redistribution caused by the edge contact resistance between the via and the MLG wiring. MLG provides higher conductivity and EM resistance compared to SE-Co and SE-Ru, especially at smaller aspect ratios. Therefore, although the overall via resistance increases with the addition of edge contact resistance between the MLG and the metal via, experiments have shown that the FO4 delay remains constant with respect to the overall via resistance.

[0048] The quality and via performance of the MLG layer were experimentally tested. Sharp G and 2D peaks were observed in the single-point Raman spectrum data. Uniform, high-quality growth was confirmed by TEM imaging. The upper MLG M2 42, fabricated on the underlying interlayer dielectric (ILD) 46, showed comparable quality and thickness to the lower MLG 40, as evidenced by the experimentally observed single-point Raman spectrum and uniform large-area Raman map. XPS measurement of the C1s content in the lower MLG film revealed the precise peak position (1202.3 eV) and atomic composition (approximately 83%) corresponding to the C=C sp2 bond observed in conventional CVD-grown MLG, confirming the high-quality growth of solid-phase MLG without requiring the high CMOS non-compatible temperatures exceeding 800°C of CVD-grown MLG.

[0049] Experimental fabrications consistent with Figures 2A–2C demonstrated a two-layer SE (subtractive etching)-MLG interconnect structure using Co vias, where via holes are etched through wiring and ILD using a single damascene process. The experimental structure had 20 nm thick MLG for both layers. Unintentionally, the use of an FeCl3 solution to remove the Ni catalyst in step 30 resulted in surface doping with Fe present on the surfaces of both the upper and lower MLG, which can reduce the resistivity of the MLG. Via resistance measurements estimated a minimum contact resistance of 137 Ω·μm at the 20 nm thick Co-MLG edge contact. This value supports the claim of partial surface doping of MLG by FeCl3, as it falls between the theoretically estimated (by DFT) edge contact resistance values ​​of Co-doped and undoped MLG. Constant current stress tests showed that the resistance increase due to vias was less than 2% over a period of more than 40 hours, indicating that the empirical emission (EM) in Co vias and / or Co-MLG contacts was negligible.

[0050] Figures 4A-4B show a preferred method for directly forming MLG on a Cu layer. In step 60, a laminate is formed consisting of SiO2 on a silicon substrate, followed by a Cu layer, a thin amorphous carbon barrier layer, a nickel catalyst layer, and a solid-phase graphene precursor which may be graphite powder, amorphous carbon, or graphite slurry as shown in Figure 2A. The thin amorphous carbon layer supports the graphene growth process by preventing interdiffusion between the Cu and Ni layers and acting as an additional source of readily available carbon at the Cu interface, which is completely consumed during MLG growth. When mechanical pressure is applied in step 64, as in the method of step 26 in Figure 2B, carbon diffuses through the Ni catalyst, forming a graphene layer on Cu. After the formation of the graphene layer, cleaning of any remaining graphite or α-carbon on the nickel and nickel etching are performed, as in steps 28 and 30 in Figure 2B. Cleaning is performed using O2 plasma to remove any graphite formation on the Ni substrate. Nickel etching involved removing the Ni catalyst metal layer by wet etching with an FeCl3 solution, but other material removal processes, including dry etching, can be used. Subsequently, the MLG layer is etched using a subtractive process, such as a process using oxygen plasma, to form the MLG interconnect. The MLG can be doped using various methods to adjust its conductivity.

[0051] Experiments were also conducted to verify the methods shown in Figures 4A and 4B. In the experiments, a 300 nm SiO2 layer was formed on a Si wafer, and then 100 nm Cu, 2 nm amorphous carbon, and 100 nm Ni layers were deposited on top of it by E-beam deposition. Next, a graphite precursor, such as 100 μm graphite powder, was uniformly applied to the entire resulting laminate. Raman spectroscopy confirmed the formation of high-quality MLG directly grown on Cu at approximately 350°C, and the layered structure, which could be confirmed by TEM imaging, was also verified. As described above, patterned interconnect MLG layers that make edge contact with metal vias were also formed in additional experiments. In the experimental example, the lower MLG was grown as shown in Figures 2A and 2B, then patterned by oxygen ICP etching using a metal mask, and subsequently removed by wet etching. After defining contacts and pads (15 nm Ni / 150 nm Au) for connecting the lower MLG, a 200 nm thick SiO2 ILD was deposited. The upper MLG is patterned to form an overlapping region with the lower MLG, and then the contacts and pads of the upper MLG are patterned. Via holes (200 nm to 2 μm wide) are opened in three steps using oxygen-, CHF3-, and oxygen-ICP to etch the upper MLG, ILD, and lower MLG, respectively, with a photoresist mask. To fill the via holes, a layer of Co approximately 220 nm thick is deposited by thermal evaporation (<100°C) at a slow deposition rate to ensure complete metal filling. Finally, the ILD on top of the bottom pad is etched to enable electrical contact. The wiring / via width is known in the art and can be further enlarged using more advanced lithography techniques.

[0052] While specific embodiments of the present invention have been shown and described, it should be understood that other modifications, substitutions, and alternatives will be obvious to those skilled in the art. Such modifications, substitutions, and alternatives can be made without departing from the spirit and scope of the invention, which should be determined from the appended claims.

[0053] Various features of the present invention are described in the appended claims.

[0054] [Note] [Note 1] A method for directly forming MLG (multilayer graphene) device layers connected using vias on a dielectric or metal layer at a CMOS (complementary metal-oxide-semiconductor) compatible process temperature, A step of providing a dielectric layer or a metal layer, A step of depositing a metal or alloy catalyst layer on the dielectric layer or metal layer, The process involves depositing a solid-phase graphene precursor onto the catalyst layer, A step of diffusing carbon from the graphene precursor through the catalyst layer, wherein MLG is deposited on the dielectric layer or metal layer by applying a diffusion pressure at the diffusion temperature to form an M1 MLG layer, A step of removing the catalyst layer, The process involves depositing an interlayer dielectric on the aforementioned M1 MLG layer, A step of forming an M2 MLG layer on the interlayer dielectric through the steps of depositing the catalyst layer, depositing the solid-phase graphene precursor layer, and diffusing the carbon, A step of forming a via hole by making an opening that penetrates through the entirety of the M2 MLG layer, the interlayer dielectric, and the M1 MLG layer, A step of depositing via metal in the via hole to form edge contacts over the thickness of the M1 MLG layer and the M2 MLG layer, Methods that include...

[0055] [Note 2] The diffusion pressure is approximately 65-80 psi, and the diffusion temperature is at least approximately 200°C. The method described in Appendix 1, characterized by the features described herein.

[0056] [Note 3] The graphene precursor is graphite powder. The method according to Appendix 1 or 2, characterized by the features described herein.

[0057] [Note 4] The graphene precursor is amorphous carbon. The method according to Appendix 1 or 2, characterized by the features described herein.

[0058] [Note 5] The graphene precursor is a graphite slurry. The method according to Appendix 1 or 2, characterized by the features described herein.

[0059] [Note 6] The process includes annealing the catalyst at a temperature of less than 500°C before depositing the solid-phase graphene precursor. A method according to any one of the appendices 1 to 5, characterized by the following:

[0060] [Note 7] The via metal is one of Co, Ru, and W. A method according to any one of the appendices 1 to 6, characterized by the following:

[0061] [Note 8] The via metal is Co. The method described in Appendix 7, characterized by the following:

[0062] [Note 9] The catalyst layer is made of Ni. A method according to any one of the appendices 1 to 8, characterized by the following:

[0063] [Note 10] The dielectric layer and the interlayer dielectric contain SiO2. A method according to any one of the appendices 1 to 9, characterized by the following:

[0064] [Note 11] A method for forming MLG (multilayer graphene) on a metal surface, The steps include forming an amorphous carbon barrier layer on the metal surface, A step of depositing a metal catalyst layer or an alloy catalyst layer on the amorphous carbon barrier layer, A step of depositing a solid-phase graphene precursor on the catalyst layer, A step of depositing MLG on the metal surface by diffusing carbon from the graphene precursor through the catalyst layer and applying diffusion pressure at the diffusion temperature, A method that includes this.

[0065] [Note 12] The aforementioned metal surface is made of copper. The method described in Appendix 9, characterized by the features described therein.

[0066] [Note 13] The catalyst layer is made of nickel. The method according to Appendix 9 or 10, characterized by the features described herein.

[0067] [Note 14] Pattern and dope M1 MLG, and pattern and dope M2 MLG layer. The method described in Appendix 1, characterized by the features described herein.

[0068] [Note 15] A multilayer graphene (MLG) device layer structure connected using vias, The M1 MLG interconnect device layer on the dielectric layer, The interlayer dielectric that isolates the M1 MLG interconnect device layer, The M2 MLG interconnect device layer on the interlayer dielectric, A metal via passing through the M2 MLG interconnect device layer, the interlayer dielectric, and the M1 MLG interconnect device layer, wherein the metal via forms an edge contact across the thickness of both the M1 MLG layer and the M2 MLG layer. MLG device layer structure comprising

[0069] [Note 16] The M1 MLG layer and the M2 MLG layer are patterned. The device layer structure described in Appendix 15, characterized by the features described herein.

[0070] [Note 17] The dielectric layer and the interlayer dielectric contain SiO2. The device layer structure according to appendix 15 or 16, characterized by the above.

[0071] [Note 18] The M1 MLG layer and the M2 MLG layer are doped. A device layer structure according to any one of appendices 15 to 17, characterized by the above.

Claims

[Claim 1] A method for directly forming MLG (multilayer graphene) device layers connected using vias on a dielectric or metal layer at a CMOS (complementary metal-oxide-semiconductor) compatible process temperature, A step of providing a dielectric layer or a metal layer, A step of depositing a metal or alloy catalyst layer on the dielectric layer or metal layer, The process involves depositing a solid-phase graphene precursor onto the catalyst layer, A step of diffusing carbon from the graphene precursor through the catalyst layer, wherein MLG is deposited on the dielectric layer or metal layer by applying diffusion pressure at the diffusion temperature, thereby forming an M1 MLG layer. A step of removing the catalyst layer, The process involves depositing an interlayer dielectric on the M1 MLG layer, A step of forming an M2 MLG layer on the interlayer dielectric through the steps of depositing the catalyst layer, depositing the solid-phase graphene precursor layer, and diffusing the carbon, A step of forming a via hole by making an opening that penetrates through the M2 MLG layer, the interlayer dielectric, and the M1 MLG layer, A step of depositing via metal in the via hole to form edge contacts over the thickness of the M1 MLG layer and the M2 MLG layer, Methods that include...

Images