Semiconductor device and method for manufacturing a semiconductor device

Abstract

The objective is to provide a technology that can improve the insulation between the upper electrode and the lower electrode. [Solution] The semiconductor device comprises a semiconductor substrate and a first trench structure. The first trench structure includes a lower electrode provided on the lower part of a trench provided on the first main surface of the semiconductor substrate via a first insulating film, and an upper electrode provided on the upper part of the trench via a third insulating film, insulated from the lower electrode by a second insulating film. The proportion of crystal orientations with (111) plane orientations is higher for the lower electrode than for the upper electrode.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] In recent years, in order to reduce switching losses, semiconductor devices having upper and lower electrodes insulated from each other in a trench have been proposed (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a semiconductor device as described above, small protrusions may occur on the upper surface of the lower electrode. In such a case, the portion of the insulating film between the upper electrode and the lower electrode that contacts the protrusion becomes thin, so there is a possibility that the insulation between the upper electrode and the lower electrode deteriorates.

[0005] [[ID=3८]] Therefore, the present disclosure has been made in view of the above problems, and an object thereof is to provide a technology capable of enhancing the insulation between an upper electrode and a lower electrode.

Means for Solving the Problems

[0006] The semiconductor device according to this disclosure comprises a semiconductor substrate having a first main surface and a first trench structure provided on the side of the first main surface of the semiconductor substrate, wherein the first trench structure includes a lower electrode provided on the lower part of the trench provided on the first main surface of the semiconductor substrate via a first insulating film and an upper electrode insulated from the lower electrode by a second insulating film and provided on the upper part of the trench via a third insulating film, wherein the upper electrode is electrically connected to a first gate electrode and the ratio of crystal orientations being (111) plane orientations is higher for the lower electrode than for the upper electrode. [Effects of the Invention]

[0007] According to this disclosure, the proportion of the crystal orientation being (111) plane orientation is higher in the lower electrode than in the upper electrode. With such a configuration, the insulation between the upper electrode and the lower electrode can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 3] (a) to (c) are cross-sectional views showing a method for manufacturing a semiconductor device according to this embodiment 1. [Figure 4] This is a cross-sectional view showing the configuration of a semiconductor device according to modified example 3. [Figure 5] This is a cross-sectional view showing the configuration of a semiconductor device according to modified example 3. [Figure 6] This is a cross-sectional view showing the configuration of a semiconductor device according to modified example 4. [Figure 7] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 2. [Figure 8] This is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 3. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the attached drawings. The features described in each embodiment below are illustrative, and not all features are necessarily required. In addition, in the following description, the same or similar reference numerals are used for similar components in multiple embodiments, and the different components will be described primarily. Also, in the following description, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily coincide with the positions and directions in actual implementation. Furthermore, a higher concentration in one part than in another part may mean, for example, that the average concentration of one part is higher than the average concentration of the other part. Conversely, a lower concentration in one part than in another part may mean, for example, that the average concentration of one part is lower than the average concentration of the other part. Furthermore, although the following description assumes that the first conductivity type is n-type and the second conductivity type is p-type, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0010] <Embodiment 1> Figures 1 and 2 are cross-sectional views showing the configuration of a semiconductor device according to this first embodiment. In the following description, a configuration in which the semiconductor device is an IGBT (Insulated Gate Bipolar Transistor) will be used as an example, but it is not limited to this. The semiconductor device may be, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or an RC-IGBT (Reverse Conducting IGBT) having an IGBT region where an IGBT is provided and a diode region where an SBD (Schottky Barrier Diode) and a PND (PN junction diode) are provided.

[0011] The semiconductor device shown in Figure 1 comprises a semiconductor substrate, a first trench structure 11, an interlayer insulating film 21, an emitter electrode 22, and a collector electrode 23.

[0012] The semiconductor substrate is n - A drift layer 1 of type n, a carrier storage layer 2 of type n, a base layer 3 of type p, and n+ It includes a source layer 4 of the p type, a buffer layer 5 of the n type, and a collector layer 6 of the p type. The semiconductor substrate has a first main surface corresponding to the upper end of the source layer 4 and a second main surface corresponding to the lower end of the collector layer 6.

[0013] Note that the semiconductor substrate may be composed of a normal semiconductor wafer or an epitaxial growth layer. Also, the semiconductor substrate may be composed of normal silicon (Si), or may be composed of a wide-bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), or diamond. When the semiconductor substrate is composed of a wide-bandgap semiconductor, stable operation of the semiconductor device under high temperature and high voltage, and high-speed switching of the semiconductor device can be achieved.

[0014] Next, each layer of the semiconductor substrate will be described. On the first main surface side of the drift layer 1, a carrier accumulation layer 2 having a higher n-type impurity concentration than the drift layer 1 is provided. On the first main surface side of the carrier accumulation layer 2, a base layer 3 is provided. On the first main surface side of the base layer 3, a source layer 4 having a higher n-type impurity concentration than the carrier accumulation layer 2 is provided.

[0015] Thus, in the semiconductor substrate according to Embodiment 1, the drift layer 1, the carrier accumulation layer 2, the base layer 3, and the source layer 4 are provided in this order toward the first main surface. On the other hand, in the semiconductor substrate, the drift layer 1, the buffer layer 5, and the collector layer 6 are provided in this order toward the second main surface. Each layer of the semiconductor substrate is selectively formed, for example, by mask formation and ion implantation.

[0016] The first trench structure 11 includes a lower insulating film 12 which is a first insulating film, a lower electrode 13, a boundary insulating film 14 which is a second insulating film, an upper insulating film 15 which is a third insulating film, and an upper electrode 16, and is provided on the first main surface side of the semiconductor substrate.

[0017] The lower insulating film 12 is provided at the bottom of a trench 17 that penetrates the source layer 4, the base layer 3, and the carrier accumulation layer 2 from the first main surface of the semiconductor substrate and reaches the drift layer 1. The lower insulating film 12 is formed, for example, by thermal oxidation and CVD (Chemical Vapor Deposition).

[0018] The lower electrode 13 is provided on the bottom of the trench 17 via the lower insulating film 12. The lower electrode 13 is made of, for example, polycrystalline silicon obtained by crystallizing amorphous silicon containing impurities. As shown in FIG. 2, the lower electrode 13 is electrically connected to the emitter electrode 22.

[0019] The boundary insulating film 14 in FIG. 1 is provided on the upper part of the lower electrode 13. The boundary insulating film 14 includes an oxide film obtained by thermally oxidizing the upper part of the lower electrode 13. The boundary insulating film 14 may have a two-layer structure including the oxide film and a CVD film provided thereon, or may have a three-layer structure including the two-layer structure and an oxide film provided thereon. In FIG. 1, the boundary insulating film 14 is a flat film, but as will be described later, it may be a film having a convex portion whose central part protrudes toward the upper electrode 16 side.

[0020] The upper insulating film 15 is provided at the upper part of the trench 17. The upper insulating film 15 is formed, for example, by thermal oxidation and CVD. The upper electrode 16 is insulated from the lower electrode 13 by the boundary insulating film 14 in the trench 17 and is provided on the upper part of the trench ^{\prime}17 via the upper insulating film 15. The position of the lower end of the upper electrode 16 is located below the position of the lower end of the base layer 3. The upper electrode 16 is made of, for example, doped polysilicon containing impurities. As shown in FIG. 2, the upper electrode 16 is electrically connected to the first gate electrode 26. Although not shown, the first gate electrode 26 is provided on the semiconductor substrate in the same manner as the emitter electrode 22 and corresponds to a first gate pad to which a first gate potential is applied from the outside.

[0021] In this embodiment 1, the proportion of crystals oriented in the (111) plane is higher in the lower electrode 13 than in the upper electrode 16, and the average crystal grain size is larger in the lower electrode 13 than in the upper electrode 16. However, it is not essential that the average crystal grain size is larger in the lower electrode 13 than in the upper electrode 16.

[0022] The interlayer insulating film 21 in Figure 1 is provided on the upper electrode 16. The emitter electrode 22 is provided so as to cover the source layer 4 and the interlayer insulating film 21, and is electrically connected to the source layer 4 in cross-sections other than those shown in Figure 1, and is insulated from the upper electrode 16 by the interlayer insulating film 21. The collector electrode 23 is provided so as to cover the collector layer 6 and is electrically connected to the collector layer 6.

[0023] <Manufacturing method> Figures 3(a), 3(b), and 3(c) are cross-sectional views showing a method for manufacturing a semiconductor device according to this first embodiment. Here, we will mainly describe the manufacturing method for the first trench structure 11.

[0024] First, a semiconductor substrate is prepared, which has layers such as the drift layer 1 and the carrier storage layer 2, as well as trenches 17. Such a semiconductor substrate is formed, for example, by mask formation and ion implantation to selectively form each layer, and etching to form the trenches 17.

[0025] As shown in Figure 3(a), a lower insulating film 12 is formed in the lower part of the trench 17 by, for example, thermal oxidation and CVD, and then a conductive member 19 is formed on the lower part of the trench 17 via the lower insulating film 12 by, for example, CVD. The conductive member 19 is made of, for example, amorphous silicon containing impurities.

[0026] Next, as shown in Figure 3(b), the upper part of the conductive member 19 is thermally oxidized to form a boundary insulating film 14 from the upper part of the conductive member 19, and the lower electrode 13 is formed from the remaining part of the conductive member 19 depending on the temperature of the thermal oxidation. In the example of Figure 3(b), the boundary insulating film 14 formed by thermal oxidation of the upper part of the conductive member 19 has a convex portion that protrudes upward in the center, but this is not essential.

[0027] In the example shown in Figure 3(b), the upper insulating film 15 is formed by thermal oxidation of the upper part of the trench 17 when the boundary insulating film 14 is formed by thermal oxidation. However, this is not the only method; the upper insulating film 15 may also be formed by thermal oxidation of the upper part of the trench 17 or by performing CVD on the upper part of the trench 17 after the boundary insulating film 14 has been formed by thermal oxidation.

[0028] Then, as shown in Figure 3(c), an upper electrode 16, which is insulated from the lower electrode 13 by a boundary insulating film 14, is formed on the upper part of the trench 17 via an upper insulating film 15, for example by CVD. The upper electrode 16 is made of, for example, doped polysilicon containing impurities. After that, an interlayer insulating film 21 and the like are formed, and the semiconductor device according to this embodiment 1 is completed.

[0029] <Summary of Embodiment 1> Typically, the oxide film formation rate when silicon crystal orientation is (111) plane orientation is greater than the oxide film formation rate when silicon crystal orientation is (100) plane orientation.

[0030] In this embodiment 1, the proportion of crystal orientations with a (111) plane orientation is higher in the lower electrode 13 than in the upper electrode 16. With this configuration, the formation rate of the boundary insulating film 14 can be increased compared to a configuration where the above ratio in the lower electrode 13 is less than or equal to the above ratio in the upper electrode 16, thus allowing the boundary insulating film 14 to be made thicker. As a result, the insulation between the upper electrode 16 and the lower electrode 13 can be improved, and the gate breakdown voltage can be increased. Furthermore, by increasing the formation rate of the boundary insulating film 14, the formation time of the boundary insulating film 14 can be shortened.

[0031] Generally, it is preferable that the thickness of the upper insulating film 15, which affects the threshold voltage of the channel, be thin, but it is preferable that the thickness of the boundary insulating film 14, which affects the insulation between the upper electrode 16 and the lower electrode 13, be thick. On the other hand, when forming the boundary insulating film 14 by thermal oxidation, if the upper insulating film 15 is formed by thermal oxidation of the upper part of the trench 17, that is, if the boundary insulating film 14 and the upper insulating film 15 are formed in parallel, the manufacturing process can be simplified.

[0032] However, with conventional manufacturing methods, it was difficult to make the upper insulating film 15 thin and the boundary insulating film 14 thick. In contrast, when forming the boundary insulating film 14 and the upper insulating film 15 in parallel, applying the configuration according to Embodiment 1 described above makes it possible to form a configuration in which the upper insulating film 15 is thin and the boundary insulating film 14 is thick while simplifying the manufacturing process.

[0033] Furthermore, generally, when an electrode with a small average crystal grain size is oxidized, some crystals migrate to prevent the compressive stress of the polycrystalline silicon within the electrode from becoming too large, which can result in protrusions smaller than the convex portion shown in Figure 3(b) forming on the electrode surface. In contrast, in this embodiment 1, the average crystal grain size is larger in the lower electrode 13 than in the upper electrode 16. With this configuration, the average crystal grain size of the lower electrode 13 can be made relatively large, thus suppressing the formation of protrusions on the upper surface of the lower electrode 13 that partially thin the boundary insulating film 14. As a result, the insulation between the upper electrode 16 and the lower electrode 13 can be improved.

[0034] <Example 1> In Embodiment 1, the average particle size of the lower electrode 13 is preferably 0.5 μm or more and 4.0 μm or less, and more preferably 0.8 μm or more and 4.0 μm or less. Alternatively, the average particle size of the lower electrode 13 is preferably 1.1 times or more and 4.0 μm or less than or equal to the average particle size of the upper electrode 16. With such a configuration, the average particle size of the crystals of the lower electrode 13 can be made relatively large, so that the occurrence of protrusions that partially thin the boundary insulating film 14 on the upper part of the lower electrode 13 can be suppressed. As a result, the insulation between the upper electrode 16 and the lower electrode 13 can be improved.

[0035] <Modification 2> In Embodiment 1, the concentration of impurities may be higher in the lower electrode 13 than in the upper electrode 16. The impurities referred to here are, for example, phosphorus, but are not limited to this. With this configuration, the oxidation rate of the lower electrode 13, that is, the formation rate of the boundary insulating film 14, can be increased, so that the boundary insulating film 14 can be made thicker. As a result, the insulation between the upper electrode 16 and the lower electrode 13 can be improved.

[0036] Furthermore, in Embodiment 1, the concentration of impurities may be lower in the lower electrode 13 than in the upper electrode 16. The impurities referred to here are, as above, for example, phosphorus, but are not limited to this. With such a configuration, when a voltage is applied to the upper electrode 16, the amount of electrons trapped from the upper electrode 16 to the boundary insulating film 14 can be reduced, thereby reducing hysteresis in the gate leakage characteristics.

[0037] <Variation 3> In Embodiment 1, as shown in Figure 4, the thickness of the lower insulating film 12 in contact with the side of the lower electrode 13 may be thinner than the thickness of the upper insulating film 15 in contact with the side of the upper electrode 16. With this configuration, the area of ​​the lower electrode 13 facing the upper electrode 16 can be reduced, thereby increasing the gate breakdown voltage. Also, the volume of the lower electrode 13 may be larger than the volume of the upper electrode 16. With this configuration, the gate current path can be reduced, thereby increasing the gate breakdown voltage.

[0038] Furthermore, in Embodiment 1, as shown in Figure 5, the thickness of the lower insulating film 12 in contact with the side of the lower electrode 13 may be greater than the thickness of the upper insulating film 15 in contact with the side of the upper electrode 16. With this configuration, the area of ​​the lower electrode 13 facing the upper electrode 16 can be reduced, thereby increasing the gate breakdown voltage. Also, the volume of the lower electrode 13 may be smaller than the volume of the upper electrode 16. With this configuration, the gate current path can be reduced, thereby increasing the gate breakdown voltage.

[0039] <Modification 4> In Embodiment 1, as shown in Figure 2, the upper electrode 16 was electrically connected to the first gate electrode 26 and the lower electrode 13 was electrically connected to the emitter electrode 22, but the configuration is not limited to this. As shown in Figure 6, the upper electrode 16 may be electrically connected to the first gate electrode 26 and the lower electrode 13 may be electrically connected to the second gate electrode 27, which has a different voltage control than the first gate electrode 26.

[0040] For example, the first gate electrode 26 and the second gate electrode 27 may be voltage-controlled such that the signal of the second gate electrode 27 rises earlier than the signal of the first gate electrode 26 and falls later than the signal of the first gate electrode 26. Although not shown in the figures, the second gate electrode 27 is provided on the semiconductor substrate, similar to the emitter electrode 22, and corresponds to a second gate pad to which a second gate potential is applied from the outside. The second gate electrode 27 and the second gate pad are sometimes called the control gate electrode and the control gate pad, respectively.

[0041] With this configuration, the area where the gate potential and emitter potential are adjacent can be reduced compared to a configuration where one of the upper electrode 16 and the lower electrode 13 is electrically connected to the first gate electrode 26 and the other is electrically connected to the emitter electrode 22. Therefore, the gate breakdown voltage of the semiconductor device can be improved.

[0042] <Embodiment 2> Figure 7 is a cross-sectional view showing the configuration of a semiconductor device according to this second embodiment. As shown in Figure 7, in this second embodiment, the upper electrode 16 and the lower electrode 13 are electrically connected to the first gate electrode 26. With this configuration, the area where the gate potential and emitter potential are adjacent can be reduced compared to a configuration in which one of the upper electrode 16 and the lower electrode 13 is electrically connected to the first gate electrode 26 and the other is electrically connected to the emitter electrode 22. Therefore, the breakdown voltage of the semiconductor device can be improved.

[0043] In this embodiment 2, in addition to the first trench structure 11, a second trench structure 31 is provided on the first main surface side of the semiconductor substrate. The second trench structure 31 is a structure corresponding to the first trench structure 11, that is, a structure similar to the first trench structure 11. However, in the second trench structure 31, the upper electrode 16 is electrically connected to the emitter electrode 22, and the lower electrode 13 is electrically connected to the first gate electrode 26.

[0044] With this configuration, since the lower electrode 13 of the second trench structure 31 is electrically connected to the first gate electrode 26, the capacitance between the lower electrode 13 of the second trench structure 31 and the collector layer 6 can be changed. By changing the capacitance in this way, switching losses can be improved.

[0045] <Embodiment 3> Figure 8 is a cross-sectional view showing the configuration of a semiconductor device according to this third embodiment. As shown in Figure 8, in this third embodiment, not only the first trench structure 11 but also a dummy trench structure 41 is provided on the first main surface side of the semiconductor substrate.

[0046] The dummy trench structure 41 includes an insulating film 42 and a dummy electrode 43. A trench 44 is provided on the first main surface side of the semiconductor substrate, penetrating the source layer 4, base layer 3, and carrier storage layer 2 to reach the drift layer 1. The dummy electrode 43 is provided on the trench 44 via the insulating film 42. The dummy electrode 43 is electrically connected to electrodes other than gate electrodes, such as the first gate electrode 26 and the second gate electrode 27, for example, the emitter electrode 22, or to a floating electrode.

[0047] With this configuration, the electric field applied to the first trench structure 11 can be shared with the dummy trench structure 41, thereby improving the gate breakdown voltage of the semiconductor device. The dummy trench structure 41 described above was configured to include one stage of dummy electrodes 43, but it is not limited to this configuration. For example, the dummy trench structure 41 may be configured to include two stages of dummy electrodes, similar to the upper electrode 16 and lower electrode 13 of the first trench structure 11.

[0048] In this disclosure in English, 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more', and 'at least one' can be used interchangeably.

[0049] Furthermore, it is possible to freely combine each embodiment and each variation, and to modify or omit each embodiment and each variation as appropriate.

[0050] The various aspects of this disclosure are summarized below as an appendix.

[0051] (Note 1) A semiconductor substrate having a first main surface, A first trench structure provided on the first main surface side of the semiconductor substrate and Equipped with, The first trench structure is, A lower electrode is provided on the lower part of a trench provided on the first main surface of the semiconductor substrate via a first insulating film, The upper electrode is insulated from the lower electrode by a second insulating film and is provided on the upper part of the trench via a third insulating film. Includes, The upper electrode is electrically connected to the first gate electrode, A semiconductor device in which the ratio of crystal orientations with a (111) plane orientation is higher for the lower electrode than for the upper electrode.

[0052] (Note 2) The semiconductor device described in Appendix 1, A semiconductor device in which the average grain size of the crystals is larger in the lower electrode than in the upper electrode.

[0053] (Note 3) The semiconductor device described in Appendix 1, A semiconductor device having an average particle size of 0.5 μm or more and 4.0 μm or less for the lower electrode.

[0054] (Note 4) The semiconductor device described in Appendix 1, A semiconductor device having an average particle size of 0.8 μm or more and 4.0 μm or less for the lower electrode.

[0055] (Note 5) The semiconductor device described in Appendix 1, A semiconductor device wherein the average particle size of the lower electrode is 1.1 times or more and 4.0 μm or less than or equal to the average particle size of the upper electrode.

[0056] (Note 6) A semiconductor device described in any one of the items 1 to 5 of the appendix, A semiconductor device in which the concentration of impurities is higher in the lower electrode than in the upper electrode.

[0057] (Note 7) A semiconductor device described in any one of the items 1 to 5 of the appendix, A semiconductor device in which the concentration of impurities is lower in the lower electrode than in the upper electrode.

[0058] (Note 8) A semiconductor device described in any one of the items from Appendix 1 to Appendix 7, A semiconductor device in which the thickness of the first insulating film in contact with the side of the lower electrode is thinner than the thickness of the third insulating film in contact with the side of the upper electrode.

[0059] (Note 9) A semiconductor device described in any one of the items from Appendix 1 to Appendix 7, A semiconductor device in which the thickness of the first insulating film in contact with the side of the lower electrode is greater than the thickness of the third insulating film in contact with the side of the upper electrode.

[0060] (Note 10) A semiconductor device described in any one of the items from Appendix 1 to Appendix 9, A semiconductor device in which the volume of the lower electrode is smaller than the volume of the upper electrode.

[0061] (Note 11) A semiconductor device described in any one of the items from Appendix 1 to Appendix 9, A semiconductor device in which the volume of the lower electrode is larger than the volume of the upper electrode.

[0062] (Note 12) A semiconductor device described in any one of the items from Appendix 1 to Appendix 11, A semiconductor device in which the lower electrode is electrically connected to the first gate electrode.

[0063] (Note 13) A semiconductor device described in any one of the items from Appendix 1 to Appendix 11, A semiconductor device in which the lower electrode is electrically connected to a second gate electrode having a different voltage control from the first gate electrode.

[0064] (Note 14) A semiconductor device described in any one of the appendices 1 to 13, A semiconductor device comprising a second trench structure corresponding to the first trench structure, wherein the upper electrode is electrically connected to the emitter electrode and the lower electrode is electrically connected to the first gate electrode.

[0065] (Note 15) A semiconductor device described in any one of the appendices 1 to 14, A semiconductor device further comprising a dummy trench structure on the first main surface side of the semiconductor substrate.

[0066] (Note 16) A step of preparing a semiconductor substrate having a first main surface on which a trench is provided, The steps include forming a conductive member on the lower part of the trench via a first insulating film, The process involves thermally oxidizing the upper part of the conductive member to form a second insulating film from the upper part of the conductive member, and forming a lower electrode from the remaining part of the conductive member. The process involves forming an upper electrode, which is insulated from the lower electrode by the second insulating film, on the upper part of the trench via a third insulating film. Equipped with, The upper electrode is connected to the first gate electrode, A method for manufacturing a semiconductor device, wherein the ratio of crystal orientations being (111) plane orientations is higher for the lower electrode than for the upper electrode.

[0067] (Note 17) A method for manufacturing a semiconductor device as described in Appendix 16, A method for manufacturing a semiconductor device, comprising forming the third insulating film by thermal oxidation of the upper part of the trench when forming the second insulating film by thermal oxidation. [Explanation of Symbols]

[0068] 11 First trench structure, 12 Lower insulating film, 13 Lower electrode, 14 Boundary insulating film, 15 Upper insulating film, 16 Upper electrode, 17 Trench, 19 Conductive member, 22 Emitter electrode, 26 First gate electrode, 27 Second gate electrode, 31 Second trench structure, 41 Dummy trench structure.

Claims

1. A semiconductor substrate having a first main surface, A first trench structure provided on the first main surface side of the semiconductor substrate and Equipped with, The first trench structure is A lower electrode is provided on the lower part of a trench provided on the first main surface of the semiconductor substrate via a first insulating film, The upper electrode is insulated from the lower electrode by a second insulating film and is provided on the upper part of the trench via a third insulating film. Includes, The upper electrode is electrically connected to the first gate electrode. A semiconductor device in which the ratio of crystal orientations with a (111) plane orientation is higher for the lower electrode than for the upper electrode.

2. A semiconductor device according to claim 1, A semiconductor device in which the average grain size of the crystals is larger in the lower electrode than in the upper electrode.

3. A semiconductor device according to claim 1, A semiconductor device having an average particle size of 0.5 μm or more and 4.0 μm or less for the lower electrode.

4. A semiconductor device according to claim 1, A semiconductor device having an average particle size of 0.8 μm or more and 4.0 μm or less for the lower electrode.

5. A semiconductor device according to claim 1, A semiconductor device wherein the average particle size of the lower electrode is 1.1 times or more and 4.0 μm or less than or equal to the average particle size of the upper electrode.

6. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the concentration of impurities is higher in the lower electrode than in the upper electrode.

7. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the concentration of impurities is lower in the lower electrode than in the upper electrode.

8. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the thickness of the first insulating film in contact with the side of the lower electrode is thinner than the thickness of the third insulating film in contact with the side of the upper electrode.

9. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the thickness of the first insulating film in contact with the side of the lower electrode is greater than the thickness of the third insulating film in contact with the side of the upper electrode.

10. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the volume of the lower electrode is smaller than the volume of the upper electrode.

11. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the volume of the lower electrode is larger than the volume of the upper electrode.

12. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the lower electrode is electrically connected to the first gate electrode.

13. A semiconductor device according to any one of claims 1 to 5, A semiconductor device in which the lower electrode is electrically connected to a second gate electrode having a different voltage control from the first gate electrode.

14. A semiconductor device according to any one of claims 1 to 5, A semiconductor device comprising a second trench structure corresponding to the first trench structure, wherein the upper electrode is electrically connected to the emitter electrode and the lower electrode is electrically connected to the first gate electrode.

15. A semiconductor device according to any one of claims 1 to 5, A semiconductor device further comprising a dummy trench structure on the first main surface side of the semiconductor substrate.

16. A step of preparing a semiconductor substrate having a first main surface on which trenches are provided, The steps include forming a conductive member on the lower part of the trench via a first insulating film, The process involves thermally oxidizing the upper part of the conductive member to form a second insulating film from the upper part of the conductive member, and forming a lower electrode from the remaining part of the conductive member. The process involves forming an upper electrode, which is insulated from the lower electrode by the second insulating film, on the upper part of the trench via a third insulating film. Equipped with, The upper electrode is connected to the first gate electrode, A method for manufacturing a semiconductor device, wherein the ratio of crystal orientations being (111) plane orientations is higher for the lower electrode than for the upper electrode.

17. A method for manufacturing a semiconductor device according to claim 16, A method for manufacturing a semiconductor device, comprising forming the third insulating film by thermal oxidation of the upper part of the trench when forming the second insulating film by thermal oxidation.

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