Systems and methods for coupling between qubits

Abstract

This solves the connectivity problem between qubits. [Solution] The superconducting integrated circuit includes a first superconducting device 102 having a first superconducting loop 108 with a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device 104 having a second superconducting loop 112 with a second superconducting trace in a second layer. The first superconducting loop intersects with the second superconducting loop in an intersection region 120. At least a portion of each of the first and second superconducting traces inside the intersection region follows a detour path that is narrower than at least a portion of each of the traces outside the intersection region and inductively approaches at least a portion of the other path.

Description

[Technical Field]

[0001] background field This disclosure generally relates to improving the performance of quantum processors, and in particular to coupling between qubits in superconducting quantum processors. [Background technology]

[0002] Quantum devices Quantum devices are structures that can observe quantum mechanical effects. Quantum devices include circuits in which current transport is governed by quantum mechanical effects. Such devices include spintronics, which use electron spin as a resource, and superconducting circuits. Both spin and superconductivity are examples of quantum mechanical phenomena. Quantum devices can be used, for example, in instruments and computing systems.

[0003] quantum computing Quantum computing and quantum information processing encompass several types of marketable products. A quantum computer is a system that performs calculations on data by directly using quantum mechanical phenomena (e.g., superposition, tunneling, and quantum entanglement).

[0004] Data can be represented in a quantum computer using quantum binary numbers (also referred to as qubits in this application). Quantum computers can provide exponential speedups to certain types of computational problems (e.g., quantum physics simulations). Favorable speedups may exist for other types of problems as well.

[0005] In some implementations, quantum computers include quantum circuit models. In other implementations, quantum computers include adiabatic quantum computers. Adiabatic quantum computers can be useful, for example, for solving NP-hard optimization problems.

[0006] Adiabatic quantum computing Adiabatic quantum computing typically involves evolving a system from a known initial Hamiltonian (a Hamiltonian is an operator whose eigenvalues are the allowed energies of the system) to a final Hamiltonian by gradually changing the Hamiltonian. A simple example of adiabatic evolution is a linear interpolation between the initial and final Hamiltonians. An example is given below. H e =(1 - s)H i + sH f where i H f is the initial Hamiltonian, H e is the final Hamiltonian, H e is the evolving or instantaneous Hamiltonian, and s is an evolution coefficient that controls the rate of evolution. As the system evolves, initially (s = 0), the evolving Hamiltonian H i is equal to the initial Hamiltonian H e and finally (s = 1), the evolving Hamiltonian H f becomes equal to the final Hamiltonian H

[0007] Before the evolution begins, the system is typically initialized to the ground state of the initial Hamiltonian H i and the goal is to evolve the system in such a way that it ends up in the ground state of the final Hamiltonian H f If the evolution is too fast, the system may be excited to a higher energy state (e.g., the first excited state).

[0008] In this application, adiabatic evolution is defined as an evolution that satisfies the adiabatic condition expressed as follows.

Equation

Equation

[0009] The process of changing the Hamiltonian in adiabatic quantum computing is referred to as evolution in this application. The rate of change of the evolution coefficient s is the rate at which the Hamiltonian H evolves as the system evolves. e It is desirable that the system remains in its ground state and is slow enough to avoid transitions in anti-crossing (when the gap size is minimal). The evolution schedule may be linear, nonlinear, parametric, etc. Further details regarding adiabatic quantum computing systems, methods, and apparatus are described, for example, in U.S. Patents 7,135,701 and 7,418,283.

[0010] Quantum annealing Quantum annealing is a computational method that can be used to find the low-energy state of a system, typically and preferably the ground state of the system. Similar in concept to classical annealing, quantum annealing relies on the fundamental principle that natural systems tend to be in lower-energy states because lower-energy states are more stable. While classical annealing uses classical thermal fluctuations to guide the system to a low-energy state (ideally, the global energy minimum), quantum annealing can reach the global energy minimum more accurately and / or quickly than classical annealing by using quantum effects (e.g., quantum tunneling). In quantum annealing, thermal effects and other noise may be present to aid the annealing process. The final low-energy state may not be the global energy minimum.

[0011] Adiabatic quantum computing can be considered a special case of quantum annealing. In adiabatic quantum computing, the system ideally starts and remains in the ground state throughout its entire adiabatic evolution.

[0012] Those skilled in the art will generally see that quantum annealing systems and methods can be implemented on adiabatic quantum computers. Throughout this specification and the accompanying claims, any reference to quantum annealing is intended to include adiabatic quantum computing, unless the context should be interpreted otherwise.

[0013] Quantum annealing can use quantum mechanics as the cause of disorder during the annealing process. To solve optimization problems using quantum annealing, the optimization problem is defined as the Hamiltonian H P Encoded as, the algorithm is for the problem Hamiltonian H P Disordered Hamiltonian H that cannot be exchanged D By adding this, quantum effects are introduced.

[0014] Examples of evolution are as follows: H E ∝A(t)H D +B(t)H p However, A(t) and B(t) are time-dependent envelope functions, and H E This is the evolutionary Hamiltonian (the evolutionary Hamiltonian H mentioned above in the context of adiabatic quantum computation). e (Similar to)

[0015] Disordered Hamiltonian H D Disorder may be eliminated or at least reduced by removing or at least reducing its effect (i.e., by reducing A(t)). Disorder may be added first and then removed. In some implementations, the time-varying envelope function is placed on the problem Hamiltonian. General disordered Hamiltonian H D This can be expressed as follows:

number

[0016] General problem: Hamiltonian H P This includes a first component proportional to the diagonal single-qubit term and a second component proportional to the diagonal multi-qubit term. The Hamiltonian in question can be expressed, for example, as follows:

number

[0017] Here, σ i z and σ i z σ j z The term is an example of a diagonal term. σ i z This is a single-qubit term, σ i z σ j z This is a 2-qubit term. In this application, the terms “problem Hamiltonian” and “final Hamiltonian” are used interchangeably.

[0018] The Hamiltonian in the above equation (for example, H D and H P This can be physically realized in various different ways. A specific example is realized by implementing a superconducting qubit (e.g., a superconducting flux qubit).

[0019] Quantum annealing of a system is a process where the system starts with an initial Hamiltonian, and the ground state encodes the final (problem) Hamiltonian H that represents the solution to the problem. P This is similar to adiabatic quantum computing, where the system evolves via an evolving Hamiltonian. If the evolution is sufficiently slow, the system typically settles to a global minimum (i.e., the exact solution) or a local minimum close to the exact solution in energy. The computational performance can be evaluated by measuring the residual energy (the difference from the exact solution using the objective function) as a function of evolution time. The computation time is the time required to generate residual energy below an acceptable threshold. In quantum annealing, the problem Hamiltonian H P Although H can encode the optimization problem, the system does not necessarily always remain in the ground state. The global minimum is the solution to the optimization problem to be solved, and a low local minimum is a good approximation of the solution. P You could create an energy landscape.

[0020] The decrease in the envelope function A(t) in quantum annealing may follow a specified schedule, referred to in this application as the annealing schedule, and is an example of an evolutionary schedule. In conventional forms of adiabatic quantum computing, the system typically starts and remains in the ground state throughout its evolution. In quantum annealing, the system may not remain in the ground state throughout the entire annealing schedule. Quantum annealing may be performed as a heuristic technique, and low-energy states with energies close to the ground state energy may provide an approximate solution to the problem.

[0021] Superconducting qubit There is a type of solid-state qubit that is based on circuits made of superconducting materials. Superconducting materials conduct without electrical resistance under certain conditions (e.g., below a critical temperature, critical current, or magnetic field strength) or above certain pressures, as is the case with some materials. The superconducting effects that can underlie how superconducting qubits operate include a) quantization of magnetic flux and b) the Josephson tunneling phenomenon.

[0022] When a loop of superconducting material, which is mediated by magnetic flux, is cooled below the superconducting critical temperature of the material while the magnetic field is cut, the magnetic flux can be quantized. The superconducting current continues in an attempt to maintain the magnetic flux. The magnetic flux is quantized. Superconductivity is a quantum mechanical effect. The current in the loop of the superconducting material can be controlled by a single wave function. For a wave function that should be evaluated independently at a point in the loop, the magnetic flux is quantized.

[0023] When an electric current in a superconducting loop passes through a small obstacle in the loop, for example, through an insulating gap of a few nanometers, the Josephson tunneling phenomenon occurs. The amount of current may have a sinusoidal dependence on the phase difference across the small obstacle in the loop. This sinusoidal dependence is a nonlinearity that can lead to anharmonicness in the energy levels of the system.

[0024] The superconducting effect can exist in different configurations to produce different types of superconducting qubits (e.g., flux qubits, phase qubits, charge qubits, and hybrid qubits). Different types of qubits can have different topologies for the loops of the superconducting material and for physical parameters (e.g., inductance, capacitance, and persistent current).

[0025] persistent current A superconducting qubit (e.g., a superconducting flux qubit) may include a loop of superconducting material (also referred to in this application as a qubit loop) that is blocked by at least one Josephson junction. The qubit loop is also referred to in this application as the body of the superconducting qubit.

[0026] Since qubit loops are superconducting, they effectively have no electrical resistance. Currents moving through qubit loops may not experience energy dissipation. If a current is generated in a qubit loop, for example, by a magnetic flux signal, the current may continue to circulate around the qubit loop even after the source of the magnetic flux signal is removed. The current may persist indefinitely until it is obstructed or the qubit loop is no longer superconducting.

[0027] For the purposes of this application, the term “persistent current” is used to describe an electric current circulating in a loop of superconducting material (a loop interrupted by at least one Josephson junction). The sign and magnitude of the persistent current are determined by a) the magnetic flux signal Φ directly coupled to the superconducting loop. X , and b) the magnetic flux signal Φ coupled to the composite Josephson junction that blocks the superconducting loop CJJ (or Φ CO It may depend on several factors, including (but not limited to) these.

[0028] Quantum processor The quantum processor may take the form of a superconducting quantum processor. The superconducting quantum processor may include two or more superconducting qubits and associated local bias devices. Furthermore, the superconducting quantum processor may include a coupling device (also referred to in this application as a coupler) that can provide a communicable coupling between the superconducting qubits. Further details and examples of quantum processors that can be used in conjunction with this system and device are described, for example, in U.S. Patents 7,533,068, 8,008,942, 8,195,596, 8,190,548, and 8,421,053.

[0029] The various types of problems that can be solved by any particular implementation of a quantum processor, and the relative size and complexity of such problems, may depend on many factors, including the number of qubits in the quantum processor and the connectivity between qubits in the quantum processor (i.e., the availability of interoperable coupling).

[0030] Throughout this specification, the term “connectivity” is used to describe an upper limit on the number of physically available paths to connect individual qubits in a quantum processor in a communicative manner without the use of intervening qubits. For example, a qubit with three connectivitys can be directly connected in a communicative manner to three other qubits, i.e., a qubit with three connectivitys can be connected in a communicative manner to three other qubits without the use of intervening qubits. In other words, for any particular application, some or all of the connectable connection paths (e.g., 0, 1, 2, or 3) can be used, but there are connectable connection paths available to three other qubits.

[0031] In a quantum processor that uses coupling devices between qubits, for example, three connectable qubits can be selectively coupled to each of the other three qubits via one of the three coupling devices. Typically, the number of qubits in a quantum processor can limit the size of the problem that can be solved, and the connectivity between qubits can limit the complexity of the problem that can be solved.

[0032] Many prior art techniques that use adiabatic quantum computing and / or quantum annealing to solve computational problems may include discovery methods that map (or incorporate) a representation of the problem into a quantum processor. For example, U.S. Patent Application Publication 2008-0052055 describes solving the protein folding problem by first assigning the protein folding problem as an Ising spin glass problem and then incorporating the Ising spin glass problem into a quantum processor. U.S. Patent 8,073,808 describes solving a computational problem (e.g., an image matching problem) by first assigning the problem as a quadratic unconstrained binary optimization ("QUBO") problem and then directly incorporating the QUBO problem into a quantum processor. In both cases, the problem is first solved by assigning the problem to a devised formulation (e.g., Ising spin glass, QUBO, etc.) because that particular formulation maps directly to a particular implementation of the quantum processor used. In other words, the intermediate formulation can be used to reassign the original problem to a form corresponding to the number and / or connectivity constraints of qubits in a particular implementation of a quantum processor, and then the intermediate formulation can be incorporated into the quantum processor. The incorporation technique can be driven by constraints specific to the architecture of the quantum processor used. For example, a quantum processor that uses only pair interactions between qubits (i.e., a quantum processor that uses a coupling device that gives communicable coupling between each pair of qubits (rather than between larger sets of qubits such as three or more qubits) is inherently well-suited to solving problems with quadratic terms (e.g., the QUBO problem) because the quadratic terms in the problem can be directly mapped to pair interactions between qubits in the quantum processor. [Overview of the project] [Means for solving the problem]

[0033] Brief Overview The superconducting integrated circuit comprises a first superconducting device comprising a first superconducting loop comprising a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device comprising a second superconducting loop comprising a second superconducting trace in a second layer of the superconducting integrated circuit, wherein the second layer lies above and / or adjacent to the first layer, and the second layer is separated from the first layer by an intervening layer, and an intersection region in which the first superconducting loop intersects the second superconducting loop by projection, wherein at least one of the first superconducting traces inside the intersection region The region can be summarized such that the region is narrower than at least a portion of the first superconducting trace outside the crossing region, at least a portion of the second superconducting trace inside the crossing region is narrower than at least a portion of the second superconducting trace outside the crossing region, at least a portion of the first superconducting trace inside the crossing region follows a first detour path, at least a portion of the second superconducting trace inside the crossing region follows a second detour path, and the first and second detour paths include a crossing region that is inductively close to each other with respect to at least a portion of the length of the first detour path.

[0034] In some implementations, the first detour route and the second detour route lie at least partially over each other for at least a portion of the length of the first detour route.

[0035] In the various implementation configurations described above, the first superconducting loop intersects the second superconducting loop substantially perpendicularly.

[0036] In the various implementation configurations described above, each of the first and second superconducting traces includes a superconducting metal. Each superconducting metal includes a superconducting metal selected from the group consisting of niobium and aluminum.

[0037] In the various implementations described above, the first superconducting device further includes a first Josephson junction, the first Josephson junction blocking a first superconducting loop, and the second superconducting device further includes a second Josephson junction, the second Josephson junction blocking a second superconducting loop.

[0038] In the various implementations described above, the first superconducting device is a first superconducting flux qubit, and the second superconducting device is a second superconducting flux qubit.

[0039] In the various implementations described above, at least a portion of the first superconducting trace inside the intersection region includes four direction changes.

[0040] In the various implementations described above, the first shape of the first detour route coincides with the second shape of the second detour route.

[0041] In the various implementation configurations described above, the intervening layer includes an insulating layer. The insulating layer may include a dielectric material and / or an air bridge. The dielectric material may include at least one of silicon dioxide or silicon nitride.

[0042] In various implementation forms described above, the present invention further includes a coupling device that is coupled to the first superconducting device and the second superconducting device and is connected in a manner that allows for communication between the first superconducting device and the second superconducting device, thereby providing mediating coupling between them.

[0043] In the various implementations described above, each of the first superconducting traces inside the intersection region and each of the second superconducting traces inside the intersection region includes one or more U-shaped contours.

[0044] Quantum computers can be summarized as including superconducting integrated circuits in various implementation forms described above.

[0045] A method for synchronizing the magnitude of a connectable coupling between a first superconducting device and a second superconducting device, wherein the magnitude of the connectable coupling is the sum of the magnitudes of the mediating connectable coupling and the direct connectable coupling, comprising: determining a target magnitude of the connectable coupling between the first and second superconducting devices; determining the difference between the magnitude of the mediating connectable coupling and the target magnitude; determining an adjustment tolerance based at least partially on the difference between the magnitude of the mediating connectable coupling and the target magnitude; attaching a first superconducting loop of the first superconducting device to a first layer; and attaching a second superconducting loop of the second superconducting device to a second layer, wherein the second The superconducting loop can be summarized as intersecting with a first superconducting loop to form an intersection region, following a first detour path and adjusting at least a portion of the first superconducting loop within the intersection region by an adjustable tolerance range such that it is narrower outside the intersection region than at least a portion of the first superconducting loop, and following a second detour path and adjusting at least a portion of the second superconducting loop within the intersection region by an adjustable tolerance range such that it is narrower outside the intersection region than at least a portion of the second superconducting loop, thereby including the first and second detour paths being inductively close to each other with respect to at least a portion of the length of the first detour path.

[0046] In some implementations, the method further includes depositing an intervening layer between a first layer and a second layer. Depositing an intervening layer between the first layer and the second layer may include depositing an insulating layer. Depositing an insulating layer may include depositing a layer of dielectric material and / or forming an air bridge.

[0047] In the various implementations described above, attaching the second superconducting loop of the second superconducting device to the second layer includes attaching the second superconducting loop of the second superconducting device to the second layer such that at least a portion of the second layer lies on top of at least a portion of the first layer.

[0048] In some implementations, adjusting at least a portion of the first superconducting loop to within an adjustable tolerance range includes adjusting at least a portion of the first superconducting loop to a width between 0.5 μm and 2.0 μm.

[0049] In some implementations, adjusting at least a portion of the first superconducting loop to an adjustable tolerance includes etching the adjustment width of at least a portion of the first superconducting loop. Etching the adjustment width of at least a portion of the first superconducting loop may include attaching a first hard mask and laying it over at least a portion of the first superconducting loop, attaching a second hard mask and laying it over at least a portion of the first hard mask, attaching a photoresist layer and laying it over at least a portion of the second hard mask, patterning the photoresist layer to define a predetermined adjustment width, and etching at least a portion of the first superconducting loop to remove the predetermined adjustment width.

[0050] A method for forming an integrated circuit can be summarized as comprising forming a first device having a first trace in a first layer of the integrated circuit, and forming a second device having a second trace in a second layer of the integrated circuit, wherein at least a portion of the second trace is inductively adjacent to at least a portion of the first trace, thereby creating an inductively communicable coupling between the first device and the second device, and at least a portion of the first trace is narrower than at least another portion of the first trace.

[0051] In some implementations, forming a second device includes forming a second device such that at least a portion of the second trace is narrower than at least another portion of the second trace.

[0052] In some implementations, forming a first device includes forming a first superconducting device, and forming a second device includes forming a second superconducting device. Forming a first superconducting device may include attaching a superconducting material. Forming a first superconducting device may further include following a first detour path and adjusting at least a portion of the first trace so that it is narrower than at least another portion of the first trace.

[0053] In the various implementations described above, forming a second superconducting device includes forming a second superconducting device inductively adjacent to a mediating coupling device, the mediating coupling device providing a communicable coupling between the first and second superconducting devices. Forming a second superconducting device inductively adjacent to a mediating coupling device may also include forming a second superconducting device inductively adjacent to a mediating coupling device that provides an antiferromagnetic (AFM) coupling between the first and second superconducting devices, thereby increasing the antiferromagnetic coupling between the first and second superconducting devices.

[0054] A superconducting integrated circuit can be summarized as comprising: a first superconducting device comprising a first superconducting loop comprising a first superconducting trace in a first layer of the superconducting integrated circuit; a second superconducting device comprising a second superconducting loop comprising a second superconducting trace in a second layer of the superconducting integrated circuit; and a region in which a portion of the first superconducting loop overlaps with a portion of the second superconducting loop, wherein at least a portion of the first superconducting trace inside the region is narrower than at least a portion of the first superconducting trace outside the region, at least a portion of the second superconducting trace inside the region is narrower than at least a portion of the second superconducting trace outside the region, at least a portion of the first superconducting trace inside the region follows a first path, at least a portion of the second superconducting trace inside the region follows a second path, and the first and second paths include regions that are inductively close to each other with respect to at least a portion of the length of the first path.

[0055] In some implementations, the first layer is a different layer from the second layer.

[0056] In some implementations, the first layer is separated from the second layer by an intervening layer.

[0057] In some implementations, the first route is a detour route. The first and second routes may coincide.

[0058] In some implementations, the first and second paths lie at least partially on top of each other.

[0059] A brief explanation of some of the figures in the drawing. In drawings, the same reference numerals identify similar elements or actions. The size and relative position of elements in drawings are not necessarily proportional to the actual size. For example, the shapes and angles of various elements are not necessarily proportional to the actual size, and some of these elements may be arbitrarily enlarged and repositioned to improve the readability of the drawing. Furthermore, the specific shapes of elements as shown are not intended to convey any information about the actual shape of a particular element, but are selected solely to facilitate recognition in the drawing. [Brief explanation of the drawing]

[0060] [Figure 1] This is a schematic diagram of an exemplary mediation coupling layout using this system and method. [Figure 2] This is a schematic diagram of exemplary hybrid-mediated and direct-coupled layouts using the present system and method. [Figure 3] This is a schematic diagram of another exemplary hybrid-mediated and direct-coupled layout using the present system and method. [Figure 4] This is a schematic diagram of another exemplary hybrid-mediated and direct-coupled layout using the present system and method. [Figure 5] This is a schematic diagram of another exemplary hybrid-mediated and direct-coupled layout using the present system and method. [Figure 6A] This is a schematic diagram illustrating an exemplary layout of a pair of superconducting devices, each of which has an inwardly curved portion in the intersection region, and which are interconnected and can communicate with one another, according to this system and method. [Figure 6B] This is a schematic diagram showing an example of the implementation configuration of the intersection region of the layout in Figure 6A using this system and method. [Figure 7A] This is a schematic diagram of another exemplary layout of a pair of superconducting devices, each superconducting device having an outwardly curved portion in the intersection region, and which are interconnected and can communicate with one another, according to the system and method. [Figure 7B] This is a schematic diagram showing an example of the implementation configuration of the intersection region of the layout in Figure 7A using this system and method. [Figure 8A] This is a schematic diagram of another exemplary layout of a pair of superconducting devices, each superconducting device having multiple curved sections in the intersection region, and which are interconnected and can communicate with one another, according to the system and method. [Figure 8B] This is a schematic diagram showing an example of the implementation configuration of the intersection region of the layout in Figure 8A using this system and method. [Figure 8C] This is a schematic diagram of another example of the implementation configuration of the intersection region of the layout in Figure 8A, using this system and method. [Figure 9] This is a schematic diagram of the topology of an exemplary superconducting quantum processor using this system and method. [Figure 10] This is a schematic diagram illustrating an exemplary layout of a pair of superconducting devices directly coupled to each other according to the present system and method. [Figure 11] This is a schematic diagram of another exemplary layout of a pair of superconducting devices coupled to each other in a manner that allows for direct communication, according to the present system and method. [Figure 12] This diagram illustrates an example of a hybrid computing system, including a digital computer coupled to an analog computer, using the system, devices, objects, and methods described herein. [Figure 13A] This is a cross-section of a part of a superconducting integrated circuit produced by this system and method. [Figure 13B] This is another cross-section of a superconducting integrated circuit obtained using this system and method. [Figure 14A] This is a flowchart illustrating an example of a method for forming an integrated circuit using this system and method. [Figure 14B] This is a flowchart illustrating an example of a method for adjusting the first path in Figure 14A using this system and method. [Modes for carrying out the invention]

[0061] Detailed explanation In the following description, certain details are included to fully understand the various embodiments of the disclosure. However, those skilled in the art will see that embodiments can be carried out without one or more of these specific details, or using other methods, components, materials, etc. In other cases, well-known structures relating to quantum processors, qubits, couplers, readout devices and / or interfaces are not shown or described in detail to avoid unnecessarily ambiguous descriptions of embodiments.

[0062] Unless the context requires otherwise, the term “comprise” and its variations, such as “comprises” and “comprising,” should be interpreted throughout the following specification and claims as having an unrestricted, inclusive meaning, i.e., “including, but not limited to.”

[0063] Throughout this specification, any reference to “one example,” “an example,” “one embodiment,” or “an embodiment” means that a particular feature, structure, or characteristic described in relation to an embodiment is included in at least one embodiment. Therefore, all occurrences of the terms “in one example,” “in an example,” “in one embodiment,” or “in an embodiment” throughout this specification do not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic may be combined in one or more embodiments in any suitable manner.

[0064] As used in this specification and the attached claims, the singular forms “a,” “an,” and “the” refer to multiple subjects unless otherwise explicitly indicated. It should also be noted that the term “or” is generally used to mean “and / or” unless otherwise explicitly indicated.

[0065] As used in this specification and claims, “inductively close” means structures (e.g., devices, lines, or traces) that are appropriately oriented and close enough to one structure that the current flow in one structure directly induces the current flow in the other structure. “Appropriately oriented” typically means parallel or at least non-orthogonal.

[0066] As used in this specification and claims, “overlapping” means a projection of a structure in a plan or elevation view that at least partially intersects with another structure or includes another structure, with or without the presence of an intervening structure.

[0067] As used in this specification and claims, “lying over” means a projection of a structure in a plan view that intersects, or includes, another structure at least partially, with another structure, which typically has one or more intervening layers.

[0068] As used in this specification and claims, “adjacent” means a projection of a structure in an elevation view that intersects, or includes, another structure at least partially, with another structure having one or more intervening materials.

[0069] The overlapping structures may lie on top of each other in a projection perpendicular to the plan view or main face or main surface (e.g., top or bottom) of the product or chip (e.g., top or bottom), and / or be adjacent to each other in a projection perpendicular to the elevation view or secondary face or secondary surface (e.g., edge) of the product or chip (e.g., parallel or in series). The overlapping structures may or may not be inductively adjacent to another structure.

[0070] A structure may overlap with another structure on the next wiring layer from below, or on two wiring layers from below, for example. Overlapping structures include partially overlapping structures and fully overlapping structures. A structure may be, for example, a superconducting loop or part of a superconducting loop. The terms “overlap,” “overlap,” etc., apply regardless of orientation, that is, regardless of whether one structure is located above or below another structure, or on the side of another structure.

[0071] The overlapping structures may be in close proximity to each other, that is, they may have at least a portion of one structure running parallel to (or at least non-orthogonal to) at least a portion of the other structure, and the portions may be arranged close enough to induce current flowing through one structure into the other structure. In this application, inductively adjacent structures can be directly inductively connected to each other.

[0072] If structures are on different layers of a multilayer integrated circuit, the structures may be inductively close to other structures, and the structures may lie at least partially on top of other structures. If structures are on the same layer of a multilayer integrated circuit, the structures may be inductively close to other structures, and the structures may lie at least partially adjacent to other structures. Provided that the structures are appropriately oriented and close enough to other structures that the current flow in one structure directly induces the current flow in the other structure, the structures may be inductively close to other structures if they are on different layers and do not lie on top of each other.

[0073] Overlapping and adjacent structures will be explained, for example, with reference to Figures 13A and 13B below. In this application, adjacent structures are separated by at least one intervening layer or material. Typically, the intervening layer or material is an insulating layer. In the case of multilayer integrated circuits, adjacent structures are typically on the same layer and separated by an intervening material.

[0074] The headings and abstracts of the disclosures provided herein are for convenience only and should not be used to define the scope or meaning of the embodiments.

[0075] It is desirable to improve the performance of quantum processors. One way to improve performance is to increase the energy scale of the quantum processor. While the energy scale of a quantum processor can be increased by increasing the critical current of the coupled devices in the quantum processor, there are constraints on how much the energy scale can be increased in this way.

[0076] The systems and methods described below aim to increase the energy scale of quantum processors by using direct interqubit coupling (i.e., without intervening coupling devices), either alone or in combination with intervening coupling via coupling devices. The systems and methods described below can provide tuneable direct coupling during fabrication. The advantages of the systems and methods described below include, advantageously, a) continuously variable tuning (rather than tuning in discrete steps), and b) little to no spatial disadvantage to integrated circuits.

[0077] The coupling between devices (e.g., a pair of superconducting qubits in a quantum processor) can be characterized by coupling strength. Coupling strength quantifies the strength of the interaction between devices. Depending on the sign of the coupling strength, the interaction between devices can be ferromagnetic or antiferromagnetic. By convention, a positive coupling strength can characterize an antiferromagnetic interaction, and a negative coupling strength can characterize a ferromagnetic interaction. The inclusion of both ferromagnetic (FM) and antiferromagnetic (AFM) interactions can be beneficial for quantum processors.

[0078] The definitions of FM and AFM interactions can be based on the direction of the persistent current in each qubit of a pair of connectable coupled qubits, and the extent to which the persistent current affects the Hamiltonian of the two-qubit system. If the mutual inductance (i.e., coupling) between the two qubits is positive, then the currents in the two qubits will flow in opposite directions. This is referred to in this application as the AFM interaction.

[0079] In some implementations, FM coupling is achieved by biasing the composite Josephson junction of the coupled device. In some implementations, improving AFM coupling (rather than FM coupling) using direct coupling of communicable coupled qubits is of preferential value.

[0080] Mutual inductance can be a measure of the coupling between two inductors (e.g., two superconducting qubits). The energy measure E that specifies the problem Hamiltonian in a quantum processor can be expressed as follows: E=M AFM I P 2 However, M AFM I is the antiferromagnetic mutual inductance between two communicable coupled superconducting devices (e.g., two superconducting qubits communicably coupled by a coupling device), and P This is the average persistent current of the two superconducting devices.

[0081] For example, mutual inductance M AFM and mean persistent current I P The performance of a quantum processor can be improved by increasing the energy measure E by increasing one or both of these factors.

[0082] The mutual inductance between two superconducting devices connected in communication by a coupling device may be limited by a) the inductance of the coupling device and b) the mutual inductance between each superconducting device and the coupling device.

[0083] The antiferromagnetic mutual inductance between two interconnectable coupled superconducting devices can be expressed as follows: M AFM =M1M2χ AFM However, M1 is the mutual inductance between the first superconducting device and the coupling device, M2 is the mutual inductance between the second superconducting device and the coupling device, and χ AFM This is the magnetic susceptibility of the coupled device.

[0084] Magnetic susceptibility χ of the coupled device AFM This can be a measure of how strongly a coupling device can couple two superconducting devices into communication. The magnetic susceptibility of the coupling device is used, and the magnetic flux bias of the coupling device is used.CO The critical current I of the coupled device can be set at least partially by this. C Increasing the magnetic susceptibility χ of the coupled device AFM is 1 / L CO (However, L CO The constant current of the coupling device can be increased up to the upper limit of the inductance of the coupling device. Increasing the persistent current of the coupling device increases the magnetic susceptibility χ of the coupling device. AFM This can be increased. For example, in some implementations, if the persistent current is increased tenfold, the magnetic susceptibility χ of the coupled device can be increased. AFM This can be increased by at least approximately double.

[0085] Increasing the persistent current of the coupling device can also increase the screening parameter of the coupling device (also referred to as beta β in this application). The beta of the coupling device is a parameter that describes the behavior of the superconducting loop in the coupling device. The beta of the coupling device can be expressed as follows: β = 2πL CO I C / φ0 However, φ0 is the magnetic flux quantum of the superconducting loop.

[0086] For example, critical current I C Increasing the beta of the coupled device by increasing the χ of the coupled device results in a change in the magnetic susceptibility χ of the coupled device in the ferromagnetic region. AFM The gradient can be increased. The critical current I of the coupled device. C Increasing this value may reduce the precision with which ferromagnetic and / or antiferromagnetic couplings can be specified.

[0087] One way to increase the energy scale of a quantum processor is to increase the critical current of the coupled device. As mentioned above, the critical current of the coupled device is C Increasing the coefficient of the coupling device can increase the beta β of the coupling device. Increasing the beta β by increasing the critical current of the coupling device increases the magnetic susceptibility χ of the coupling device. AFMThis can be increased, that is, increasing beta β increases the derivative dI of the current flowing through the body of the coupling device with respect to the applied magnetic flux. P / dφ x It is possible to increase the magnetic susceptibility χ. There is a limit to how much the magnetic susceptibility can be increased by increasing the critical current. The magnetic susceptibility is a nonlinear function, and as a result, increasing the critical current of the coupled device changes the magnetic susceptibility χ. AFM This can increase as the return decreases.

[0088] Another technique for increasing the energy scale of a quantum processor is to implement direct coupling between the bodies of two or more superconducting devices. In some implementations, there is direct coupling (i.e., without intervening devices) between a pair of superconducting devices that are further connected communicatively by a coupling device. In some implementations, the direct coupling is inductive coupling. The pair of superconducting devices connected communicatively by a coupling device may be a) a pair of superconducting qubits, b) a superconducting qubit and another superconducting device, or c) any pair of superconducting loops that can be coupled to one another (e.g., superconducting qubits, quantum flux parametrons (QFPs), multipliers, and L-tuners). A pair of superconducting devices, each containing a loop of superconducting material separated by at least one Josephson junction, may be configured to include direct coupling between the pair of superconducting devices.

[0089] Detailed descriptions of other such superconducting devices are provided, for example, in U.S. Patents 8,169,231 and 7,843,209, and U.S. Patent Publications 2011-0057169A1 and 2011-0060780A1. Examples of systems and methods for increasing the energy scale of quantum processors are given in U.S. Patent 9,129,224.

[0090] Direct coupling between superconducting devices is undesirable because, for example, the direct coupling may cause unwanted crosstalk between the superconducting devices. This application finds that adding a known antiferromagnetic or ferromagnetic direct coupling between two communicable coupled superconducting devices can be beneficial in utilizing the asymmetric sensitivity of the coupled devices.

[0091] For example, when there is no direct coupling, the mutual inductance M (as described above) AFM may be limited to M1M1χ AFM However, as described below, a stronger antiferromagnetic coupling may be achieved by adding a direct coupling. M AFM =M1M1χ AFM +M QQ where M QQ is the mutual inductance of the direct coupling.

[0092] By configuring the device to induce a direct ferromagnetic or antiferromagnetic coupling between communicable coupled superconducting devices, a direct coupling may be added between communicable coupled superconducting devices (e.g., a pair of communicable coupled superconducting devices). Configuring qubits (e.g., a pair of qubits) to induce a direct coupling between communicable coupled superconducting devices can include, for example, configuring the intersecting shape of the qubits.

[0093] As described above, each qubit can include a loop of superconducting material (also referred to herein as a superconducting loop) interrupted by at least one Josephson junction. In some implementations, the Josephson junction is a composite Josephson junction. In some implementations, the Josephson junction is a composite-composite Josephson junction, i.e., a composite Josephson junction in which at least one of the constituent Josephson junctions is itself a composite Josephson junction.

[0094] The direct coupling between qubits can be an antiferromagnetic coupling, a ferromagnetic coupling, or a zero coupling.

[0095] In some implementations, zero direct coupling can be achieved by arranging the major axes of each of a pair of communicable coupled qubits so that they are orthogonal to each other, regardless of whether or not the qubit traces are adjusted in the region where the qubits overlap.

[0096] In some implementations, ferromagnetic coupling can be achieved, for example, by adjusting the qubit traces so that they have outward-curving portions (see, for example, Figure 7).

[0097] The various implementations described in this application provide systems and methods for increasing the energy scale of a quantum processor by adding direct coupling between connectable coupled superconducting devices (e.g., a pair of superconducting qubits). Furthermore, the connectable coupled superconducting devices may have connectable coupling mediated by a coupling device.

[0098] Furthermore, the various implementations described in this application provide systems and methods for increasing the energy scale of a quantum processor by increasing the linearity of the response or sensitivity of coupled devices in the quantum processor.

[0099] As a helpful example, a superconducting quantum processor designed to perform adiabatic quantum computing and / or quantum annealing will be used in the following description. However, those skilled in the art will see that the system and method can be applied to other forms of quantum processor hardware and quantum processors that perform other forms of quantum algorithms (e.g., adiabatic quantum computing, quantum annealing, and gate and / or circuit-based quantum computing).

[0100] Figure 1 is a schematic diagram of an exemplary mediation coupling layout 100. The exemplary mediation coupling layout 100 includes a pair of superconducting devices 102 and 104 that are coupled to each other in a communicative manner by a coupling device 106. In the exemplary mediation coupling layout 100, there is little to no direct coupling induced between the two superconducting devices 102 and 104. In the exemplary layout 100, there is a mediation-enabled coupling between the superconducting devices 102 and 104. The mediation-enabled coupling can be mediated by the coupling device 106.

[0101] The superconducting device 102 includes a superconducting loop 108 that is interrupted by a Josephson junction 110. The superconducting device 104 includes a superconducting loop 112 (shown as a dotted line in Figure 1) that is interrupted by a Josephson junction 114. Josephson junctions (e.g., Josephson junctions 110 and 114) are represented by an "x" in Figures 1 to 5, 6A, 7A, and 8A of this application.

[0102] In this application, a superconducting loop is defined as a closed loop of a material that is superconducting below its critical temperature. In some implementations, a superconducting loop is a closed loop of a superconducting wire. In some implementations, a superconducting loop is a superconducting circuit trace (also referred to in this application as a trace) running in a closed loop in a superconducting integrated circuit. A superconducting trace is a path in a superconducting integrated circuit. A superconducting trace includes, for example, a wire of superconducting material through which current can flow in a closed loop or between component circuits of a superconducting integrated circuit. In some implementations, a superconducting loop includes a superconducting wire and at least one superconducting trace.

[0103] In some implementations, a superconducting loop is an elongated loop having a long axis and a short axis. The orientation of the superconducting loop may be defined as the direction of the long axis. For example, superconducting loop 108 has a long axis 128 and a short axis 130. The orientation 132 of superconducting loop 108 may be defined as the direction of the long axis 128. A superconducting integrated circuit is an integrated circuit that includes one or more superconducting component circuits.

[0104] In some implementations, the superconducting loops are traces formed in the layers of a multilayer superconducting integrated circuit. In some implementations, one or both of the superconducting loops 108 and 112 contain a superconducting metal (e.g., niobium and / or aluminum). In some implementations, each of the superconducting loops 108 and 112 is a trace formed in each layer of a multilayer superconducting integrated circuit, with each layer separated from the other by an insulating layer. In some implementations, each insulating layer contains silicon dioxide and / or silicon nitride.

[0105] The superconducting devices 102 and 104 may include more than one Josephson junction. In some implementations, one or both of the Josephson junctions 110 and 114 are composite Josephson junctions. In some implementations, one or both of the Josephson junctions 110 and 114 are composite-composite Josephson junctions. A composite Josephson junction is a Josephson junction that includes a pair of Josephson junctions that are electrically parallel to each other. A composite-composite Josephson junction is a composite Josephson junction in which at least one constituent Josephson junction is a composite Josephson junction.

[0106] The coupling device 106 is operable to couple the superconducting devices 102 and 104 to communicate with each other by mutual inductance between the superconducting loops 108 and 112 of the superconducting devices 102 and 104, respectively. The coupling device 106 includes a superconducting loop 116. In some implementations, such as layout 100 in Figure 1, the superconducting loop 116 is interrupted by a Josephson junction 118. The Josephson junction 118 may be a composite Josephson junction or a composite-composite Josephson junction. In some implementations, the coupling device 106 includes one or more Josephson junctions.

[0107] In Figure 1, to more clearly illustrate the intersection shape of superconducting devices 102 and 104, superconducting device 102 is drawn with a solid line, while superconducting device 104 is drawn with a dotted line. In exemplary layout 100, superconducting device 102 intersects superconducting device 104 substantially perpendicularly. The region where superconducting devices 102 and 104 intersect is referred to in this application as the intersection region 120. This application describes a layout of the intersection region 120 in which a portion of superconducting device 102 lies over a portion of superconducting device 104 to provide coupling. See, for example, the layouts of the intersection region shown in Figures 6B, 7B, 8B, and 8C, which are suitable for the arrangement in Figure 1. Other layouts of the intersection region 120 with bypass paths may be used similarly. For example, by selective adjustment of superconducting loops 108 and 112 in the intersection region 120 during manufacturing, the magnitude of the direct-communication coupling between superconducting devices 102 and 104 can be controlled in some implementation configurations without incurring spatial disadvantages to the superconducting circuit.

[0108] In this application, if a portion of one superconducting device (e.g., a trace or loop) intersects a portion of another superconducting device at an angle of 90° ± 10°, then one superconducting device is considered to intersect the other superconducting device substantially perpendicularly.

[0109] In some implementations, the superconducting device includes a superconducting loop. The orientation of the superconducting device may be defined by the orientation of the superconducting loop. In some implementations, the superconducting loop has an elongated shape with a major axis in the longitudinal direction and a minor axis perpendicular to the major axis. In this case, the orientation of the superconducting loop can be defined by the orientation of the major axis. If the major axis of one superconducting loop intersects the major axis of another superconducting loop at an angle of 90° ± 10°, one superconducting loop can be considered to intersect the other superconducting loop substantially perpendicularly. The implementation shown in Figure 1 is described. When the major axes (also called longitudinal axes in this application) of superconducting loops 108 and 112 intersect at an angle of 90° ± 10°, superconducting device 102 is substantially perpendicular to superconducting device 104.

[0110] The excitation current 122 in the superconducting loop 112 can induce a current 124 in the coupling device 106, and then can induce a current 126 in the superconducting loop 108, thereby providing a mediated inductive communicable coupling between the superconducting devices 102 and 104.

[0111] In some implementations, a direct coupling can be disabled by applying a bias to the coupling device 106. In some implementations, a digital / analog converter (DAC) is used to apply a bias, disable the direct coupling, and / or adjust the strength of the combined direct and mediated couplings.

[0112] In some implementations, the superconducting devices 102 and 104 are a pair of superconducting qubits. In other implementations, the superconducting device 102 is a superconducting qubit and the superconducting device 104 is another type of superconducting device that communicably couples the superconducting device 102 by the coupling device 106. For example, the superconducting device 104 may be one of a quantum flux paramon (QFP), a multiplier, a DAC, and a synchronous Josephson inductance (also abbreviated as an inductance synchronizer or L synchronizer in this application). In still other implementations, the superconducting devices 102 and 104 form a suitable combination of a pair of communicably coupled superconducting devices (e.g., superconducting qubits, QFPs, multipliers, and / or L synchronizers).

[0113] The mutual inductance between the superconducting devices 102 and 104 can be expressed as follows. M AFM =M 102 M 104 χ 106 where M 102 is the mutual inductance between the superconducting device 102 and the coupling device 106, M 104 is the mutual inductance between the superconducting device 104 and the coupling device 106, and χ 106is the magnetic susceptibility of the coupled device 106. In the exemplary layout 100, the superconducting loop 108 of the superconducting device 102 runs substantially perpendicular to the superconducting loop 112 of the superconducting device 104, so that there is little to no direct coupling induced between the superconducting devices 102 and 104 by the mutual inductance between the superconducting loops 108 and 112.

[0114] Direct coupling may be induced between a pair of communicable coupled superconducting devices by arranging the shapes of the superconducting devices relative to each other. For example, direct coupling may be induced by arranging at least a portion of the superconducting loop of one superconducting device at a non-orthogonal angle to at least a portion of the superconducting loop of the other superconducting device.

[0115] Intersections of at least some superconducting loops at non-orthogonal angles to each other can cause crosstalk between the superconducting loops. Crosstalk can increase the mutual inductance of two communicable coupled superconducting loops. If the two superconducting devices are elements of a quantum processor, crosstalk can increase the energy measure of the quantum processor. In some situations, crosstalk can be undesirable, but advantageously, it can be used to controllably increase the energy measure of a quantum processor, thereby beneficially improving the performance of the quantum processor. The improvement in quantum processor performance may include an improvement in the quality of the solution realized by the quantum processor and / or a reduction in the time to reach the solution.

[0116] Figure 2 is a schematic diagram of exemplary hybrid-mediated and direct-coupled layouts 200. The exemplary layout 200 includes a pair of superconducting devices 202 and 204 that are coupled to each other in a communicative manner by a coupling device 206. To more clearly illustrate the intersection shape of the superconducting devices 202 and 204, superconducting device 202 is drawn with a solid line, while superconducting device 204 is drawn with a dotted line. In the exemplary layout 200, superconducting device 202 intersects superconducting device 204 substantially perpendicularly.

[0117] The superconducting device 202 includes a superconducting loop 208 that is interrupted by a Josephson junction 210. The superconducting device 204 includes a superconducting loop 212 that is interrupted by a Josephson junction 214. In some implementations, one or both of the superconducting loops 208 and 212 include a superconducting metal (e.g., niobium and / or aluminum).

[0118] The superconducting devices 202 and 204 may include more than one Josephson junction. In some implementations, one or both of the Josephson junctions 210 and 214 are composite Josephson junctions. In some implementations, one or both of the Josephson junctions 210 and 214 are composite-composite Josephson junctions. In some implementations, the superconducting devices 202 and 204 are superconducting qubits (e.g., superconducting flux qubits).

[0119] The coupling device 206 is operable to couple the superconducting devices 202 and 204 to communicate with each other through the mutual inductance between the superconducting loops 208 and 212, respectively.

[0120] Unlike the exemplary layout 100 in Figure 1, a portion of the superconducting loop 208 of superconducting device 202 is positioned at a non-orthogonal angle to a portion of the superconducting loop 212 of superconducting device 204 in the molded region 216. This arrangement reduces the mutual inductance M between superconducting devices 202 and 204. QQA direct coupling (also referred to in this application as a direct coupling) can be induced. The direct coupling may also be a direct inductive coupling. In the exemplary layout 200 of Figure 2, a portion of the superconducting loop 208 of the superconducting device 202 is positioned substantially parallel to a portion of the superconducting loop 212 of the superconducting device 204 in the molded region 216.

[0121] In some implementations, a portion of the superconducting loop 208 of the superconducting device 202 has a curved section, i.e., a short, abrupt change in direction that interrupts the orientation of the rest of the loop. For example, layout 200 includes a curved section 218. The curved section 218 causes a portion of the superconducting loop 208 to be substantially parallel to a portion of the superconducting loop 212 of the superconducting device 204. In some implementations, the superconducting loop 208 of the superconducting device 202 is Z-shaped. In other implementations, the superconducting loop 208 of the superconducting device 202 is L-shaped.

[0122] The excitation current 220 in the superconducting loop 212 can induce a current 222 in the superconducting loop 208.

[0123] Mutual inductance M induced by the proximity and relative orientation of superconducting loops 208 and 212 QQ In addition, the coupling device 206 (which provides a communicable coupling between the superconducting devices 202 and 204) has mutual inductance M as described above. AFM This can provide the inductive mutual inductance, for example, can provide antiferromagnetic coupling. The total mutual inductance between superconducting devices 202 and 204 is the mutual inductance M AFM and M QQ It can include contributions from...

[0124] The direction of direct coupling induced between superconducting devices 202 and 204 in or near the molded region 216 may be at least partially dependent on the direction of the current flowing through the superconducting loops 208 and 212 of superconducting devices 202 and 204, respectively. The direction of direct coupling may be dependent on the shape of the traces of superconducting devices 202 and 204 in the region where their traces overlap. The intersection shape of superconducting devices 202 and 204 (for example, in or near the molded region 216) is related to the mutual inductance M QQ However, it is possible to at least partially determine whether it is ferromagnetic, antiferromagnetic, or close to zero. In the example shown in Figure 2, the mutual inductance M QQ It is antiferromagnetic and has mutual inductance M QQ The mutual inductance M AFM This increases the mutual inductance M, thereby increasing the antiferromagnetic (AFM) coupling of the superconducting devices 202 and 204. QQ If it is an AFM, the mutual inductance M is increased by increasing the mediating coupling provided by the coupling device 206. QQ The mutual inductance M AFM This can be increased, thereby increasing the total mutual inductance.

[0125] This application includes a description of a molded region 216 that can accommodate a portion of the superconducting device 202 lying over a portion of the superconducting device 204 to provide coupling. See, for example, the crossing region layouts shown in Figures 6B, 7B, 8B, and 8C that are suitable for the arrangement in Figure 2. Other layouts of the molded region 216 with bypass paths may be used similarly. For example, by selective adjustment of the superconducting loops 208 and 212 during manufacturing, the magnitude of the directly connectable coupling between the superconducting devices 202 and 204 can be controlled in some implementations, advantageously without incurring space disadvantages to the superconducting circuit.

[0126] This system and method apply more generally to connectable coupled superconducting devices, each of which includes a loop of superconducting material. The system and method may provide direct inductive coupling between superconducting devices that can be tuned during fabrication to tuned inductive coupling between superconducting devices.

[0127] Figure 3 is a schematic diagram of another exemplary intermediary and direct coupling layout 300. The exemplary layout 300 includes a pair of superconducting devices 302 and 304 that are coupled to each other in communication by a coupling device 306. To more clearly illustrate the intersection shape of the superconducting devices 302 and 304, superconducting device 302 is drawn with a solid line, while superconducting device 304 is drawn with a dotted line.

[0128] The superconducting device 302 includes a superconducting loop 308 that is interrupted by a Josephson junction 310. The superconducting device 304 includes a superconducting loop 312 that is interrupted by a Josephson junction 314.

[0129] A superconducting loop formed in phase by a 180° out-of-plane rotation of a portion of the superconducting loop is referred to in this application as a superconducting loop with a crossover. Current flowing through the superconducting loop on one side of the crossover flows clockwise around the loop, and current flowing through the superconducting loop on the other side of the crossover flows counterclockwise around the loop. Two segments of a superconducting loop that cross over each other are DC-isolated by the crossover. A superconducting loop may contain more than one crossover; for example, superconducting loop 308 contains two crossovers 316 and 318.

[0130] The intersection shape of the superconducting devices 302 and 304 in Figure 3 in or near the intersection region 320 is directly coupled between the superconducting loops 308 and 312 of the superconducting devices 302 and 304, respectively. QQ This can be generated. For clarity, the intersection region 320 is shown as the molding region in Figure 3.

[0131] A vector perpendicular to the plane containing the region of the superconducting loop 308 in the intersection region 320 has substantially opposite orientations to both i) a vector perpendicular to the plane containing the region of the superconducting loop 308 outside the intersection region 320, and ii) a vector perpendicular to the plane containing the region of the superconducting loop 312 of the superconducting device 304. The substantially opposite orientation of one vector to another means an orientation of 180° ± 10° between the two vectors.

[0132] A portion of the superconducting loop 308 of superconducting device 302 has a curved portion 322 such that the portion of superconducting loop 308 is substantially parallel to a portion of the superconducting loop 312 of superconducting device 304. When portions of superconducting loops 308 and 312 run parallel to each other, portions of superconducting loops 308 and 312 can lie on top of each other and / or be adjacent to each other. In some implementations, superconducting loops 308 and 312 define traces in separate layers of a multilayer superconducting integrated circuit. The traces of superconducting loops 308 and 312 may lie on top of each other and / or be adjacent to each other, and may be separated, for example, by an electrically insulating layer (e.g., a layer of dielectric material). The lying and / or adjacent portions of superconducting loops 308 and 312 can generate mutual inductance, which can provide a directly inductively communicable coupling between superconducting devices 302 and 304.

[0133] The excitation current 324 in the superconducting loop 312 can induce a current 326 in the superconducting loop 308.

[0134] The presence of crossovers 316 and 318 in the superconducting loop 308 allows the current flowing counterclockwise in the crossing region 320 to (by induction) flow clockwise in the portion of the superconducting loop 308 outside the crossing region 320. The portion of the superconducting loop 308 outside the crossing region 320 is also referred to in this application as the body of the superconducting device 302. Mutual inductance M QQ The mutual inductance M AFMThis increases the AFM coupling between the superconducting devices 302 and 304.

[0135] This application includes a description of layouts that can accommodate an intersection region 320 in which a portion of the superconducting device 302 lies over a portion of the superconducting device 304 to provide coupling. For example, see the intersection region layouts shown in Figures 6B, 7B, 8B, and 8C, which are suitable for the mediated and direct coupling layout 300 of Figure 3. Other layouts of the intersection region 320 with bypass paths may be used similarly. For example, by selective adjustment of the superconducting loops 308 and 312 during manufacturing, the magnitude of the direct coupling between the superconducting devices 302 and 304 can be controlled in some implementations, advantageously without incurring space disadvantages to the superconducting circuit.

[0136] Figure 4 is a schematic diagram of another exemplary layout 400. Layout 400 includes a pair of superconducting devices 402 and 404 that are coupled to each other in communication by a coupling device 406. To more clearly illustrate the intersection shape of the superconducting devices 402 and 404, superconducting device 402 is drawn with a solid line, while superconducting device 404 is drawn with a dotted line.

[0137] The superconducting device 402 includes a superconducting loop 408 that is interrupted by a Josephson junction 410. The superconducting device 404 includes a superconducting loop 412 that is interrupted by a Josephson junction 414. The superconducting loop 408 includes crossovers 416 and 418.

[0138] The intersection shape of superconducting devices 402 and 404 in Figure 4 in or near the intersection region 420 is directly coupled between the superconducting loops 408 and 412 of superconducting devices 402 and 404, respectively. QQ This can be generated. For clarity, the intersection region 420 is shown as the molding region in Figure 4.

[0139] A vector perpendicular to the plane containing the region of the superconducting loop 408 in the intersection region 420 has substantially opposite orientation to both i) a vector perpendicular to the plane containing the region of the superconducting loop 408 outside the intersection region 420, and ii) a vector perpendicular to the plane containing the region of the superconducting loop 412 of the superconducting device 404.

[0140] Each of the two portions of the superconducting loop 408 of the superconducting device 402 has a curved portion such that each curved portion 422 and 424 of the superconducting loop 408 is substantially parallel to a portion of the superconducting loop 412 of the superconducting device 404. When portions of the superconducting loops 408 and 412 run parallel to each other, portions of the superconducting loops 408 and 412 can lie on top of each other and / or be adjacent to each other. In some implementations, the superconducting loops 408 and 412 define traces in separate layers of a multilayer superconducting integrated circuit. The traces of the superconducting loops 408 and 412 may lie on top of each other and / or be adjacent to each other, and may be separated, for example, by an electrically insulating layer (e.g., a layer of dielectric material). The lying and / or adjacent portions of the superconducting loops 408 and 412 can generate mutual inductance, which can provide a directly inductively communicable coupling between the superconducting devices 402 and 404.

[0141] The excitation current 426 in the superconducting loop 412 can induce a current 428 in the superconducting loop 408.

[0142] The presence of crossovers 416 and 418 in the superconducting loop 408 causes the current flowing counterclockwise in the crossing region 420 to flow clockwise in the portion of the superconducting loop 408 outside the crossing region 420 (also referred to in this application as the body of the superconducting device 402). Mutual inductance M QQ The mutual inductance M AFM This increases the AFM coupling between superconducting devices 402 and 404.

[0143] In the cases of layouts 300 and 400 in Figures 3 and 4, respectively, the mutual inductance may be increased by increasing the length of the superconducting loops or traces lying over and / or adjacent to each other. The direct coupling generated between the bodies of two communicable coupled superconducting devices (e.g., superconducting devices 302 and 304 in Figure 3) combined with mediating coupling (e.g., by coupling device 306 in Figure 3) may result in communicable coupling between ferromagnetic, antiferromagnetic, or substantially zero-coupling superconducting devices. For example, zero coupling may occur if the mediating coupling and direct coupling cancel each other out.

[0144] This application includes a description of layouts that can accommodate an intersection region 420 in which a portion of the superconducting device 402 lies over a portion of the superconducting device 404 to provide coupling. For example, see the intersection region layouts shown in Figures 6B, 7B, 8B, and 8C, which are suitable for the layout 400 of Figure 4. Other layouts of the intersection region 420 with bypass paths may be used similarly. For example, by selective adjustment of the superconducting loops 408 and 412 during manufacturing, the magnitude of the direct-connectable coupling between the superconducting devices 402 and 404 can be controlled in some implementations, advantageously without incurring space disadvantages to the superconducting circuit.

[0145] Figure 5 is a schematic diagram of another exemplary layout 500. Layout 500 includes a pair of superconducting devices 502 and 504 that are coupled to each other in communication by a coupling device 506. To more clearly illustrate the intersection shape of the superconducting devices 502 and 504, superconducting device 502 is drawn with a solid line, while superconducting device 504 is drawn with a dotted line.

[0146] The superconducting device 502 includes a superconducting loop 508 that is interrupted by a Josephson junction 510. The superconducting device 504 includes a superconducting loop 512 that is interrupted by a Josephson junction 514.

[0147] The intersection shape of superconducting devices 502 and 504 in Figure 5 in or near the intersection region 516 is directly coupled between the superconducting loops 508 and 512 of superconducting devices 502 and 504, respectively. QQ This can be generated. For clarity, the intersection region 516 is shown as the molding region in Figure 5.

[0148] Each of the two portions of the superconducting loop 508 of the superconducting device 502 has an outward curved portion (defined as a curved portion away from the center of the loop) such that each curved portion 518 and 520 of the superconducting loop 508 is substantially parallel to a portion of the superconducting loop 512 of the superconducting device 504. If the portions of the superconducting loops 508 and 512 run parallel to each other (or at least non-orthogonal), the portions of the superconducting loops 508 and 512 may lie on top of each other and / or be adjacent to each other. In some implementations, the superconducting loops 508 and 512 define traces in separate layers of a multilayer superconducting integrated circuit. The traces of the superconducting loops 508 and 512 may lie on top of each other and / or be adjacent to each other, and may be separated, for example, by an electrical insulating layer (e.g., a layer of dielectric material). Some of the lying and / or adjacent portions of the superconducting loops 508 and 512 can generate mutual inductance, which can provide a direct inductively connectable coupling between the superconducting devices 502 and 504.

[0149] The excitation current 522 in the superconducting loop 512 can induce a current 524 in the superconducting loop 508.

[0150] If there is no crossover in the superconducting loop 508 (for example, crossovers 416 and 418 in the superconducting loop 408 in Figure 4), then a scenario can occur where the current flows counterclockwise in the crossing region 516 and counterclockwise in the portion of the superconducting loop 508 outside the crossing region 516 (also referred to in this application as the body of the superconducting device 502). Mutual inductance M QQThis can cause ferromagnetic (FM) coupling, resulting in mutual inductance M AFM This can be subtracted, thereby reducing the AFM coupling of superconducting devices 502 and 504 (e.g., AFM coupling mediated by coupling device 506).

[0151] A vector perpendicular to the plane containing the region of the superconducting loop 508 in the molded intersection region 516 has substantially the same orientation as both i) a vector perpendicular to the remaining region of the superconducting loop 508 of the superconducting device 502, and ii) a vector perpendicular to the region of the superconducting loop 512 of the superconducting device 504.

[0152] In some implementations, the superconducting devices 502 and 504 are superconducting qubits (e.g., superconducting flux qubits).

[0153] This application includes a description of layouts that can be adapted to an intersection region 516 in which a portion of the superconducting device 502 lies over a portion of the superconducting device 504 to provide coupling. For example, see the intersection region layouts shown in Figures 6B, 7B, 8B, and 8C, which are suitable for the layout 500 of Figure 5. Other layouts of the intersection region 516 with bypass paths may be used similarly. For example, by selective adjustment of the superconducting loops 508 and 512 during manufacturing, the magnitude of the direct-communication coupling between the superconducting devices 502 and 504 can be controlled in some implementations, advantageously without incurring space disadvantages to the superconducting circuit.

[0154] Figure 6A is a schematic diagram of an exemplary layout 600 of a pair of superconducting devices 602 and 604, which are connected to each other in a communicative manner, with each loop of each superconducting device having an inwardly curved portion in the intersection region, according to the system and method.

[0155] Layout 600 includes a pair of superconducting devices 602 and 604. Superconducting device 602 includes a superconducting loop 606 that is interrupted by a Josephson junction 608. Superconducting device 604 includes a superconducting loop 610 that is interrupted by a Josephson junction 612. The superconducting loops 606 and / or 610 may or may not be interrupted by each Josephson junction. Superconducting devices 602 and / or 604 may include other elements not shown in Figure 6A. Superconducting devices 602 and / or 604 may be superconducting qubits (e.g., superconducting flux qubits).

[0156] Although the coupling described with reference to Figure 6A is direct inductive coupling (i.e., without an intervening coupling device), the superconducting devices 602 and 604 may instead, or optionally, be coupled by galvanic coupling and / or mediation coupling via at least one intervening coupling device. The same applies to devices 702 and 704, 802 and 804, 902 and 904, and 1002 and 1004 in Figures 7A and 7B, 8A, 8B and 8C, 10, and 11, respectively.

[0157] Each of the superconducting devices 602 and 604 has inwardly curved portions 614 and 616, respectively (in this application, each inwardly curved portion is defined as a curve directed toward the center of each loop). The inwardly curved portions 614 and 616 are placed in the intersection region 618 at or near the point where the superconducting devices 602 and 604 intersect each other. The inwardly curved portions 614 and 616 are such that a portion of the superconducting loop 606 of the superconducting device 602 is substantially parallel (or at least non-orthogonal) to a portion of the superconducting loop 610 of the superconducting device 604 in regions 620, 622, 624, and 626 of layout 600.

[0158] If portions of the superconducting loops 606 and 610 run parallel to each other (or at least non-orthogonal), portions of the superconducting loops 606 and 610 can lie on top of each other and / or be adjacent to each other. In some implementations, the superconducting loops 606 and 610 define traces in separate layers of a multilayer superconducting integrated circuit. The traces of the superconducting loops 606 and 610 may lie on top of each other and / or be adjacent to each other, and may be separated, for example, by an electrically insulating layer (e.g., a layer of dielectric material). The lying and / or adjacent portions of the superconducting loops 606 and 610 can generate mutual inductance, which can provide a directly inductively communicable coupling between the superconducting devices 602 and 604. When describing in this application the act of lying on a portion of a superconducting loop to generate mutual inductance and direct inductive coupling, it will be apparent to those skilled in the art that the implementation can include lying on a portion of a superconducting loop and / or arranging portions of a superconducting loop adjacent to each other to generate mutual inductance and direct inductive coupling.

[0159] The excitation current flowing in direction 628 in the superconducting loop 610 can induce a current flowing in direction 630 in the superconducting loop 606.

[0160] Figure 6B is a schematic diagram of an example of the implementation configuration of the intersection region 618 of layout 600 in Figure 6A using the present system and method. The intersection region 618 includes the region where the superconducting loops 606 and 610 of the superconducting devices 602 and 604 in Figure 6A intersect each other.

[0161] The superconducting loops 606 and 610 overlap (for example, lying on top of each other in a multilayer superconducting integrated circuit) and run parallel to each other (or at least non-orthogonal) in each region 632, 634, 636, and 638.

[0162] Figure 6B shows an example of the layout of layout 600 in a plan view. In several implementations, layout 600 is manufactured in a multilayer superconducting integrated circuit using different layers for the superconducting loops 606 and 610. In several implementations, the layers are manufactured using a superconducting metal and separated by an insulating layer (e.g., a dielectric material layer). In several implementations, the superconducting loops 606 and 610 contain niobium. In several implementations, the superconducting loops 606 and 610 contain aluminum and / or another suitable superconducting material. In several implementations, the insulating layer contains silicon dioxide.

[0163] The superconducting loops 606 and 610 may be loops of superconducting wires. The superconducting wires may lie on top of each other in regions 632, 634, 636, and 638, which may provide a direct communication coupling between the superconducting devices 602 and 604. The fabrication of layout 600 may include methods for adjusting the superconducting wires to achieve the desired curvature and overlap (i.e., the degree to which the wires lie on top of each other). For example, in Figure 6B, regions 640, 642, and 644 of the left leg of the superconducting loop 606 are adjusted to produce the inward curved portion 616 in Figure 6A.

[0164] A superconducting loop in a superconducting integrated circuit (e.g., superconducting loop 606 in a multilayer superconducting integrated circuit of layout 600) may contain one or more traces of superconducting material. Each trace (also referred to herein as a superconducting trace) has a thickness and a width. The length of a superconducting trace is the length of the path through which current can flow. The width is defined as the perpendicular distance between opposing outer edges of a superconducting trace at any given point along its length. The width is the distance measured in the plane of the layer of the multilayer integrated circuit. The thickness is defined as being perpendicular to the length and width of the superconducting trace. The thickness is the distance measured in the stacking direction (i.e., perpendicular to the plane of the layer).

[0165] In this application, the description of a portion of a superconducting loop that is narrower within a region than outside the region means a trace of a portion of a superconducting loop that has a smaller width within the region than outside the region. A narrower trace occupies a smaller surface area on the integrated circuit than a wider trace of the same length.

[0166] In several implementation configurations (for example, the implementation configuration illustrated in Figure 6B), at least a portion of each superconducting loop 606 and 610 is narrower inside the intersection region 618 than outside the intersection region 618. That is, the width of each superconducting loop 606 and 610 inside the intersection region 618 is narrower than the width of each superconducting loop 606 and 610 outside the intersection region 618.

[0167] The fabrication of layout 600 may include generating detours for the superconducting traces of superconducting loops 606 and 610 inside the intersection region 618. A detour is a path between two points that takes a longer route than the most direct path (e.g., the shortest line). A detour may include one or more turns or changes of direction. For example, a detour between two points may include a straight path between the two points that is obstructed by a series of right-angle left turns, right-angle right turns, another right-angle right turn, and another right-angle left turn, followed by a straight path of appropriate length after each turn. In Figure 6B, for example, the path of the superconducting trace of superconducting loop 606 passing through the intersection region 618 makes four changes of direction in the direction of current 630, and the path makes a right-angle right turn, a right-angle left turn, another right-angle left turn, and another right-angle right turn.

[0168] The bypass path of the superconducting trace of superconducting loop 606 in the intersection region 618 may coincide with the bypass path of the superconducting trace of superconducting loop 610 in the intersection region 618.

[0169] For example, the magnitude of the direct-communication coupling between superconducting devices 602 and 604 can be controlled by selective tuning of superconducting loops 606 and 610 during manufacturing. For instance, the width of the superconducting wires of superconducting loops 606 and 610 in the intersection region 618 can be adjusted by selective tuning without incurring spatial disadvantages to the superconducting circuit. Selective tuning of the superconducting wires during manufacturing allows for adjustable tuning of the magnitude of the direct-communication coupling between superconducting devices 602 and 604, not merely as a discrete value, but over a continuous range. In one implementation configuration, the magnitude of the direct-communication coupling between two superconducting devices is adjustable from 0 to twice the magnitude of the mediation coupling by selectively tuning the superconducting trace and configuring it to follow an appropriate detour path. Tuning the superconducting trace reduces the trace width. In one implementation configuration, the superconducting trace can be selectively tuned from a width of 2 μm to a width of 0.5 μm.

[0170] Intermediate coupling is not shown in Figures 6A and 6B. Intermediate coupling can be implemented in combination with the layout 600 in Figures 6A and 6B by a coupling device (for example, coupling device 506 in Figure 5).

[0171] In several implementations, controlling the size of the direct connectable coupling between superconducting devices 602 and 604 includes determining a target size for the connectable coupling between superconducting devices 602 and 604, determining the difference between the size of the mediating connectable coupling and the target size, determining an adjustment tolerance based at least partially on the difference between the size of the mediating coupling and the target size, and adjusting the width of the superconducting traces of the superconducting loops 606 and 610 in the cross region 618.

[0172] As described above, the manufacturing of layout 600 may include methods for adjusting the superconducting traces to achieve the desired curvature and overlap (i.e., the degree to which the lines lie on top of each other). For example, in Figure 6B, region 642 of the superconducting loop 606 is adjusted by an adjustment tolerance of 646.

[0173] Figure 7A is a schematic diagram of another exemplary layout 700 of a pair of superconducting devices 702 and 704, which are connected to each other in a communicative manner, with each loop of each superconducting device having an outwardly curved portion in the intersection region, according to the system and method.

[0174] Layout 700 includes a pair of superconducting devices 702 and 704. Superconducting device 702 includes a superconducting loop 706 which is interrupted by a Josephson junction 708. Superconducting device 704 includes a superconducting loop 710 which is interrupted by a Josephson junction 712.

[0175] Each of the superconducting devices 702 and 704 has outward-curving portions 714 and 716, respectively (in this application, each outward-curving portion is defined as a curved portion located away from the center of each superconducting loop). The outward-curving portions 714 and 716 are placed in the intersection region 718 at or near the point where the superconducting devices 702 and 704 intersect each other. The outward-curving portions 714 and 716 are such that a portion of the superconducting loop 706 of the superconducting device 702 is substantially parallel (or at least non-orthogonal) to a portion of the superconducting loop 710 of the superconducting device 704 in regions 720, 722, 724, and 726 of layout 700.

[0176] If portions of the superconducting loops 706 and 710 run parallel to each other (or at least non-orthogonal), portions of the superconducting loops 706 and 710 can lie on top of each other and / or be adjacent to each other. In some implementations, the superconducting loops 706 and 710 define traces in separate layers of a multilayer superconducting integrated circuit. The traces of the superconducting loops 706 and 710 may lie on top of each other and / or be adjacent to each other, and may be separated, for example, by an electrically insulating layer (e.g., a layer of dielectric material). The lying and / or adjacent portions of the superconducting loops 706 and 710 can generate mutual inductance, which can provide a directly inductively communicable coupling between the superconducting devices 702 and 704.

[0177] The excitation current flowing in direction 728 in the superconducting loop 710 can induce a current flowing in direction 730 in the superconducting loop 706.

[0178] Figure 7B is a schematic diagram of an example of the implementation configuration of the intersection region 718 of layout 700 in Figure 7A using the present system and method. The intersection region 718 includes the region where the superconducting loops 706 and 710 of the superconducting devices 702 and 704 in Figure 7A intersect with each other.

[0179] The superconducting loops 706 and 710 overlap (for example, lying on top of each other in a multilayer superconducting integrated circuit) and run parallel to each other (or at least non-orthogonal) in each region 732, 734, 736, and 738.

[0180] Figure 7B shows an example of the layout of layout 700 in a plan view. In several implementations, layout 700 is manufactured in a multilayer superconducting integrated circuit using different layers for the superconducting loops 706 and 710. In several implementations, the layers are manufactured using a superconducting metal and separated by an insulating layer (e.g., a dielectric material layer). In several implementations, the superconducting loops 706 and 710 contain niobium. In several implementations, the superconducting loops 706 and 710 contain aluminum and / or another suitable superconducting material. In several implementations, the insulating layer contains silicon dioxide.

[0181] The superconducting loops 706 and 710 may be loops of superconducting wires. The superconducting wires may lie on top of each other in regions 732, 734, 736, and 738, which may provide a direct communication coupling between the superconducting devices 702 and 704. The fabrication of layout 700 may include methods for adjusting the superconducting wires to achieve the desired curvature and overlap (i.e., the degree to which the wires lie on top of each other). For example, in Figure 7B, regions 740, 742, and 744 of the right leg of the superconducting loop 706 are adjusted to produce the outward curved portion 716 in Figure 7A.

[0182] The fabrication of layout 700 may include generating detours for the superconducting traces of superconducting loops 706 and 710 inside the crossing region 718.

[0183] For example, the magnitude of the direct-connectable coupling between superconducting devices 702 and 704 can be controlled by selectively adjusting the superconducting loops 706 and 710 during manufacturing. For instance, the width of the superconducting wires of superconducting loops 706 and 710 in the intersection region 718 can be adjusted by selective adjustment without incurring spatial disadvantages to the superconducting circuit. Selective adjustment of the superconducting wires allows for adjustable tuning of the magnitude of the direct-connectable coupling between superconducting devices 702 and 704, not merely as a discrete value, but over a continuous range. In one implementation configuration, the magnitude of the direct-connectable coupling between two superconducting devices is adjustable from 0 to twice the magnitude of the mediating coupling by selectively adjusting the superconducting trace and configuring it to follow an appropriate detour path. In one implementation configuration, the superconducting trace can be selectively adjusted from a width of 2 μm to a width of 0.5 μm.

[0184] Selective adjustment of the superconducting trace may be achieved by an appropriate adjustment width etching process. The adjustment width etching process may include, for example, depositing a first hard mask layer on a layer of superconducting material, depositing a second hard mask layer on the first hard mask layer, depositing a photoresist layer on the second hard mask layer, forming a pattern on the photoresist layer, transferring the pattern to the second hard mask layer, and adjusting the second hard mask layer with the photoresist layer on top of the second hard mask layer. During adjustment width etching, the top surface of the second hard mask layer is protected by the photoresist, and the substrate is protected by the first hard mask layer lying on top of it.

[0185] The fabrication of superconducting traces with a desired width may be achieved by depositing superconducting material.

[0186] Intermediate coupling is not shown in Figures 7A and 7B. Intermediate coupling can be implemented in combination with the layout 700 in Figures 7A and 7B by a coupling device (for example, coupling device 506 in Figure 5).

[0187] Figure 8A is a schematic diagram of another exemplary layout 800 of a pair of superconducting devices 802 and 804, which are connected to each other in a communicative manner, with each loop of each superconducting device having numerous curved sections in the intersecting region, according to the system and method.

[0188] Layout 800 includes a pair of superconducting devices 802 and 804. Superconducting device 802 includes a superconducting loop 806 which is interrupted by a Josephson junction 808. Superconducting device 804 includes a superconducting loop 810 which is interrupted by a Josephson junction 812. Superconducting devices 802 and 804 intersect each other in an intersection region 814 (shown as a shaded area in Figure 8A).

[0189] The excitation current flowing in direction 816 in the superconducting loop 810 can induce a current (not shown in Figure 8A) in the superconducting loop 806.

[0190] Figure 8B is a schematic diagram of an example of the implementation configuration of the intersection region 814 of layout 800 in Figure 8A using the present system and method. The intersection region 814 includes the region where the superconducting loops 806 and 810 of the superconducting devices 802 and 804 in Figure 8A intersect with each other.

[0191] The superconducting loops 806 and 810 overlap (for example, lying on top of each other in a multilayer superconducting integrated circuit) and run parallel to each other (or at least non-orthogonal) in each region 820, 822, 824, and 826.

[0192] Figure 8B shows an example of the layout of layout 800 in a plan view. In several implementations, layout 800 is manufactured in a multilayer superconducting integrated circuit using different layers for the superconducting loops 806 and 810. In several implementations, the layers are manufactured using a superconducting metal and separated by an insulating layer of dielectric material. In several implementations, the superconducting loops 806 and 810 contain niobium. In several implementations, the superconducting loops 806 and 810 contain aluminum and / or another suitable superconducting material. In several implementations, the insulating layer contains silicon dioxide.

[0193] The superconducting loops 806 and 810 may be loops of superconducting wires. The superconducting wires may lie on top of each other in regions 820, 822, 824, and 826, which may provide a direct communication coupling between the superconducting devices 802 and 804. The fabrication of layout 800 may include methods for adjusting the superconducting wires to achieve the desired curvature and overlap (i.e., the degree to which the wires lie on top of each other). For example, in Figure 8B, the regions 828, 830, 832, 834, 836, and 838 of the right leg of the superconducting loop 806 are adjusted to generate a detour path through the intersection region 814.

[0194] The fabrication of layout 800 may include generating detours for the superconducting traces of superconducting loops 806 and 810 inside the intersection region 814.

[0195] For example, the size of the direct-connectable coupling between superconducting devices 802 and 804 can be controlled by selective tuning of superconducting loops 806 and 810 during manufacturing. For instance, it is possible to adjust the width of the superconducting wires of superconducting loops 806 and 810 in the intersection region 814 by selective tuning without incurring spatial disadvantages to the superconducting circuit. Selective tuning of the superconducting wires allows for adjustable tuning (during manufacturing) of the size of the direct-connectable coupling between superconducting devices 802 and 804 over a continuous range, not just a discrete value. In order to change the size of the direct coupling using the previous method, it is generally necessary to change the layout of the integrated circuit and / or the area occupied by the integrated circuit. These changes typically constrain the size of the direct coupling to a discrete value.

[0196] In one implementation, the magnitude of the direct communication coupling between two superconducting devices can be adjusted from 0 to twice the magnitude of the mediation coupling by selectively adjusting the superconducting trace and configuring it to follow an appropriate detour path. In one implementation, the superconducting trace can be selectively adjusted from a width of 2 μm to 0.5 μm.

[0197] Figure 8C is a schematic diagram of another example of the implementation of the intersection region 814 of layout 800 in Figure 8A according to the present system and method. The intersection region 814 includes the region where the superconducting loops 806 and 810 of the superconducting devices 802 and 804 in Figure 8A intersect each other. The induced current 840 flows in the direction indicated by the arrow in the superconducting loop 806, and the excitation current 816 flows in the direction indicated by the arrow in the superconducting loop 810.

[0198] The superconducting loops 806 and 810 overlap (for example, lying on top of each other in a multilayer superconducting integrated circuit) and run parallel to each other (or at least non-orthogonal) in each region 842, 844, 846, and 848.

[0199] Figure 8C shows an example of the layout of layout 800 in a plan view. In several implementations, layout 800 is fabricated in a multilayer superconducting integrated circuit using different layers for the superconducting loops 806 and 810. In several implementations, the layers are fabricated using superconducting metals and separated by intercalating layers. In several implementations, the intercalating layers include an insulating layer of dielectric material. In several implementations, the superconducting loops 806 and 810 contain niobium. In several implementations, the superconducting loops 806 and 810 contain aluminum and / or another suitable superconducting material. In several implementations, the insulating layer contains silicon dioxide and / or silicon nitride. In several implementations, the integrated circuit air bridge insulates the superconducting loops 806 and 810. A typical air bridge can be formed using layers of metal deposited and patterned on a sacrificial material. Subsequently, the sacrificial material can be removed, leaving a metal trace that is at least partially insulated from other metal traces or properties by a fluid (e.g., air) rather than a dielectric (e.g., silicon dioxide).

[0200] The superconducting loops 806 and 810 may be loops of superconducting wires. The superconducting wires may lie on top of each other in regions 842, 844, 846, and 848, which may provide a direct communication coupling between the superconducting devices 802 and 804. The fabrication of layout 800 may include methods for adjusting the superconducting wires to achieve the desired curvature and overlap (i.e., the degree to which the wires lie on top of each other). For example, in Figure 8B, regions 850, 852, and 854 of the right leg of the superconducting loop 806 are adjusted to generate a detour path through the intersection region 814.

[0201] The fabrication of layout 800 may include generating detours for the superconducting traces of superconducting loops 806 and 810 inside the intersection region 814.

[0202] For example, the magnitude of the direct-connectable coupling between superconducting devices 802 and 804 can be controlled by selectively adjusting the superconducting loops 806 and 810 during manufacturing. For instance, the width of the superconducting wires of superconducting loops 806 and 810 in the intersection region 814 can be adjusted by selective adjustment without incurring spatial disadvantages to the superconducting circuit. Selective adjustment of the superconducting wires allows for adjustable tuning of the magnitude of the direct-connectable coupling between superconducting devices 802 and 804 over a continuous range, not just a discrete value. In one implementation configuration, the magnitude of the direct-connectable coupling between two superconducting devices is adjustable from 0 to twice the magnitude of the mediating coupling by selectively adjusting the superconducting trace and configuring it to follow an appropriate detour path. In one implementation configuration, the superconducting trace can be selectively adjusted from a width of 2 μm to a width of 0.5 μm.

[0203] Intermediate coupling is not shown in Figures 8A, 8B, and 8C. Intermediate coupling can be implemented in combination with the layout 800 in Figures 8A, 8B, and 8C by a coupling device (for example, coupling device 506 in Figure 5).

[0204] One benefit of the system and method of this application is improved robustness against manufacturing errors and / or misalignment. Another benefit of the system and method of this application is improved synchronization of the layout of a superconducting integrated circuit and / or direct communicable couplings between superconducting devices during manufacturing, without affecting the amount of space used by superconducting devices and / or other devices on the superconducting integrated circuit.

[0205] Another benefit of the system and method of this application is the reduction of crosstalk to adjacent devices. The implementation described in this application is smaller, more integrated, and more symmetrical than previous methods, resulting in little to no crosstalk to adjacent devices.

[0206] The cross region layouts shown in Figures 6B, 7B, 8B, and 8C are suitable for use in any of the above arrangements when a portion of the first superconducting device lies on top of a portion of the second superconducting device to provide coupling, and other cross region layouts with bypass paths can be used in a similar manner.

[0207] Figure 9 is a schematic diagram of topology 900 of an exemplary superconducting quantum processor according to the present disclosure. For example, a superconducting quantum processor having topology 900 may be used for quantum annealing and / or adiabatic quantum computing.

[0208] The coupled layout described above with reference to Figures 1, 2, 3, 4, 5, 6A, 6B, 7A, 7B, 8A, 8B, and 8C, and Figures 10 and 11 described later, may be used in a superconducting quantum processor having topology 900. Furthermore, the coupled layout may be used in a superconducting quantum processor and / or other superconducting integrated circuit having another suitable topology.

[0209] Topology 900 includes multiple qubits, for example, qubits 902a, 902b, 902c, and 902d (collectively referred to as qubit 902). Qubits 902 are shown as points in topology 900 in Figure 9. In one implementation, each qubit in the first subset of qubit 902 includes its own elongated superconducting loop oriented in a first direction, and each qubit in the second subset includes its own elongated superconducting loop oriented in a second direction that is at least substantially orthogonal to the first direction.

[0210] Furthermore, topology 900 includes multiple coupling devices, for example, coupling devices 904a, 904b, and 904c (collectively referred to as coupling device 904). The coupling device 904 is shown as a line in topology 900 in Figure 9. The coupling device 904 can provide a communicable coupling between pairs of qubits 902.

[0211] Each qubit 902 contains an elongated superconducting loop having a long axis and a short axis. The orientation of the qubit may be defined as the direction of the long axis.

[0212] The qubits 902a and 902b are oriented at least substantially orthogonal to each other. That is, the long axes of their respective elongated superconducting loops are oriented at least substantially orthogonal to each other. A coupling device 904a (also referred to in this application as an internal coupling device) can provide a communicable coupling between the qubits 902a and 902b. Figures 1, 2, 3, 4, 5, 6A, 6B, 7A, 7B, 8A, 8B, and 8C include examples of superconducting devices (e.g., qubits) oriented at least substantially orthogonal to each other and coupled by an intermediary coupling device called an internal coupling device in the architecture of Figure 9.

[0213] The qubits 902b and 902c are oriented at least substantially parallel to each other. That is, the long axes of the elongated superconducting loops of each qubit 902c and 902d are oriented at least substantially parallel to each other. The qubits 902c and 902d are in the same row or column of qubits in topology 900. The coupling device 904b can provide a communicable coupling between the qubits 902b and 902c.

[0214] The qubits 902a and 902d are oriented at least substantially parallel to each other. That is, the long axes of the elongated superconducting loops of each qubit 902a and 902d are oriented at least substantially parallel to each other. The qubits 902a and 902d are in adjacent rows or columns of qubits in topology 900. The coupling device 904c can provide a communicable coupling between the qubits 902a and 902d.

[0215] In topology 900, each qubit can be coupled in a communicative manner to 12 orthogonal oriented qubits, and can be coupled in a communicative manner to a total of 15 qubits, including the 12 orthogonal oriented qubits. Communicative coupling between pairs of qubits in topology 900 can include direct coupling and / or mediated coupling by an intermediate coupling device.

[0216] Figures 6A, 6B, 7A, 7B, 8A, 8B, and 8C illustrate a pair of superconducting devices (e.g., qubits) having at least a portion of superconducting loops of superconducting devices that run orthogonal to each other (at least not parallel). The superconducting loops intersect each other in projection in each intersection region. In the intersection region, portions of the superconducting traces of the superconducting loops can be arranged to run parallel to each other (or at least non-orthogonal) and can be arranged close enough that a current flowing through one of the pair of superconducting loops induces a current in the other superconducting loop (i.e., portions of the superconducting traces of the superconducting loops can be arranged to be inductively close to each other).

[0217] In other implementations, the long axes of the superconducting loops in a superconducting device run parallel to each other (or at least non-orthogonal). In some of these implementations, the loops are arranged in parallel, at least partially, and in the rest of these implementations, the loops are arranged in series. Some of the superconducting loops can be inductively close to each other, that is, they can be arranged close enough that a current flowing through one of a pair of superconducting loops induces a current in the other superconducting loop.

[0218] Figure 10A is a schematic diagram of another exemplary layout 1000 of a pair of superconducting devices 1002 and 1004 that are directly coupled to each other according to the present system and method.

[0219] Each superconducting device 1002 and 1004 includes each superconducting loop 1006 and 1008. The superconducting loops 1002 and 1004 are arranged in series. Each superconducting loop 1006 and 1008 may be separated by each Josephson junction 1010 and 1012. The superconducting devices 1002 and 1004 may be superconducting qubits (e.g., superconducting flux qubits). The superconducting loops 1006 and 1008 may be located in the same layer or plane or in different layers or planes. In addition to being directly inductively coupled to each other, the superconducting devices 1002 and 1004 may be coupled in communication by a mediating coupling device (e.g., coupling device 904b in Figure 9). For clarity, the mediating coupling device is not shown in Figure 10A.

[0220] Layout 1000 includes an association region 1014. The association region 1014 is a region of the integrated circuit in which parts of the superconducting loops 1006 and 1008 of the superconducting devices 1002 and 1004 in Figure 10A are inductively close to each other. In this application, the two superconducting devices are inductively close to each other if the two superconducting devices are appropriately oriented relative to each other and arranged close enough that the first superconducting device of the two superconducting devices is directly inductively coupled to the second superconducting device of the two superconducting devices when current flows through the superconducting loop of the first superconducting device.

[0221] The superconducting devices 1002 and 1004 can be directly inductively coupled to each other in the association region 1014. For example, the excitation current flowing through the superconducting loop 1006 can induce a current flowing through the superconducting loop 1008.

[0222] Parts of the superconducting loops 1006 and 1008 run parallel to each other (or at least non-orthogonal) and inductively approach each other in the association region 1014.

[0223] Layout 1000 of Figure 10 can be implemented using superconducting loops 1006 and 1008 fabricated in the same layer of the superconducting integrated circuit. The superconducting integrated circuit may be a multilayer superconducting integrated circuit. In some implementations, the layers are fabricated using a superconducting metal and separated by an insulating layer of dielectric material. The superconducting loops 1006 and 1008 may contain niobium, aluminum and / or another suitable superconducting material. The insulating layer may contain silicon dioxide.

[0224] The superconducting loops 1006 and 1008 may be loops of superconducting wires. The superconducting wires can be implemented, for example, as one or more superconducting traces in a wiring layer in a fabrication stack. Superconducting traces may also be called interconnection lines. The width of the superconducting traces may also be called the line width of the interconnection lines.

[0225] The fabrication of layout 1000 may include a method of arranging the superconducting traces such that at least a portion of the traces are inductively close to each other, i.e., run parallel to each other, or at least non-orthogonal, and are dense enough for the current flow in one trace to directly induce the current flow in the other trace. The association region 1014 may include traces that are attached and / or arranged to generate bypass paths for portions of the superconducting loops 1006 and 1008 passing through the association region 1014.

[0226] For example, during manufacturing, by selectively depositing and / or adjusting superconducting loops 1006 and 1008, the magnitude of the directly communicable coupling of superconducting devices 1002 and 1004 can be controlled. For example, it is possible to achieve adjusting the width of the superconducting traces of superconducting loops 1006 and 1008 in the meeting area 1014 by selective adjustment without suffering spatial disadvantages for the superconducting circuit. The selective adjustment of the superconducting traces can perform adjustable tuning of the magnitude of the directly communicable coupling of superconducting devices 1002 and 1004 not only at discrete values but also over a continuous range. In one implementation, the magnitude of the directly communicable coupling between two superconducting devices can be adjusted over a range from 0 to twice the magnitude of the mediating coupling by selectively adjusting the superconducting traces and configuring the superconducting traces to follow appropriate detour paths. In one implementation, the superconducting traces are selectively adjusted from a width of 2 μm to a width of 0.5 μm.

[0227] FIG. 10B is a schematic diagram of an example implementation of the meeting area 1014 of the layout 1000 of FIG. 10A according to the present system and method. The meeting area 1014 includes areas 1016 where the superconducting traces of each superconducting loop 1006 and 1008 follow each detour path.

[0228] FIG. 11 is a schematic diagram of another exemplary layout 1100 of a pair of superconducting devices 1102 and 1104 that are directly communicably coupled to each other according to the present system and method.

[0229] Each superconducting device 1102 and 1104 includes each superconducting loop 1106 and 1108. The superconducting loops 1102 and 1104 are arranged at least partially in parallel. Each superconducting loop 1106 and 1108 may be interrupted by each Josephson junction 1110 and 1112. The superconducting devices 1102 and 1104 may be superconducting qubits (e.g., superconducting flux qubits). The superconducting devices 1102 and 1104 may be communicably coupled by a mediating coupling device (e.g., one of the coupling devices 904 in FIG. 9).

[0230] At least a part of the superconducting loops 1106 and 1108 of the superconducting devices 1102 and 1104 in FIG. 11 are inductively close to each other in the meeting area 1114. The superconducting devices 1102 and 1104 can be directly inductively coupled to each other in the area 1110. For example, the exciting current flowing through the superconducting loop 1106 can make an induced current flow through the superconducting loop 1108.

[0231] At least a part of the superconducting loops 1106 and 1108 run parallel to each other (or at least non - orthogonally) in the area 1110, and the flow of current in a part of the superconducting loop 1106 is dense enough to directly induce the flow of current in a part of the superconducting loop 1108.

[0232] The layout 1100 in FIG. 11 can be implemented using the superconducting loops 1106 and 1108 manufactured in the same layer of a superconducting integrated circuit. The superconducting integrated circuit may be a multi - layer superconducting integrated circuit. In some implementation forms, the layers are manufactured using superconducting metals and separated by insulating layers of dielectric materials. The superconducting loops 1106 and 1108 may include niobium, aluminum and / or other suitable superconducting materials. The insulating layer may include silicon dioxide. Instead, the layout 1100 can be implemented using the superconducting loops 1106 and 1008 manufactured in different layers of a multi - layer superconducting integrated circuit.

[0233] The superconducting loops 1106 and 1108 may be loops of superconducting wires. The loop of superconducting wire can include one or more superconducting traces. The manufacture of the layout 1100 may include a method of adjusting the superconducting traces so that at least a part of the superconducting traces are inductively close to each other. The area 1110 may include traces that are attached and / or adjusted to generate a detour path for a part of the superconducting loops 1106 and 1108 passing through the area 1110.

[0234] Similar to the method described above with reference to Figure 10, the magnitude of the direct-communication coupling between superconducting devices 1102 and 1104 can be controlled, for example, by selective adjustment and / or attachment of superconducting loops 1106 and 1108 during manufacturing. For example, it is possible to adjust the width of the superconducting wires of superconducting loops 1106 and 1108 in region 1110 by selective adjustment without incurring spatial disadvantages to the superconducting circuit. Selective adjustment of the superconducting wires allows for adjustable tuning of the magnitude of the direct-communication coupling between superconducting devices 1102 and 1104 over a continuous range, not merely a discrete value. In one implementation configuration, the magnitude of the direct-communication coupling between two superconducting devices is adjustable from 0 to twice the magnitude of the mediation coupling by selectively adjusting the superconducting wires and configuring them to follow appropriate detour paths. In one implementation configuration, the superconducting wires are selectively adjusted from a width of 2 μm to a width of 0.5 μm.

[0235] Figure 11B is a schematic diagram of an example of an implementation of the meeting region 1114 of layout 1100 in Figure 11A using the present system and method. The meeting region 1114 includes the region 1116 through which the superconducting traces of each superconducting loop 1106 and 1108 follow their respective detour paths.

[0236] Figure 12 shows an example of a hybrid computing system 1200, which includes a digital computer 1202 coupled to an analog computer 1204. In some implementations, the analog computer 1204 is a quantum computer, and the digital computer 1202 is a classical computer.

[0237] An exemplary digital computer 1202 includes at least one digital processor 1206, each digital processor 1206 may include one or more central processing units (not shown in Figure 12). Figure 12 shows a digital processor 1206 with only one digital processor. The classic digital processing tasks described in this system and method may be performed using the digital processors 1206. In other implementations, the digital computer 1202 may include more than one digital processor. Those skilled in the art will see that this system and method can be carried out using other digital computers, including handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, personal computers ("PCs"), network PCs, minicomputers, mainframe computers, etc., when they are appropriately configured or programmed to form a dedicated machine and / or coupled in a communicative manner to control an analog computer (e.g., a quantum computer).

[0238] Although the digital computer 1202 is sometimes described singly here, this is not intended to limit the application to a single digital computer. The system and method can also be implemented in a distributed computing environment in which a set of tasks or instructions are performed or executed by remote processing devices linked over a communication network. In a distributed computing environment, computer or processor-readable instructions (also referred to here as program modules), application programs and / or data may be stored in both local and remote memory storage devices (e.g., persistent computers or processor-readable media).

[0239] The digital computer 1202 may include at least one digital processor 1206, at least one system memory 1208, and at least one system bus 1210 that provides communicative coupling between various system components (e.g., between the system memory 1208 and the digital processor 1206). The system memory 1208 may include non-volatile memory (e.g., read-only memory ("ROM"), static random-access memory ("SRAM"), flash NAND), and volatile memory (e.g., random-access memory ("RAM")) (not shown), all of which are examples of persistent computer or processor-readable media. The system bus 1210 may use any known bus structure or architecture, including a memory bus, peripheral bus, and local bus, each having a memory controller.

[0240] The digital processor 1206 may be, for example, any logic processing unit having one or more cores (e.g., one or more central processing units ("CPU"), graphics processing units ("GPU"), digital signal processors ("DSP"), application-specific integrated circuits ("ASIC"), programmable gate arrays ("FPGA"), etc.).

[0241] Unless otherwise stated, the configuration and operation of the various blocks shown in Figure 12 are conventional designs. As such, those skilled in the art will understand these blocks, and therefore there is no need to describe them in more detail here.

[0242] The digital computer 1202 may include a user input / output subsystem 1212. In some implementations, the user input / output subsystem includes one or more user input / output components (e.g., a display 1214, a mouse 1216, and / or a keyboard 1218).

[0243] A basic input / output system ("BIOS") 1220, which may form part of the ROM, includes, for example, basic routines that assist in the transfer of information between elements within the digital computer 1202 during startup.

[0244] Furthermore, the digital computer 1202 may include other non-volatile memory 1222. The non-volatile memory 1222 may take various forms, including a hard disk drive for reading and writing to a hard disk, an optical disk drive for reading and writing to a removable optical disk, and / or a magnetic disk drive for reading and writing to a magnetic disk, all of which are examples of persistent computer or processor-readable media. The optical disk may be a CD-ROM or DVD, while the magnetic disk may be a magnetic floppy disk or diskette. The non-volatile memory 1222 may communicate with the digital processor via the system bus 1210 and may include a suitable interface or controller 1224 coupled to the system bus 1210. The non-volatile memory 1222 may function as long-term storage for computer or processor-readable instructions, data structures, or other data for the digital computer 1202 (also known as program modules).

[0245] Although the digital computer 1202 is described as using hard disks, optical disks and / or magnetic disks, those skilled in the art will see that other types of non-volatile computer-readable media (such as magnetic cassettes, flash memory cards, flash memory, ROM, smart cards, etc., all of which are further examples of persistent computer or processor-readable media) may be used. Those skilled in the art will see that some computer architectures combine volatile and non-volatile memory. For example, data in volatile memory can be cached in non-volatile memory. Alternatively, solid-state disks may use integrated circuits to provide non-volatile memory. Some computers place data conventionally stored on disks in memory. Similarly, some media conventionally considered volatile may have non-volatile forms (e.g., a variation of a dual in-line memory module, such as a non-volatile dual in-line memory module).

[0246] Various sets of computer or processor-readable instructions (also referred to in this application as program modules), application programs, and / or data can be stored in the system memory 1208. For example, the system memory 1208 may store an operating system 1226 and a set of computer or processor-readable server instructions (i.e., server modules) 1228. In some implementations, the server module 1228 includes instructions for communicating with a remote client and scheduling the use of resources, including resources on the digital computer 1202 and the analog computer 1204. For example, a web server application and / or web client or browser application on which the digital computer 1202 can exchange data with other server applications running on the source and server computers via the Internet, a corporate intranet, or other network.

[0247] In some implementations, the system memory 1208 may store other sets of computer or processor-readable instructions 1230 (e.g., calculation instructions, analog computer interface instructions, etc.).

[0248] Although Figure 12 shows that server instructions 1228, other instructions 1230, and other data (not shown in Figure 12) are stored in system memory 1208, they may also be stored in non-volatile memory 1222, or in other locations including one or more other persistent computer or processor-readable media.

[0249] The analog computer 1204 can be placed in an isolated environment (not shown in Figure 12). For example, if the analog computer 1204 is a quantum computer, the isolated environment shields the internal components of the quantum computer from heat, magnetic fields, and other external noise (not shown in Figure 12), and / or cools the analog processor 1204 to a temperature at or below which the circuits of the analog processor 1204 become superconducting. In contrast, the digital computer 1202 typically operates at very high temperatures where superconductivity does not occur (e.g., room temperature), and / or can use materials that are not superconducting even at or below the critical temperature. The analog computer 1204 includes an analog processor 1232. An example of the analog processor 1232 includes a quantum processor (e.g., a superconducting quantum processor).

[0250] A quantum processor includes programmable elements (e.g., qubits, couplers, and other devices). Qubits can be read out via a readout system 1234. Readout values can be supplied to various sets of computer or processor-readable instructions for a digital computer 1202, including a server module 1228 or other modules 1230 stored in a non-volatile memory 1222 returned on a network or the like. Qubits can be controlled via a qubit control system 1236. In some implementations, a qubit control system 1236 and a coupler control system 1238 are used to perform quantum annealing with an analog processor 1232 as described in this application. In some implementations, the analog processor 1232 includes a conductive integrated circuit 1240 including superconducting qubits having mediated and / or direct qubit-qubit couplings according to the various implementations described above.

[0251] In some implementations, the digital computer 1202 can operate in a networking environment using logical connections to at least one client computer system. In some implementations, the digital computer 1202 is connected via logical connections to at least one database system. These logical connections may be formed using any means of digital communication over a network, such as a local area network ("LAN") or wide area network ("WAN"), including the Internet. The networking environment may include wired or wireless enterprise-scale computer networks, intranets, extranets, and / or the Internet. Other embodiments may include other types of communication networks (e.g., telecommunications networks, cellular networks, paging networks, and other mobile networks). Information transmitted or received over the logical connections may or may not be encrypted. When used in a LAN networking environment, the digital computer 1202 may be connected to the LAN via an adapter or network interface card ("NIC") (communicatively linked to the system bus 1210). When used in a WAN networking environment, the digital computer 1202 may include an interface and modem (not shown), or a device for establishing communication over the WAN (e.g., a NIC). Alternatively, non-networked communication may be used.

[0252] Figure 13A is a cross-section of a portion of a superconducting integrated circuit 1300a according to the present system and method. The superconducting integrated circuit 1300a includes a substrate 1302. The substrate 1302 may be, for example, a silicon substrate or a layer of dielectric material. Furthermore, the superconducting integrated circuit 1300a includes a pair of superconducting traces 1304 and 1306 separated from each other by an intervening layer 1308, with superconducting trace 1306 lying on top of superconducting trace 1304. The superconducting traces 1304 and 1306 may contain or consist of a superconducting metal (e.g., niobium or aluminum). The superconducting traces 1304 and 1306 may be adjacent to layers of dielectric material 1310 and 1312, respectively. The intervening layer 1308 may be an insulating layer. The insulating layer may contain a layer of dielectric material or an air bridge. The thickness of the intervening layer 1308 may be selected so that the superconducting traces 1304 and 1306 are directly inductively coupled to each other.

[0253] Figure 13B is a cross-section of a portion of a superconducting integrated circuit 1300b according to the present system and method. The superconducting integrated circuit 1300b includes a substrate 1314. The substrate 1314 may be, for example, a silicon substrate or a layer of dielectric material. Furthermore, the superconducting integrated circuit 1300b includes a pair of adjacent superconducting traces 1316 and 1318 separated from each other by an intervening layer 1320. The superconducting traces 1316 and 1318 may include or consist of a superconducting metal (e.g., niobium or aluminum). The superconducting traces 1316 and 1318 may be adjacent to an upper layer of dielectric material 1322. The intervening layer 1320 may be an insulating layer. The insulating layer includes a layer of dielectric material or an air bridge. The separation of adjacent superconducting traces 1316 and 1318 by the intervening layer 1320 may be chosen to allow the superconducting traces 1316 and 1318 to be directly inductively coupled to each other.

[0254] In Figure 13A, superconducting traces 1304 and 1306 lie on top of each other. Superconducting traces 1304 and 1306 are separated by an intervening layer 1308. Superconducting traces 1304 and 1306 can be inductively brought close to each other, that is, they can be appropriately oriented and sufficiently densely arranged so that a current in superconducting trace 1304 can induce a current in superconducting trace 1306 (and vice versa) regardless of the orientation of the superconducting integrated circuit. In Figure 13B, superconducting traces 1316 and 1318 are adjacent to each other. Superconducting traces 1316 and 1318 are separated by an intervening layer 1320. Superconducting traces can be inductively brought close to each other, that is, they can be appropriately oriented and sufficiently densely arranged so that a current in superconducting trace 1316 can induce a current in superconducting trace 1318 (and vice versa) regardless of the orientation of the superconducting integrated circuit.

[0255] Figure 14A is a flowchart of an example of method 1400 for forming an integrated circuit using the present system and method. Those skilled in the art will see that in alternative implementations, certain operations may be omitted and / or additional operations may be added, but method 1400 includes operations 1402-1418. Those skilled in the art will see that the order in which the operations are illustrated is shown for illustrative purposes only and may vary in alternative implementations.

[0256] In 1402, method 1400 is invoked. In some implementations, method 1400 is invoked when the manufacturing system is ready to start manufacturing an integrated circuit or to continue manufacturing a partially completed integrated circuit. In 1404, the system determines the target size of the connectable coupling between a pair of devices (e.g., superconducting devices) on the integrated circuit. In 1406, the system determines the difference between the size of the mediatically connectable coupling and the target size. The mediatically connectable coupling may be provided by a mediating coupling device (e.g., one of the coupling devices 904 in Figure 9).

[0257] In 1408, the system determines an adjustment tolerance (also referred to in this application as adjustment range) based at least in part on the difference between the size of the mediating coupling and the size of the target. The adjustment range determined in 1408 is referred to as the determined adjustment range with reference to Figure 14B.

[0258] At 1410, the system deposits a first loop of material (e.g., a superconducting metal), and at 1412, the system deposits a second loop of material. In some implementations, the system deposits the first and second loops of material to achieve predetermined communicable couplings and / or bypass paths, including trace narrowing, in the intersection or meeting regions, as described above. In other implementations, the system performs adjustment width etching to form a first path at 1414 and a second path at 1416.

[0259] At 1418, the method ends.

[0260] Figure 14B is a flowchart of an example of Method 1419 for adjusting the first path 1414 of Method 1400 (Figure 14A) according to the present system and method. Although those skilled in the art will see that certain operations may be omitted and / or additional operations may be added in alternative implementations, Method 1419 includes operations 1420-1428. Those skilled in the art will see that the order in which the operations are illustrated is shown for illustrative purposes only and may change in alternative implementations. Using a similar method, adjustment width etching can be performed to form a second path 1416 of Method 1400 (Figure 14A).

[0261] At 1420, the system applies a first hard mask, and at 1422, the system applies a second hard mask. At 1424, the system applies a photoresist layer, and at 1426, the photoresist layer is patterned. At 1428, the system performs etching to remove material from the first path and achieve a predetermined adjustment width and target size.

[0262] The above-described examples of implementations of this technology include direct inductive coupling between superconducting devices, but other implementations include direct galvanic coupling between superconducting devices. Instead of, or in addition to, direct inductive coupling between the same superconducting devices, there may be direct galvanic coupling between superconducting devices. Direct galvanic coupling between two superconducting devices may include a shared portion of the superconducting loop of one device with the superconducting loop of the other device. Direct galvanic coupling may increase the magnitude of the coupling between superconducting devices. Other implementations include capacitive coupling between superconducting devices, either alone or in combination with direct coupling by this system and method, and / or mediated coupling by this system and method, and / or a combination of direct and mediated coupling. For a description of various coupling topologies, including galvanic and capacitive coupling, see, for example, PCT Patent Application Publication WO2019126396A1, “SYSTEMS AND METHODS FOR COUPLING QUBITS IN A QUANTUM PROCESSOR”.

[0263] While the above-described examples of implementations of this technology include direct connectable coupling between a pair of superconducting devices, other implementations include direct connectable coupling between two or more superconducting devices. In general, connectable coupling between two or more superconducting devices by this technology may include combinations of inductive, galvanic, direct, and mediation connectable coupling. The above-described layouts and the selective adjustment of superconducting traces to achieve the desired coupling size are suitable for use in various of these configurations.

[0264] In some implementations, direct coupling between superconducting devices in a quantum processor is used only for a selected subset of superconducting devices in the quantum processor.

[0265] The advantages of this technology include the following: The layout implementation can be symmetrical and compact, and the layout does not require any additional ingenuity in the qubit itself (unlike other methods). • The size of direct bonds can be controlled by appropriately selecting the width of the adjustment metal piece without incurring disadvantages in layout space. For example, continuous tuning of bond sizes from 0 to twice the size of a typical mediating bond can be achieved. The trace can be adjusted, for example, from a width of 2 μm to 0.5 μm. • The technology is extendable to more symmetric / multiplex implementation forms. • The technology is robust against manufacturing misalignment and defects. One reason for its robustness against manufacturing errors (e.g., interlayer misalignment) is the symmetrical arrangement, which provides at least some protection to the size of the direct coupling from manufacturing errors. In one implementation configuration, the direct coupling is robust against interlayer misalignment up to 120 nm.

[0266] Throughout this specification and the accompanying claims, the term “ferromagnetic region” is used, for example, to describe the sensitivity of a coupling device, to describe a range of flux bias that can be applied to a coupling device to ferromagnetically couple a pair of superconducting devices that are communicated together by the coupling device. Similarly, throughout this specification and the accompanying claims, the term “antiferromagnetic region” is used, for example, to describe the sensitivity of a coupling device, to describe a range of flux bias that can be applied to a coupling device to antiferromagnetically couple a pair of superconducting devices that are communicated together by the coupling device.

[0267] Throughout this specification and the accompanying claims, the terms “coupler” and “coupled device” are used interchangeably. However, both “coupler” and “coupled device” are used to describe a coupling loop of superconducting materials that is interrupted by at least one Josephson junction that can be used to ferromagnetically or antiferromagnetically couple a pair of superconducting devices together. Furthermore, throughout this specification and the accompanying claims, the term “a pair of communicable coupled superconducting devices” is used to describe a pair of superconducting devices that can be directly coupled or ferromagnetically or antiferromagnetically coupled together by a coupling device.

[0268] Throughout this specification and the accompanying claims, where used to describe physical structures such as “loops in superconducting material,” the term “superconducting” is used to indicate a material capable of behaving as a superconductor at a suitable temperature. Superconducting materials do not necessarily always function as superconductors in all embodiments of the System and Method.

[0269] The above description of exemplary implementations, including those described in the abstract, is not intended to be exhaustive or to limit embodiments to the exact form of the disclosure. While specific embodiments and examples are described herein for illustrative purposes, various modifications of equivalents can be made without departing from the spirit and scope of the disclosure, as will be apparent to those skilled in the art. The teachings given herein for various embodiments can be applied to other analog processors (not necessarily limited to the generally exemplary quantum processors described above).

[0270] Further embodiments can be provided by combining the various embodiments described above. All of the U.S. patent publications, U.S. patent applications, foreign patents, and foreign patent applications by the same applicant referenced in this specification and / or listed in the application datasheet, including U.S. Patent No. 9,129,224 entitled “SYSTEMS AND METHODS FOR INCREASING THE ENERGY SCALE OF A QUANTUM PROCESSOR,” PCT Patent Application Publication WO2019 / 126396A1 entitled “SYSTEMS AND METHODS FOR COUPLING QUBITS IN A QUANTUM PROCESSOR,” and U.S. Patent Application No. 63 / 046,394 entitled “SYSTEMS AND METHODS FOR COUPLING BETWEEN QUBITS,” published on September 8, 2015 (but not limited to these), are incorporated herein by reference as a whole. In light of the detailed description above, these and other modifications can be added to the embodiment implementations. In general, the terms used in the following claims should not be interpreted to limit the claims to any particular embodiment disclosed in the specification and claims, but rather to include all possible embodiments together with the entire scope of equivalents given to such claims. Accordingly, the claims are not limited by the disclosure.

Claims

1. A first superconducting device comprising a first superconducting loop including a first superconducting trace in a first layer of a superconducting integrated circuit, A second superconducting device comprising a second superconducting loop including a second superconducting trace in a second layer of the superconducting integrated circuit, wherein the second layer lies on and / or adjacent to the first layer, and the second layer is separated from the first layer by an intervening layer, An intersection region in which the first superconducting loop intersects the second superconducting loop by projection, wherein at least a portion of the first superconducting trace inside the intersection region is narrower than at least a portion of the first superconducting trace outside the intersection region, and at least a portion of the second superconducting trace inside the intersection region is narrower than at least a portion of the second superconducting trace outside the intersection region, and the at least portion of the first superconducting trace inside the intersection region follows a first detour path, and the at least portion of the second superconducting trace inside the intersection region follows a second detour path, and the first detour path and the second detour path are inductively close to each other with respect to at least a portion of the length of the first detour path and A superconducting integrated circuit containing a superconducting circuit.

2. The superconducting integrated circuit according to claim 1, wherein the first detour path and the second detour path lie at least partially over each other with respect to at least a portion of the length of the first detour path.

3. The superconducting integrated circuit according to claim 1 or 2, wherein the first superconducting loop intersects substantially perpendicularly with the second superconducting loop.

4. The superconducting integrated circuit according to claim 1 or 2, wherein each of the first superconducting trace and the second superconducting trace comprises a superconducting metal.

5. The superconducting integrated circuit according to claim 4, wherein each of the superconducting metals includes a superconducting metal selected from the group consisting of niobium and aluminum.

6. The superconducting integrated circuit according to claim 1 or 2, wherein the first superconducting device further includes a first Josephson junction, the first Josephson junction blocking the first superconducting loop, and the second superconducting device further includes a second Josephson junction, the second Josephson junction blocking the second superconducting loop.

7. The superconducting integrated circuit according to claim 1 or 2, wherein the first superconducting device is a first superconducting flux qubit, and the second superconducting device is a second superconducting flux qubit.

8. The superconducting integrated circuit according to claim 1 or 2, wherein at least a portion of the first superconducting trace inside the intersection region includes four direction changes.

9. The superconducting integrated circuit according to claim 1 or 2, wherein the first shape of the first detour path coincides with the second shape of the second detour path.

10. The superconducting integrated circuit according to claim 1 or 2, wherein the intervening layer includes an insulating layer.

11. The superconducting integrated circuit according to claim 10, wherein the insulating layer includes a dielectric material and / or an air bridge.

12. The superconducting integrated circuit according to claim 11, wherein the dielectric material comprises at least one of silicon dioxide or silicon nitride.

13. The superconducting integrated circuit according to claim 1 or 2, further comprising a coupling device coupled to the first superconducting device and the second superconducting device, and coupled in a manner that enables communication between the first superconducting device and the second superconducting device to provide mediating coupling.

14. The superconducting integrated circuit according to claim 1 or 2, wherein each of the at least portion of the first superconducting trace inside the intersection region and each of the at least portion of the second superconducting trace inside the intersection region includes one or more U-shaped contours.

15. A quantum computer comprising a superconducting integrated circuit according to any one of claims 1 to 14.

16. A method for synchronizing the magnitude of a connectable coupling between a first superconducting device and a second superconducting device, wherein the magnitude of the connectable coupling is the sum of the magnitudes of the mediating connectable coupling and the direct connectable coupling. To determine the target size of the communicable coupling between the first and second superconducting devices, Determining the difference between the size of the mediating connectable coupling and the size of the target, Determining the adjustment tolerance based at least partially on the difference between the size of the mediating coupling and the size of the target, The first superconducting loop of the first superconducting device is attached to the first layer, The second superconducting loop of the second superconducting device is attached to the second layer, wherein the second superconducting loop intersects with the first superconducting loop to form an intersection region. By following the first detour path, at least a portion of the first superconducting loop inside the intersection region is adjusted by the adjustment tolerance range such that it becomes narrower outside the intersection region than at least a portion of the first superconducting loop, The method involves following a second detour path and adjusting at least a portion of the second superconducting loop within the intersection region by the allowable adjustment range such that the second detour path is narrower outside the intersection region than at least a portion of the second superconducting loop, and as a result, the first detour path and the second detour path are inductively close to each other with respect to at least a portion of the length of the first detour path. A method that includes this.

17. The method according to claim 16, further comprising attaching an intervening layer between the first layer and the second layer.

18. The method according to claim 17, wherein the attachment of an intervening layer between the first layer and the second layer includes attaching an insulating layer.

19. The method according to claim 18, wherein the deposition of an insulating layer includes deposition of a dielectric material and / or the formation of an air bridge.

20. The method according to any one of claims 16 to 19, wherein attaching the second superconducting loop of the second superconducting device to the second layer includes attaching the second superconducting loop of the second superconducting device to the second layer such that at least a portion of the second layer lies on top of at least a portion of the first layer.

21. The method according to claim 16, wherein adjusting at least a portion of the first superconducting loop by the allowable adjustment range includes adjusting at least a portion of the first superconducting loop to a width between 0.5 μm and 2.0 μm.

22. The method according to claim 16, wherein adjusting at least a portion of the first superconducting loop by the adjustment tolerance range includes performing adjustment width etching of at least a portion of the first superconducting loop.

23. Performing the adjustment width etching of at least a portion of the first superconducting loop is Attaching the first rigid mask and laying it on at least a portion of the first superconducting loop, Attaching a second rigid mask and lying on at least a portion of the first rigid mask, A photoresist layer is attached and laid on at least a portion of the second rigid mask, The photoresist layer is patterned, and a predetermined adjustment width is defined. Etching at least a portion of the first superconducting loop to remove the predetermined adjustment width The method according to claim 22, including the method described in claim 22.

24. A method for forming an integrated circuit, A first device including a first trace is formed on the first layer of the integrated circuit, The present invention relates to forming a second device including a second trace in a second layer of the integrated circuit, wherein at least a portion of the second trace is inductively adjacent to at least a portion of the first trace, thereby creating an inductively communicable coupling between the first device and the second device, and the at least portion of the first trace is narrower than at least another portion of the first trace. A method that includes this.

25. The method according to claim 24, wherein forming a second device comprises forming a second device wherein at least a portion of the second trace is narrower than at least another portion of the second trace.

26. The method according to claim 24, wherein forming a first device includes forming a first superconducting device, and forming a second device includes forming a second superconducting device.

27. The method according to claim 26, wherein forming a first superconducting device includes attaching a superconducting material.

28. The method according to claim 27, further comprising forming a first superconducting device by adjusting at least a portion of the first trace such that it follows a first detour path and is narrower than at least another portion of the first trace.

29. The method according to any one of claims 24 to 28, wherein forming a second superconducting device includes forming the second superconducting device inductively adjacent to a mediating coupling device, the mediating coupling device providing a communicable coupling between the first superconducting device and the second superconducting device.

30. The method according to claim 29, wherein forming the second superconducting device inductively close to the mediating coupling device includes forming the second superconducting device inductively close to a mediating coupling device that provides an antiferromagnetic (AFM) coupling between the first superconducting device and the second superconducting device, thereby increasing the antiferromagnetic coupling between the first superconducting device and the second superconducting device.

31. A first superconducting device comprising a first superconducting loop including a first superconducting trace in a first layer of a superconducting integrated circuit, A second superconducting device comprising a second superconducting loop including a second superconducting trace in the second layer of the superconducting integrated circuit, A region in which a portion of the first superconducting loop overlaps with a portion of the second superconducting loop, wherein at least a portion of the first superconducting trace inside the region is narrower than at least a portion of the first superconducting trace outside the region, and at least a portion of the second superconducting trace inside the region is narrower than at least a portion of the second superconducting trace outside the region, and the at least portion of the first superconducting trace inside the region follows a first path, and the at least portion of the second superconducting trace inside the region follows a second path, and the first path and the second path are inductively close to each other with respect to at least a portion of the length of the first path. A superconducting integrated circuit containing a superconducting circuit.

32. The superconducting integrated circuit according to claim 31, wherein the first layer is a different layer from the second layer.

33. The superconducting integrated circuit according to claim 31, wherein the first layer is separated from the second layer by an intervening layer.

34. The superconducting integrated circuit according to claim 31, wherein the first path is a detour path.

35. The superconducting integrated circuit according to claim 34, wherein the first path and the second path coincide.

36. The superconducting integrated circuit according to claim 31, wherein the first path and the second path lie at least partially on each other.

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