Semiconductor equipment

Abstract

This reduces the warping of the semiconductor substrate while shortening the length of the gate trench. [Solution] The semiconductor device (400) comprises a semiconductor layer (14) formed on a semiconductor substrate (12), a plurality of sets of gate trenches formed in the semiconductor layer (14), including a first set (S1) and a second set (S2), a plurality of gate electrodes, and gate wiring (52) electrically connected to the plurality of gate electrodes. Each of the gate trenches of the first set (S1) extends along a first direction in a plan view. Each of the gate trenches of the second set (S2) extends along a second direction perpendicular to the first direction in a plan view. The semiconductor device (400) further comprises a first communicating trench (402) extending along a second direction in a plan view, which connects the first set of gate trenches (S1) to each other at their ends, and a second communicating trench (404) extending along a first direction in a plan view, which connects the second set of gate trenches (S2) to each other at their ends.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device equipped with a metal-insulator-semiconductor field-effect transistor (MISFET) having a trench gate structure. In the semiconductor device of Patent Document 1, gate electrodes embedded in each of the multiple gate trenches are electrically connected to gate wiring (gate fingers) via gate contacts. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-202313

[0004] [overview] In a MISFET having a trench gate structure, the shorter the length of the gate trench, the lower the resistance of the electrode embedded in the gate trench (e.g., the gate electrode). Using a gate finger as described in Patent Document 1 makes it possible to make the length of the gate trench placed in the chip relatively short. However, an arrangement in which each of the multiple gate trenches extends along the same direction in a plan view has the problem that the warping of the semiconductor substrate (wafer) on which the MISFET is formed becomes relatively large during the process.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate and including an outer peripheral region and an active region surrounded by the outer peripheral region in a plan view, a plurality of gate trenches formed in the semiconductor layer including a first set and a second set, a plurality of gate electrodes, each embedded in a corresponding gate trench of the plurality of gate trenches, an insulating layer formed on the semiconductor layer, gate wiring formed on the insulating layer and electrically connected to the plurality of gate electrodes, and source wiring formed on the insulating layer and spaced apart from the gate wiring. Each of the first set of gate trenches extends along a first direction in a plan view. Each of the second set of gate trenches extends along a second direction perpendicular to the first direction in a plan view. The semiconductor device further comprises a first communicating trench extending in a plan view along the second direction, which connects the first set of gate trenches at their ends, and a second communicating trench extending in a plan view along the first direction, which connects the second set of gate trenches at their ends. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a schematic plan view of an exemplary semiconductor device according to one embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view of the semiconductor device along the line F2-F2 in Figure 1. [Figure 3] Figure 3 is a schematic cross-sectional view of the semiconductor device along the line F3-F3 in Figure 1. [Figure 4] Figure 4 is a schematic plan view of an exemplary semiconductor device relating to the first modification example. [Figure 5] Figure 5 is a schematic plan view of an exemplary semiconductor device relating to the second modification example. [Figure 6] Figure 6 is a schematic plan view of an exemplary semiconductor device relating to the third modification example. [Figure 7] Figure 7 is a schematic plan view of an exemplary semiconductor device relating to the fourth modification example.

[0007] [Detailed Description] Hereinafter, some embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that, for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, in cross-sectional views, hatching lines may be omitted. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0008] The following detailed description includes apparatuses, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is merely for explanatory purposes and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] FIG. 1 is a schematic plan view of an exemplary semiconductor device 10 according to an embodiment. Note that, in the present disclosure, the term "plan view" refers to viewing the semiconductor device 10 in the Z direction of the XYZ axes orthogonal to each other shown in FIG. 1.

[0010] The semiconductor device 10 is, for example, a MISFET having a trench gate structure. The semiconductor device 10 includes a semiconductor substrate 12, a semiconductor layer 14 formed on the semiconductor substrate 12, a plurality of sets of gate trenches S1, S2 formed in the semiconductor layer 14, and an insulating layer 16 formed on the semiconductor layer 14. In the present embodiment, the semiconductor substrate 12 may be a Si substrate. The semiconductor substrate 1 includes a bottom surface 12A to be described later with reference to FIG. 2 and an upper surface 12B opposite to the bottom surface 12A. In FIG. 1, the Z direction is the direction orthogonal to the bottom surface 12A and the upper surface 12B of the semiconductor substrate 12.

[0011] In the example of FIG. 1, the upper surface 12B of the semiconductor substrate 12 includes two sides (first sides) 12C and 12E extending along the X direction, and two sides (second sides) 12D and 12F extending along the Y direction. Since the upper surface 12B of the semiconductor substrate 12 is covered by the semiconductor layer 14 and the insulating layer 16, only the rectangular outer edge (i.e., the four sides 12C, 12D, 12E, 12F) of the semiconductor substrate 12 is shown in FIG. 1. The region defined by the outer edge of the semiconductor substrate 12 shown in FIG. 1 may correspond to one chip (die). In the present disclosure, the X direction is also referred to as the first direction, and the Y direction is also referred to as the second direction. In the example of FIG. 1, the sides 12C and 12E extending along the X direction have the same length as each other and are shorter than the sides 12D and 12F extending along the Y direction. The sides 12D and 12F extending along the Y direction have the same length as each other and are longer than the sides 12C and 12E extending along the X direction. That is, the short side direction and the long side direction of the upper surface 12B of the semiconductor substrate 12 correspond to the X direction and the Y direction, respectively. In another example, the sides 12C and 12E may have the same length as the sides 12D and 12F, or may have a length greater than that of the sides 12D and 12F.

[0012] The semiconductor layer 14 can be formed of a Si epitaxial layer. The semiconductor layer 14 has the same shape as the semiconductor substrate 12 in plan view. Details of the semiconductor layer 14 will be described later with reference to FIG. 2.

[0013] The insulating layer 16 may include at least one of a silicon oxide (SiO2) layer and a silicon nitride (SiN) layer. The insulating layer 16 is also called an inter-layer dielectric (ILD).

[0014] Multiple sets of gate trenches S1 and S2 are shown by dashed lines in Figure 1. Each set of gate trenches S1 and S2 contains multiple gate trenches that are aligned parallel to each other at equal intervals. Each set of gate trenches S1 and S2 includes a first set of gate trenches S1 and a second set of gate trenches S2. Each gate trench S1_n in the first set extends along the X direction in a plan view. Each gate trench S2_n in the second set extends along the Y direction in a plan view.

[0015] In the example shown in Figure 1, the first set of gate trenches S1 includes six gate trenches S1_1, ..., S1_6 arranged at equal intervals and parallel to each other, and the second set of gate trenches S2 includes four gate trenches S2_1, ..., S2_4 arranged at equal intervals and parallel to each other. Furthermore, multiple sets of gate trenches S1, S2 include four first sets of gate trenches S1 and four second sets of gate trenches S2. Thus, in one example, the number of gate trenches in the first set may be greater than the number of gate trenches in the second set. The number of sets of gate trenches and the number of gate trenches in each set can take any values ​​selectable for mounting the semiconductor device 10 of this disclosure.

[0016] Each of the multiple gate trenches S1 and S2, S1_n and S2_n, is embedded with a field plate electrode 18 and a gate electrode 20, which will be described below with reference to Figure 2.

[0017] Figure 2 is a schematic cross-sectional view of the semiconductor device 10 along the line F2-F2 in Figure 1. Here, a cross-section in the YZ plane of one gate trench S1_n from the first set of gate trenches S1 is shown, but the cross-sections in the XZ plane of each gate trench S2_n from the second set of gate trenches S2 are similar to those in Figure 2. The following description will focus on one gate trench S1_n from the first set of gate trenches S1 and its associated configuration, but it should be noted that such a description can be similarly applied to each gate trench and its associated configuration from multiple sets of gate trenches S1, S2.

[0018] The semiconductor substrate 12 corresponds to the drain region of the MISFET. The semiconductor layer 14 includes a drift region 22 formed on the semiconductor substrate (drain region) 12, a body region 24 formed on the drift region 22, and a source region 26 formed on the body region 24.

[0019] The drain region formed by the semiconductor substrate 12 is an n-type region containing n-type impurities. The n-type impurity concentration of the semiconductor substrate 12 is 1×10 18 cm -3 or more and 1×10 20 cm -3 or less. The semiconductor substrate 12 can have a thickness of 50 μm or more and 450 μm or less.

[0020] The drift region 22 is an n-type region containing n-type impurities at a lower concentration than the semiconductor substrate (drain region) 12. The n-type impurity concentration of the drift region 22 is 1×10 15 cm -3 or more and 1×10 18 cm -3 or less. The drift region 22 can have a thickness of 1 μm or more and 25 μm or less.

[0021] The body region 24 is a p-type region containing p-type impurities. The p-type impurity concentration of the body region 24 is 1×10 16 cm -3 or more and 1×10 18 cm -3 or less. The body region 24 can have a thickness of 0.5 μm or more and 1.5 μm or less.

[0022] The source region 26 is an n-type region containing n-type impurities at a higher concentration than the drift region 22. The n-type impurity concentration of the source region 26 is 1×10 19 cm -3 or more and 1×10 21 cm -3 or less. The source region 26 can have a thickness of 0.1 μm or more and 1 μm or less.

[0023] In this disclosure, n-type is also referred to as the first conductivity type, and p-type as the second conductivity type. n-type impurities may be, for example, phosphorus (P) or arsenic (As). p-type impurities may be, for example, boron (B) or aluminum (Al).

[0024] The semiconductor device 10 may further include a drain electrode 28 formed on the bottom surface 12A of the semiconductor substrate 12. The drain electrode 28 is electrically connected to the semiconductor substrate (drain region) 12. The drain electrode 28 may be formed from at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, Cu alloy, and Al alloy.

[0025] Gate trench S1_n, one of several sets of gate trenches S1, is formed in the semiconductor layer 14. Gate trench S1_n has side walls 30 and a bottom wall 32. Gate trench S1_n penetrates the source region 26 and body region 24 of the semiconductor layer 14 and reaches the drift region 22. Therefore, the bottom wall 32 of gate trench S1_n is adjacent to the drift region 22. Gate trench S1_n can have a depth of 1 μm or more and 15 μm or less.

[0026] The field plate electrode 18 and the gate electrode 20 are formed within the gate trench S1_n. The field plate electrode 18 and the gate electrode 20 are separated from each other by a trench insulating layer 34. The trench insulating layer 34 covers the side walls 30 and bottom wall 32 of the gate trench S1_n. The gate electrode 20 is positioned above the field plate electrode 18 within the gate trench S1_n. Such a structure in which two divided electrodes are embedded in a gate trench can be called a split-gate structure.

[0027] The field plate electrode 18 is positioned within the gate trench S1_n, between the bottom wall 32 of the gate trench S1_n and the bottom surface 20A of the gate electrode 20. The field plate electrode 18 is surrounded by a trench insulating layer 34. By applying a source voltage to the field plate electrode 18, electric field concentration within the gate trench S1_n can be mitigated, thereby improving the breakdown voltage of the semiconductor device 10. Therefore, the field plate electrode 18 can be at the same potential as the source region 26.

[0028] The gate electrode 20 includes a bottom surface 20A that faces at least a portion of the field plate electrode 18. The gate electrode 20 also includes an upper surface 20B opposite to the bottom surface 20A. The upper surface 20B of the gate electrode 20 may be located below the upper surface of the semiconductor layer 14.

[0029] In one example, the field plate electrode 18 and the gate electrode 20 are formed from conductive polysilicon. The trench insulating layer 34 includes a gate insulating portion 38 interposed between the gate electrode 20 and the semiconductor layer 14, covering the side wall 30 of the gate trench S1_n. The gate electrode 20 and the semiconductor layer 14 are separated in the Y direction by the gate insulating portion 38. When a predetermined voltage is applied to the gate electrode 20, a channel is formed in the p-type body region 24 adjacent to the gate insulating portion 38. The semiconductor device 10 can control the flow of electrons in the Z direction between the n-type source region 26 and the n-type drift region 22 through this channel.

[0030] The trench insulating layer 34 further includes a lower insulating portion 40 that covers the side walls 30 and bottom wall 32 of the gate trench S1_n between the field plate electrode 18 and the semiconductor layer 14, and an intermediate insulating portion 42 located between the field plate electrode 18 and the gate electrode 20 in the depth direction of the gate trench S1_n. The lower insulating portion 40 can be formed thicker than the gate insulating portion 38 on the side walls 30 of the gate trench S1_n. In one example, the trench insulating layer 34 can be formed from SiO2.

[0031] The insulating layer 16 is formed on the semiconductor layer 14 and covers the gate electrode 20 embedded in the gate trench S1_n and the trench insulating layer 34. The insulating layer 16 may include a cap insulating layer (not shown) that covers the upper surface 20B of the gate electrode 20.

[0032] The insulating layer 16 has a contact trench 44 and a contact region 46 adjacent to the bottom wall of the contact trench 44. The contact trench 44 penetrates the insulating layer 16 and the source region 26 and reaches the body region 24. The contact region 46 is a p-type region containing p-type impurities. The concentration of p-type impurities in the contact region 46 is higher than in the body region 24, at 1 × 10⁻⁶. 19 cm -3 The above 1 x 10 21 cm -3 The following may be the case: A source contact 48 is embedded in the contact trench 44. The source wiring 50 is formed on the insulating layer 16 and is electrically connected to the contact area 46 via the source contact 48.

[0033] As shown in Figure 1, the semiconductor device 10 includes multiple sets of gate trenches S1 and S2. Therefore, the semiconductor device 10 can include the same number of field plate electrodes 18 as there are gate trenches in the multiple sets of gate trenches S1 and S2, and the same number of gate electrodes 20 as there are gate trenches in the multiple sets of gate trenches S1 and S2. In other words, each field plate electrode 18 is embedded in a corresponding gate trench among the multiple sets of gate trenches S1 and S2. Similarly, each gate electrode 20 is embedded in a corresponding gate trench among the multiple sets of gate trenches S1 and S2.

[0034] Next, referring again to Figure 1, the source wiring 50 and gate wiring 52 formed on the insulating layer 16 will be described. The semiconductor device 10 further includes a gate wiring 52 formed on an insulating layer 16, and a source wiring 50 formed on the insulating layer 16 and spaced apart from the gate wiring 52. In Figure 1, for the sake of clarity and simplicity, the inter-metal dielectric (IMD) insulating film that separates the source wiring 50 from the gate wiring 52 is omitted.

[0035] The semiconductor layer 14 includes an outer peripheral region 54 and an inner region 56 surrounded by the outer peripheral region 54 in a plan view. The gate wiring 52 includes an outer gate wiring portion 58 located in the outer peripheral region 54 in a plan view and an inner gate wiring portion 60 located in the inner region 56 in a plan view. The boundary between the outer peripheral region 54 and the inner region 56 is shown by a dashed line in Figure 1. The semiconductor layer 14 covers the semiconductor substrate 12, and in one example, the outer edge of the semiconductor layer 14 substantially coincides with the outer edge of the semiconductor substrate 12 in a plan view. Therefore, the outer edge of the outer peripheral region 54 may also substantially coincide with the outer edge of the semiconductor substrate 12 in a plan view.

[0036] The inner region 56 is a rectangular region that is slightly smaller than the top surface of the semiconductor layer 14. In the example in Figure 1, the top surface of the semiconductor layer 14 is rectangular, and the short and long directions of the top surface of the semiconductor layer 14 correspond to the X and Y directions, respectively.

[0037] The outer region 54 is a rectangular frame-shaped region that surrounds the inner region 56 in a plan view. Therefore, in the example in Figure 1, the boundary between the outer region 54 and the inner region 56 is formed in a rectangular shape. The outer region 54 is located between the rectangular outer edge of the semiconductor layer 14 and the inner region 56. The inner region 56 can also be called the active region, and it mainly forms the main part of the MISFET, that is, the part that contributes to the operation as a transistor.

[0038] The outer periphery gate wiring section 58, located in the outer periphery region 54, can be formed to at least partially surround the inner region 56. The outer periphery gate wiring section 58 can extend along the boundary between the inner region 56 and the outer periphery region 54 within the outer periphery region 54.

[0039] The outer periphery gate wiring section 58 includes a gate finger 58A1 extending along the X direction in a plan view and a gate finger 58B1 extending along the Y direction in a plan view. The gate finger 58A1 is formed near the edge 12C of the semiconductor substrate 12 in a plan view. The gate finger 58B1 is formed near the edge 12D of the semiconductor substrate 12 in a plan view. The end of the gate finger 58A1 is connected to the end of the gate finger 58B1.

[0040] The outer periphery gate wiring section 58 further includes a gate finger 58A2 extending along the X direction in a plan view and a gate finger 58B2 extending along the Y direction in a plan view. The gate finger 58A2 is formed closer to the edge 12E of the semiconductor substrate 12 in a plan view. The gate finger 58B2 is formed closer to the edge 12F of the semiconductor substrate 12 in a plan view. One end of the gate finger 58A2 is connected to the end of the gate finger 58B1 (which is not connected to the gate finger 58A1). The other end of the gate finger 58A2 is connected to the end of the gate finger 58B2.

[0041] In the example shown in Figure 1, gate finger 58A1 is shorter than gate finger 58A2, and as a result, gate finger 58A1 is spaced apart from gate finger 58B2. Source wiring 50 passes between gate finger 58A1 and gate finger 58B2.

[0042] Thus, the outer gate wiring section 58, which at least partially surrounds the rectangular inner region 56, forms a rectangular open loop in a plan view. The open portion of the loop of the outer gate wiring section 58 corresponds to the gap between the gate finger 58A1 and the gate finger 58B2, and the outer source wiring section 64 and the inner source wiring section 66, which will be described later, are connected through this gap.

[0043] The outer perimeter gate wiring section 58 may include a gate pad 62. The gate pad 62 can be located away from the open portion of the loop of the outer perimeter gate wiring section 58. In the example in Figure 1, the open portion of the loop of the outer perimeter gate wiring section 58 is located near side 12C. On the other hand, the gate pad 62 is connected to a gate finger 58A2 located near side 12E, opposite to side 12C. In another example, the gate pad 62 may be connected to other gate fingers included in the outer perimeter gate wiring section 58.

[0044] The inner gate wiring section 60 may include a gate finger 60B extending along the Y direction in a plan view, and at least one other gate finger intersecting the gate finger 60B in a plan view. In this embodiment, the gate finger 60B is connected to the gate finger 58A2. The at least one other gate finger includes a gate finger 60A extending along the X direction in a plan view. The gate finger 60A intersects the gate finger 60B in a plan view, for example, approximately in the center of the inner region 56.

[0045] The gate fingers 60B of the inner gate wiring section 60 extend in the same direction (Y direction) as the gate fingers 58B1 and 58B2 of the outer gate wiring section 58. When gate fingers extending in the same direction (Y direction) exist in both the outer region 54 and the inner region 56, it becomes possible to arrange multiple first sets of gate trenches S1 adjacent to each other in the X direction, and as a result, the length of the gate trenches S1_n can be shortened. In the example in Figure 1, two first sets of gate trenches S1 are arranged adjacent to each other in the X direction, and each gate trench S1_n in the first set has a length of about 1 / 4 of the dimension of side 12C.

[0046] The gate fingers 60A of the inner gate wiring section 60 extend in the same direction (X direction) as the gate fingers 58A1 and 58A2 of the outer gate wiring section 58. When gate fingers extending in the same direction (X direction) exist in both the outer region 54 and the inner region 56, it becomes possible to arrange multiple second sets of gate trenches S2 adjacent to each other in the Y direction, and as a result, the length of the gate trenches S2_n can be shortened. In the example in Figure 1, two second sets of gate trenches S2 are arranged adjacent to each other in the Y direction, and each gate trench S2_n in the second set has a length of about 1 / 4 of the dimension of side 12D.

[0047] In the example in Figure 1, the dimension of side 12D is greater than the dimension of side 12C, and therefore the length of gate trench S2_n is greater than the length of gate trench S1_n. In one example, the number of relatively short gate trenches S1_n within a single chip can be greater than the number of relatively long gate trenches S2_n. In another example, the length of gate trench S2_n may be the same as the length of gate trench S1_n, or it may be less than the length of gate trench S1_n.

[0048] The source wiring 50 includes an outer source wiring section 64 located in the outer region 54 and an inner source wiring section 66 located in the inner region 56. In the example shown in Figure 1, the outer source wiring section 64 is continuously formed within the outer peripheral region 54, excluding the area where the gate pad 62 is formed, and surrounds the inner region 56 in plan view. The outer source wiring section 64 is connected to the inner source wiring section 66 in the region between the gate finger 58A1 and the gate finger 58B2 in plan view. Therefore, the outer source wiring section 64 and the inner source wiring section 66 are at the same potential.

[0049] The inner source wiring section 66 can be positioned so as to be separated from both the outer gate wiring section 58 and the inner gate wiring section 60 by a predetermined distance that can be appropriately determined considering the voltage withstand capability and other factors. In the example shown in Figure 1, the inner source wiring section 66 is separated by a certain distance from the outer edges of the gate fingers 60A and 60B that intersect with each other, and therefore has a cross-shaped notch in plan view.

[0050] Multiple sets of gate trenches S1 and S2 are arranged so as to at least partially overlap both the source wiring 50 and the gate wiring 52 in a plan view. Each set of gate trenches is positioned so as to intersect with one gate finger in a plan view, where the gate electrode 20 embedded in that set of gate trenches is connected to the gate wiring 52.

[0051] Each gate trench S1_n in the first set, which extends along the X direction in a plan view, intersects with one of the gate fingers 58B1, 58B2, or 60B that extend along the Y direction in a plan view. Similarly, each gate trench S2_n in the second set, which extends along the Y direction in a plan view, intersects with one of the gate fingers 58A1, 58A2, or 60A that extend along the X direction in a plan view.

[0052] For example, gate electrodes 20 embedded in each of the first pair of gate trenches S1_n that intersect with the gate finger 60B are electrically connected to the gate finger 60B in the region where each of the first pair of gate trenches S1_n and the gate finger 60B intersect in a plan view.

[0053] Similarly, gate electrodes 20 embedded in each of the second set of gate trenches S2_n that intersect with the gate fingers 58A1 or 58A2 are electrically connected to the gate fingers 58A1 or 58A2 in the region where each of the second set of gate trenches S2_n intersects with the gate fingers 58A1 or 58A2 in a plan view.

[0054] Each of the first pair of gate trenches S1_n that intersect with the gate fingers 58B1 or 58B2 of the outer gate wiring section 58 is arranged to span the inner region 56 and the outer region 54. On the other hand, each of the first pair of gate trenches S1_n that intersect with the gate fingers 60B of the inner gate wiring section 60 is entirely located within the inner region 56.

[0055] Similarly, each of the second set of gate trenches S2_n that intersect with the gate fingers 58A1 or 58A2 of the outer gate wiring section 58 is arranged to span the inner region 56 and the outer region 54. On the other hand, each of the second set of gate trenches S2_n that intersect with the gate fingers 60A of the inner gate wiring section 60 is entirely located within the inner region 56.

[0056] A gate finger extending along the Y direction in a plan view can intersect two or more first sets of gate trenches S1 in a plan view. In the example in Figure 1, gate finger 60B intersects two first sets of gate trenches S1 in a plan view.

[0057] Furthermore, a gate finger extending along the X direction in a plan view can intersect with two or more second sets of gate trenches S2 in a plan view. In the example in Figure 1, the gate finger 60A intersects with two second sets of gate trenches S2 in a plan view.

[0058] With the above-described layout of source wiring 50 and gate wiring 52, in the example of Figure 1, each gate trench S1_n in the first set can have a length of 1 / 3 or less of the dimension of side 12C. Similarly, each gate trench S2_n in the second set can have a length of 1 / 3 or less of the dimension of side 12D.

[0059] Figure 3 is a schematic cross-sectional view of a semiconductor device along the line F3-F3 in Figure 1, showing the XZ cross-section of two adjacent first pairs of gate trenches S1, including two gate trenches S1_n formed in the semiconductor layer 14.

[0060] A field plate electrode 18 and a gate electrode 20 are embedded in the gate trench S1_n. The gate electrode 20 is positioned above the field plate electrode 18. The field plate electrode 18 includes two ends 18A and 18B connected to the source wiring 50, and the ends 18A and 18B extend along the Z direction from the bottom of the gate trench S1_n to the opening. Therefore, the gate electrode 20 is not located above the ends 18A and 18B.

[0061] The two ends 18A and 18B of the field plate electrode 18 are connected to the source wiring 50 via two field plate contacts 68. Both of the two ends 18A and 18B of the field plate electrode 18 may be connected to the inner source wiring section 66. Alternatively, one of the two ends 18A and 18B of the field plate electrode 18 may be connected to the inner source wiring section 66, and the other end 18A and 18B may be connected to the outer source wiring section 64. For example, in a field plate electrode 18 embedded in each of a first pair of gate trenches S1_n that intersect with the gate fingers 60B of the inner gate wiring section 60 in a plan view, both of the two ends 18A and 18B are connected to the inner source wiring section 66. On the other hand, in the field plate electrode 18 embedded in each of the second set of gate trenches S2_n that intersect with the gate fingers 58A1 or 58A2 of the outer peripheral gate wiring section 58 in a plan view, one of the two ends 18A and 18B is connected to the inner source wiring section 66, and the other of the two ends 18A and 18B is connected to the outer peripheral source wiring section 64.

[0062] In the example shown in Figure 3, both of the two ends 18A and 18B of the right-hand field plate electrode 18 are connected to the inner source wiring section 66. On the other hand, the ends 18A and 18B of the left-hand field plate electrode 18 are connected to the inner source wiring section 66 and the outer source wiring section 64, respectively.

[0063] The gate electrode 20 embedded in the gate trench S1_n is connected to the gate wiring 52. More specifically, the gate electrode 20 is connected to the gate wiring 52 via a gate contact 70 that penetrates the insulating layer 16. Unlike the field plate electrode 18, which is connected to the source wiring 50 via two field plate contacts 68, the gate electrode 20 is connected to the gate wiring 52 via a single gate contact 70. In the example of Figure 3, the gate wiring 52 to which the gate electrode 20 is connected is a gate finger extending along the Y direction. Specifically, the gate electrode 20 on the right side of Figure 3 is connected to gate finger 60B, and the gate electrode 20 on the left side is connected to gate finger 58B2.

[0064] An insulating layer 72 is formed between the source wiring 50 and the gate wiring 52. The insulating layer 72 electrically isolates the source wiring 50 and the gate wiring 52. The insulating layer 72 corresponds to IMD (Insulated Magnetic Diode).

[0065] The cross-sections of two adjacent second sets of gate trenches S2 in the YZ plane are the same as in Figure 3, except that gate trench S2_n has a different length from gate trench S1_n. In the example in Figure 1, gate trench S2_n is longer than gate trench S1_n, but gate trench S2_n may be shorter than gate trench S1_n, or it may be the same length as gate trench S1_n.

[0066] The operation of the semiconductor device 10 of this embodiment will be described below. According to the semiconductor device 10 of this embodiment, each of the multiple field plate electrodes 18 includes two ends 18A and 18B connected to the source wiring 50. With this configuration, since both ends 18A and 18B of each field plate electrode 18 are connected to the source wiring 50, the resistance R of the field plate electrode 18 is reduced compared to the case where only one end is connected. S The length of the gate trench contributing to this can be reduced by approximately half.

[0067] Furthermore, according to the semiconductor device 10 of this embodiment, the outer gate wiring portion 58 includes a gate finger 58A1 or 58A2 (first gate finger) extending along the X direction in a plan view, and the inner gate wiring portion 60 includes a gate finger 60B (second gate finger) extending along the Y direction in a plan view. In addition, each gate trench S1_n of the first set extends along the X direction in a plan view and intersects with the gate finger 60B (second gate finger), and each gate trench S2_n of the second set extends along the Y direction in a plan view and intersects with the gate finger 58A1 or 58A2 (first gate finger).

[0068] In this configuration, each of the gate trenches S1_n extending along the X direction in a plan view and the gate trench S2_n extending along the Y direction in a plan view are arranged within the semiconductor layer 14 formed on the semiconductor substrate 12 such that they intersect with a corresponding gate finger. As a result, warping of the semiconductor substrate 12 during wafer processing can be reduced compared to the case where only gate trenches extending along the same direction are formed.

[0069] In a MISFET having a split-gate structure in which the field plate electrode and gate electrode are embedded in a gate trench, the resistance R of the field plate electrode S The displacement current flowing through it causes the potential V of the field plate electrode to change. BS The potential V may rise. BS An increase in R reduces the breakdown voltage of the MISFET, which can result in a phenomenon called false firing, where an avalanche current flows. Also, the gate electrode resistor R G The displacement current flowing through it causes the potential V of the gate electrode. G The threshold voltage V rises th If the current exceeds a certain level, a self-turn-on phenomenon may occur, causing the MISFET to turn on unintentionally. These phenomena are collectively called the shoot-through phenomenon. Since unintended shoot-through current flowing through a circuit containing a MISFET increases switching losses, it is desirable to suppress the shoot-through phenomenon.

[0070] The shoot-through phenomenon occurs when the resistance R of the field plate electrode is S and / or the resistor R of the gate electrode G This can be caused by the displacement current flowing through the resistor R. S and resistor R G By reducing the resistance R of the field plate electrode, the shoot-through phenomenon can be suppressed. Generally, the longer the gate trench, the greater the resistance R of the field plate electrode. S and the resistor R of the gate electrode G The value increases. Therefore, in order to suppress the shoot-through phenomenon without changing the process for manufacturing the MISFET, the resistor R S and resistor R G It is effective to shorten the length of the gate trench that contributes to this. According to the semiconductor device 10 of this disclosure, the length of the gate trench can be substantially shortened as described above, and thus the occurrence of the shoot-through phenomenon can be suppressed.

[0071] The semiconductor device 10 of this embodiment has the following advantages. (1) Each of the multiple field plate electrodes 18 includes two ends 18A, 18B connected to the source wiring 50. With this configuration, since both ends 18A, 18B of each field plate electrode 18 are connected to the source wiring 50, the resistance R of the field plate electrode 18 is greater than when only one end is connected. S The length of the gate trench contributing to this can be reduced by approximately half.

[0072] (2) The outer gate wiring section 58 includes a gate finger 58A1 or 58A2 (first gate finger) that extends along the X direction in a plan view, and the inner gate wiring section 60 includes a gate finger 60B (second gate finger) that extends along the Y direction in a plan view. In addition, each gate trench S1_n of the first set extends along the X direction in a plan view and intersects with the gate finger 60B (second gate finger), and each gate trench S2_n of the second set extends along the Y direction in a plan view and intersects with the gate finger 58A1 or 58A2 (first gate finger).

[0073] In this configuration, both gate trenches S1_n extending along the X direction in a plan view and gate trenches S2_n extending along the Y direction in a plan view are arranged within a semiconductor layer 14 formed on the semiconductor substrate 12 so as to intersect with a corresponding gate finger. As a result, warping of the semiconductor substrate 12 during wafer processing can be reduced compared to the case where only gate trenches extending along the same direction are formed.

[0074] (3) The inner gate wiring section 60 further includes at least one other gate finger 60A that intersects with the gate finger 60B (second gate finger) in a plan view. With this configuration, since there are gate fingers extending in the same direction (X direction) in both the outer region 54 and the inner region 56, it is possible to arrange the two second sets of gate trenches S2 adjacent to each other in the Y direction, and as a result the length of the gate trench S2_n can be shortened.

[0075] (4) The outer peripheral gate wiring section 58 further includes gate fingers 58B1 or 58B2 (fourth gate fingers) that extend along the Y direction in a plan view. With this configuration, since gate fingers extending along the same direction (Y direction) exist in both the outer peripheral region 54 and the inner region 56, it becomes possible to arrange two first pairs of gate trenches S1 adjacent to each other in the X direction, and as a result, the length of the gate trench S1_n can be shortened.

[0076] [Example of change 1] Figure 4 is a schematic plan view of an exemplary semiconductor device 100 according to Modification Example 1 of the above embodiment. In Figure 4, the same reference numerals are used for components similar to those in the semiconductor device 10 of Figure 1. Detailed explanations of components similar to those in the semiconductor device 10 are omitted.

[0077] The semiconductor device 100 in Modification Example 1 includes a gate wiring 102 formed on an insulating layer 16 and a source wiring 104 formed on the insulating layer 16 and spaced apart from the gate wiring 102. In Figure 4, for the sake of clarity and simplification, the IMD that separates the source wiring 104 from the gate wiring 102 is omitted.

[0078] The gate wiring 102 includes an outer gate wiring section 106 located in the outer peripheral region 54 in a plan view, and an inner gate wiring section 108 located in the inner region 56 in a plan view. The outer gate wiring section 106 located in the outer peripheral region 54 can be formed to at least partially enclose the inner region 56. The outer gate wiring section 106 can extend in the outer peripheral region 54 along the boundary between the inner region 56 and the outer peripheral region 54.

[0079] The outer periphery gate wiring section 106 includes a gate finger 106A1 extending along the X direction in a plan view and a gate finger 106B1 extending along the Y direction in a plan view. The gate finger 106A1 is formed near the edge 12C of the semiconductor substrate 12 in a plan view. The gate finger 106B1 is formed near the edge 12F of the semiconductor substrate 12 in a plan view. The end of the gate finger 106A1 is connected to the end of the gate finger 106B1.

[0080] The outer periphery gate wiring section 106 further includes a gate finger 106A2 extending along the X direction in a plan view and a gate finger 106B2 extending along the Y direction in a plan view. The gate finger 106A2 is formed closer to the edge 12E of the semiconductor substrate 12 in a plan view. The gate finger 106B2 is formed closer to the edge 12D of the semiconductor substrate 12 in a plan view. One end of the gate finger 106A2 is connected to the end of the gate finger 106B1 (which is not connected to the gate finger 106A1). The other end of the gate finger 106A2 is connected to the end of the gate finger 106B2.

[0081] In the example shown in Figure 4, gate finger 106A1 is shorter than gate finger 106A2, and as a result, gate finger 106A1 is spaced apart from gate finger 106B2. Source wiring 104 passes between gate finger 106A1 and gate finger 106B2.

[0082] Thus, the outer periphery gate wiring section 106, which at least partially encloses the rectangular inner region 56, forms a rectangular open loop in a plan view. The open portion of the loop of the outer periphery gate wiring section 106 corresponds to the gap between the gate finger 106A1 and the gate finger 106B2, and the outer periphery source wiring section 112 and the inner source wiring section 114, which will be described later, are connected through this gap.

[0083] The inner gate wiring section 108 includes a gate finger 108B extending along the Y direction in a plan view, and a gate pad 110 connected to the gate finger 108B. The gate pad 110 can be located away from the open portion of the loop of the outer gate wiring section 106 described above. In the example in Figure 4, the open portion of the loop of the outer gate wiring section 106 is located near side 12C. On the other hand, the gate pad 110 is connected to a gate finger 106A2 located near side 12E, opposite to side 12C. The outer gate wiring section 106 is connected to the inner gate wiring section 108 via the gate pad 110. In another example, the gate pad 110 may be connected to other gate fingers included in the outer gate wiring section 106.

[0084] The gate finger 108B of the inner gate wiring section 108 extends along the same direction (Y direction) as the gate fingers 106B1 and 106B2 of the outer gate wiring section 106. When gate fingers extending along the same direction (Y direction) exist in both the outer region 54 and the inner region 56, it becomes possible to arrange multiple first sets of gate trenches S1 adjacent to each other in the X direction, and as a result, the length of the gate trenches S1_n can be shortened. In the example in Figure 4, three first sets of gate trenches S1 are arranged adjacent to each other in the X direction, and each gate trench S1_n in the first set has a length of about 1 / 3 of the dimension of side 12C.

[0085] The gate finger 108B can have a length of 1 / 2 or less of the dimension of side 12D. In this case, even if each of the second set of gate trenches S2_n has a length of about 1 / 2 of the dimension of side 12D, the second set of gate trenches S2 can be arranged so as not to overlap with the gate finger 108B in a plan view.

[0086] In the example in Figure 4, the dimension of side 12D is greater than the dimension of side 12C, and therefore the length of gate trench S2_n is greater than the length of gate trench S1_n. In one example, the number of relatively short gate trenches S1_n within a single chip can be greater than the number of relatively long gate trenches S2_n. In another example, the length of gate trench S2_n may be the same as the length of gate trench S1_n, or it may be less than the length of gate trench S1_n.

[0087] The source wiring 104 includes an outer source wiring section 112 located in the outer region 54 and an inner source wiring section 114 located in the inner region 56. In the example shown in Figure 4, the outer source wiring section 112 is continuously formed within the outer region 54 and surrounds the inner region 56 in plan view. The outer source wiring section 112 is connected to the inner source wiring section 114 in the region between the gate fingers 106A1 and 106B2 in plan view. Therefore, the outer source wiring section 112 and the inner source wiring section 114 are at the same potential.

[0088] The inner source wiring section 114 can be positioned so as to be separated from both the outer gate wiring section 106 and the inner gate wiring section 108 by a predetermined distance that can be appropriately determined considering the voltage withstand capability and other factors. In the example shown in Figure 4, the inner source wiring section 114 is separated from the outer edge of the gate finger 108B by a certain distance, and therefore has a notch that extends along the Y direction in a plan view.

[0089] Multiple sets of gate trenches S1 and S2 are positioned so as to at least partially overlap both the gate wiring 102 and the source wiring 104 in a plan view. Each set of gate trenches is positioned so as to intersect with one gate finger in a plan view, where the gate electrode 20 embedded in that set of gate trenches is connected to the gate wiring 102.

[0090] Each gate trench S1_n in the first set, which extends along the X direction in a plan view, intersects with one of the gate fingers 106B1, 106B2, or 108B, which extends along the Y direction in a plan view. Similarly, each gate trench S2_n in the second set, which extends along the Y direction in a plan view, intersects with the gate finger 106A1, which extends along the X direction in a plan view.

[0091] For example, gate electrodes 20 embedded in each of the first pair of gate trenches S1_n that intersect with the gate finger 108B are electrically connected to the gate finger 108B in the region where each of the first pair of gate trenches S1_n and the gate finger 108B intersect in a plan view.

[0092] Similarly, gate electrodes 20 embedded in each of the second set of gate trenches S2_n that intersect with the gate finger 106A1 are electrically connected to the gate finger 106A1 in the region where each of the second set of gate trenches S2_n intersects with the gate finger 106A1 in a plan view.

[0093] Each of the first pair of gate trenches S1_n that intersect with the gate fingers 106B1 or 106B2 of the outer gate wiring section 106 is arranged to span the inner region 56 and the outer region 54. On the other hand, each of the first pair of gate trenches S1_n that intersect with the gate fingers 108B of the inner gate wiring section 108 is entirely located within the inner region 56.

[0094] Similarly, each of the second set of gate trenches S2_n that intersect with the gate fingers 106A1 of the outer peripheral gate wiring section 106 is arranged to span the inner region 56 and the outer peripheral region 54. In the example shown in Figure 4, the first set of gate trenches S1 includes eight gate trenches S1_1, ..., S1_8 arranged at equal intervals and parallel to each other, and the second set of gate trenches S2 includes eleven gate trenches S2_1, ..., S2_11 arranged at equal intervals and parallel to each other. Furthermore, multiple sets of gate trenches S1 and S2 include three first sets of gate trenches S1 and one second set of gate trenches S2.

[0095] With the gate wiring 102 and source wiring 104 layout described above, in the example of Figure 4, each gate trench S1_n in the first set can have a length of 1 / 3 or less of the dimension of side 12C. Similarly, each gate trench S2_n in the second set can have a length of 1 / 2 or less of the dimension of side 12D.

[0096] The connection relationship between the field plate electrode 18 and the source wiring 104 (outer source wiring portion 112 and inner source wiring portion 114) can be described using the same explanation as for the connection between the field plate electrode 18 and the source wiring 50.

[0097] [Example of change 2] Figure 5 is a schematic plan view of an exemplary semiconductor device 200 according to the second modification example of the above embodiment. In Figure 5, the same reference numerals are used for components similar to those in the semiconductor device 10 of Figure 1. Detailed explanations of components similar to those in the semiconductor device 10 are omitted.

[0098] The semiconductor device 200 in modification example 2 includes a gate wiring 202 formed on an insulating layer 16 and a source wiring 204 formed on the insulating layer 16 and spaced apart from the gate wiring 202. In Figure 5, for the sake of clarity and simplification, the IMD that separates the source wiring 204 from the gate wiring 202 is omitted.

[0099] The gate wiring 202 includes an outer gate wiring section 206 located in the outer peripheral region 54 in a plan view, and an inner gate wiring section 208 located in the inner region 56 in a plan view. The outer gate wiring section 206 located in the outer peripheral region 54 can be formed to at least partially enclose the inner region 56. The outer gate wiring section 206 can extend in the outer peripheral region 54 along the boundary between the inner region 56 and the outer peripheral region 54.

[0100] The outer periphery gate wiring section 206 includes a gate finger 206A1 extending along the X direction in a plan view and a gate finger 206B1 extending along the Y direction in a plan view. The gate finger 206A1 is formed near the edge 12C of the semiconductor substrate 12 in a plan view. The gate finger 206B1 is formed near the edge 12F of the semiconductor substrate 12 in a plan view. The end of the gate finger 206A1 is connected to the end of the gate finger 206B1.

[0101] The outer periphery gate wiring section 206 further includes a gate finger 206A2 extending along the X direction in a plan view, a gate finger 206B2 extending along the Y direction in a plan view, and a gate finger 206A3 extending along the X direction in a plan view. The gate finger 206A2 is formed near the edge 12E of the semiconductor substrate 12 in a plan view. The gate finger 206B2 is formed near the edge 12D of the semiconductor substrate 12 in a plan view. The gate finger 206A3 is formed near the edge 12C of the semiconductor substrate 12 in a plan view. One end of the gate finger 206A2 is connected to the end of the gate finger 206B1 (which is not connected to the gate finger 206A1). The other end of the gate finger 206A2 is connected to the end of the gate finger 206B2. The end of gate finger 206A3 is connected to the end of gate finger 206B2 (which is not connected to gate finger 206A2).

[0102] In the example shown in Figure 5, the combined length of gate fingers 206A1 and 206A3 is shorter than the length of gate finger 206A2, resulting in gate finger 206A1 being spaced apart from gate finger 206A3. Source wiring 204 passes between gate finger 206A1 and gate finger 206A3.

[0103] Thus, the outer gate wiring section 206, which at least partially encloses the rectangular inner region 56, forms a rectangular open loop in a plan view. The open portion of the loop of the outer gate wiring section 206 corresponds to the gap between the gate finger 206A1 and the gate finger 206A3, and the outer source wiring section 212 and the inner source wiring section 214, which will be described later, are connected through this gap.

[0104] The inner gate wiring section 208 includes a gate finger 208A extending along the X direction in a plan view, a gate finger 208B extending along the Y direction in a plan view, and a gate pad 210. The gate pad 210 can be located away from the open portion of the loop of the outer periphery gate wiring section 206. In the example of Figure 5, the open portion of the loop of the outer periphery gate wiring section 206 is located near side 12C. On the other hand, the gate pad 210 is connected to a gate finger 206A2 located near side 12E, opposite to side 12C. The gate finger 208A forms a T-shaped joint with the gate finger 208B in a plan view. The gate finger 208B is also connected to the gate pad 210. Therefore, the outer periphery gate wiring section 206 is connected to the gate finger 208B via the gate pad 210. In another example, the gate pad 210 may be connected to other gate fingers included in the outer periphery gate wiring section 206.

[0105] The gate fingers 208A of the inner gate wiring section 208 extend in the same direction (X direction) as the gate fingers 206A1, 206A2, and 206A3 of the outer gate wiring section 206. When gate fingers extending in the same direction (X direction) exist in both the outer region 54 and the inner region 56, it becomes possible to arrange multiple second sets of gate trenches S2 adjacent to each other in the Y direction, and as a result, the length of the gate trenches S2_n can be shortened. In the example in Figure 5, two second sets of gate trenches S2 are arranged adjacent to each other in the Y direction, and each gate trench S2_n in the second set has a length of about 1 / 3 of the dimension of side 12D.

[0106] The gate fingers 208B of the inner gate wiring section 208 extend in the same direction (Y direction) as the gate fingers 206B1 and 206B2 of the outer gate wiring section 206. When gate fingers extending in the same direction (Y direction) exist in both the outer region 54 and the inner region 56, it becomes possible to arrange multiple first sets of gate trenches S1 adjacent to each other in the X direction, and as a result, the length of the gate trenches S1_n can be shortened. In the example in Figure 5, three first sets of gate trenches S1 are arranged adjacent to each other in the X direction, and each gate trench S1_n in the first set has a length of about 1 / 3 of the dimension of side 12C.

[0107] In the example shown in Figure 5, the dimension of side 12D is greater than the dimension of side 12C, and therefore the length of gate trench S2_n is greater than the length of gate trench S1_n. In another example, the length of gate trench S2_n may be the same as the length of gate trench S1_n, or it may be less than the length of gate trench S1_n.

[0108] The source wiring 204 includes an outer source wiring section 212 located in the outer region 54 and an inner source wiring section 214 located in the inner region 56. In the example shown in Figure 5, the outer source wiring section 212 is continuously formed within the outer region 54 and surrounds the inner region 56 in plan view. The outer source wiring section 212 is connected to the inner source wiring section 214 in the region between the gate fingers 206A1 and 206A3 in plan view. Therefore, the outer source wiring section 212 and the inner source wiring section 214 are at the same potential.

[0109] The inner source wiring section 214 can be positioned so as to be separated from both the outer gate wiring section 206 and the inner gate wiring section 208 by a predetermined distance that can be appropriately determined considering the voltage withstand capability and other factors. In the example shown in Figure 5, the inner source wiring section 214 is separated from the outer edges of the gate fingers 208A and 208B by a certain distance, and therefore has a T-shaped notch in plan view.

[0110] Multiple sets of gate trenches S1 and S2 are positioned so as to at least partially overlap both the gate wiring 202 and the source wiring 204 in a plan view. Each set of gate trenches is positioned so as to intersect with one gate finger in a plan view, where the gate electrode 20 embedded in that set of gate trenches is connected to the gate wiring 202.

[0111] Each gate trench S1_n in the first set, extending along the X direction in a plan view, intersects with one of the gate fingers 206B1, 206B2, or 208B extending along the Y direction in a plan view. Similarly, each gate trench S2_n in the second set, extending along the Y direction in a plan view, intersects with one of the gate fingers 206A1, 206A3, or 208A extending along the X direction in a plan view.

[0112] For example, gate electrodes 20 embedded in each of the first pair of gate trenches S1_n that intersect with the gate finger 208B are electrically connected to the gate finger 208B in the region where each of the first pair of gate trenches S1_n and the gate finger 208B intersect in a plan view.

[0113] Similarly, the gate electrodes 20 embedded in each of the second set of gate trenches S2_n that intersect with the gate finger 206A1 are electrically connected to the gate finger 206A1 in the region where each of the second set of gate trenches S2_n intersects with the gate finger 206A1 in a plan view.

[0114] Each of the first pair of gate trenches S1_n that intersect with the gate fingers 206B1 or 206B2 of the outer gate wiring section 206 is arranged to span the inner region 56 and the outer region 54. On the other hand, each of the first pair of gate trenches S1_n that intersect with the gate fingers 208B of the inner gate wiring section 208 is entirely located within the inner region 56.

[0115] Similarly, each of the second set of gate trenches S2_n that intersect with the gate fingers 206A1 or 206A3 of the outer periphery gate wiring section 206 is arranged to span the inner region 56 and the outer periphery region 54.

[0116] In the example shown in Figure 5, the first set of gate trenches S1 includes six gate trenches S1_1, ..., S1_6 arranged at equal intervals and parallel to each other, and the second set of gate trenches S2 includes four gate trenches S2_1, ..., S2_4 arranged at equal intervals and parallel to each other. Furthermore, multiple sets of gate trenches S1 and S2 include three first sets of gate trenches S1 and four second sets of gate trenches S2.

[0117] With the gate wiring 202 and source wiring 204 layout described above, in the example of Figure 5, each gate trench S1_n in the first set can have a length of 1 / 3 or less of the dimension of side 12C. Similarly, each gate trench S2_n in the second set can have a length of 1 / 3 or less of the dimension of side 12D.

[0118] The connection relationship between the field plate electrode 18 and the source wiring 204 (outer source wiring portion 212 and inner source wiring portion 214) can be described using the same explanation as for the connection between the field plate electrode 18 and the source wiring 50.

[0119] [Example of change 3] Figure 6 is a schematic plan view of an exemplary semiconductor device 300 according to the third modification example of the above embodiment. In Figure 6, the same reference numerals are used for components similar to those in the semiconductor device 10 of Figure 1. Detailed explanations of components similar to those in the semiconductor device 10 are omitted.

[0120] The semiconductor device 300 in modification example 3 includes a gate wiring 302 formed on an insulating layer 16 and a source wiring 304 formed on the insulating layer 16 and spaced apart from the gate wiring 302. In Figure 6, for the sake of clarity and simplification, the IMD that separates the source wiring 304 from the gate wiring 302 is omitted.

[0121] The gate wiring 302 includes an outer gate wiring section 306 located in the outer peripheral region 54 in a plan view, and an inner gate wiring section 308 located in the inner region 56 in a plan view. The outer gate wiring section 306 located in the outer peripheral region 54 can be formed to at least partially enclose the inner region 56. The outer gate wiring section 306 can extend in the outer peripheral region 54 along the boundary between the inner region 56 and the outer peripheral region 54.

[0122] The outer periphery gate wiring section 306 includes a gate finger 306A1 extending along the X direction in a plan view and a gate finger 306B1 extending along the Y direction in a plan view. The gate finger 306A1 is formed near the edge 12C of the semiconductor substrate 12 in a plan view. The gate finger 306B1 is formed near the edge 12D of the semiconductor substrate 12 in a plan view. The end of the gate finger 306A1 is connected to the end of the gate finger 306B1.

[0123] The outer periphery gate wiring section 306 further includes a gate finger 306A2 extending along the X direction in a plan view and a gate finger 306B2 extending along the Y direction in a plan view. The gate finger 306A2 is formed closer to the edge 12E of the semiconductor substrate 12 in a plan view. The gate finger 306B2 is formed closer to the edge 12F of the semiconductor substrate 12 in a plan view. One end of the gate finger 306A2 is connected to the end of the gate finger 306B1 (which is not connected to the gate finger 306A1). The other end of the gate finger 306A2 is connected to the end of the gate finger 306B2.

[0124] In the example shown in Figure 6, gate finger 306A1 is shorter than gate finger 306A2, and as a result, gate finger 306A1 is spaced apart from gate finger 306B2. Source wiring 304 passes between gate finger 306A1 and gate finger 306B2.

[0125] Thus, the outer gate wiring section 306, which at least partially encloses the rectangular inner region 56, forms a rectangular open loop in a plan view. The open portion of the loop of the outer gate wiring section 306 corresponds to the gap between the gate finger 306A1 and the gate finger 306B2, and the outer source wiring section 312 and the inner source wiring section 314, which will be described later, are connected through this gap.

[0126] The outer perimeter gate wiring section 306 may include a gate pad 310. The gate pad 310 can be located away from the open portion of the loop of the outer perimeter gate wiring section 306. In the example in Figure 6, the open portion of the loop of the outer perimeter gate wiring section 306 is located near side 12C. On the other hand, the gate pad 310 is connected to a gate finger 306A2 located near side 12E, opposite to side 12C. In another example, the gate pad 310 may be connected to other gate fingers included in the outer perimeter gate wiring section 306.

[0127] The inner gate wiring section 308 may include a gate finger 308B extending along the Y direction in a plan view, and at least one other gate finger intersecting the gate finger 308B in a plan view. In this embodiment, the gate finger 308B is connected to the gate finger 306A2. The at least one other gate finger includes two gate fingers 308A1, 308A2 extending along the X direction in a plan view. In the example in Figure 6, the gate fingers 306A2, 308A1, 308A2, and 306A1 are aligned parallel to each other at equal intervals.

[0128] The gate finger 308B of the inner gate wiring section 308 extends along the same direction (Y direction) as the gate fingers 306B1 and 306B2 of the outer gate wiring section 306. When gate fingers extending along the same direction (Y direction) exist in both the outer region 54 and the inner region 56, it becomes possible to arrange multiple first sets of gate trenches S1 adjacent to each other in the X direction, and as a result, the length of the gate trenches S1_n can be shortened. In the example in Figure 6, two first sets of gate trenches S1 are arranged adjacent to each other in the X direction, and each gate trench S1_n in the first set has a length of about 1 / 4 of the dimension of side 12C.

[0129] The two gate fingers 308A1 and 308A2 of the inner gate wiring section 308 extend in the same direction (X direction) as the gate fingers 306A1 and 306A2 of the outer gate wiring section 306. The presence of gate fingers extending in the same direction (X direction) in both the outer region 54 and the inner region 56 makes it possible to arrange multiple second sets of gate trenches S2 adjacent to each other in the Y direction, thereby shortening the length of the gate trenches S2_n. In the example shown in Figure 6, two second sets of gate trenches S2 are arranged adjacent to each other in the Y direction. Unlike the semiconductor device 10 shown in Figure 1, the semiconductor device 300 includes two gate fingers 308A1 and 308A2 in the inner gate wiring section 308 that extend along the X direction. Therefore, six second sets of gate trenches S2 can be arranged, and each gate trench S2_n in a second set has a length of approximately 1 / 6 of the dimension of side 12D.

[0130] The source wiring 304 includes an outer source wiring section 312 located in the outer region 54 and an inner source wiring section 314 located in the inner region 56. In the example shown in Figure 6, the outer source wiring section 312 is continuously formed within the outer peripheral region 54, excluding the area where the gate pad 310 is formed, and surrounds the inner region 56 in plan view. The outer source wiring section 312 is connected to the inner source wiring section 314 in the region between the gate finger 306A1 and the gate finger 306B2 in plan view. Therefore, the outer source wiring section 312 and the inner source wiring section 314 are at the same potential.

[0131] The inner source wiring section 314 can be positioned so as to be separated from both the outer gate wiring section 306 and the inner gate wiring section 308 by a predetermined distance that can be appropriately determined considering the voltage withstand capability and other factors. In the example shown in Figure 6, the inner source wiring section 314 is separated by a certain distance from the outer edges of the gate finger 308B and the two gate fingers 308A1 and 308A2 that intersect the gate finger 308B, and therefore has a cutout that follows the shape of these in a plan view.

[0132] Multiple sets of gate trenches S1 and S2 are positioned so as to at least partially overlap both the gate wiring 302 and the source wiring 304 in a plan view. Each set of gate trenches is positioned so as to intersect with one gate finger in a plan view, where the gate electrode 20 embedded in that set of gate trenches is connected to the gate wiring 302.

[0133] Each gate trench S1_n in the first set, which extends along the X direction in a plan view, intersects with one of the gate fingers 306B1, 306B2, or 308B that extend along the Y direction in a plan view. Similarly, each gate trench S2_n in the second set, which extends along the Y direction in a plan view, intersects with one of the gate fingers 306A1, 306A2, 308A1, or 308A2 that extend along the X direction in a plan view.

[0134] For example, gate electrodes 20 embedded in each of the first pair of gate trenches S1_n that intersect with the gate finger 308B are electrically connected to the gate finger 308B in the region where each of the first pair of gate trenches S1_n and the gate finger 308B intersect in a plan view.

[0135] Similarly, the gate electrodes 20 embedded in each of the second set of gate trenches S2_n that intersect with the gate finger 306A1 are electrically connected to the gate finger 306A1 in the region where each of the second set of gate trenches S2_n intersects with the gate finger 306A1 in a plan view.

[0136] Each of the first pair of gate trenches S1_n that intersect with the gate fingers 306B1 or 306B2 of the outer gate wiring section 306 is arranged to span the inner region 56 and the outer region 54. On the other hand, each of the first pair of gate trenches S1_n that intersect with the gate fingers 308B of the inner gate wiring section 308 is entirely located within the inner region 56.

[0137] Similarly, each of the second set of gate trenches S2_n that intersect with the gate fingers 306A1 or 306A2 of the outer gate wiring section 306 is arranged to span the inner region 56 and the outer region 54. On the other hand, each of the second set of gate trenches S2_n that intersect with the gate fingers 308A1 or 308A2 of the inner gate wiring section 308 is entirely located within the inner region 56.

[0138] In the example shown in Figure 6, the first set of gate trenches S1 includes four gate trenches S1_1, ..., S1_4 arranged at equal intervals and parallel to each other, and the second set of gate trenches S2 includes four gate trenches S2_1, ..., S2_4 arranged at equal intervals and parallel to each other. Furthermore, multiple sets of gate trenches S1 and S2 include six first sets of gate trenches S1 and six second sets of gate trenches S2.

[0139] With the gate wiring 302 and source wiring 304 layout described above, in the example of Figure 6, each gate trench S1_n in the first set can have a length of 1 / 3 or less of the dimension of side 12C. Similarly, each gate trench S2_n in the second set can have a length of 1 / 4 or less of the dimension of side 12D.

[0140] The connection relationship between the field plate electrode 18 and the source wiring 304 (outer source wiring portion 312 and inner source wiring portion 314) can be described using the same explanation as for the connection between the field plate electrode 18 and the source wiring 50.

[0141] [Example of change 4] Figure 7 is a schematic plan view of an exemplary semiconductor device 400 according to the modified example 4 of the above embodiment. In Figure 7, the same reference numerals are used for components similar to those in the semiconductor device 10 of Figure 1. Detailed explanations of components similar to those in the semiconductor device 10 are omitted.

[0142] The semiconductor device 400 includes, in addition to components similar to those of the semiconductor device 10, a pair of first communicating trenches 402 extending along the Y direction in a plan view, which connect the first set of gate trenches S1 to each other, and a pair of second communicating trenches 404 extending along the X direction in a plan view, which connect the second set of gate trenches S2 to each other.

[0143] Multiple field plate electrodes 18 embedded in the first set of gate trenches S1 are interconnected within a pair of first communication trenches 402. Multiple field plate electrodes 18 embedded in the second set of gate trenches S2 are interconnected within a pair of second communication trenches 404. Each field plate electrode 18 is connected to other field plate electrodes 18 at two ends 18A, 18B (see Figure 3).

[0144] In the semiconductor device 10 shown in Figure 1, the multiple field plate electrodes 18 are electrically connected to each other through source wiring 50. On the other hand, in the semiconductor device 400 according to modification example 4, the multiple field plate electrodes 18 can be directly connected to each other within a pair of first communication trenches 402 or a pair of second communication trenches 404. This improves the withstand voltage of the semiconductor device 400.

[0145] [Other examples of changes] The above embodiments and their respective modifications can be implemented with the following changes. The internal gate wiring section may include three or more gate fingers extending along the X direction.

[0146] Each set of gate trenches may contain only one gate trench instead of multiple gate trenches arranged at equal intervals and parallel to each other. In the modification example 1 shown in Figure 4, the length of the gate finger 108B may be longer than half the dimension of side 12D. This allows for an increase in the number of gate trenches included in the first set of gate trenches S1, while shortening the length of each gate trench S2_n in the second set (for example, to the same length as each gate trench S1_n in the first set).

[0147] In the modification example 2 shown in Figure 5, the length of the gate finger 208B may be longer than half the dimension of side 12D. This allows for an increase in the number of gate trenches included in the first set of gate trenches S1, while shortening the length of each gate trench S2_n in the second set (for example, to about the same length as each gate trench S1_n in the first set).

[0148] A structure in which the conductivity type of each region within the semiconductor layer 14 is reversed may be adopted. That is, a p-type region may become an n-type region, and an n-type region may become a p-type region. Further wiring structures may be formed on top of the layer containing source and gate wiring.

[0149] As used in this disclosure, the term “on” includes the meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, the expression “the first layer is formed on the second layer” is intended to mean that in one embodiment the first layer may be in contact with and directly positioned on the second layer, while in other embodiments the first layer may be positioned above the second layer without contact. In other words, the term “on” does not preclude structures in which another layer is formed between the first and second layers.

[0150] The Z-direction used in this disclosure does not necessarily have to be vertical, nor does it have to coincide perfectly with the vertical. Therefore, the various structures described herein (e.g., the structure shown in Figure 1) are not limited to the Z-direction "up" and "down" being the same as the Z-direction "up" and "down" being the same as the vertical. For example, the X-direction may be vertical, or the Y-axis direction may be vertical.

[0151] [Note] The technical concepts that can be understood from each of the above embodiments and their modifications are described below. Note that, not as an limitation but for the purpose of aiding understanding, the corresponding reference numerals in the embodiments for the components described in the appendices are shown in parentheses. These reference numerals are provided as examples for the purpose of aiding understanding, and the components described in each appendice should not be limited to those indicated by these reference numerals.

[0152] (Note A1) Semiconductor substrate (12) and A semiconductor layer (14) formed on the semiconductor substrate (12) includes an outer peripheral region (54) and an active region (56) surrounded by the outer peripheral region (54) in a plan view, Multiple sets of gate trenches (S1, S2), including a first set (S1) and a second set (S2), are formed in the semiconductor layer (14), A plurality of gate electrodes (20), each embedded in a corresponding gate trench among the plurality of sets of gate trenches (S1, S2), A plurality of field plate electrodes (18), each of which is embedded in a corresponding gate trench among the plurality of sets of gate trenches (S1, S2) while being insulated from the gate electrode (20), An insulating layer (16) formed on the semiconductor layer (14), A gate wiring (52;102;202;302) formed on the insulating layer (16) and connected to the plurality of gate electrodes (20), comprising an outer gate wiring portion (58;106;206;306) arranged in the outer peripheral region (54) in a plan view, and an inner gate wiring portion (60;108;208;308) arranged in the active region (56) in a plan view, Source wiring (50;104;204;304) formed on the insulating layer (16) and spaced apart from the gate wiring (52;102;202;302) and Equipped with, Each of the plurality of field plate electrodes (18) includes two ends (18A, 18B) connected to the source wiring (50; 104; 204; 304), The outer gate wiring section (58; 106; 206; 306) includes first gate fingers (58A1 or 58A2; 106A1; 206A1 or 206A3; 306A1 or 306A2) extending along a first direction in a plan view, and the inner gate wiring section (60; 108; 208; 308) includes second gate fingers (60B; 108B; 208B; 308B) extending along a second direction perpendicular to the first direction in a plan view. Each of the first set of gate trenches (S1_n) extends along the first direction in a plan view and intersects with the second gate fingers (60B; 108B; 208B; 308B), Each of the second set of gate trenches (S2_n) extends along the second direction in a plan view and intersects with the first gate fingers (58A1 or 58A2; 106A1; 206A1 or 206A3; 306A1 or 306A2). Semiconductor equipment.

[0153] (Appendix A2) Each of the first set of gate trenches (S1_n) intersects with the second gate fingers (60B; 108B; 208B; 308B) between the two ends (18A, 18B) of the field plate electrode (18) embedded in the gate trench in a plan view. Each of the second set of gate trenches (S2_n) intersects with the first gate fingers (58A1 or 58A2; 106A1; 206A1 or 206A3; 306A1 or 306A2) between the two ends (18A, 18B) of the field plate electrode (18) embedded in the gate trench in a plan view. The semiconductor device described in Appendix A1.

[0154] (Note A3) The aforementioned source wiring (50; 104; 204; 304) Outer peripheral source wiring sections (64;112;212;312) arranged in the outer peripheral region (54), The inner source wiring section (66;114;214;314) located in the active region (56) and Semiconductor devices as described in Appendix A1 or A2, including those specified.

[0155] (Note A4) Each of the first set of gate trenches (S1_n) is entirely located within the active region (56), Each of the second set of gate trenches (S2_n) is arranged to span the active region (56) and the outer peripheral region (54), In each of the first set of gate trenches (S1_n), the field plate electrode (18) embedded in it has both of its two ends (18A, 18B) connected to the inner source wiring section (66; 114; 214; 314). The semiconductor device as described in Appendix A3, wherein in each of the second set of gate trenches (S2_n), the field plate electrode (18) embedded in the field plate electrode (18) has one of its two ends (18A, 18B) connected to the inner source wiring section (66; 114; 214; 314) and the other of its two ends (18A, 18B) connected to the outer source wiring section (64; 112; 212; 312).

[0156] (Note A5) Each gate electrode (20) embedded in each of the first set of gate trenches (S1_n) is electrically connected to the second gate fingers (60B;108B;208B;308B) in the region where each of the first set of gate trenches (S1_n) and the second gate fingers (60B;108B;208B;308B) intersect in a plan view. The semiconductor device according to any one of the appendices A1 to A4, wherein the gate electrodes (20) embedded in each of the second set of gate trenches (S2_n) are electrically connected to the first gate fingers (58A1 or 58A2; 106A1; 206A1 or 206A3; 306A1 or 306A2) in the region where each of the second set of gate trenches (S2_n) intersects with the first gate fingers (58A1 or 58A2; 106A1; 206A1 or 206A3; 306A1 or 306A2) in a plan view.

[0157] (Note A6) The semiconductor device according to any one of the appendices A1 to A5, wherein the second gate fingers (60B; 108B; 208B; 308B) intersect with two or more sets of gate trenches, including the first set of gate trenches (S1), in a plan view.

[0158] (Note A7) The semiconductor device according to any one of appendices A1 to A6, wherein the inner gate wiring portion (60;308) further includes at least one other gate finger (60A;308A1,308A2) that intersects the second gate finger (60B;308B) in a plan view.

[0159] (Note A8) The semiconductor device according to Appendix A7, wherein the at least one other gate finger (60A; 308A1, 308A2) includes one gate finger (60A) extending in the first direction in a plan view.

[0160] (Note A9) The semiconductor device according to Appendix A7, wherein the at least one other gate finger (60A; 308A1, 308A2) includes two gate fingers (308A1, 308A2) extending in the first direction in a plan view.

[0161] (Note A10) The semiconductor device according to any one of the appendices A1 to A9, wherein the inner gate wiring portion (208) further includes a third gate finger (208A) that forms a T-shaped joint with the second gate finger (208B) in a plan view.

[0162] (Note A11) The semiconductor device according to any one of appendices A1 to A10, wherein the outer peripheral gate wiring portion (58; 106; 206; 306) further includes a fourth gate finger (58B1 or 58B2; 106B1 or 106B2; 206B1 or 206B2; 306B1 or 306B2) extending along the second direction in a plan view.

[0163] (Note A12) The semiconductor device described in any one of the appendices A1 to A11, wherein each set of the aforementioned sets of gate trenches (S1, S2) includes a plurality of gate trenches arranged at equal intervals and parallel to each other.

[0164] (Note A13) A pair of first connecting trenches (402) extending along the second direction in a plan view, which connect the first set of gate trenches (S1) to each other, A pair of second connecting trenches (404) extending along the first direction in a plan view, which connect the second set of gate trenches (S2) to each other, It further includes, The plurality of field plate electrodes (18) embedded in the first set of gate trenches (S1) are interconnected within the pair of first communicating trenches (402), and the plurality of field plate electrodes (18) embedded in the second set of gate trenches (S2) are interconnected within the pair of second communicating trenches (404), and each field plate electrode (18) is connected to other field plate electrodes at the two ends (18A, 18B). A semiconductor device as described in any one of the appendices A1 to A12.

[0165] (Note A14) The semiconductor substrate (12) includes a surface (12B) on which the semiconductor layer (14) is formed, and the surface (12B) includes a first edge (12C or 12E) extending along the first direction and a second edge (12D or 12F) extending along the second direction. Each of the first set of gate trenches (S1_n) has a length of no more than half the dimension of the first side (12C or 12E), Each of the second set of gate trenches (S2_n) has a length of no more than half the dimension of the second side (12D or 12F). A semiconductor device as described in any one of the appendices A1 to A13.

[0166] (Note A15) The semiconductor device according to Appendix A14, wherein each gate trench (S1_n) in the first set has a length of 1 / 3 or less of the dimension of the first side (12C or 12E).

[0167] (Note A16) The semiconductor device according to Appendix A14 or A15, wherein each of the second set of gate trenches (S2_n) has a length of no more than one-third of the dimension of the second side (12D or 12F).

[0168] (Note A17) A semiconductor device as described in any one of appendices A14 to A16, wherein the dimension of the second side is greater than the dimension of the first side, and the length of each gate trench in the second set is greater than the length of each gate trench in the first set.

[0169] (Note A18) A semiconductor device as described in any one of the appendices A1 to A17, wherein the number of gate trenches included in the first set is greater than the number of gate trenches included in the second set.

[0170] (Note A19) The semiconductor device according to any one of the appendices A1 to A18, wherein the active region (56) is a rectangular region, the short direction of the active region (56) corresponds to the first direction, and the long direction of the active region (56) corresponds to the second direction.

[0171] (Note A20) The outer peripheral region (54) is a rectangular frame-shaped region surrounding the active region (56), The semiconductor device according to Appendix A19, wherein the outer peripheral gate wiring portions (58; 106; 206; 306) extend along the boundary between the active region (56) and the outer peripheral region (54) in the outer peripheral region (54).

[0172] (Note B1) A semiconductor device, Semiconductor substrate (12) and A semiconductor layer (14) formed on the semiconductor substrate (12) includes an outer peripheral region (54) and an active region (56) surrounded by the outer peripheral region (54) in a plan view, Multiple sets of gate trenches (S1, S2), including a first set (S1) and a second set (S2), are formed in the semiconductor layer (14), A plurality of gate electrodes (20), each embedded in a corresponding gate trench among the plurality of sets of gate trenches (S1, S2), An insulating layer (16) formed on the semiconductor layer (14), The gate wiring (52;102;202;302) is formed on the insulating layer (16) and electrically connected to the plurality of gate electrodes (20), Source wiring (50;104;204;304) formed on the insulating layer (16) and spaced apart from the gate wiring (52;102;202;302) and Equipped with, Each of the first set of gate trenches (S1_n) extends along a first direction in a plan view, Each of the second set of gate trenches (S2_n) extends along a second direction perpendicular to the first direction in a plan view, The aforementioned semiconductor device is A first connecting trench (402) extending in the second direction in a plan view, which connects the first set of gate trenches (S1) to each other at their ends, A second connecting trench (404) extending in the first direction in a plan view connects the second set of gate trenches (S2) to each other at their ends. Furthermore, Semiconductor equipment.

[0173] (Note B2) The gate wiring (52;102;202;302) includes outer gate wiring sections (58;106;206;306) arranged in the outer peripheral region (54) in a plan view, and inner gate wiring sections (60;108;208;308) arranged in the active region (56) in a plan view. The outer peripheral gate wiring section (58; 106; 206; 306) includes first gate fingers (58A1 or 58A2; 106A1; 206A1 or 206A3; 306A1 or 306A2) that extend along the first direction in a plan view. The inner gate wiring section (60;108;208;308) includes a second gate finger (60B;108B;208B;308B) that extends along the second direction in a plan view. Each of the first set of gate trenches (S1_n) includes two ends and intersects with the second gate fingers (60B;108B;208B;308B) between the two ends in plan view, Each of the second set of gate trenches (S2_n) includes two ends and intersects the first gate fingers (58A1 or 58A2; 106A1; 206A1 or 206A3; 306A1 or 306A2) between the two ends in plan view. The semiconductor device described in Appendix B1.

[0174] (Note B3) The aforementioned source wiring (50; 104; 204; 304) Outer peripheral source wiring sections (64;112;212;312) arranged in the outer peripheral region (54), The inner source wiring section (66;114;214;314) located in the active region (56) and Semiconductor devices as described in Appendix B2, including the semiconductor device described in Appendix B2.

[0175] (Note B4) Each of the first set of gate trenches (S1_n) is entirely located within the active region (56), The semiconductor device according to Appendix B3, wherein each of the second set of gate trenches (S2_n) is arranged to span the active region (56) and the outer peripheral region (54).

[0176] (Note B5) Each gate electrode (20) embedded in each of the first set of gate trenches (S1_n) is electrically connected to the second gate fingers (60B;108B;208B;308B) in the region where each of the first set of gate trenches (S1_n) and the second gate fingers (60B;108B;208B;308B) intersect in a plan view. The semiconductor device according to any one of the appendices B2 to B4, wherein the gate electrodes (20) embedded in each of the second set of gate trenches (S2_n) are electrically connected to the first gate fingers (58A1 or 58A2; 106A1; 206A1 or 206A3; 306A1 or 306A2) in the region where each of the second set of gate trenches (S2_n) intersects with the first gate fingers (58A1 or 58A2; 106A1; 206A1 or 206A3; 306A1 or 306A2) in a plan view.

[0177] (Note B6) The semiconductor device according to any one of the appendices B2 to B5, wherein the second gate fingers (60B; 108B; 208B; 308B) intersect with two or more sets of gate trenches, including the first set of gate trenches (S1), in a plan view.

[0178] (Note B7) The semiconductor device according to any one of appendices B2 to B6, wherein the inner gate wiring portion (60;308) further includes at least one other gate finger (60A;308A1,308A2) that intersects the second gate finger (60B;308B) in a plan view.

[0179] (Note B8) The semiconductor device according to Appendix B7, wherein the at least one other gate finger (60A; 308A1, 308A2) includes one gate finger (60A) extending in the first direction in a plan view.

[0180] (Note B9) The semiconductor device according to Appendix B7, wherein the at least one additional gate finger (60A; 308A1, 308A2) includes two gate fingers (308A1, 308A2) extending in the first direction in a plan view.

[0181] (Note B10) The semiconductor device according to any one of appendices B2 to B9, wherein the inner gate wiring portion (208) further includes a third gate finger (208A) that forms a T-shaped joint with the second gate finger (208B) in a plan view.

[0182] (Note B11) The semiconductor device according to any one of appendices B2 to B10, wherein the outer peripheral gate wiring portion (58; 106; 206; 306) further includes a fourth gate finger (58B1 or 58B2; 106B1 or 106B2; 206B1 or 206B2; 306B1 or 306B2) extending along the second direction in a plan view.

[0183] (Note B12) The semiconductor device described in any one of the appendices B1 to B11, wherein each set of the aforementioned multiple sets of gate trenches (S1, S2) includes multiple gate trenches that are aligned parallel to each other at equal intervals.

[0184] (Note B13) The semiconductor substrate (12) includes a surface (12B) on which the semiconductor layer (14) is formed, and the surface (12B) includes a first edge (12C or 12E) extending along the first direction and a second edge (12D or 12F) extending along the second direction. Each of the first set of gate trenches (S1_n) has a length of no more than half the dimension of the first side (12C or 12E), Each of the second set of gate trenches (S2_n) has a length of no more than half the dimension of the second side (12D or 12F). A semiconductor device as described in any one of the appendices B1 to B12.

[0185] (Note B14) The semiconductor device according to Appendix B13, wherein each of the first set of gate trenches (S1_n) has a length of 1 / 3 or less of the dimension of the first side (12C or 12E).

[0186] (Note B15) The semiconductor device described in any one of the appendices B1 to B14, wherein the first communicating trench (402) and the second communicating trench (404) are arranged adjacent to each other at right angles to each other.

[0187] The above description is illustrative only. Those skilled in the art will recognize that many more possible combinations and substitutions are possible beyond the components and methods (manufacturing processes) enumerated for the purpose of illustrating the technology of this disclosure. This disclosure is intended to encompass all alternatives, variations, and modifications that fall within the scope of this disclosure, including the claims. [Explanation of Symbols]

[0188] 10, 100, 200, 300, 400… Semiconductor equipment, 12… Semiconductor substrate, 12A… Bottom surface, 12B… Top surface, 12C, 12E… First side, 12D, 12F… Second side, 14… Semiconductor layer, 16… Insulating layer, 18… Field plate electrode, 18A, 18B… Edge, 20… Electrode electrode, 22… Drift region, 24… Body region, 26… Source region, 28… Drain electrode, 30… Side wall, 32… Bottom wall, 34... Trench insulation layer, 38... Gate insulation section, 40... Lower insulation section, 42... Intermediate insulation section, 44... Contact trench, 46... Contact area, 48... Source contact, 50, 104, 204, 304... Source wiring, 52, 102, 202, 302... Gate wiring, 54... Outer perimeter area, 56... Inner area (active area), 58, 106, 206, 306... Outer gate wiring section, 60, 108, 208, 308… Inner gate wiring section, 58A1, 58A2, 58B1, 58B2, 60A, 60B, 106A1, 106A2, 106B1, 106B2, 108B, 206A1, 206A2, 206A3, 206B1, 206B2, 208A, 208B, 306A1, 306A2, 306B1, 306B2, 308A1, 308A2, 308B… Gate finger, 62, 110, 2 10, 310…Gate pad, 64, 112, 212, 312…Outer perimeter source wiring section, 66, 114, 214, 314…Inner source wiring section, 68…Field plate contact, 70…Gate contact, 72…Insulation layer, 402…First connecting trench, 404…Second connecting trench, S1…First set of gate trenches, S2…Second set of gate trenches, S1_n, S2_n…Gate trenches.

Claims

1. A semiconductor device, Semiconductor substrate and A semiconductor layer formed on the semiconductor substrate, including an outer peripheral region and an active region surrounded by the outer peripheral region in a plan view, Multiple sets of gate trenches, including a first set and a second set, are formed in the semiconductor layer. Multiple gate electrodes, each embedded in a corresponding gate trench among the multiple sets of gate trenches, An insulating layer formed on the semiconductor layer, A gate wiring formed on the insulating layer and electrically connected to the plurality of gate electrodes, Source wiring formed on the insulating layer and spaced apart from the gate wiring and Equipped with, Each of the first set of gate trenches extends along a first direction in a plan view, Each of the second set of gate trenches extends along a second direction perpendicular to the first direction in a plan view, The aforementioned semiconductor device is A first connecting trench extending along the second direction in a plan view, which connects the first set of gate trenches to each other at their ends, A second connecting trench, extending in the first direction in a plan view, connects the second set of gate trenches to each other at their ends. Furthermore, Semiconductor equipment.

2. The gate wiring includes an outer gate wiring section arranged in the outer peripheral region in a plan view, and an inner gate wiring section arranged in the active region in a plan view. The outer peripheral gate wiring portion includes a first gate finger that extends along the first direction in a plan view, The inner gate wiring portion includes a second gate finger that extends along the second direction in a plan view, Each of the first set of gate trenches includes two ends, and in plan view intersects the second gate finger between the two ends, Each of the second set of gate trenches includes two ends, and in plan view, intersects the first gate finger between the two ends. The semiconductor device according to claim 1.

3. The aforementioned source wiring is The outer peripheral source wiring section arranged in the outer peripheral region, The inner source wiring section arranged in the active region The semiconductor device according to claim 2, including the above.

4. Each of the first set of gate trenches is entirely located within the active area. The semiconductor device according to claim 3, wherein each of the second set of gate trenches is arranged to span the active region and the outer peripheral region.

5. Each gate electrode embedded in the first set of gate trenches is electrically connected to the second gate finger in the region where the first set of gate trenches and the second gate finger intersect in a plan view. The semiconductor device according to any one of claims 2 to 4, wherein the gate electrodes embedded in each of the second set of gate trenches are electrically connected to the first gate finger in the region where each of the second set of gate trenches and the first gate finger intersect in a plan view.

6. The semiconductor device according to any one of claims 2 to 5, wherein the second gate finger intersects with two or more sets of gate trenches, including the first set of gate trenches, in a plan view.

7. The semiconductor device according to any one of claims 2 to 6, wherein the inner gate wiring portion further includes at least one other gate finger that intersects the second gate finger in a plan view.

8. The semiconductor device according to claim 7, wherein the at least one additional gate finger includes one gate finger extending in the first direction in a plan view.

9. The semiconductor device according to claim 7, wherein the at least one additional gate finger includes two gate fingers extending in the first direction in a plan view.

10. The semiconductor device according to any one of claims 2 to 9, wherein the inner gate wiring portion further includes a third gate finger that forms a T-shaped joint with the second gate finger in a plan view.

11. The semiconductor device according to any one of claims 2 to 10, wherein the outer peripheral gate wiring portion further includes a fourth gate finger extending along the second direction in a plan view.

12. The semiconductor device according to any one of claims 1 to 11, wherein each set of the plurality of gate trenches includes a plurality of gate trenches arranged at equal intervals and parallel to each other.

13. The semiconductor substrate includes a surface on which the semiconductor layer is formed, and the surface includes a first edge extending along the first direction and a second edge extending along the second direction. Each of the first set of gate trenches has a length of 1 / 2 or less of the dimension of the first side, Each of the second set of gate trenches has a length of no more than half the dimension of the second side. A semiconductor device according to any one of claims 1 to 12.

14. The semiconductor device according to claim 13, wherein each of the first set of gate trenches has a length of 1 / 3 or less of the dimension of the first side.

15. The semiconductor device according to any one of claims 1 to 14, wherein the first communicating trench and the second communicating trench are arranged adjacent to each other at right angles to each other.

Images