Semiconductor equipment

Abstract

To provide a semiconductor device with improved characteristics. [Solution] According to the embodiment, the semiconductor device includes first to fourth electrodes, a semiconductor member, and first and second insulating members. At least a portion of the semiconductor member is located between the first electrode and the second electrode. The semiconductor member includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a fourth semiconductor region of a first conductivity type, a fifth semiconductor region of the second conductivity type, and a sixth semiconductor region of a first conductivity type. The fifth semiconductor region includes first to fourth partial regions. At least a portion of the second insulating member is located between the fourth electrode and the first semiconductor portion, between the fourth electrode and the second partial region, and between the fourth electrode and the fourth semiconductor region. The first electrode is electrically connected to the fifth semiconductor region. In the first direction, the sixth semiconductor region is not provided between the first electrode and the fourth partial region.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] For example, in semiconductor devices, improved performance is desired. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-49610 [Overview of the project] [Problems that the invention aims to solve]

[0004] Embodiments of the present invention provide a semiconductor device capable of improving its characteristics. [Means for solving the problem]

[0005] According to embodiments of the present invention, the semiconductor device includes a first electrode, a second electrode, a third electrode, a fourth electrode, a semiconductor member, a first insulating member, and a second insulating member. At least a portion of the semiconductor member is located between the first electrode and the second electrode in a first direction from the first electrode to the second electrode. The semiconductor member includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, and a sixth semiconductor region of the first conductivity type. The second electrode is electrically connected to the third semiconductor region. At least a portion of the second semiconductor region is located between the first semiconductor region and the third semiconductor region. At least a portion of the first insulating member is located between the third electrode and the first semiconductor region, between the third electrode and the second semiconductor region, and between the third electrode and the third semiconductor region. The fifth semiconductor region includes a first partial region, a second partial region, a third partial region, and a fourth partial region. The fourth semiconductor region is located between the second and fourth subregions in a second direction intersecting the first direction. The sixth semiconductor region includes the first semiconductor region. The first semiconductor region is located between the third and fourth semiconductor regions in the second direction. The second subregion is located between the first semiconductor region and the fourth semiconductor region. A portion of the first semiconductor region is located between the first electrode and the first subregion in the first direction. Another portion of the first semiconductor region is located between the fourth electrode and the first subregion in the first direction. The fourth subregion is located between the first electrode and the first semiconductor region in the first direction. At least a portion of the second insulating member is located between the fourth electrode and the first semiconductor region, between the fourth electrode and the second subregion, and between the fourth electrode and the fourth semiconductor region. The first electrode is electrically connected to the fifth semiconductor region. The sixth semiconductor region is not provided between the first electrode and the fourth subregion in the first direction. [Brief explanation of the drawing]

[0006] [Figure 1]FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view illustrating a semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a schematic plan view illustrating a semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a schematic plan view illustrating a semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a schematic plan view illustrating a semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a schematic plan view illustrating a semiconductor device according to the second embodiment. [Figure 13] FIG. 13 is a schematic plan view illustrating a semiconductor device according to the second embodiment. [Figure 14] FIG. 14 is a schematic plan view illustrating a semiconductor device according to the second embodiment. [Figure 15] FIG. 15 is a schematic plan view illustrating a semiconductor device according to the second embodiment. [Figure 16] FIG. 16 is a schematic plan view illustrating a semiconductor device according to the second embodiment. [Figure 17] FIG. 17 is a schematic plan view illustrating a semiconductor device according to the second embodiment. [Figure 18] Figure 18 is a schematic transparent plane illustrating a semiconductor device according to the second embodiment. [Figure 19] Figure 19 is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those described above are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] (First Embodiment) Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. Figure 2 is a schematic transparent plane illustrating a semiconductor device according to the first embodiment. Figure 1 corresponds to the cross-sectional view along line A1-A2 in Figure 2. As shown in Figure 1, the semiconductor device 110 according to this embodiment includes a first electrode 51, a second electrode 52, a third electrode 53, a fourth electrode 54, a semiconductor member 10M, a first insulating member 41, and a second insulating member 42.

[0009] At least a portion of the semiconductor member 10M is located between the first electrode 51 and the second electrode 52 in a first direction D1 from the first electrode 51 to the second electrode 52.

[0010] The first direction D1 is defined as the Z-axis direction. One direction perpendicular to the Z-axis direction is defined as the X-axis direction. The direction perpendicular to both the Z-axis and X-axis directions is defined as the Y-axis direction.

[0011] The semiconductor component 10M includes a first semiconductor region 11 of a first conductivity type, a second semiconductor region 12 of a second conductivity type, a third semiconductor region 13 of a first conductivity type, a fourth semiconductor region 14 of a first conductivity type, a fifth semiconductor region 15 of a second conductivity type, and a sixth semiconductor region 16 of a first conductivity type. The first conductivity type is either n-type or p-type. The second conductivity type is the other of n-type and p-type. Hereafter, the first conductivity type will be assumed to be n-type and the second conductivity type to be p-type.

[0012] The second electrode 52 is electrically connected to the third semiconductor region 13. At least a portion of the second semiconductor region 12 lies between the first semiconductor region 11 and the third semiconductor region 13. At least a portion of the first insulating member 41 lies between the third electrode 53 and a portion of the first semiconductor region 11, between the third electrode 53 and the second semiconductor region 12, and between the third electrode 53 and the third semiconductor region 13. At least a portion of the third electrode 53 faces a portion of the first semiconductor region 11, the second semiconductor region 12, and the third semiconductor region 13.

[0013] The fifth semiconductor region 15 includes the first subregion 15a, the second subregion 15b, the third subregion 15c, and the fourth subregion 15d. The fifth semiconductor region 15 may further include other subregions (e.g., the fifth subregion 15e). In these subregions, the boundaries between them may be clear or unclear.

[0014] The fourth semiconductor region 14 is located between the second subregion 15b and the fourth subregion 15d in the second direction D2, which intersects with the first direction D1.

[0015] The sixth semiconductor region 16 includes the first semiconductor portion 16a. The first semiconductor portion 16a is located between the third partial region 15c and the fourth semiconductor region 14 in the second direction D2. The second partial region 15b is located between the first semiconductor portion 16a and the fourth semiconductor region 14 in the second direction D2.

[0016] A portion of the first semiconductor portion 16a lies between the first electrode 51 and the first partial region 15a in the first direction D1. Another portion of the first semiconductor portion 16a lies between the fourth electrode 54 and the first partial region 15a in the first direction D1.

[0017] The fourth subregion 15d is located between the first electrode 51 and the first semiconductor region 11 in the first direction D1. In this example, a portion of the fourth subregion 15d is located between the fifth subregion 15e and the first semiconductor region 11 in the first direction D1.

[0018] At least a portion of the second insulating member 42 is located between the fourth electrode 54 and the first semiconductor portion 16a, between the fourth electrode 54 and the second partial region 15b, and between the fourth electrode 54 and the fourth semiconductor region 14. The first electrode 51 is electrically connected to the fifth semiconductor region 15. For example, the first electrode 51 is electrically connected to the third partial region 15c, the fourth partial region 15d, and the fifth partial region 15e. The first electrode 51 may be in contact with the third partial region 15c, the fourth partial region 15d, and the fifth partial region 15e.

[0019] As shown in Figure 1, in the first direction D1, the sixth semiconductor region 16 is not provided between the first electrode 51 and the fourth partial region 15d. As shown in Figure 1, the semiconductor member 10M is asymmetric with respect to the axis along the first direction D1, including the fourth electrode 54. For example, the sixth semiconductor region 16 is not provided between the fourth semiconductor region 14 and the fifth partial region 15e.

[0020] The current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The first electrode 51 functions as a collector electrode. The second electrode 52 functions as an emitter electrode. The third electrode 53 functions as a gate electrode. The semiconductor device 110 is, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0021] The semiconductor device 110 includes the fourth electrode 54 described above. A portion of the fourth electrode 54 faces the sixth semiconductor region 16 of the first conductivity type, a portion of the fifth semiconductor region 15 of the second conductivity type, and the fourth semiconductor region 14 of the first conductivity type. By controlling the potential of the fourth electrode 54, for example, the charge (e.g., holes) injected from the first electrode 51 can be controlled. For example, the charge (e.g., holes) injected from the fifth semiconductor region 15 toward the seventh semiconductor region 17, which will be described later, can be controlled.

[0022] In the left portion of Figure 1, the current path, which includes the first semiconductor portion 16a, the second subregion 15b, and the fourth semiconductor region 14, can be controlled by the potential of the fourth electrode 54. For example, when the potential of the fourth electrode 54 exceeds a threshold, a current path is formed in the portion of the second subregion 15b facing the fourth electrode 54. By controlling the potential of the fourth electrode 54, the current path is opened and closed. For example, when the current path is open, electrons can move from the fourth semiconductor region 14 towards the first electrode 51 via the second subregion 15b and the first semiconductor portion 16a. For example, electrons are discharged towards the first electrode 51.

[0023] On the other hand, no such current path is provided in the right-hand portion of Figure 1. In the right-hand portion of Figure 1, the potential of the fourth electrode 54 controls the injection of holes from the first electrode 51 to the first semiconductor region 11 via the fourth subregion 15d. This is thought to be due to the control of the potential of the region including the fourth semiconductor region 14 and the fourth subregion 15d by the potential of the fourth electrode 54. This is thought to be a phenomenon associated with charge discharge in the left-hand portion of Figure 1.

[0024] In this embodiment, electrons are ejected by switching a current path that includes the first semiconductor portion 16a, the second partial region 15b, and the fourth semiconductor region 14. On the other hand, in the region including the fourth partial region 15d, hole injection is controlled by controlling the potential. Carriers can be effectively controlled by multiple different mechanisms. In the semiconductor device 110, hole injection may also be controlled in the region including the first partial region 15a.

[0025] In the embodiment, efficient electron discharge and suppression of hole injection are effectively achieved. For example, conduction loss is effectively suppressed. According to the embodiment, a semiconductor device capable of improving characteristics is provided.

[0026] As shown in Figure 1, the semiconductor device 110 may include a control unit 70. The control unit 70 may be included in the semiconductor device 110. The control unit 70 may be provided separately from the semiconductor device 110. The control unit 70 is electrically connected to the first electrode 51, the second electrode 52, the third electrode 53, and the fourth electrode 54. An example of the operation of the semiconductor device 110 will be described below.

[0027] Figure 3 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. In Figure 3, the horizontal axis represents time tm. Figure 3 illustrates the potential of the third electrode 53 (third electrode potential V3) and the potential of the fourth electrode 54 (fourth electrode potential V4). The control unit 70 is configured to perform the first operation. This corresponds to the off operation in the semiconductor device 110.

[0028] As shown in Figure 3, in the first operation, the control unit 70 is configured to set the third electrode potential V3 of the third electrode 53 to a first potential E1 with respect to the second electrode potential of the second electrode 52 at the first time t1. In the first operation, the control unit 70 is configured to set the third electrode potential V3 to a second potential E2 with respect to the second electrode potential at the second time t2. The second time t2 is after the first time t1. The first potential E1 is higher than the second potential E2. In the first operation, the control unit 70 is configured to set the fourth electrode potential V4 of the fourth electrode 54 to a third potential E3 with respect to the first electrode potential of the first electrode 51 at the third time t3. In the first operation, the control unit 70 is configured to set the fourth electrode potential V4 to a fourth potential E4 with respect to the first electrode potential at the fourth time t4. The fourth time t4 is after the third time t3. The third potential E3 is lower than the fourth potential E4. The fourth time t4 is before the second time t2, or is the same as the second time t2.

[0029] Such operations may be applied to the third electrode 53 and the fourth electrode 54. By appropriately controlling the potential of the fourth electrode 54, for example, electrons can be effectively discharged. By applying an asymmetric configuration, for example, appropriate opening and closing of the current path and suppression of hole injection in the region including the fourth subregion 15d can be achieved. For example, losses can be effectively reduced. A semiconductor device with improved characteristics can be provided. In the embodiment, for example, a current path is formed in one of the second directions D2 of the fourth electrode 54. For example, the current density can be increased. For example, the constraints on the position of the fourth electrode 54 are relaxed, and the fourth electrode 54 can be obtained stably with high productivity.

[0030] As shown in Figure 2, at least a portion of the fourth electrode 54 may extend along the third direction D3. The third direction D3 intersects the plane containing the first direction D1 and the second direction D2. The third direction D3 may be, for example, the Y-axis direction.

[0031] The fourth semiconductor region 14 may extend along the third direction D3. The first semiconductor portion 16a may extend along the third direction D3.

[0032] As shown in Figure 1, the semiconductor member 10M may further include a seventh semiconductor region 17 of the first conductivity type. Part of the seventh semiconductor region 17 lies between the fourth semiconductor region 14 and the first semiconductor region 11 in the first direction D1. Another part of the seventh semiconductor region 17 lies between the fifth semiconductor region 15 and the first semiconductor region 11 in the first direction D1. The impurity concentration of the first conductivity type in the seventh semiconductor region 17 is higher than the impurity concentration of the first conductivity type in the first semiconductor region 11.

[0033] As shown in Figure 1, in this example, the direction from the third electrode 53 to the second semiconductor region 12 follows the fourth direction D4, which intersects the first direction D1. The direction from the third electrode 53 to the third semiconductor region 13 follows the fourth direction D4.

[0034] The fourth direction D4 may be along the second direction D2. The fourth direction D4 may also intersect the second direction D2. The angle between the fourth direction D4 and the second direction D2 is arbitrary.

[0035] As shown in Figure 1, in this example, the direction from a portion 10p of the first semiconductor region 11 to the third electrode 53 is along the first direction D1. The direction from the third electrode 53 to another portion 10q of the first semiconductor region 11 is along the fourth direction D4. In this example, the third electrode 53 is a trench gate. The third electrode 53 may extend along the fifth direction D5. The fifth direction D5 intersects the plane containing the first direction D1 and the fourth direction D4.

[0036] In this example, the semiconductor member 10M includes an eighth semiconductor region 18 of the second conductivity type. In the fourth direction D4, the third electrode 53 may be provided between the eighth semiconductor region 18 and the second semiconductor region 12.

[0037] In this embodiment, the direction from the third semiconductor region 13 to the third electrode 53 may also be along the first direction D1.

[0038] Multiple third electrodes 53 may be provided. The multiple third electrodes 53 are arranged along the fourth direction D4.

[0039] In this embodiment, a plurality of fourth electrodes 54 may be provided. The plurality of fourth electrodes 54 extend in the fifth direction D5. The plurality of fourth electrodes 54 may be arranged along the fourth direction D4. Corresponding to one fourth electrode 54, a set is provided that includes a first partial region 15a, a fourth semiconductor region 14, and a fourth partial region 15d. Multiple sets may be arranged along the second direction D2.

[0040] The pitch of the multiple fourth electrodes 54 in the second direction D2 (second pitch) may be longer than the pitch of the multiple third electrodes 53 in the fourth direction D4 (first pitch).

[0041] For example, in the first reference example, a sixth semiconductor region 16 is provided between the fourth electrode 54 and the fourth partial region 15d. In the first reference example, two sixth semiconductor regions 16 are provided, and two current paths are opened and closed corresponding to the potential of one fourth electrode 54. In the first reference example, the semiconductor member 10M is symmetrical with respect to an axis that includes the fourth electrode 54 and is aligned with the first direction D1.

[0042] On the other hand, in this embodiment, one sixth semiconductor region 16 is provided corresponding to one of the multiple fourth electrodes 54. One current path is opened and closed corresponding to the potential of one of the fourth electrodes 54. If the pitch of the multiple fourth electrodes 54 in this embodiment is the same as the pitch in the first reference example, the density of the sixth semiconductor region 16 corresponding to the pitch in this embodiment is half the density in the first reference example. In this embodiment, compared to the first reference example, charge control by the potential of the fourth electrode 54 can be performed without reducing the area of ​​the fifth semiconductor region 15.

[0043] In the first reference example, if the area of ​​the sixth semiconductor region 16 is large and the area of ​​the fifth semiconductor region 15 is small, for example, the area of ​​the region contributing to charge injection when the current path is closed becomes smaller. This results in, for example, increased conduction loss. In the first reference example, for example, the change in the potential of the fourth semiconductor region 14 that occurs in response to the change in the potential of the fourth electrode 54 tends to decrease excessively. This tends to reduce the switching time margin. For example, the effect is significant if the switching timing of the third electrode 53 and the fourth electrode 54 is shifted from the appropriate timing. Stable operation is difficult to obtain.

[0044] In contrast, in the embodiment, compared with the first reference example, the density of the sixth semiconductor region 16 is half and the area of the fifth semiconductor region 15 is large. In the embodiment, for example, when closing the current path, the area of the region contributing to charge injection is large. Thereby, for example, conduction loss can be reduced. For example, the power per unit volume can be increased. For example, the time margin can be increased. For example, when the switching timing of each of the third electrode 53 and the fourth electrode 54 shifts from an appropriate timing, the influence is small. It is easy to obtain stable operation. When the current path is opened by the potential of the fourth electrode 54, charge control equal to or higher than that of the first reference example is possible. Thereby, for example, the combined loss of conduction loss and turn-off loss can be reduced.

[0045] In the embodiment, the impurity concentration of the first conductivity type (the sixth impurity concentration) in the sixth semiconductor region 16 may be higher than the impurity concentration of the first conductivity type (the fourth impurity concentration) in the fourth semiconductor region 14. The sixth impurity concentration is, for example, 1×10 14 cm -3 or more and 1×10 21 cm -3 or less. The fourth impurity concentration is, for example, 1×10 11 cm -3 or more and 1×10 15 cm -3 or less.

[0046] The impurity concentration of the second conductivity type (the third partial region impurity concentration) in the third partial region 15c may be higher than the impurity concentration of the second conductivity type (the second partial region impurity concentration) in the second partial region 15b. The third partial region impurity concentration is, for example, 1×10 13 cm -3 or more and 1×10 21 cm -3 or less. The second partial region impurity concentration is, for example, 1×10 13 cm -3 or more and 1×10 19 cm -3The following is acceptable. The impurity concentration in the third subregion may be higher than the impurity concentration of the second conductivity type in the first subregion 15a (the impurity concentration in the first subregion). The impurity concentration in the first subregion is, for example, 1 × 10⁻⁶ 13 cm -3 The above is 1 x 10 19 cm -3 The following is fine.

[0047] The impurity concentration of the second conductivity type in the fifth subregion 15e (fifth subregion impurity concentration) may be higher than the impurity concentration of the second conductivity type in the fourth subregion 15d (fourth subregion impurity concentration). The impurity concentration of the fifth subregion is, for example, 1 × 10⁻⁶ 13 cm -3 The above is 1 x 10 21 cm -3 The following is acceptable. The impurity concentration in the fourth subregion is, for example, 1 × 10⁻⁶. 13 cm -3 The above is 1 x 10 19 cm -3 The following is fine.

[0048] The impurity concentration of the first conductivity type (third impurity concentration) in the third semiconductor region 13 is higher than the impurity concentration of the first conductivity type (first impurity concentration) in the first semiconductor region 11. The third impurity concentration is, for example, 1 × 10⁻⁶ 14 cm -3 The above is 1 x 10 21 cm -3 The following is acceptable. The first impurity concentration is, for example, 1 × 10⁻⁶ 11 cm -3 The above is 1 x 10 15 cm -3 The following is fine.

[0049] The impurity concentration of the first conductivity type in the seventh semiconductor region 17 is, for example, 1 × 10⁻⁶ 13 cm -3 The above is 1 x 10 19 cm -3 The following is acceptable. The impurity concentration of the second conductivity type in the eighth semiconductor region 18 is, for example, 1 × 10⁻⁶. 11 cm -3 The above is 1 x 10 18 cm -3 The following is fine.

[0050] As shown in Figure 1, the semiconductor device 110 may further include a third insulating member 43. At least a portion of the third insulating member 43 is located between the third electrode 53 and the second electrode 52.

[0051] Figures 4 to 7 are schematic cross-sectional views illustrating a semiconductor device according to the first embodiment. Figure 8 is a schematic transparent plane illustrating a semiconductor device according to the first embodiment. Figure 4 corresponds to the section view along line A1-A2 in Figure 8. Figure 5 corresponds to the section view along line A3-A4 in Figure 8. Figure 6 corresponds to the section view along line A5-A6 in Figure 8. Figure 7 corresponds to the section view along line A7-A8 in Figure 8.

[0052] As shown in Figure 8, in the semiconductor device 111 according to this embodiment, the sixth semiconductor region 16 further includes the third semiconductor portion 16c. The configuration of the semiconductor device 112, excluding this region, may be the same as that of the semiconductor device 110.

[0053] As shown in Figures 5 and 8, the sixth semiconductor region 16 may further include the second semiconductor portion 16b. The fourth semiconductor region 14 is located between the second partial region 15b and the second semiconductor portion 16b in the second direction D2. The second semiconductor portion 16b is located between the first electrode 51 and a part of the fourth partial region 15d in the first direction D1.

[0054] In this example, the fifth semiconductor region 15 further includes a fifth subregion 15e and a sixth subregion 15f. The sixth subregion 15f lies between the fourth semiconductor region 14 and the second semiconductor subregion 16b in the second direction D2. The second semiconductor subregion 16b lies between the sixth subregion 15f and the fifth subregion 15e in the second direction D2. A portion of the fourth electrode 54 faces the sixth subregion 15f and the second semiconductor subregion 16b in the first direction D1. The first electrode 51 is electrically connected to the fifth subregion 15e.

[0055] As shown in Figure 5, a portion of the semiconductor member 10M may be symmetrical with respect to the axis including the fourth electrode 54 and along the first direction D1. As shown in Figure 4, another portion of the semiconductor member 10M may be asymmetrical with respect to the axis including the fourth electrode 54 and along the first direction D1. Even with such a configuration, conduction loss is effectively suppressed, and the characteristics can be improved.

[0056] As shown in Figures 6 and 8, the fifth semiconductor region 15 may further include the seventh subregion 15g. As shown in Figure 8, the third direction D3 from the seventh subregion 15g to the first semiconductor region 16a intersects the plane containing the first direction D1 and the second direction D2.

[0057] As shown in Figures 6 and 8, the fifth semiconductor region 15 may further include the eighth subregion 15h. As shown in Figure 8, the direction from the eighth subregion 15h to the second semiconductor region 16b is along the third direction D3. As shown in Figure 6, another part of the semiconductor member 10M may be symmetrical with respect to an axis that includes the fourth electrode 54 and is along the first direction D1.

[0058] As shown in Figures 7 and 8, the sixth semiconductor region 16 may further include the third semiconductor portion 16c. The eighth portion region 15h is located between the third semiconductor portion 16c and the second semiconductor portion 16b in the third direction D3.

[0059] As shown in Figures 7 and 8, the fifth semiconductor region 15 may further include a ninth subregion 15i. The ninth subregion 15i is located between the fourth semiconductor region 14 and the third semiconductor region 16c in the second direction D2.

[0060] As shown in Figure 7, a portion of the fourth electrode 54 faces the ninth subregion 15i and the third semiconductor portion 16c in the first direction D1. As shown in Figure 7, another portion of the semiconductor member 10M may be asymmetrical with respect to the axis along the first direction D1 that includes the fourth electrode 54.

[0061] Figure 9 is a schematic transparent plane illustrating a semiconductor device according to the first embodiment. As shown in Figure 9, in the semiconductor device 112 according to this embodiment, the sixth semiconductor region 16 further includes the third semiconductor portion 16c. The configuration of the semiconductor device 112 excluding this region may be the same as that of the semiconductor device 110.

[0062] In the semiconductor device 112, the fifth semiconductor region 15 further includes a ninth subregion 15i. The ninth subregion 15i lies between the fourth semiconductor region 14 and the third semiconductor region 16c in the second direction D2. The position of the third semiconductor region 16c in the third direction D3 (third semiconductor region position) is different from the position of the first semiconductor region 16a in the third direction D3 (first semiconductor region position). As already explained, the third direction D3 intersects the plane containing the first direction D1 and the second direction D2.

[0063] As in semiconductor device 112, the two parts of the semiconductor member 10M may be asymmetrical with respect to an axis along the first direction D1, including the fourth electrode 54.

[0064] Figure 10 is a schematic transparent plane illustrating a semiconductor device according to the first embodiment. As shown in Figure 10, in the semiconductor device 113 according to this embodiment, the sixth semiconductor region 16 further includes the fourth semiconductor portion 16d. The configuration of the semiconductor device 113 excluding this portion may be the same as that of the semiconductor device 110.

[0065] The fifth semiconductor region 15 may further include the seventh subregion 15g and the tenth subregion 15j. The tenth subregion 15j lies between the fourth semiconductor portion 16d and the fourth semiconductor region 14 in the second direction D2. The seventh subregion 15g lies between the fourth semiconductor portion 16d and the first semiconductor portion 16a in the third direction D3. As already explained, the third direction D3 intersects the plane containing the first direction D1 and the second direction D2.

[0066] As shown in Figures 2, 8, 9, and 10, in semiconductor devices 110, 111, 112, and 113, the fourth electrode 54 may overlap with the second subregion 15b and the fourth subregion 15d in the first direction D1.

[0067] (Second Embodiment) Figure 11 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. Figure 12 is a schematic transparent plane illustrating a semiconductor device according to the second embodiment. Figure 11 is a cross-sectional view taken along the line A1-A2 in Figure 12. As shown in Figures 11 and 12, the configuration of the fourth electrode 54 in the semiconductor device 120 according to this embodiment is different from that of the semiconductor device 110. The rest of the configuration of the semiconductor device 120 may be the same as that of the semiconductor device 110.

[0068] As shown in Figures 11 and 12, in the semiconductor device 120, the fourth electrode 54 overlaps with the first semiconductor portion 16a, the second partial region 15b, and the fourth semiconductor region 14 in the first direction D1. The fourth electrode 54 does not overlap with the fourth partial region 15d in the first direction D1. In such a semiconductor device 120, the opening and closing of the current path including the first semiconductor portion 16a, the second partial region 15b, and the fourth semiconductor region 14 is controlled by controlling the potential of the fourth electrode 54. By controlling the potential of the fourth electrode 54, for example, the potential of the fourth semiconductor region 14 can be controlled. By appropriately controlling the potential of the fourth semiconductor region 14, for example, hole injection from the fourth partial region 15d to the first semiconductor region 11 is suppressed. Conduction loss is effectively suppressed. Characteristics can be improved. For example, the controllability of opening and closing the current path of the second partial region 15b can be improved.

[0069] Figure 13 is a schematic transparent plane illustrating a semiconductor device according to the second embodiment. As shown in Figure 13, the semiconductor device 121 according to this embodiment is provided with a plurality of fourth electrodes 54. The configuration of the semiconductor device 121, aside from these electrodes, may be the same as that of the semiconductor device 111.

[0070] In the semiconductor device 121, one of the multiple fourth electrodes 54 overlaps with the first semiconductor portion 16a and the fourth semiconductor region 14 in the first direction D1. Another of the multiple fourth electrodes 54 overlaps with the second semiconductor portion 16b and the fourth semiconductor region 14 in the first direction D1.

[0071] Figure 14 is a schematic transparent plane illustrating a semiconductor device according to the second embodiment. As shown in Figure 14, the semiconductor device 121a according to this embodiment is provided with a plurality of fourth electrodes 54. The configuration of the semiconductor device 121a, aside from these electrodes, may be the same as that of the semiconductor device 111.

[0072] In the semiconductor device 121a, one of the plurality of fourth electrodes 54 overlaps with the first semiconductor portion 16a and the fourth semiconductor region 14 in the first direction D1. Another of the plurality of fourth electrodes 54 overlaps with the third semiconductor portion 16c and the fourth semiconductor region 14 in the first direction D1. Yet another of the plurality of fourth electrodes 54 may overlap with the second semiconductor portion 16b and the fourth semiconductor region 14 in the first direction D1.

[0073] Figure 15 is a schematic transparent plane illustrating a semiconductor device according to the second embodiment. As shown in Figure 15, the semiconductor device 122 according to this embodiment is provided with a plurality of fourth electrodes 54. The configuration of the semiconductor device 122, aside from these electrodes, may be the same as that of the semiconductor device 112.

[0074] In the semiconductor device 122, one of the plurality of fourth electrodes 54 overlaps with the first semiconductor portion 16a and the fourth semiconductor region 14 in the first direction D1. Another of the plurality of fourth electrodes 54 overlaps with the third semiconductor portion 16c and the fourth semiconductor region 14 in the first direction D1. The direction from one of the plurality of fourth electrodes 54 to another of the plurality of fourth electrodes 54 is along the second direction D2.

[0075] Figure 16 is a schematic transparent plane illustrating a semiconductor device according to the second embodiment. As shown in Figure 16, the semiconductor device 122a according to this embodiment is provided with a plurality of fourth electrodes 54. The configuration of the semiconductor device 122a, excluding these electrodes, may be the same as that of the semiconductor device 112.

[0076] In the semiconductor device 122a, one of the multiple fourth electrodes 54 overlaps with the first semiconductor portion 16a and the fourth semiconductor region 14 in the first direction D1. Another of the multiple fourth electrodes 54 overlaps with the third semiconductor portion 16c and the fourth semiconductor region 14 in the first direction D1. One of the multiple fourth electrodes 54 does not overlap with another of the multiple fourth electrodes 54 in the second direction D2.

[0077] Figure 17 is a schematic transparent plane illustrating a semiconductor device according to the second embodiment. As shown in Figure 17, in the semiconductor device 123 according to this embodiment, the configuration of the fourth electrode 54 is different from that of the semiconductor device 113. The configuration of the semiconductor device 123, excluding this, may be the same as that of the semiconductor device 113.

[0078] In the semiconductor device 123, the fourth electrode 54 overlaps with the first semiconductor portion 16a, the fourth semiconductor portion 16d, and the fourth semiconductor region 14. The fourth electrode 54 does not overlap with the fourth partial region 15d.

[0079] Figure 18 is a schematic transparent plane illustrating a semiconductor device according to the second embodiment. As shown in Figure 18, in the semiconductor device 123a according to this embodiment, the configuration of the fourth electrode 54 is different from that of the semiconductor device 113. The configuration of the semiconductor device 123, excluding this, may be the same as that of the semiconductor device 113.

[0080] In the semiconductor device 123a, one of the multiple fourth electrodes 54 overlaps with the first semiconductor portion 16a and the fourth semiconductor region 14. Another of the multiple fourth electrodes 54 overlaps with the fourth semiconductor portion 16d and the fourth semiconductor region 14. Each of the multiple fourth electrodes 54 does not overlap with the fourth partial region 15d.

[0081] In semiconductor devices 121, 121a, 122, 122a, 123, and 123a, for example, conduction loss can be effectively suppressed, thereby improving performance.

[0082] (Second Embodiment) Figure 19 is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment. As shown in Figure 19, in the semiconductor device 130 according to this embodiment, the configuration of the fourth partial region 15d is different from that of the semiconductor device according to the first or second embodiment. The configuration of the semiconductor device 130, excluding this region, may be the same as that of the semiconductor device according to the first or second embodiment (for example, semiconductor device 110).

[0083] In the semiconductor device 130, the fifth partial region 15e is located between the first electrode 51 and the fourth partial region 15d. The fourth partial region 15d is located between the fifth partial region 15e and the first semiconductor region 11. In the semiconductor device 130 as well, for example, conduction loss is effectively suppressed. Characteristics can be improved. The configuration described with respect to the semiconductor device 130 may be applied, for example, to the first embodiment, the second embodiment and variations thereof.

[0084] In embodiments, at least one of the first electrode 51 and the second electrode 52 may contain a metal. The metal may include, for example, at least one selected from the group consisting of Al, Ti, Ni, Au, Ag, and Cu. At least one of the third electrode 53 and the fourth electrode 54 may contain polysilicon. The semiconductor member 10M may contain silicon. The semiconductor member 10M may contain a compound semiconductor. The compound semiconductor may contain at least one selected from the group consisting of SiC, GaN, GaO, and GaAs.

[0085] In the embodiment, information regarding the shape of the nitride region can be obtained, for example, by electron microscope images. Information regarding composition and elemental concentration can be obtained, for example, by EDX (Energy Dispersive X-ray Spectroscopy) or SIMS (Secondary Ion Mass Spectrometry). Information regarding composition may also be obtained, for example, by reciprocal lattice space mapping.

[0086] The embodiments may include the following technical proposals. (Technical proposal 1) First electrode and, The second electrode and The third electrode and The fourth electrode and Semiconductor components and First insulating member and The second insulating member, Equipped with, At least a portion of the semiconductor member is located between the first electrode and the second electrode in a first direction from the first electrode to the second electrode, The aforementioned semiconductor member is The first semiconductor region of the first conductivity type, The second semiconductor region of the second conductivity type, The third semiconductor region of the first conductivity type, The fourth semiconductor region of the first conductivity type, The fifth semiconductor region of the second conductivity type, The sixth semiconductor region of the first conductivity type, Includes, The second electrode is electrically connected to the third semiconductor region. At least a portion of the second semiconductor region lies between the first semiconductor region and the third semiconductor region. At least a portion of the first insulating member is located between the third electrode and the first semiconductor region, between the third electrode and the second semiconductor region, and between the third electrode and the third semiconductor region. The fifth semiconductor region includes a first subregion, a second subregion, a third subregion, and a fourth subregion. The fourth semiconductor region is located between the second and fourth subregions in a second direction intersecting the first direction. The sixth semiconductor region includes the first semiconductor portion, The first semiconductor portion is located between the third subregion and the fourth semiconductor region in the second direction. The aforementioned second subregion is located between the first semiconductor subregion and the fourth semiconductor subregion. A portion of the first semiconductor part is located between the first electrode and the first partial region in the first direction. Another part of the first semiconductor portion is located between the fourth electrode and the first subregion in the first direction. The fourth subregion is located between the first electrode and the first semiconductor region in the first direction. At least a portion of the second insulating member is located between the fourth electrode and the first semiconductor portion, between the fourth electrode and the second partial region, and between the fourth electrode and the fourth semiconductor region. The first electrode is electrically connected to the fifth semiconductor region. A semiconductor device in which, in the first direction, the sixth semiconductor region is not provided between the first electrode and the fourth partial region.

[0087] (Technical proposal 2) The sixth semiconductor region further includes the second semiconductor portion, The aforementioned fourth semiconductor region is located between the aforementioned second subregion and the aforementioned second semiconductor portion in the aforementioned second direction. The semiconductor device according to Technical Proposal 1, wherein the second semiconductor portion is located between the first electrode and a part of the fourth subregion in the first direction.

[0088] (Technical proposal 3) The fifth semiconductor region further includes a fifth subregion and a sixth subregion, The sixth subregion is located between the fourth semiconductor region and the second semiconductor region in the second direction. The semiconductor device according to Technical Proposal 2, wherein the second semiconductor portion is located between the sixth subregion and the fifth subregion in the second direction.

[0089] (Technical proposal 4) The fifth semiconductor region further includes a seventh subregion, The semiconductor device according to Technical Proposal 2, wherein the third direction from the seventh subregion to the first semiconductor subregion intersects a plane including the first and second directions.

[0090] (Technical proposal 5) The fifth semiconductor region further includes an eighth subregion, The semiconductor device according to Technical Proposal 4, wherein the direction from the eighth subregion to the second semiconductor subregion is along the third direction.

[0091] (Technical proposal 6) The sixth semiconductor region further includes the third semiconductor portion, The semiconductor device according to Technical Proposal 5, wherein the eighth sub-region is located between the third semiconductor portion and the second semiconductor portion in the third direction.

[0092] (Technical proposal 7) The fifth semiconductor region further includes a ninth subregion, The semiconductor device according to Technical Proposal 6, wherein the ninth sub-region is located between the fourth semiconductor region and the third semiconductor portion in the second direction.

[0093] (Technical proposal 8) Including a plurality of the above-mentioned fourth electrodes, One of the plurality of fourth electrodes overlaps with the first semiconductor portion and the fourth semiconductor region in the first direction. The semiconductor device according to any one of the above-mentioned fourth electrodes, wherein another one of the plurality of fourth electrodes overlaps with the second semiconductor portion and the fourth semiconductor region in the first direction, as described in any one of the technical proposals 2 to 7.

[0094] (Technical proposal 9) Including a plurality of the above-mentioned fourth electrodes, One of the plurality of fourth electrodes overlaps with the first semiconductor portion and the fourth semiconductor region in the first direction. The semiconductor device according to Art Proposal 6 or 7, wherein one of the plurality of fourth electrodes overlaps with the third semiconductor portion and the fourth semiconductor region in the first direction.

[0095] (Technical proposal 10) The semiconductor device according to any one of the technical proposals 1 to 9, wherein the fourth electrode overlaps with the fourth subregion in the first direction.

[0096] (Technical proposal 11) The semiconductor device according to any one of the technical proposals 1 to 9, wherein the fourth electrode does not overlap with the fourth subregion in the first direction.

[0097] (Technical proposal 12) The sixth semiconductor region further includes the third semiconductor portion, The fifth semiconductor region further includes a ninth subregion, The ninth subregion is located between the fourth semiconductor region and the third semiconductor region in the second direction. The position of the third semiconductor portion in the third direction is different from the position of the first semiconductor portion in the third direction of the first semiconductor portion. The semiconductor device according to Technical Proposal 1, wherein the third direction intersects with a plane including the first and second directions.

[0098] (Technical proposal 13) The sixth semiconductor region further includes the fourth semiconductor portion, The fifth semiconductor region further includes the seventh and tenth subregions, The 10th subregion is located between the 4th semiconductor portion and the 4th semiconductor region in the 2nd direction. The semiconductor device according to Technical Proposal 1, wherein the seventh sub-region is located between the fourth semiconductor portion and the first semiconductor portion in a third direction intersecting a plane including the first and second directions.

[0099] (Technical proposal 14) The semiconductor device according to any one of Technical Proposals 1 to 13, wherein the concentration of the sixth impurity of the first conductivity type in the sixth semiconductor region is higher than the concentration of the fourth impurity of the first conductivity type in the fourth semiconductor region. (Technical proposal 15) The semiconductor device according to any one of Technical Proposals 1 to 13, wherein the concentration of the third subregion impurity of the second conductivity type in the third subregion is higher than the concentration of the second subregion impurity of the second conductivity type in the second subregion.

[0100] (Technical proposal 16) The semiconductor device according to Technical Proposal 3, wherein the concentration of the second conductivity type impurity in the fifth subregion is higher than the concentration of the second conductivity type impurity in the fourth subregion.

[0101] (Technical proposal 17) The semiconductor device according to any one of Technical Proposals 1 to 16, wherein the concentration of the third impurity of the first conductivity type in the third semiconductor region is higher than the concentration of the first impurity of the first conductivity type in the first semiconductor region.

[0102] (Technical proposal 18) The direction from the third electrode to the second semiconductor region is along a fourth direction that intersects with the first direction. The semiconductor device according to any one of Technical Proposals 1 to 17, wherein the direction from the third electrode to the third semiconductor region is along the fourth direction.

[0103] (Technical proposal 19) Further comprising a third insulating member, A semiconductor device according to any one of the technical proposals 1 to 18, wherein at least a portion of the third insulating member is located between the third electrode and the second electrode.

[0104] (Technical proposal 20) The unit further comprises a control unit configured to perform a first operation, In the first operation, the control unit is configured to set the third electrode potential of the third electrode to a first potential with reference to the second electrode potential of the second electrode at a first time point. In the first operation, the control unit is configured to set the third electrode potential to a second potential with respect to the second electrode potential at a second time after the first time, The first potential is higher than the second potential. In the first operation, the control unit is configured to set the fourth electrode potential of the fourth electrode to a third potential with reference to the first electrode potential of the first electrode at the third time step. In the first operation, the control unit is configured to set the fourth electrode potential to a fourth potential with respect to the first electrode potential at a fourth time after the third time, The third potential is lower than the fourth potential. The semiconductor device according to any one of Technical Proposals 1 to 19, wherein the fourth time is earlier than or the same as the second time.

[0105] According to the embodiment, a semiconductor device capable of improving characteristics is provided.

[0106] Embodiments of the present invention have been described above with reference to examples. However, the present invention is not limited to these examples. For example, the specific configuration of each element included in a semiconductor device, such as electrodes, semiconductor members, semiconductor regions, and insulating members, is included within the scope of the present invention as long as those skilled in the art can appropriately select from the known range to implement the present invention and obtain similar effects.

[0107] Combinations of two or more elements from each example, to the extent technically feasible, are also included within the scope of the present invention, insofar as they encompass the gist of the invention.

[0108] All semiconductor devices and their manufacturing methods that a person skilled in the art can implement by appropriately modifying the design based on the semiconductor device and its manufacturing method described above as embodiments of the present invention also fall within the scope of the present invention, insofar as they encompass the gist of the present invention.

[0109] Within the scope of the concept of this invention, a person skilled in the art would be able to conceive of various modifications and alterations, and it is understood that such modifications and alterations also fall within the scope of this invention.

[0110] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0111] 10M: Semiconductor material, 10p, 10q: Partial, 11~18: 1st to 8th semiconductor regions, 15a~15j: 1st to 10th partial regions, 16a~16d: 1st to 4th semiconductor regions, 41~43: 1st to 3rd insulating materials, 51~54: 1st to 4th electrodes, 70: Control unit, 110~113, 120~123, 121a, 122a, 123a, 130: Semiconductor device, D1~D5: 1st to 5th directions, E1~E4: 1st to 4th potentials, V3, V4: 3rd and 4th electrode potentials, t1~t4: 1st to 4th time points

Claims

1. First electrode and The second electrode and The third electrode and The fourth electrode and Semiconductor components and First insulating member and The second insulating member, Equipped with, At least a portion of the semiconductor member is located between the first electrode and the second electrode in a first direction from the first electrode to the second electrode, The aforementioned semiconductor member is The first semiconductor region of the first conductivity type, The second semiconductor region of the second conductivity type, The third semiconductor region of the first conductivity type, The fourth semiconductor region of the first conductivity type, The fifth semiconductor region of the second conductivity type, The sixth semiconductor region of the first conductivity type, Includes, The second electrode is electrically connected to the third semiconductor region. At least a portion of the second semiconductor region is located between the first semiconductor region and the third semiconductor region. At least a portion of the first insulating member is located between the third electrode and the first semiconductor region, between the third electrode and the second semiconductor region, and between the third electrode and the third semiconductor region. The fifth semiconductor region includes a first subregion, a second subregion, a third subregion, and a fourth subregion. The fourth semiconductor region is located between the second and fourth subregions in a second direction intersecting the first direction. The sixth semiconductor region includes the first semiconductor portion, The first semiconductor portion is located between the third subregion and the fourth semiconductor region in the second direction. The second subregion is located between the first semiconductor region and the fourth semiconductor region. A portion of the first semiconductor part is located between the first electrode and the first partial region in the first direction. Another part of the first semiconductor portion is located between the fourth electrode and the first partial region in the first direction. The fourth subregion is located between the first electrode and the first semiconductor region in the first direction. At least a portion of the second insulating member is located between the fourth electrode and the first semiconductor portion, between the fourth electrode and the second partial region, and between the fourth electrode and the fourth semiconductor region. The first electrode is electrically connected to the fifth semiconductor region. A semiconductor device in which, in the first direction, the sixth semiconductor region is not provided between the first electrode and the fourth partial region.

2. The sixth semiconductor region further includes the second semiconductor portion, The fourth semiconductor region is located between the second partial region and the second semiconductor portion in the second direction. The semiconductor device according to claim 1, wherein the second semiconductor portion is located between the first electrode and a part of the fourth subregion in the first direction.

3. The fifth semiconductor region further includes a fifth subregion and a sixth subregion, The sixth subregion is located between the fourth semiconductor region and the second semiconductor region in the second direction. The semiconductor device according to claim 2, wherein the second semiconductor portion is located between the sixth subregion and the fifth subregion in the second direction.

4. The fifth semiconductor region further includes a seventh subregion, The semiconductor device according to claim 2, wherein the third direction from the seventh partial region to the first semiconductor portion intersects a plane including the first and second directions.

5. The fifth semiconductor region further includes an eighth subregion, The semiconductor device according to claim 4, wherein the direction from the eighth partial region to the second semiconductor portion is along the third direction.

6. The sixth semiconductor region further includes the third semiconductor portion, The semiconductor device according to claim 5, wherein the eighth sub-region is located between the third semiconductor portion and the second semiconductor portion in the third direction.

7. The fifth semiconductor region further includes a ninth subregion, The semiconductor device according to claim 6, wherein the ninth subregion is located between the fourth semiconductor region and the third semiconductor portion in the second direction.

8. Including a plurality of the above fourth electrodes, One of the plurality of fourth electrodes overlaps with the first semiconductor portion and the fourth semiconductor region in the first direction. The semiconductor device according to any one of claims 2 to 7, wherein another one of the plurality of fourth electrodes overlaps with the second semiconductor portion and the fourth semiconductor region in the first direction.

9. Including a plurality of the above fourth electrodes, One of the plurality of fourth electrodes overlaps with the first semiconductor portion and the fourth semiconductor region in the first direction. The semiconductor device according to claim 6 or 7, wherein one of the plurality of fourth electrodes overlaps with the third semiconductor portion and the fourth semiconductor region in the first direction.

10. The semiconductor device according to any one of claims 1 to 7, wherein the fourth electrode overlaps with the fourth subregion in the first direction.

11. The semiconductor device according to any one of claims 1 to 7, wherein the fourth electrode does not overlap with the fourth subregion in the first direction.

12. The sixth semiconductor region further includes the third semiconductor portion, The fifth semiconductor region further includes a ninth subregion, The ninth subregion is located between the fourth semiconductor region and the third semiconductor region in the second direction. The position of the third semiconductor portion in the third direction is different from the position of the first semiconductor portion in the third direction of the first semiconductor portion. The semiconductor device according to claim 1, wherein the third direction intersects a plane including the first and second directions.

13. The sixth semiconductor region further includes the fourth semiconductor portion, The fifth semiconductor region further includes a seventh subregion and a tenth subregion, The tenth subregion is located between the fourth semiconductor portion and the fourth semiconductor region in the second direction. The semiconductor device according to claim 1, wherein the seventh sub-region is located between the fourth semiconductor portion and the first semiconductor portion in a third direction intersecting a plane including the first and second directions.

14. The semiconductor device according to any one of claims 1 to 7, wherein the concentration of the sixth impurity of the first conductivity type in the sixth semiconductor region is higher than the concentration of the fourth impurity of the first conductivity type in the fourth semiconductor region.

15. The semiconductor device according to any one of claims 1 to 7, wherein the concentration of the third subregion impurity of the second conductivity type in the third subregion is higher than the concentration of the second subregion impurity of the second conductivity type in the second subregion.

16. The semiconductor device according to claim 3, wherein the concentration of the fifth subregion impurity of the second conductivity type in the fifth subregion is higher than the concentration of the second subregion impurity of the second conductivity type in the fourth subregion.

17. The semiconductor device according to any one of claims 1 to 7, wherein the concentration of the third impurity of the first conductivity type in the third semiconductor region is higher than the concentration of the first impurity of the first conductivity type in the first semiconductor region.

18. The direction from the third electrode to the second semiconductor region is along a fourth direction that intersects with the first direction. The semiconductor device according to any one of claims 1 to 7, wherein the direction from the third electrode to the third semiconductor region is along the fourth direction.

19. Further comprising a third insulating member, The semiconductor device according to any one of claims 1 to 7, wherein at least a portion of the third insulating member is located between the third electrode and the second electrode.

20. The system further comprises a control unit configured to perform a first operation, In the first operation, the control unit is configured to set the third electrode potential of the third electrode to a first potential with reference to the second electrode potential of the second electrode at a first time point. In the first operation, the control unit is configured to set the third electrode potential to a second potential with respect to the second electrode potential at a second time after the first time, The first potential is higher than the second potential. In the first operation, the control unit is configured to set the fourth electrode potential of the fourth electrode to a third potential with reference to the first electrode potential of the first electrode at the third time step. In the first operation, the control unit is configured to set the fourth electrode potential to a fourth potential with respect to the first electrode potential at a fourth time after the third time, The third potential is lower than the fourth potential. The semiconductor device according to any one of claims 1 to 7, wherein the fourth time is earlier than the second time, or is the same as the second time.

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