Nitride semiconductor equipment

Abstract

The present invention provides a nitride semiconductor device that enables suppression of self-turn-on during high-speed switching while maintaining low on-resistance in a nitride semiconductor transistor. [Solution] The nitride semiconductor device 10 includes a first nitride semiconductor transistor 24 including a first source electrode 30, a first drain electrode 32, and a first gate electrode 34, a first gate pad 12 electrically connected to the first gate electrode 34, a second nitride semiconductor transistor 26 including a second source electrode 40, a second drain electrode 42, and a second gate electrode 44, and a second gate pad electrically connected to the second gate electrode 44. The first source electrode 30 is electrically connected to the second source electrode 40, and the first gate electrode 34 is electrically connected to the second drain electrode 42. At least a portion of the second nitride semiconductor transistor 26 overlaps with the first gate pad 12 in a plan view.

Description

[Technical Field]

[0001] This disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Currently, the commercialization of high-electron-mobility transistors (HEMTs) using group III nitride semiconductors such as gallium nitride (GaN) and aluminum gallium nitride (AlGaN) is progressing. In HEMTs, a two-dimensional electron gas (2DEG) formed near the interface of the heterojunction between the electron transport layer (e.g., GaN layer) and the electron supply layer (e.g., AlGaN layer) is used as a conductive path (see, for example, Patent Document 1). Power devices utilizing HEMTs are recognized as devices with low on-resistance and capable of high-speed and high-frequency operation compared to typical silicon (Si) power devices. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2017-73506

[0004] [overview] A Miller clamp circuit is sometimes used to suppress self-turn-on during high-speed switching of HEMTs. However, if a Miller clamp circuit is provided within the chip, for example, the proportion of the HEMT's area within the chip decreases relatively, which may increase the HEMT's on-resistance.

[0005] A nitride semiconductor device according to one aspect of the present disclosure includes a first nitride semiconductor transistor comprising a first source electrode, a first drain electrode, and a first gate electrode; a first gate pad electrically connected to the first gate electrode; a second nitride semiconductor transistor comprising a second source electrode, a second drain electrode, and a second gate electrode; and a second gate pad electrically connected to the second gate electrode and electrically isolated from the first gate pad. The first source electrode is electrically connected to the second source electrode. The first gate electrode is electrically connected to the second drain electrode. At least a portion of the second nitride semiconductor transistor overlaps with the first gate pad in a plan view.

[0006] Other features and embodiments will become apparent from the following detailed description, drawings, and claims. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic plan view of an exemplary nitride semiconductor device according to one embodiment of the present disclosure. [Figure 2] Figure 2 is an enlarged plan view of the region indicated by the symbol F2 in Figure 1. [Figure 3] Figure 3 is a schematic plan view showing the internal structure of a nitride semiconductor device in the region shown in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view of the first nitride semiconductor transistor and the second nitride semiconductor transistor. [Figure 5] Figure 5 is an enlarged plan view of the region indicated by the symbol F5 in Figure 1. [Figure 6] Figure 6 is a schematic plan view showing the internal structure of a nitride semiconductor device in the region shown in Figure 5. [Figure 7] Figure 7 is an enlarged plan view of the region indicated by the symbol F7 in Figure 1. [Figure 8] Figure 8 is a schematic cross-sectional view along the line F8-F8 in Figure 7. [Figure 9]FIG. 9 is a schematic cross-sectional view showing an exemplary manufacturing process of the nitride semiconductor device shown in FIG. 4. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 9. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 10. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 11. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 12. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 13. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 14. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 15. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 16. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 17. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 18. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 19. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 20. [Figure 22] FIG. 22 is a schematic cross-sectional view showing a manufacturing process following the process shown in FIG. 21. [Figure 23] [[ID=4E]]FIG. 23 is a circuit diagram of an exemplary half-bridge type converter including a nitride semiconductor device according to an embodiment of the present disclosure. [Figure 24] FIG. 24 is a schematic cross-sectional view of a nitride semiconductor device according to a modified example.

[0008] [Detailed Description] Hereinafter, several embodiments of the nitride semiconductor devices of this disclosure will be described with reference to the accompanying drawings. Throughout the drawings and detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated for clarity, illustrative purposes, and convenience.

[0009] The following detailed description provides a comprehensive understanding of the described methods, apparatus, and / or systems. Modifications and equivalents of the described methods, apparatus, and / or systems will be obvious to those skilled in the art. Except for operations that necessarily occur in a specific order, the order of operations is exemplary and can be modified as obvious to those skilled in the art. Descriptions of functions and structures well known to those skilled in the art may be omitted. Exemplary embodiments may have different forms and are not limited to the examples described.

[0010] (Overall structure of nitride semiconductor device) An exemplary nitride semiconductor device 10 will be described with reference to Figure 1. The Z-axis direction of the mutually orthogonal XYZ axes shown in Figure 1 is the direction that intersects (for example, is orthogonal to) the first surface 72A of the substrate 72 (see Figure 4). As used herein, the term “plan view” means viewing the nitride semiconductor device 10 from above along the Z-axis direction, unless otherwise explicitly stated. In this disclosure, the X-axis direction may be referred to as the first direction, and the Y-axis direction as the second direction. The second direction may be orthogonal to the first direction in a plan view.

[0011] Figure 1 is a schematic plan view of the nitride semiconductor device 10. As shown in Figure 1, the nitride semiconductor device 10 includes a first gate pad 12 and a second gate pad 14. The second gate pad 14 is electrically insulated from the first gate pad 12. As will be described later with reference to Figures 2 to 4, the first gate pad 12 is electrically connected to the first gate electrode 34 of the first nitride semiconductor transistor 24, and the second gate pad 14 is electrically connected to the second gate electrode 44 of the second nitride semiconductor transistor 26.

[0012] The nitride semiconductor device 10 may include an insulating layer 16. In the example shown in Figure 1, the first gate pad 12 and the second gate pad 14 are located on the periphery of the rectangular insulating layer 16 in plan view. More specifically, the first gate pad 12 is located at a corner of the insulating layer 16, and the second gate pad 14 is spaced apart from the first gate pad 12 in the Y-axis direction. The area of ​​the second gate pad 14 may be smaller than the area of ​​the first gate pad 12.

[0013] The nitride semiconductor device 10 may include a plurality of source pads 18 and a plurality of drain pads 20. As will be described later with reference to Figures 2 to 4, the plurality of source pads 18 are electrically connected to the first source electrode 30 of the first nitride semiconductor transistor 24. The plurality of drain pads 20 are electrically connected to the first drain electrode 32 of the first nitride semiconductor transistor 24.

[0014] In the example shown in Figure 1, the nitride semiconductor device 10 includes two source pads 18 and two drain pads 20. The two source pads 18 and the two drain pads 20 are arranged alternately with spacing in the X-axis direction in a plan view. One of the multiple source pads 18 has a smaller area than the other source pads 18 and drain pads 20, and can be aligned in the Y-axis direction with the first gate pad 12 and the second gate pad 14. In one example, the first gate pad 12 may have a smaller area than each of the multiple source pads 18. Also, the first gate pad 12 may have a smaller area than each of the multiple drain pads 20.

[0015] Optionally, the nitride semiconductor device 10 may include a Kelvin source pad 22 located on the insulating layer 16. The Kelvin source pad 22 may be electrically connected to the first source electrode 30 (see Figures 2 to 4) of the first nitride semiconductor transistor 24. In the example of Figure 1, the Kelvin source pad 22 may be located between the second gate pad 14 and a source pad 18 aligned with the second gate pad 14 in the Y-axis direction.

[0016] The number and arrangement of the first gate pad 12, second gate pad 14, source pad 18, drain pad 20, and Kelvin source pad 22 are arbitrary and not limited to the example shown in Figure 1.

[0017] The insulating layer 16 may be composed of any dielectric material. For example, the insulating layer 16 may contain one or any combination of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and polyimide.

[0018] The first gate pad 12, the second gate pad 14, the source pad 18, the drain pad 20, and the Kelvin source pad 22 may be made of any conductive material. For example, each of the first gate pad 12, the second gate pad 14, the source pad 18, the drain pad 20, and the Kelvin source pad 22 may contain one or any combination of copper (Cu), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), titanium (Ti), and titanium nitride (TiN).

[0019] (Planar structure of first and second nitride semiconductor transistors) Figure 2 is an enlarged plan view of the region indicated by the symbol F2 in Figure 1. Figure 3 is a schematic plan view showing the internal structure of the nitride semiconductor device 10 in the region shown in Figure 2. As shown in Figures 2 and 3, the nitride semiconductor device 10 includes a first nitride semiconductor transistor 24 and a second nitride semiconductor transistor 26. The first nitride semiconductor transistor 24 may occupy a relatively large portion of the area of ​​the nitride semiconductor device 10. Specifically, the first nitride semiconductor transistor 24 may be arranged over a relatively large area so as to overlap with a plurality of source pads 18 and a plurality of drain pads 20 (see Figure 1).

[0020] On the other hand, the second nitride semiconductor transistor 26 may have a smaller area than the first nitride semiconductor transistor 24. At least a portion of the second nitride semiconductor transistor 26 overlaps with the first gate pad 12 in a plan view. In one example, more than half of the area of ​​the second nitride semiconductor transistor 26 may overlap with the first gate pad 12 in a plan view. More preferably, more than 80% of the area of ​​the second nitride semiconductor transistor 26 may overlap with the first gate pad 12 in a plan view. Alternatively, the entire second nitride semiconductor transistor 26 may overlap with the first gate pad 12 in a plan view.

[0021] Here, the area of ​​the second nitride semiconductor transistor 26 can be defined as the area of ​​the active region of the second nitride semiconductor transistor 26. The active region of the second nitride semiconductor transistor 26 includes at least the region through which current flows when the second nitride semiconductor transistor 26 is in the ON state.

[0022] In a plan view, most of the second nitride semiconductor transistor 26 may overlap with the first gate pad 12; therefore, the second nitride semiconductor transistor 26 does not need to overlap with, or only slightly overlap with, multiple source pads 18 or multiple drain pads 20.

[0023] The nitride semiconductor device 10 may include an element isolation region 28 that electrically isolates the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26. At least a portion of the element isolation region 28 may be located between the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26 in a plan view. In one example, the element isolation region 28 may surround the second nitride semiconductor transistor 26 in a plan view. Further details of the element isolation region 28 will be described later with reference to Figure 4.

[0024] As shown in Figures 2 and 3, the first nitride semiconductor transistor 24 includes a first source electrode 30, a first drain electrode 32, and a first gate electrode 34. In the examples of Figures 2 and 3, the first source electrode 30 and the first drain electrode 32 extend in the Y-axis direction in a plan view. The first source electrode 30 and the first drain electrode 32 are separated from each other in the X-axis direction. The first gate electrode 34 may be loop-shaped in a plan view so as to surround the first drain electrode 32. More specifically, the first gate electrode 34 may include a main electrode portion 36 that extends in the Y-axis direction and is separated from the first drain electrode 32 in the X-axis direction, and a connecting portion 38 that extends in the X-axis direction. In the example of Figure 3, the first source electrode 30 may overlap with the main electrode portion 36 of the first gate electrode 34 in a plan view.

[0025] The first nitride semiconductor transistor 24 may include a plurality of first source electrodes 30, a plurality of first drain electrodes 32, and a plurality of first gate electrodes 34. The plurality of first source electrodes 30 and the plurality of first drain electrodes 32 can be arranged alternately in the X-axis direction. Each of the plurality of first drain electrodes 32 may be surrounded in a plan view by a corresponding one of the plurality of first gate electrodes 34. Each of the plurality of first source electrodes 30 may overlap with two first gate electrodes 34 in a plan view.

[0026] As shown in Figures 2 and 3, the second nitride semiconductor transistor 26 includes a second source electrode 40, a second drain electrode 42, and a second gate electrode 44. In the examples of Figures 2 and 3, the second source electrode 40 and the second drain electrode 42 extend in the Y-axis direction in a plan view. The second source electrode 40 and the second drain electrode 42 are separated from each other in the X-axis direction. The second gate electrode 44 may be loop-shaped in a plan view so as to surround the second drain electrode 42. More specifically, the second gate electrode 44 may include a main electrode portion 46 that extends in the Y-axis direction and is separated from the second drain electrode 42 in the X-axis direction, and a connecting portion 48 that extends in the X-axis direction. In the example of Figure 3, the second source electrode 40 may overlap with the main electrode portion 46 of the second gate electrode 44 in a plan view.

[0027] The second nitride semiconductor transistor 26 may include a plurality of second source electrodes 40, a plurality of second drain electrodes 42, and a plurality of second gate electrodes 44. The plurality of second source electrodes 40 and the plurality of second drain electrodes 42 can be arranged alternately in the X-axis direction. Each of the plurality of second drain electrodes 42 may be surrounded in a plan view by a corresponding one of the plurality of second gate electrodes 44. Each of the plurality of second source electrodes 40 may overlap with two second gate electrodes 44 in a plan view.

[0028] (Wiring between the first and second nitride semiconductor transistors and the pads) As shown in Figure 3, the nitride semiconductor device 10 may include a first wiring 50 electrically connected to the first source electrode 30, a second wiring 52 electrically connected to the first drain electrode 32, and a third wiring 54 electrically connected to the first gate electrode 34. The third wiring 54 is also electrically connected to the second drain electrode 42. Therefore, the first gate electrode 34 of the first nitride semiconductor transistor 24 is electrically connected to the second drain electrode 42 of the second nitride semiconductor transistor 26. The nitride semiconductor device 10 may also include a fourth wiring 56 electrically connected to the second source electrode 40 and a fifth wiring 58 electrically connected to the second gate electrode 44.

[0029] The first wiring 50 extends so as to overlap with the first source electrode 30 in a plan view. The nitride semiconductor device 10 may include at least one connecting conductor 60 that connects the first source electrode 30 to the first wiring 50. The at least one connecting conductor 60 may be located within the region where the first source electrode 30 and the first wiring 50 overlap in a plan view.

[0030] The second wiring 52 extends so as to overlap with the first drain electrode 32 in a plan view. The nitride semiconductor device 10 may include at least one connecting conductor 62 that connects the first drain electrode 32 to the second wiring 52. The at least one connecting conductor 62 may be located within the region where the first drain electrode 32 and the second wiring 52 overlap in a plan view.

[0031] The third wiring 54 extends so as to overlap the connection portion 38 of the first gate electrode 34 and the second drain electrode 42 in a plan view. The nitride semiconductor device 10 may include at least one connecting conductor 64 connecting the first gate electrode 34 to the third wiring 54 and at least one connecting conductor 66 connecting the second drain electrode 42 to the third wiring 54. The at least one connecting conductor 64 may be located in the region where the connection portion 38 of the first gate electrode 34 and the third wiring 54 overlap in a plan view. The at least one connecting conductor 66 may be located in the region where the second drain electrode 42 and the third wiring 54 overlap in a plan view.

[0032] The fourth wiring 56 extends so as to overlap with the second source electrode 40 in a plan view. The nitride semiconductor device 10 may include at least one connecting conductor 68 that connects the second source electrode 40 to the fourth wiring 56. The at least one connecting conductor 68 may be located within the region where the second source electrode 40 and the fourth wiring 56 overlap in a plan view.

[0033] The fifth wiring 58 extends so as to overlap with the connection portion 48 of the second gate electrode 44 in a plan view. The nitride semiconductor device 10 may include at least one connecting conductor 70 that connects the second gate electrode 44 to the fifth wiring 58. The at least one connecting conductor 70 may be located within the region where the connection portion 48 of the second gate electrode 44 and the fifth wiring 58 overlap in a plan view.

[0034] Referring again to Figure 2, the first gate pad 12 is connected to the third wiring 54. The third wiring 54 is covered by the insulating layer 16 shown in Figure 1, but the first gate pad 12 can be connected to the third wiring 54 through at least one opening 16A in the insulating layer 16. As a result, the first gate pad 12 is electrically connected to the first gate electrode 34 and the second drain electrode 42 via the third wiring 54. The drain pad 20 is connected to the second wiring 52. The second wiring 52 is covered by the insulating layer 16, but the drain pad 20 can be connected to the second wiring 52 through at least one opening 16B in the insulating layer 16. As a result, the drain pad 20 is electrically connected to the first drain electrode 32 via the second wiring 52. Although not shown in Figure 2, the source pad 18 (see Figure 1) is connected to the first wiring 50. As a result, the source pad 18 is electrically connected to the first source electrode 30 via the first wiring 50.

[0035] (Cross-sectional structure of the first and second nitride semiconductor transistors) Figure 4 is a schematic cross-sectional view of the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26. Note that in Figure 4, some of the structures shown in Figures 2 and 3 have been omitted to facilitate understanding of the structure and connections of the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26.

[0036] As shown in Figure 4, the nitride semiconductor device 10 includes a substrate 72. The substrate 72 may be made of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. The thickness of the substrate 72 may be, for example, 100 μm or more and 1500 μm or less.

[0037] The nitride semiconductor device 10 may further include a buffer layer 74 located on the substrate 72. The buffer layer 74 may include one or more nitride semiconductor layers. The buffer layer 74 can be made of any material that can reduce warping and cracking of the nitride semiconductor device 10 caused by the difference in thermal expansion coefficients between the substrate 72 and the layers formed on the buffer layer 74 (such as the first nitride semiconductor layer 76 in the example of Figure 4). For example, the buffer layer 74 may include at least one of AlN layers, AlGaN layers, and graded AlGaN layers having different Al compositions. For example, the buffer layer 74 may consist of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0038] In one example, the buffer layer 74 may include a first buffer layer which is an AlN layer formed on the substrate 72, and a second buffer layer which is an AlGaN layer formed on the AlN layer. The first buffer layer may be, for example, an AlN layer having a thickness of 100 nm to 300 nm, while the second buffer layer may include multiple AlGaN layers with different compositions, each having a thickness of 100 nm to 300 nm. In order to reduce leakage current in the buffer layer 74, impurities may be introduced into a part of the buffer layer 74 to make it semi-insulating. In that case, the impurities may be, for example, carbon (C) or iron (Fe), and the concentration of the impurities may be, for example, 4 × 10⁻⁶. 16 cm -3 This can be done.

[0039] The nitride semiconductor device 10 includes a first nitride semiconductor layer 76 located above the substrate 72 and a second nitride semiconductor layer 78 located on the first nitride semiconductor layer 76. The first nitride semiconductor layer 76 may be located on the buffer layer 74. In this embodiment, the first nitride semiconductor layer 76 may be a GaN layer. The thickness of the first nitride semiconductor layer 76 may be, for example, 0.5 μm or more and 2 μm or less. In order to reduce the leakage current in the first nitride semiconductor layer 76, by introducing impurities into a part of the first nitride semiconductor layer 76, the region other than the surface layer region of the first nitride semiconductor layer 76 may be made semi-insulating. In this case, the impurity may be, for example, C. The impurity concentration in the first nitride semiconductor layer 76 may be, for example, 4×10 16 cm -3 or more.

[0040] That is, the first nitride semiconductor layer 76 may include a plurality of GaN layers with different impurity concentrations, for example, a C-doped GaN layer and an undoped GaN layer. In this case, the C-doped GaN layer may be in contact with the buffer layer 74. The C-doped GaN layer may have a thickness of 0.3 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer may be 5×10 17 cm -3 or more and 9×10 19 cm -3 or less. The undoped GaN layer is formed on the C-doped GaN layer and may have a thickness of 0.05 μm or more and 0.4 μm or less. The undoped GaN layer may be in contact with the second nitride semiconductor layer 78. For example, the first nitride semiconductor layer 76 may include a C-doped GaN layer with a thickness of 0.4 μm and an undoped GaN layer with a thickness of 0.4 μm. Also, the C concentration in the C-doped GaN layer may be about 2×10 19 cm -3 or so.

[0041] The second nitride semiconductor layer 78 has a larger bandgap than the first nitride semiconductor layer 76. In this embodiment, the second nitride semiconductor layer 78 may be an AlGaN layer. For example, the second nitride semiconductor layer 78 is Al z Ga 1-zIt is composed of N, where 0.1 < z < 0.4, and more preferably, 0.1 < z < 0.3. The second nitride semiconductor layer 78 may have a thickness of 5 nm or more and 20 nm or less. In one example, the second nitride semiconductor layer 78 may have a thickness of 8 nm or more.

[0042] The first nitride semiconductor layer 76 (e.g., GaN layer) and the second nitride semiconductor layer 78 (e.g., AlGaN layer) have different lattice constants from each other. Therefore, the first nitride semiconductor layer 76 and the second nitride semiconductor layer 78 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the first nitride semiconductor layer 76 and the second nitride semiconductor layer 78 and the piezo-polarization caused by the crystal strain near the hetero-junction interface, the energy level of the conduction band of the first nitride semiconductor layer 76 near the hetero-junction interface becomes lower than the Fermi level. As a result, 2DEG occurs in the first nitride semiconductor layer 76 at a position close to the hetero-junction interface between the first nitride semiconductor layer 76 and the second nitride semiconductor layer 78 (e.g., within a range of about several nm from the interface). The 2DEG in the first nitride semiconductor layer 76 can function as the channels of the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26.

[0043] The nitride semiconductor device 10 includes a third nitride semiconductor layer 80 containing acceptor-type impurities, which is located on the second nitride semiconductor layer 78. The third nitride semiconductor layer 80 may have a smaller bandgap than the second nitride semiconductor layer 78. In one example, the third nitride semiconductor layer 80 may be a GaN layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities can include at least one of magnesium (Mg), zinc (Zn), and carbon (C). In one example, the acceptor-type impurities may be Mg. The maximum concentration of the acceptor-type impurities in the third nitride semiconductor layer 80 is 7×10 18 cm -3 or more and 1×10 20 cm -3 or less. The thickness of the third nitride semiconductor layer 80 may be, for example, 80 nm or more and 150 nm or less.

[0044] The first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26 include different portions of the first nitride semiconductor layer 76, the second nitride semiconductor layer 78, and the third nitride semiconductor layer 80. The first gate electrode 34 of the first nitride semiconductor transistor 24 is located on the third nitride semiconductor layer 80. The first source electrode 30 and the first drain electrode 32 of the first nitride semiconductor transistor 24 are located on the second nitride semiconductor layer 78. The second gate electrode 44 of the second nitride semiconductor transistor 26 is located on the third nitride semiconductor layer 80. The second source electrode 40 and the second drain electrode 42 of the second nitride semiconductor transistor 26 are located on the second nitride semiconductor layer 78.

[0045] More specifically, the third nitride semiconductor layer 80 may include a first gate portion 82 included in the first nitride semiconductor transistor 24 and a second gate portion 84 included in the second nitride semiconductor transistor 26.

[0046] The first gate electrode 34 is located on the first gate portion 82. The first gate portion 82, like the first gate electrode 34, may be loop-shaped in a plan view so as to surround the first drain electrode 32 (see Figure 3, etc.).

[0047] The second gate electrode 44 is located on the second gate portion 84. The second gate portion 84, like the second gate electrode 44, may be loop-shaped in a plan view so as to surround the second drain electrode 42 (see Figure 3, etc.).

[0048] The first gate electrode 34 and the second gate electrode 44 may be in Schottky contact with the third nitride semiconductor layer 80. The first gate electrode 34 and the second gate electrode 44 may be made of any conductive material capable of making Schottky contact with the third nitride semiconductor layer 80. The first gate electrode 34 and the second gate electrode 44 may be made of one or more conductive layers. In one example, each of the first gate electrode 34 and the second gate electrode 44 may be made of TiN. In another example, each of the first gate electrode 34 and the second gate electrode 44 may include a first conductive layer made of Ti and a second conductive layer made of TiN located on the first conductive layer.

[0049] The nitride semiconductor device 10 may include a first passivation layer 86 covering a second nitride semiconductor layer 78, a third nitride semiconductor layer 80, a first gate electrode 34, and a second gate electrode 44. The first passivation layer 86 includes a first aperture 86A, a second aperture 86B, a third aperture 86C, and a fourth aperture 86D. The first aperture 86A, the second aperture 86B, the third aperture 86C, and the fourth aperture 86D are spaced apart from each other in the X-axis direction. The first gate portion 82 is located between the first aperture 86A and the second aperture 86B. The first gate portion 82 may be located between the first aperture 86A and the second aperture 86B, closer to the first aperture 86A than to the second aperture 86B. The second gate portion 84 is located between the third aperture 86C and the fourth aperture 86D. The second gate portion 84 may be located between the third opening 86C and the fourth opening 86D, and closer to the third opening 86C than to the fourth opening 86D. Each of the first opening 86A, the second opening 86B, the third opening 86C, and the fourth opening 86D exposes the second nitride semiconductor layer 78.

[0050] The first passivation layer 86 may be composed of any dielectric material. For example, the first passivation layer 86 may contain one or any combination of SiN, SiO2, SiON, aluminum oxide (Al2O3), AlN, and aluminum oxynitride (AlON). The thickness of the first passivation layer 86 may be, for example, 50 nm or more and less than 150 nm.

[0051] The first source electrode 30 is in contact with the second nitride semiconductor layer 78 through the first aperture 86A. The first drain electrode 32 is in contact with the second nitride semiconductor layer 78 through the second aperture 86B. The second source electrode 40 is in contact with the second nitride semiconductor layer 78 through the third aperture 86C. The second drain electrode 42 is in contact with the second nitride semiconductor layer 78 through the fourth aperture 86D.

[0052] The first source electrode 30, the first drain electrode 32, the second source electrode 40, and the second drain electrode 42 can make ohmic contact with the 2DEG directly beneath the second nitride semiconductor layer 78 through the first aperture 86A, the second aperture 86B, the third aperture 86C, and the fourth aperture 86D, respectively. Each of the first source electrode 30, the first drain electrode 32, the second source electrode 40, and the second drain electrode 42 may be composed of one or more conductive layers. For example, each of the first source electrode 30, the first drain electrode 32, the second source electrode 40, and the second drain electrode 42 may contain one or any combination of Cu, Al, AlCu, AlSiCu, Ti, and TiN.

[0053] The first source electrode 30 may include a first contact portion 30A that contacts the second nitride semiconductor layer 78 and a first field plate portion 30B that extends above the first gate electrode 34 toward the first drain electrode 32.

[0054] The second source electrode 40 may include a second contact portion 40A that contacts the second nitride semiconductor layer 78 and a second field plate portion 40B that extends above the second gate electrode 44 toward the second drain electrode 42.

[0055] As shown in Figure 4, the distance L between the second gate electrode 44 and the second drain electrode 42 gd2 This is the distance L between the first gate electrode 34 and the first drain electrode 32. gd1 It can be smaller than that. Also, the dimension L in the X-axis direction of the second source electrode 40. s2The dimension L in the X-axis direction of the first source electrode 30 is... s1 It can be smaller than that.

[0056] When a voltage exceeding the gate threshold voltage is applied to the first gate electrode 34, a channel formed by 2DEG is created in the first nitride semiconductor layer 76. As a result, current can flow between the first source electrode 30 and the first drain electrode 32. On the other hand, when a voltage below the gate threshold voltage is applied to the first gate electrode 34 (including the case where no voltage is applied to the first gate electrode 34), 2DEG is not formed in at least a portion of the region located below the first gate portion 82 in the first nitride semiconductor layer 76. This is because the first gate portion 82 (third nitride semiconductor layer 80) contains acceptor-type impurities, which raises the energy levels of the first nitride semiconductor layer 76 and the second nitride semiconductor layer 78, resulting in the depletion of 2DEG. This enables normally-off operation of the first nitride semiconductor transistor 24.

[0057] Similarly, when a voltage exceeding the gate threshold voltage is applied to the second gate electrode 44, a channel formed by 2DEG is created in the first nitride semiconductor layer 76. As a result, current can flow between the second source electrode 40 and the second drain electrode 42. On the other hand, when a voltage below the gate threshold voltage is applied to the second gate electrode 44 (including the case where no voltage is applied to the second gate electrode 44), 2DEG is not formed in at least a portion of the region located below the second gate portion 84 in the first nitride semiconductor layer 76. This is because the second gate portion 84 (third nitride semiconductor layer 80) contains acceptor-type impurities, which raises the energy levels of the first nitride semiconductor layer 76 and the second nitride semiconductor layer 78, resulting in the depletion of 2DEG. This enables normally-off operation of the second nitride semiconductor transistor 26.

[0058] The nitride semiconductor device 10 may include a back surface electrode 88 in contact with the substrate 72. The substrate 72 includes a first surface 72A and a second surface 72B opposite to the first surface 72A. The first surface 72A of the substrate 72 may be in contact with a buffer layer 74, while the second surface 72B of the substrate 72 may be in contact with the back surface electrode 88. The back surface electrode 88 is electrically connected to the first source electrode 30. The back surface electrode 88 may contain one or any combination of Ti, nickel (Ni), and gold (Au).

[0059] The nitride semiconductor device 10 may include an interlayer insulating layer 90 located on a first passivation layer 86. The interlayer insulating layer 90 may cover a first source electrode 30, a first drain electrode 32, a second source electrode 40, and a second drain electrode 42. The first wiring 50, second wiring 52, third wiring 54, fourth wiring 56, and fifth wiring 58, as described with reference to Figure 3, may be located on the interlayer insulating layer 90. In Figure 4, a portion of the third wiring 54 and a portion of the fifth wiring 58 are shown. As shown in Figure 4, the first gate electrode 34 is connected to the third wiring 54 by a connecting conductor 64, and the third wiring 54 is connected to the second drain electrode 42 by a connecting conductor 66. Thus, the first gate electrode 34 is electrically connected to the second drain electrode 42.

[0060] The interlayer insulating layer 90 may be composed of any dielectric material. For example, the interlayer insulating layer 90 may contain one or any combination of SiN, SiO2, SiON, Al2O3, AlN, and AlON.

[0061] Additionally, the nitride semiconductor device 10 may include a second passivation layer 92 covering the first wiring 50, second wiring 52, third wiring 54, fourth wiring 56, and fifth wiring 58. The insulating layer 16 may be located on the second passivation layer 92.

[0062] The second passivation layer 92 may be composed of any dielectric material. For example, the second passivation layer 92 may contain one or any combination of SiN, SiO2, SiON, Al2O3, AlN, and AlON.

[0063] Additionally, the nitride semiconductor device 10 may include a barrier metal layer 94 between the insulating layer 16 and the first gate pad 12. The barrier metal layer 94 may contain one or any combination of titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN), Ti, and TiN.

[0064] At least a portion of the element isolation region 28 is located between the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26. In the example of Figure 4, in the element isolation region 28, the second nitride semiconductor layer 78 and the first nitride semiconductor layer 76 include a recess 96 that penetrates the second nitride semiconductor layer 78 and reaches the first nitride semiconductor layer 76. The element isolation region 28 can also be said to be defined by the recess 96. The recess 96 may be embedded by an interlayer insulating layer 90.

[0065] In the element isolation region 28 including the recess 96, there is no interface between the second nitride semiconductor layer 78 and the first nitride semiconductor layer 76, so 2DEG does not occur. As a result, the element isolation region 28 can electrically isolate the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26.

[0066] In another example, in the device isolation region 28, the first nitride semiconductor layer 76 and the second nitride semiconductor layer 78 may contain inert atoms. Examples of inert atoms may include helium (He) and argon (Ar). This can reduce or inhibit the generation of 2DEG in the device isolation region 28. In this case, the interface between the second nitride semiconductor layer 78 and the first nitride semiconductor layer 76 does not need to be removed (by a recess 96, etc.).

[0067] Referring again to Figures 2 and 3, the nitride semiconductor device 10 may optionally include a plurality of guard rings 98. Each guard ring 98 may surround a first nitride semiconductor transistor 24 or a second nitride semiconductor transistor 26 in a plan view. Each guard ring 98 includes a guard ring layer 98A and a guard ring electrode 98B located on the guard ring layer 98A. Details of the structure of the guard rings 98 will be described later with reference to Figure 8.

[0068] (Internal structure below the second gate pad) Next, the internal structure of the nitride semiconductor device 10 below the second gate pad 14 will be described with reference to Figures 5 and 6. Figure 5 is an enlarged plan view of the region indicated by the reference numeral F5 in Figure 1. Figure 6 is a schematic plan view showing the internal structure of the nitride semiconductor device 10 in the region shown in Figure 5.

[0069] Figure 5 shows the region where the first gate pad 12 and the second gate pad 14 are adjacent. As shown in Figure 5, the second nitride semiconductor transistor 26 is located below the first gate pad 12. On the other hand, the second nitride semiconductor transistor 26 does not have to be located below the second gate pad 14. The fifth wiring 58 extends below the second gate pad 14. The second gate pad 14 may be connected to the fifth wiring 58 via at least one opening 16C in the insulating layer 16 (see Figure 1). The fifth wiring 58 extends below both the first gate pad 12 and the second gate pad 14.

[0070] As shown in Figure 6, the fifth wiring 58 is electrically connected to the second gate electrode 44 via the connecting conductor 70. Therefore, the second gate pad 14 is electrically connected to the second gate electrode 44 of the second nitride semiconductor transistor 26 via the fifth wiring 58.

[0071] Furthermore, the nitride semiconductor device 10 may include at least one connecting conductor 100 that connects the guard ring electrode 98B of the guard ring 98 to the fifth wiring 58. In the example shown in Figure 5, the guard ring 98, along with the element isolation region 28, extends between the first gate pad 12 and the second gate pad 14 in a plan view.

[0072] (Structure of the outer region) Next, the outer periphery region of the nitride semiconductor device 10 will be described with reference to Figures 7 and 8. Figure 7 is an enlarged plan view of the region indicated by the reference numeral F7 in Figure 1. Figure 8 is a schematic cross-sectional view along the line F8-F8 in Figure 7.

[0073] As shown in Figure 7, the fourth wiring 56 extends in the X-axis direction so as to intersect with the second nitride semiconductor transistor 26 and the guard ring 98. In the region shown in Figure 7, the fourth wiring 56 also extends in the Y-axis direction so as to overlap with the element isolation region 28.

[0074] As shown in Figure 8, the nitride semiconductor device 10 includes a substrate contact plug 102 connected to the fourth wiring 56. The substrate contact plug 102 extends from the fourth wiring 56 to the substrate 72 in the element isolation region 28. Therefore, the fourth wiring 56 is electrically connected to the substrate 72 and the back electrode 88 by the substrate contact plug 102.

[0075] The fourth wiring 56 is connected to the second source electrode 40 by a connecting conductor 68, so the second source electrode 40 is electrically connected to the substrate 72. Also, the back electrode 88 is electrically connected to the first source electrode 30, so the first source electrode 30 is electrically connected to the substrate 72. In this way, the first source electrode 30 and the second source electrode 40 are electrically connected to the substrate 72.

[0076] Figure 8 shows the cross-sectional structure of the guard ring 98. As mentioned above, the guard ring 98 includes a guard ring layer 98A and a guard ring electrode 98B located on the guard ring layer 98A. The guard ring layer 98A, like the third nitride semiconductor layer 80, is located on the second nitride semiconductor layer 78. The guard ring layer 98A may be made of the same material as the third nitride semiconductor layer 80. The guard ring electrode 98B may also be made of the same material as the first gate electrode 34 and the second gate electrode 44. The guard ring layer 98A and the guard ring electrode 98B are covered by the first passivation layer 86.

[0077] (Exemplary method for manufacturing nitride semiconductor devices) Next, an example of a manufacturing method for the nitride semiconductor device 10 will be described with reference to Figures 9 to 22. For ease of understanding, in Figures 9 to 22, components similar to those in Figure 4 are denoted by the same reference numerals.

[0078] As shown in Figure 9, the manufacturing method of the nitride semiconductor device 10 includes sequentially stacking a buffer layer 74, a first nitride semiconductor layer 76, a second nitride semiconductor layer 78, and a third nitride semiconductor layer 80 on a substrate 72. The substrate 72 may be, for example, a Si substrate. The buffer layer 74, the first nitride semiconductor layer 76, the second nitride semiconductor layer 78, and the third nitride semiconductor layer 80 can be epitaxially grown using metal-organic chemical vapor deposition (MOCVD).

[0079] Although detailed illustrations are omitted, in one example, the buffer layer 74 may be a multilayer buffer layer. The multilayer buffer layer may include an AlN layer (first buffer layer) formed on the substrate 72 and a graded AlGaN layer (second buffer layer) formed on the AlN layer. The graded AlGaN layer can be formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25% in order from the side closest to the AlN layer.

[0080] The first nitride semiconductor layer 76 formed on the buffer layer 74 may be a GaN layer. Furthermore, the second nitride semiconductor layer 78 formed on the first nitride semiconductor layer 76 may be an AlGaN layer. The second nitride semiconductor layer 78 has a larger band gap than the first nitride semiconductor layer 76.

[0081] The third nitride semiconductor layer 80 may be a GaN layer containing acceptor-type impurities. In one example, the third nitride semiconductor layer 80 containing acceptor-type impurities can be formed by doping it with magnesium while it is growing. The amount of magnesium doped into the third nitride semiconductor layer 80 can be adjusted, for example, by controlling the flow rate of the doping gas (e.g., biscyclopentadienylmagnesium (Cp2Mg)) introduced into the growth chamber, the growth temperature, etc. In one example, the third nitride semiconductor layer 80 may be 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 20 cm -3 It is permissible to include magnesium as an impurity at concentrations below a certain level.

[0082] As shown in Figure 10, the method for manufacturing the nitride semiconductor device 10 includes forming a first electrode layer 150 on a third nitride semiconductor layer 80 and forming a first mask layer 152 on the first electrode layer 150.

[0083] The first electrode layer 150 can be used to form the first gate electrode 34 and the second gate electrode 44 shown in Figure 4. The first electrode layer 150 may be, for example, a TiN layer. The first mask layer 152 can be used as a mask to protect the first electrode layer 150 when etching the third nitride semiconductor layer 80 in a later process. The first mask layer 152 may be, for example, a SiN layer.

[0084] As shown in Figure 11, the method for manufacturing the nitride semiconductor device 10 includes selectively removing the first mask layer 152 and the first electrode layer 150, and forming a second mask layer 154. By selectively removing the first mask layer 152 and the first electrode layer 150, the first gate electrode 34 and the second gate electrode 44, and the portion of the first mask layer 152 covering the upper surfaces of the first gate electrode 34 and the second gate electrode 44 are left on the third nitride semiconductor layer 80. The second mask layer 154 is formed to cover the first gate electrode 34 and the side surfaces of the first mask layer 152 on the first gate electrode 34, and the side surfaces of the first mask layer 152 on the second gate electrode 44. The second mask layer 154 may be, for example, a SiN layer.

[0085] As shown in Figure 12, the method for manufacturing the nitride semiconductor device 10 includes selective etching of the third nitride semiconductor layer 80. The third nitride semiconductor layer 80 is etched using the first mask layer 152 and the second mask layer 154 shown in Figure 11. The portion of the third nitride semiconductor layer 80 located beneath the first mask layer 152 and the second mask layer 154 remains after etching, and as a result, the first gate portion 82 and the second gate portion 84, as described with reference to Figure 4, are formed. The first gate portion 82 and the second gate portion 84 can each have a larger area than the first gate electrode 34 and the second gate electrode 44 by the amount of the area that was covered by the second mask layer 154. The first mask layer 152 and the second mask layer 154 can be removed after the first gate portion 82 and the second gate portion 84 have been formed.

[0086] As shown in Figure 13, the method for manufacturing the nitride semiconductor device 10 includes forming a first passivation layer 86 that covers the second nitride semiconductor layer 78, the first gate portion 82, the first gate electrode 34, the second gate portion 84, and the second gate electrode 44. The first passivation layer 86 may be, for example, a SiN layer.

[0087] As shown in Figure 14, the manufacturing method of the nitride semiconductor device 10 includes forming a recess 96 that penetrates the second nitride semiconductor layer 78 and reaches the first nitride semiconductor layer 76. The recess 96 is provided to form the element isolation region 28 shown in Figure 4. In order to form the recess 96, the first passivation layer 86 is also partially removed.

[0088] Alternatively, the method for manufacturing the nitride semiconductor device 10 may include implanting inert atoms into the first nitride semiconductor layer 76 and the second nitride semiconductor layer 78. Examples of inert atoms may include helium (He), argon (Ar), and the like.

[0089] As shown in Figure 15, the method for manufacturing the nitride semiconductor device 10 includes selectively removing the first passivation layer 86 to form a first aperture 86A, a second aperture 86B, a third aperture 86C, and a fourth aperture 86D that expose the second nitride semiconductor layer 78.

[0090] The first gate portion 82 is located between the first opening 86A and the second opening 86B. The first gate portion 82 may be located between the first opening 86A and the second opening 86B, closer to the first opening 86A than to the second opening 86B. The second gate portion 84 is located between the third opening 86C and the fourth opening 86D. The second gate portion 84 may be located between the third opening 86C and the fourth opening 86D, closer to the third opening 86C than to the fourth opening 86D.

[0091] As shown in Figure 16, the method for manufacturing the nitride semiconductor device 10 includes forming a second electrode layer 156 that contacts the second nitride semiconductor layer 78 through a first aperture 86A, a second aperture 86B, a third aperture 86C, and a fourth aperture 86D.

[0092] The second electrode layer 156 may contain one or any combination of Cu, Al, AlCu, AlSiCu, Ti, and TiN. As shown in Figure 17, the manufacturing method of the nitride semiconductor device 10 includes selectively removing the second electrode layer 156 to form the first source electrode 30, the first drain electrode 32, the first gate electrode 34, the second source electrode 40, the second drain electrode 42, and the second gate electrode 44. At this time, the second electrode layer 156, which was embedded in the recess 96, is removed, and the first nitride semiconductor layer 76 in the recess 96 can be exposed.

[0093] As shown in Figure 18, the method for manufacturing the nitride semiconductor device 10 includes forming an interlayer insulating layer 90 that covers the first passivation layer 86, the first source electrode 30, the first drain electrode 32, the first gate electrode 34, the second source electrode 40, the second drain electrode 42, and the second gate electrode 44. The interlayer insulating layer 90 may be, for example, an SiO2 layer. The interlayer insulating layer 90 may be embedded in the recess 96.

[0094] As shown in Figure 19, the manufacturing method of the nitride semiconductor device 10 includes forming a plurality of connecting conductors 60, 62, 64, 66, 68, 70, and 100 that penetrate the interlayer insulating layer 90, and forming a first wiring 50, a second wiring 52, a third wiring 54, a fourth wiring 56, and a fifth wiring 58 on the interlayer insulating layer 90. Note that Figure 19 shows only a portion of the plurality of connecting conductors 60, 62, 64, 66, 68, 70, and 100, and a portion of the first wiring 50, the second wiring 52, the third wiring 54, the fourth wiring 56, and the fifth wiring 58.

[0095] As shown in Figure 20, the method for manufacturing the nitride semiconductor device 10 includes forming a second passivation layer 92 that covers the first wiring 50, the second wiring 52, the third wiring 54, the fourth wiring 56, and the fifth wiring 58. The second passivation layer 92 may include at least one of an SiO2 layer and a SiN layer.

[0096] As shown in Figure 21, the method for manufacturing the nitride semiconductor device 10 includes selectively removing the second passivation layer 92 and forming an insulating layer 16 on the second passivation layer 92. By selectively removing the second passivation layer 92, the first wiring 50, second wiring 52, third wiring 54, fourth wiring 56, and fifth wiring 58 are partially covered by the insulating layer 16.

[0097] As shown in Figure 22, the manufacturing method of the nitride semiconductor device 10 includes forming a first gate pad 12, a second gate pad 14, a plurality of source pads 18, and a plurality of drain pads 20 on an insulating layer 16. Note that only the first gate pad 12 is shown in Figure 22. The first gate pad 12 is in contact with the third wiring 54 through an opening 16A formed in the insulating layer 16. The opening 16A may be formed in a region where the second passivation layer 92 is selectively removed in the process shown in Figure 21.

[0098] In one example, forming a first gate pad 12, a second gate pad 14, a plurality of source pads 18, and a plurality of drain pads 20 may include forming a barrier metal layer 94 on the insulating layer 16, forming a Cu seed layer on the barrier metal layer 94, and forming a Cu plating layer on the Cu seed layer. For example, the barrier metal layer 94 may be a TiW layer.

[0099] The manufacturing method for the nitride semiconductor device 10 then includes grinding the substrate 72 from the back surface and forming a back surface electrode 88 on the substrate 72. Through these steps, the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26 can be formed on the same substrate 72 through a common process.

[0100] (The function of nitride semiconductor devices) The operation of the nitride semiconductor device 10 according to this embodiment will be described below. The nitride semiconductor device 10 includes a first nitride semiconductor transistor 24 including a first source electrode 30, a first drain electrode 32, and a first gate electrode 34; a first gate pad 12 electrically connected to the first gate electrode 34; a second nitride semiconductor transistor 26 including a second source electrode 40, a second drain electrode 42, and a second gate electrode 44; and a second gate pad 14 electrically connected to the second gate electrode 44 and electrically insulated from the first gate pad 12. The first source electrode 30 is electrically connected to the second source electrode 40. The first gate electrode 34 is electrically connected to the second drain electrode 42. At least a portion of the second nitride semiconductor transistor 26 overlaps with the first gate pad 12 in a plan view.

[0101] The second nitride semiconductor transistor 26 is connected between the first gate electrode 34 and the first source electrode 30 of the first nitride semiconductor transistor 24. By turning on the second nitride semiconductor transistor 26 when the first nitride semiconductor transistor 24 is in the off state, the gate-source of the first nitride semiconductor transistor 24 can be short-circuited. This suppresses the rise in gate voltage caused by a rapid increase in the drain-source voltage of the first nitride semiconductor transistor 24. As a result, the occurrence of self-turn-on of the first nitride semiconductor transistor 24 can be suppressed.

[0102] Here, with reference to Figure 23, an example of the application of the nitride semiconductor device 10 will be described. Figure 23 shows a circuit diagram of an exemplary half-bridge converter 160 including the nitride semiconductor device 10. The half-bridge converter 160 includes a high-side nitride semiconductor device 10H and a low-side nitride semiconductor device 10L connected in series with each other. Each of the high-side nitride semiconductor device 10H and the low-side nitride semiconductor device 10L may correspond to the nitride semiconductor device 10 of this embodiment.

[0103] The first nitride semiconductor transistor 24 of the low-side nitride semiconductor device 10L is switched on or off by a gate drive signal from the signal generation unit 162. The second nitride semiconductor transistor 26 of the low-side nitride semiconductor device 10L is switched on or off by a gate drive signal from the signal generation unit 164. The first nitride semiconductor transistor 24 of the high-side nitride semiconductor device 10H is switched on or off by a gate drive signal from the signal generation unit 166. The second nitride semiconductor transistor 26 of the high-side nitride semiconductor device 10H is switched on or off by a gate drive signal from the signal generation unit 168.

[0104] In the half-bridge converter 160, the high-side nitride semiconductor device 10H and the low-side nitride semiconductor device 10L are connected in series between the power supply. Therefore, when both the high-side nitride semiconductor device 10H and the low-side nitride semiconductor device 10L are turned on simultaneously, a relatively large shoot-through current flows between the power supply, which can result in increased switching losses.

[0105] When the first nitride semiconductor transistor 24 of the high-side nitride semiconductor device 10H changes from the off state to the on state, the drain-source voltage of the first nitride semiconductor transistor 24 of the low-side nitride semiconductor device 10L may rise sharply. At this time, if the second nitride semiconductor transistor 26 of the low-side nitride semiconductor device 10L is turned on, the gate-source of the first nitride semiconductor transistor 24 of the low-side nitride semiconductor device 10L can be short-circuited. This prevents the first nitride semiconductor transistor 24 of the low-side nitride semiconductor device 10L from being accidentally turned on.

[0106] Thus, the second nitride semiconductor transistor 26 can function as a Miller clamp circuit that suppresses the occurrence of self-turn-on of the first nitride semiconductor transistor 24. In addition, in this embodiment, at least a portion of the second nitride semiconductor transistor 26 overlaps with the first gate pad 12 in a plan view. Therefore, the reduction in the area of ​​the first nitride semiconductor transistor 24 in the nitride semiconductor device 10 can be suppressed, and as a result, low on-resistance can be maintained.

[0107] Therefore, according to the nitride semiconductor device 10 of this embodiment, it is possible to suppress the occurrence of self-turn-on during high-speed switching in the first nitride semiconductor transistor 24 while maintaining low on-resistance.

[0108] The nitride semiconductor device 10 of this embodiment has the following advantages. (1) The nitride semiconductor device 10 includes a first nitride semiconductor transistor 24 including a first source electrode 30, a first drain electrode 32, and a first gate electrode 34; a first gate pad 12 electrically connected to the first gate electrode 34; a second nitride semiconductor transistor 26 including a second source electrode 40, a second drain electrode 42, and a second gate electrode 44; and a second gate pad 14 electrically connected to the second gate electrode 44 and electrically insulated from the first gate pad 12. The first source electrode 30 is electrically connected to the second source electrode 40. The first gate electrode 34 is electrically connected to the second drain electrode 42. At least a portion of the second nitride semiconductor transistor 26 overlaps with the first gate pad 12 in a plan view.

[0109] This configuration makes it possible to suppress the occurrence of self-turn-on during high-speed switching in the first nitride semiconductor transistor 24 while maintaining low on-resistance.

[0110] (2) The nitride semiconductor device 10 comprises a substrate 72, a first nitride semiconductor layer 76 located above the substrate 72, a second nitride semiconductor layer 78 located on the first nitride semiconductor layer 76 and having a larger band gap than the first nitride semiconductor layer 76, and a third nitride semiconductor layer 80 located on the second nitride semiconductor layer 78 and containing acceptor-type impurities. The first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26 include different portions of the first nitride semiconductor layer 76, the second nitride semiconductor layer 78, and the third nitride semiconductor layer 80. The first gate electrode 34 is located on the third nitride semiconductor layer 80, and the first source electrode 30 and the first drain electrode 32 are located on the second nitride semiconductor layer 78. The second gate electrode 44 is located on the third nitride semiconductor layer 80, and the second source electrode 40 and the second drain electrode 42 are located on the second nitride semiconductor layer 78.

[0111] With this configuration, the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26 can be provided on the same substrate 72 using a common nitride semiconductor layer. Therefore, the manufacturing cost of the nitride semiconductor device 10 can be reduced.

[0112] (3) The first source electrode 30 and the second source electrode 40 may be electrically connected to the substrate 72. With this configuration, the first source electrode 30 and the second source electrode 40 can be electrically connected without providing additional wiring to connect them.

[0113] (4) The nitride semiconductor device 10 may further include an element isolation region 28 that electrically isolates the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26. This configuration allows for the electrical isolation of the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26, which are provided on the same substrate 72.

[0114] (5) At least a portion of the element isolation region 28 is located between the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26 in a plan view, and in the element isolation region 28, the second nitride semiconductor layer 78 and the first nitride semiconductor layer 76 may include a recess 96 that penetrates the second nitride semiconductor layer 78 and reaches the first nitride semiconductor layer 76.

[0115] With this configuration, since there is no interface between the second nitride semiconductor layer 78 and the first nitride semiconductor layer 76 in the element isolation region 28, 2DEG does not occur. As a result, the element isolation region 28 can electrically isolate the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26.

[0116] (6) At least a portion of the element isolation region 28 is located between the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26 in a plan view, and in the element isolation region 28, the first nitride semiconductor layer 76 and the second nitride semiconductor layer 78 may contain inert atoms.

[0117] With this configuration, the generation of 2DEG can be reduced or inhibited by inert atoms in the element isolation region 28. As a result, the element isolation region 28 can electrically isolate the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26.

[0118] (7) The element isolation region 28 may surround the second nitride semiconductor transistor 26 in a plan view. With this configuration, the second nitride semiconductor transistor 26 can be electrically isolated from the surrounding structure.

[0119] (8) The first source electrode 30 may include a first contact portion 30A that contacts the second nitride semiconductor layer 78 and a first field plate portion 30B that extends over the first gate electrode 34 toward the first drain electrode 32. The second source electrode 40 may include a second contact portion 40A that contacts the second nitride semiconductor layer 78 and a second field plate portion 40B that extends over the second gate electrode 44 toward the second drain electrode 42.

[0120] With this configuration, the breakdown voltage of the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26 can be improved by mitigating electric field concentration near the edge of the third nitride semiconductor layer 80 with the first field plate portion 30B and the second field plate portion 40B.

[0121] (9) Distance L between the second gate electrode 44 and the second drain electrode 42 gd2 This is the distance L between the first gate electrode 34 and the first drain electrode 32. gd1 It can be smaller than that. The drain-source breakdown voltage of the second nitride semiconductor transistor 26 only needs to exceed the gate breakdown voltage of the first nitride semiconductor transistor 24. With this configuration, the area of ​​the second nitride semiconductor transistor 26 can be reduced by optimizing the design.

[0122] (10) The first source electrode 30 and the first drain electrode 32 are separated in the first direction, and the second source electrode 40 and the second drain electrode 42 are separated in the first direction, and the dimension L of the second source electrode 40 in the first direction s2 This is the dimension L in the first direction of the first source electrode 30. s1 It can be smaller than that. The drain-source breakdown voltage of the second nitride semiconductor transistor 26 only needs to exceed the gate breakdown voltage of the first nitride semiconductor transistor 24. With this configuration, the parasitic capacitance of the second nitride semiconductor transistor 26 can be reduced by optimizing the design.

[0123] (11) The area of ​​the second gate pad 14 may be smaller than the area of ​​the first gate pad 12. The area of ​​the second gate pad 14 is sufficient to be the minimum size required to connect the wire wiring, and with this configuration, the chip area of ​​the nitride semiconductor device 10 can be reduced.

[0124] (12) More than half of the area of ​​the second nitride semiconductor transistor 26 may overlap with the first gate pad 12 in a plan view. With this configuration, most of the second nitride semiconductor transistor 26 can be placed below the first gate pad 12, so the chip area of ​​the nitride semiconductor device 10 can be reduced.

[0125] (13) The entire second nitride semiconductor transistor 26 may overlap the first gate pad 12 in a plan view. With this configuration, the entire second nitride semiconductor transistor 26 can be placed below the first gate pad 12, so the chip area of ​​the nitride semiconductor device 10 can be further reduced.

[0126] <Example of changes> The above embodiment can be implemented with the following modifications. Figure 24 is a schematic cross-sectional view of the nitride semiconductor device 200 according to a modified example. In Figure 24, the same reference numerals are used for components that are the same as those in the nitride semiconductor device 10. Detailed explanations of components that are the same as those in the nitride semiconductor device 10 are omitted.

[0127] The nitride semiconductor device 200 includes a second nitride semiconductor transistor 202 which comprises a second source electrode 204, a second drain electrode 42, and a second gate electrode 44. The second source electrode 204 does not overlap with the second gate electrode 44 in a plan view. The second gate electrode 44 is located between the second source electrode 204 and the second drain electrode 42 in a plan view.

[0128] On the other hand, the first source electrode 30 of the first nitride semiconductor transistor 24 includes a first contact portion 30A that contacts the second nitride semiconductor layer 78, and a first field plate portion 30B that extends above the first gate electrode 34 toward the first drain electrode 32, similar to the example in Figure 4. Therefore, in the modified nitride semiconductor device 200, the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 202 differ not only in dimensions but also in source electrode structure. In the second nitride semiconductor transistor 202, the second source electrode 204 does not overlap with the second gate electrode 44 in a plan view, thus reducing parasitic capacitance.

[0129] The dimension of the second gate portion 84 in the X-axis direction may be less than or equal to the dimension of the first gate portion 82 in the X-axis direction. This makes it possible to reduce the area ratio of the second nitride semiconductor transistor 26 in the nitride semiconductor device 10.

[0130] Multiple pads included in the nitride semiconductor device 10 may be connected to the first nitride semiconductor transistor 24 and the second nitride semiconductor transistor 26 using any wiring process. For example, in the example in Figure 4, the nitride semiconductor device 10 may not include the second passivation layer 92.

[0131] In the half-bridge converter 160 shown in Figure 23, both the high-side nitride semiconductor device 10H and the low-side nitride semiconductor device 10L are described as corresponding to the nitride semiconductor device 10. However, the nitride semiconductor device 10 may be applied only to the low-side nitride semiconductor device 10L. In that case, the high-side nitride semiconductor device 10H may be a nitride semiconductor device that does not include a Miller clamp circuit.

[0132] The nitride semiconductor device 10 can be used in a variety of applications, including motor circuits. One or more of the various examples described herein can be combined to the extent that they do not conflict with the technical specifications.

[0133] In this specification, “at least one of A and B” should be understood to mean “A only, or B only, or both A and B.” The terms indicating direction, such as “vertical,” “horizontal,” “upward,” “downward,” “up,” “down,” “forward,” “backward,” “longitudinal,” “lateral,” “left,” “right,” “front,” and “rear,” as used in this disclosure depend on the specific orientation of the described and illustrated apparatus. Various alternative orientations can be assumed in this disclosure, and therefore these terms indicating direction should not be interpreted narrowly.

[0134] For example, the Z-axis direction used in this disclosure does not necessarily have to be vertical, nor does it have to be perfectly aligned with the vertical. Therefore, the various structures according to this disclosure (e.g., the structure shown in Figure 1) are not limited to the Z-axis direction "up" and "down" being described herein being vertical "up" and "down". For example, the X-axis direction may be vertical, or the Y-axis direction may be vertical.

[0135] The terms "first," "second," "third," etc., used in this disclosure are used simply to distinguish between the subjects and do not rank them. <Note> The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0136] (Note 1) A first nitride semiconductor transistor (24) including a first source electrode (30), a first drain electrode (32), and a first gate electrode (34), A first gate pad (12) electrically connected to the first gate electrode (34), A second nitride semiconductor transistor (26) including a second source electrode (40), a second drain electrode (42), and a second gate electrode (44), A second gate pad (14) is electrically connected to the second gate electrode (44) and electrically insulated from the first gate pad (12). Equipped with, The first source electrode (30) is electrically connected to the second source electrode (40), and the first gate electrode (34) is electrically connected to the second drain electrode (42). A nitride semiconductor device wherein at least a portion of the second nitride semiconductor transistor (26) overlaps with the first gate pad (12) in a plan view.

[0137] (Note 2) Circuit board (72) and A first nitride semiconductor layer (76) located above the substrate (72), A second nitride semiconductor layer (78) is located on the first nitride semiconductor layer (76) and has a larger band gap than the first nitride semiconductor layer (76), A third nitride semiconductor layer (80) containing acceptor-type impurities is located on the second nitride semiconductor layer (78) and Equipped with, The first nitride semiconductor transistor (24) and the second nitride semiconductor transistor (26) include different portions of the first nitride semiconductor layer (76), the second nitride semiconductor layer (78), and the third nitride semiconductor layer (80), The first gate electrode (34) is located on the third nitride semiconductor layer (80), and the first source electrode (30) and the first drain electrode (32) are located on the second nitride semiconductor layer (78). The nitride semiconductor device according to Appendix 1, wherein the second gate electrode (44) is located on the third nitride semiconductor layer (80), and the second source electrode (40) and the second drain electrode (42) are located on the second nitride semiconductor layer (78).

[0138] (Note 3) The nitride semiconductor device as described in Appendix 2, wherein the first source electrode (30) and the second source electrode (40) are electrically connected to the substrate (72).

[0139] (Note 4) The nitride semiconductor device according to Appendix 2 or 3, further comprising an element isolation region (28) that electrically isolates the first nitride semiconductor transistor (24) and the second nitride semiconductor transistor (26).

[0140] (Note 5) At least a portion of the element isolation region (28) is located between the first nitride semiconductor transistor (24) and the second nitride semiconductor transistor (26) in a plan view. The nitride semiconductor device according to Appendix 4, wherein in the element isolation region (28), the second nitride semiconductor layer (78) and the first nitride semiconductor layer (76) include a recess (96) that penetrates the second nitride semiconductor layer (78) and reaches the first nitride semiconductor layer (76).

[0141] (Note 6) The nitride semiconductor device according to Appendix 4, wherein at least a portion of the element isolation region (28) is located between the first nitride semiconductor transistor (24) and the second nitride semiconductor transistor (26) in a plan view, and in the element isolation region (28), the first nitride semiconductor layer (76) and the second nitride semiconductor layer (78) contain inert atoms.

[0142] (Note 7) The nitride semiconductor device according to any one of the appendices 4 to 6, wherein the element isolation region (28) surrounds the second nitride semiconductor transistor (26) in a plan view.

[0143] (Note 8) The first source electrode (30) includes a first contact portion (30A) that contacts the second nitride semiconductor layer (78) and a first field plate portion (30B) that extends above the first gate electrode (34) toward the first drain electrode (32). The nitride semiconductor device according to any one of the appendices 2 to 7, wherein the second source electrode (40) includes a second contact portion (40A) that contacts the second nitride semiconductor layer (78) and a second field plate portion (40B) that extends above the second gate electrode (44) toward the second drain electrode (42).

[0144] (Note 9) The first source electrode (30) includes a first contact portion (30A) that contacts the second nitride semiconductor layer (78) and a first field plate portion (30B) that extends above the first gate electrode (34) toward the first drain electrode (32). The nitride semiconductor device according to any one of the appendices 2 to 7, wherein the second source electrode (204) does not overlap with the second gate electrode (44) in a plan view, and the second gate electrode (44) is located between the second source electrode (204) and the second drain electrode (42) in a plan view.

[0145] (Note 10) The distance (L) between the second gate electrode (44) and the second drain electrode (42) gd2 ) is the distance (L) between the first gate electrode (34) and the first drain electrode (32). gd1 A nitride semiconductor device described in any one of the appendices 1 to 9, which is smaller than ).

[0146] (Note 11) The first source electrode (30) and the first drain electrode (32) are separated in a first direction. The second source electrode (40) and the second drain electrode (42) are separated in the first direction. The dimension (L) of the second source electrode (40) in the first direction s2 ) is the dimension (L) of the first source electrode (30) in the first direction. s1 A nitride semiconductor device described in any one of the appendices 1 to 10, which is smaller than ).

[0147] (Note 12) The nitride semiconductor device according to any one of the appendices 1 to 11, wherein the area of ​​the second gate pad (14) is smaller than the area of ​​the first gate pad (12).

[0148] (Note 13) A nitride semiconductor device according to any one of the appendices 1 to 12, wherein more than half of the area of ​​the second nitride semiconductor transistor (26) overlaps with the first gate pad (12) in a plan view.

[0149] (Note 14) The nitride semiconductor device according to any one of the appendices 1 to 13, wherein the entirety of the second nitride semiconductor transistor (26) overlaps with the first gate pad (12) in a plan view.

[0150] Various modifications in form and detail can be made to the above-described examples without departing from the claims and their equivalents. The above-described examples are for illustrative purposes only and are not intended to be limiting. The descriptions of features in each example should be considered applicable to similar features or embodiments in other examples. Preferred results can be achieved when consecutive events occur in a different order, and / or when components within the described systems, architectures, devices, or circuits are combined in different ways and / or replaced or complemented by other components or their equivalents. The scope of this disclosure is defined not by the detailed description, but by the claims and their equivalents. All variations of the claims and their equivalents are included in this disclosure. [Explanation of Symbols]

[0151] 10,200… Nitride semiconductor equipment 10H... High-side nitride semiconductor equipment 10L... Low-side nitride semiconductor equipment 12…Gate Pad 1 14…Gate Pad 2 16…Insulating layer 16A, 16B, 16C…Aperture 18…Sourcepad 20... Drain pad 22... Kelvin Source Pad 24…First nitride semiconductor transistor 26,202…Second nitride semiconductor transistor 28... Element isolation region 30…First source electrode 30A…First contact section 30B...First field plate section 32...First drain electrode 34…Gate 1 36…Main electrode part 38…Connection part 40,204…Second source electrode 40A...Second contact section 40B...Second field plate section 42...Second drain electrode 44...2nd Gate 46…Main electrode section 48...Connection part 50...1st wiring 52…Second wiring 54...Third wiring 56…4th wiring 58…5th wiring 60, 62, 64, 66, 68, 70, 100… Connecting conductors 72... Circuit board 74... Buffer layer 76…First nitride semiconductor layer 78…Second nitride semiconductor layer 80...Third nitride semiconductor layer 82...Gate 1 section 84...Gate 2 86…First Passivation Layer 86A…1st opening 86B…Second opening 86C…Third opening 86D…4th opening 88…Back surface electrode 90...Interlayer insulating layer 92...Second Passivation Layer 94... Barrier metal layer 96…recess 98... Guard Ring 98A...Guard Ring Layer 98B... Guard ring electrode 102... Circuit board contact plug 150...first electrode layer 152…First mask layer 154...Second mask layer 156…Second electrode layer 160... Half-bridge type converter 162, 164, 166, 168… Signal generation section

Claims

1. A first nitride semiconductor transistor comprising a first source electrode, a first drain electrode, and a first gate electrode, A first gate pad electrically connected to the first gate electrode, A second nitride semiconductor transistor comprising a second source electrode, a second drain electrode, and a second gate electrode, A second gate pad is electrically connected to the second gate electrode and electrically isolated from the first gate pad. Equipped with, The first source electrode is electrically connected to the second source electrode, and the first gate electrode is electrically connected to the second drain electrode. A nitride semiconductor device wherein at least a portion of the second nitride semiconductor transistor overlaps with the first gate pad in a plan view.

2. circuit board and A first nitride semiconductor layer located above the substrate, A second nitride semiconductor layer located on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, A third nitride semiconductor layer containing acceptor-type impurities is located on the second nitride semiconductor layer. Equipped with, The first nitride semiconductor transistor and the second nitride semiconductor transistor include different portions of the first nitride semiconductor layer, the second nitride semiconductor layer, and the third nitride semiconductor layer. The first gate electrode is located on the third nitride semiconductor layer, and the first source electrode and the first drain electrode are located on the second nitride semiconductor layer. The nitride semiconductor device according to claim 1, wherein the second gate electrode is located on the third nitride semiconductor layer, and the second source electrode and the second drain electrode are located on the second nitride semiconductor layer.

3. The nitride semiconductor device according to claim 2, wherein the first source electrode and the second source electrode are electrically connected to the substrate.

4. The nitride semiconductor device according to claim 2, further comprising an element isolation region for electrically separating the first nitride semiconductor transistor and the second nitride semiconductor transistor.

5. At least a portion of the element isolation region is located between the first nitride semiconductor transistor and the second nitride semiconductor transistor in a plan view. The nitride semiconductor device according to claim 4, wherein in the element isolation region, the second nitride semiconductor layer and the first nitride semiconductor layer include a recess that penetrates the second nitride semiconductor layer and reaches the first nitride semiconductor layer.

6. The nitride semiconductor device according to claim 4, wherein at least a portion of the element isolation region is located between the first nitride semiconductor transistor and the second nitride semiconductor transistor in a plan view, and in the element isolation region, the first nitride semiconductor layer and the second nitride semiconductor layer contain inert atoms.

7. The nitride semiconductor device according to claim 4, wherein the element isolation region surrounds the second nitride semiconductor transistor in a plan view.

8. The first source electrode includes a first contact portion that contacts the second nitride semiconductor layer and a first field plate portion that extends above the first gate electrode toward the first drain electrode. The nitride semiconductor device according to claim 2, wherein the second source electrode includes a second contact portion that contacts the second nitride semiconductor layer and a second field plate portion that extends above the second gate electrode toward the second drain electrode.

9. The first source electrode includes a first contact portion that contacts the second nitride semiconductor layer and a first field plate portion that extends above the first gate electrode toward the first drain electrode. The nitride semiconductor device according to claim 2, wherein the second source electrode does not overlap with the second gate electrode in a plan view, and the second gate electrode is located between the second source electrode and the second drain electrode in a plan view.

10. The nitride semiconductor device according to any one of claims 1 to 9, wherein the distance between the second gate electrode and the second drain electrode is smaller than the distance between the first gate electrode and the first drain electrode.

11. The first source electrode and the first drain electrode are separated in a first direction. The second source electrode and the second drain electrode are separated in the first direction. The nitride semiconductor device according to any one of claims 1 to 9, wherein the dimension of the second source electrode in the first direction is smaller than the dimension of the first source electrode in the first direction.

12. The nitride semiconductor device according to any one of claims 1 to 9, wherein the area of ​​the second gate pad is smaller than the area of ​​the first gate pad.

13. The nitride semiconductor device according to any one of claims 1 to 9, wherein more than half of the area of ​​the second nitride semiconductor transistor overlaps with the first gate pad in a plan view.

14. The nitride semiconductor device according to any one of claims 1 to 9, wherein the entirety of the second nitride semiconductor transistor overlaps with the first gate pad in a plan view.

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