Semiconductor equipment

Abstract

The present invention provides a semiconductor device with an FLR structure that can reduce variations in dimensionality and voltage breakdown due to edge surface charge. [Solution] The semiconductor device 70 comprises an active region 50 and a termination region 60 surrounding the active region 50 on a semiconductor substrate 1 of a first conductivity type. The active region 50 has a first semiconductor layer 2 of the first conductivity type and a first semiconductor region 6 of the second conductivity type. The termination region 60 has a first semiconductor layer 2 and a plurality of second semiconductor regions 30 of the second conductivity type. The plurality of second semiconductor regions 30 are arranged in a ring shape so as to surround the first semiconductor region 6, and a predetermined number of third semiconductor regions 32 of the first conductivity type are provided in the center of the surface of the second semiconductor regions 30 from the end on the side of the first semiconductor region 6.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, semiconductor devices have been proposed that include guard rings 11 to 16 provided at a constant pitch at the edge termination and an embedded injection layer 30 connecting the bottoms of guard rings 11 to 16 (see, for example, Patent Document 1 below). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 5676002 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, conventional FLR (Field Limiting Ring) structures consisting of guard rings have drawbacks, such as large variations in dimensionality and fluctuations in withstand voltage due to edge surface charge.

[0005] This disclosure aims to provide a semiconductor device with an FLR structure that can reduce variations in dimensionality and voltage breakdown due to edge surface charge, thereby solving the problems of the prior art described above. [Means for solving the problem]

[0006] To solve the above-mentioned problems and achieve the objectives of this disclosure, the semiconductor device according to this disclosure has the following features: It comprises an active region for which a main current flows and a termination region surrounding the active region on a semiconductor substrate of a first conductivity type. The active region has a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, provided on the semiconductor substrate, and a first semiconductor region of a second conductivity type provided on the surface of the first semiconductor layer on the side opposite to the semiconductor substrate. The termination region has the first semiconductor layer and a plurality of second semiconductor regions of a second conductivity type provided in contact with and spaced apart from the surface of the first semiconductor layer. The plurality of second semiconductor regions are provided in a ring shape surrounding the first semiconductor region, and a predetermined number of third semiconductor regions of a first conductivity type are provided at the center of the surface of the second semiconductor regions from the end on the first semiconductor region side.

[0007] According to the above disclosure, the first semiconductor layer (n - The third semiconductor region (within the FLR) retains the drift region. - By providing a type region, the concentration of the electric field is mitigated. This further improves the breakdown voltage compared to conventional structures, reducing the risk of dielectric breakdown at the edge, and suppresses the increase in surface electric field strength when charge accumulates on the edge surface, thereby reducing the risk of discharge. In addition, FLR and the inside of the FLR n - By not using SiC etching or high-acceleration ion implantation to form the mold region, manufacturing costs can be reduced. [Effects of the Invention]

[0008] The semiconductor device described herein has an FLR structure, which has the effect of reducing variations in dimensionality and fluctuations in breakdown voltage due to edge surface charge. [Brief explanation of the drawing]

[0009] [Figure 1] This is a top view of a silicon carbide semiconductor device according to an embodiment. [Figure 2] This is an enlarged view of region Z shown in Figure 1 of the silicon carbide semiconductor device according to the embodiment. [Figure 3] This is a cross-sectional view A-A' showing the edge termination structure of a silicon carbide semiconductor device according to an embodiment. [Figure 4A] This is a cross-sectional view B-B' showing the active structure of the silicon carbide semiconductor device according to the embodiment. [Figure 4B] This is a C-C' cross-sectional view showing the active structure of a silicon carbide semiconductor device according to an embodiment. [Figure 4C] This is a D-D' cross-sectional view showing the active structure of a silicon carbide semiconductor device according to an embodiment. [Figure 5A] This graph shows the depth distribution of Al concentration in the FLR of a conventional silicon carbide semiconductor device. [Figure 5B] This graph shows the depth distribution of Al concentration in the FLR of a silicon carbide semiconductor device according to the embodiment. [Figure 6A] This graph shows the edge breakdown voltage of conventional and embodiment-based silicon carbide semiconductor devices. [Figure 6B] This graph shows the horizontal electric field strength at the edge surface of conventional and embodiment silicon carbide semiconductor devices. [Figure 7A] This graph shows the edge breakdown voltage of conventional and embodiment silicon carbide semiconductor devices with an FLR dose of +10%. [Figure 7B] This graph shows the horizontal field strength at the edge surface of a silicon carbide semiconductor device with an FLR dose of +10% according to conventional and embodimental methods. [Figure 8A] This graph shows the edge breakdown voltage of conventional and embodiment silicon carbide semiconductor devices with an FLR dose of -10%. [Figure 8B] This graph shows the horizontal field strength at the edge surface of a conventional silicon carbide semiconductor device with an FLR dose of -10%. [Figure 9A] This graph shows the edge breakdown voltage of conventional and embodiment silicon carbide semiconductor devices with an FLR width of +0.3 μm. [Figure 9B] This graph shows the horizontal field strength at the edge surface of a silicon carbide semiconductor device with an FLR width of +0.3 μm, according to conventional and embodimental models. [Figure 10A] This graph shows the edge breakdown voltage of conventional and embodiment silicon carbide semiconductor devices with an FLR width of -0.3 μm. [Figure 10B] This graph shows the horizontal field strength at the edge surface of a conventional silicon carbide semiconductor device with an FLR width of -0.3 μm. [Figure 11] This graph shows the edge surface electric field distribution of conventional and embodiment-based silicon carbide semiconductor devices. [Figure 12] This is a top view of a conventional silicon carbide semiconductor device. [Figure 13] This is an enlarged view of region Z shown in Figure 12 of a conventional silicon carbide semiconductor device. [Figure 14] This is a cross-sectional view A-A' showing the edge termination structure of a conventional silicon carbide semiconductor device. [Figure 15A] This is a B-B' cross-sectional view showing the active structure of a conventional silicon carbide semiconductor device. [Figure 15B] This is a C-C' cross-sectional view showing the active structure of a conventional silicon carbide semiconductor device. [Figure 15C] This is a D-D' cross-sectional view showing the active structure of a conventional silicon carbide semiconductor device. [Modes for carrying out the invention]

[0010] <Summary of the embodiments of this disclosure> To solve the above-mentioned problems and achieve the objectives of this disclosure, the semiconductor device according to this disclosure has the following features: It comprises an active region for which a main current flows and a termination region surrounding the active region on a semiconductor substrate of a first conductivity type. The active region has a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, provided on the semiconductor substrate, and a first semiconductor region of a second conductivity type provided on the surface of the first semiconductor layer on the side opposite to the semiconductor substrate. The termination region has the first semiconductor layer and a plurality of second semiconductor regions of a second conductivity type provided in contact with and spaced apart from the surface of the first semiconductor layer. The plurality of second semiconductor regions are provided in a ring shape surrounding the first semiconductor region, and a predetermined number of third semiconductor regions of a first conductivity type are provided at the center of the surface of the second semiconductor regions from the end on the first semiconductor region side.

[0011] According to the above disclosure, the first semiconductor layer (n - The third semiconductor region (within the FLR) retains the drift region. - By providing a type region, the concentration of the electric field is mitigated. This further improves the breakdown voltage compared to conventional structures, reducing the risk of dielectric breakdown at the edge, and suppresses the increase in surface electric field strength when charge accumulates on the edge surface, thereby reducing the risk of discharge. In addition, FLR and the inside of the FLR n - By not using SiC etching or high-acceleration ion implantation to form the mold region, manufacturing costs can be reduced.

[0012] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the third semiconductor region is provided within a range of 1 / 5 to 1 / 3 of the distance from the surface of the first semiconductor layer to the lower surface of the second semiconductor region.

[0013] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the third semiconductor region is located at a distance of 10% to 25% of the width of the second semiconductor region from the edge of the second semiconductor region.

[0014] Furthermore, the semiconductor device relating to this disclosure is characterized in that, in the disclosure described above, the width of the third semiconductor region is 50% or more and 80% or less of the width of the second semiconductor region.

[0015] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the impurity concentration of the third semiconductor region is 1 / 10 to 10 times the impurity concentration of the first semiconductor layer at a predetermined location in the third semiconductor region.

[0016] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the predetermined position of the third semiconductor region is the center of the depth of the third semiconductor region and the center of the width of the third semiconductor region.

[0017] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the predetermined position of the third semiconductor region is the center of the depth of the third semiconductor region and is a region 20% inward from both ends of the third semiconductor region when the width of the third semiconductor region is set to 100%.

[0018] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the above-described disclosure, the impurity concentration of the third semiconductor region is higher towards the surface of the third semiconductor region than towards the center of the depth of the third semiconductor region.

[0019] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the third semiconductor region is provided in the second semiconductor region that is closest to the active region.

[0020] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the third semiconductor region is provided in the second semiconductor region, which is at least 1 / 4 of the way from the active region side.

[0021] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the third semiconductor region is not provided in the second semiconductor region having a width of 1.5 μm or less.

[0022] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the second semiconductor region is provided from the surface of the first semiconductor layer to a depth of 1.0 μm or more and 2.0 μm or less.

[0023] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the second semiconductor region takes the maximum value of the impurity concentration within a range of 1 / 2 to 3 / 4 of the distance from the surface of the first semiconductor layer to the bottom surface of the second semiconductor region.

[0024] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the above-described disclosure, the second semiconductor region is not electrically connected to the electrodes of the semiconductor device and is at a floating potential.

[0025] <Knowledge forming the basis of this disclosure> First, let's explain the challenges of conventional semiconductor devices. In semiconductor devices, an edge termination region with a breakdown structure is provided around the active region where current flows when the device is ON. In power semiconductor devices, the breakdown structure is fabricated by forming a p-type structure on the surface of an n-type substrate. In semiconductor devices using silicon carbide (SiC) as the semiconductor material (hereinafter referred to as silicon carbide semiconductor devices), spatially modulated JTE (Junction Termination Extension) structures, FLR structures, or combinations thereof are mainly used.

[0026] The breakdown voltage structure in the edge termination region plays a role in ensuring that the edge breakdown voltage is higher than that of the active region by mitigating electric field concentration at the edge of the active region. This reduces the risk of thermal breakdown of the chip by causing dielectric breakdown to occur in the active region, which has a larger area than the edge termination region, and also stabilizes the breakdown voltage by reducing the influence of charge accumulated on the surface of the edge termination region.

[0027] The spatially modulated JTE structure forms a structural concentration distribution through patterned p-type regions (JTEs), preventing electric field concentration. The FLR structure disperses the electric field and achieves breakdown voltage by arranging the p-type regions in a ring shape when viewed from the surface. Furthermore, a structure in which the FLR is placed on the active region side and combined with JTEs to cover it is also conceivable.

[0028] While spatially modulated JTE structures can reduce the effects of dimensional variations and surface charge in the edge termination regions, they have high manufacturing costs because they require multiple ion implantation steps separate from the active region formation process. Furthermore, in SiC, where impurities do not diffuse easily, etching of the surface SiC or ion implantation at high acceleration energy is required to ensure a depth equivalent to the active region, which also contributes to increased manufacturing costs. On the other hand, FLR structures require only one ion implantation step and allow for simultaneous formation with the p-type region of the active region, resulting in relatively low manufacturing costs. However, they suffer from significant variations in dimensional variations and voltage breakdown due to edge surface charge.

[0029] Figure 12 is a top view of a conventional silicon carbide semiconductor device 170. Figure 13 is an enlarged view of region Z shown in Figure 12 of the conventional silicon carbide semiconductor device 170. Figure 13 is an enlarged view of region Z shown in Figure 12 of the conventional silicon carbide semiconductor device.

[0030] The silicon carbide semiconductor device 170 in Figure 12 has an active region 150, an edge termination region 160 surrounding the active region 150, and a boundary region 155 between the active region 150 and the edge termination region 160. The active region 150 is the region through which current flows when it is in the ON state, and the edge termination region 160 is n -It is a region that relaxes the electric field on the front surface side of the drift region 102 and maintains the breakdown voltage. The boundary region 155 is a region that connects the active region 150 and the edge termination region 160. In this example, an FLR structure 130 composed of a plurality of FLR 131 is provided in the edge termination region 160 so as to surround the boundary region 155. A gate wiring (not shown) is provided in the boundary region 155 and is connected to the gate pad 112. The region indicated by the hatching is the source electrode 116. The source electrode 116 is provided from the active region 150 to the boundary region 155.

[0031] FIG. 13 is an enlarged view of the region Z in FIG. 12 and is a plan view at the depth position of the E-E' line in FIGS. 15A to 15C described later. In the active region 150, a trench 125 provided in a stripe shape and a gate electrode 113 provided therein via a gate insulating film (not shown), n ++ -type source region 107, p ++ -type contact region 106 are provided. The boundary between the active region 150 and the boundary region 155 in the extending direction of the trench 125 is the end of the n ++ -type source region 107 closest to the edge termination region 160 side. The boundary between the active region 150 and the boundary region 155 in the direction perpendicular to the extending direction of the trench 125 is the center of the trench 125 provided closest to the edge termination region 160 side. Note that the region indicated by the hatching in FIG. 13 is the p ++ -type contact region 106.

[0032] FIG. 14 is an A-A' cross-sectional view showing the edge termination structure of a conventional silicon carbide semiconductor device. FIG. 15A is a B-B' cross-sectional view showing the active structure of a conventional silicon carbide semiconductor device. FIG. 15B is a C-C' cross-sectional view showing the active structure of a conventional silicon carbide semiconductor device. FIG. 15C is a D-D' cross-sectional view showing the active structure of a conventional silicon carbide semiconductor device. The E-E' line in FIGS. 14 to 15C indicates the depth position of the plan view in FIG. 13.

[0033] FIG. 14 is the A-A' cross-section shown in FIG. 12 and shows the boundary region 155 and the edge termination region 160. The boundary between the boundary region 155 and the edge termination region 160 is the p between trenches+ This is the end of the mold portion region 104 on the edge termination region 160 side. Figure 15A is a cross section B-B' shown in Figure 13, and in a direction perpendicular to the extension direction of the trench 125, p ++ Figure 15B shows a cross-sectional view of the boundary between the boundary region 155 and the active region 150 at the location where the type contact region 106 is provided. Figure 15B is the C-C' section shown in Figure 13, and in the direction perpendicular to the extension direction of the trench 125, n ++ Figure 15C shows a cross-sectional view of the boundary between the boundary region 155 and the active region 150 at the location where the mold source region 107 is provided. Figure 15C is the D-D' section shown in Figure 13, and shows a cross-sectional view of the boundary between the boundary region 155 and the active region 150 in the extension direction of the trench 125.

[0034] As shown in Figures 14, 15A, 15B, and 15C, the boundary region 155 of the conventional silicon carbide semiconductor device 170 has n + Silicon carbide substrate 101, n - Type drift region 102, below trench p + Type subregion 103, between trenches p + Type subregion 104, p ++ A type contact region 106, an n-type high-density region layer 108, a gate insulating film 111, a gate electrode 113, an interlayer insulating film 114, a barrier metal 115, a source electrode 116, a drain electrode 117, and a trench 125 are provided. Conventional silicon carbide semiconductor devices 170 are n + A silicon carbide substrate 101 and n + n - A type drift region 102 is provided. Hereinafter, n + Silicon carbide substrate and n - The type drift region 102 is combined to form the silicon carbide substrate 180.

[0035] As shown in Figures 15A and 15B, the active region 150 of the conventional silicon carbide semiconductor device 170 contains n + Silicon carbide substrate 101, n - Type drift region 102, below trench p + Type subregion 103, between trenches p + Type partial region 104, p-type base region 105, p++ Type contact area 106, n ++ The silicon carbide semiconductor device 170 has an n-type source region 107, an n-type high-density region layer 108, a gate insulating film 111, a gate electrode 113, an interlayer insulating film 114, a source electrode 116, a drain electrode 117, and a trench 125. - An interlayer insulating film 114 and a source electrode 116 are provided on the surface of the type drift region 102 (hereinafter referred to as the first main surface of the silicon carbide substrate 180).

[0036] The active region 150 in Figure 15A is n - An n-type high-concentration region 108 is provided on the surface layer of the n-type drift region 102, a p-type base region 105 is provided on the upper surface of the n-type high-concentration region 108, and an n-type high-concentration region 108 is provided on the upper surface of the p-type base region 105 ++ It has a type source region 107. The trench 125 is the first main surface (n ++ From the surface of type source region 107) n + It is provided facing the silicon carbide substrate 101. The trench 125 is n ++ The n-type source region 107 and the p-type base region 105 are penetrated to reach the n-type high-density region 108. A gate electrode 113 is provided in the trench 125 via a gate insulating film 111. Between adjacent trenches 125, there is a trench-to-trench p + Type subregion 104 and p ++ A type contact region 106 is provided. Between the trenches p + Type subregion 104 is p ++ It is provided in contact with the lower surface of the type contact area 106. ++ The side surface of the type contact area 106 is n ++ It is adjacent to the type source region 107. Trench space p + The side of the type subregion 104 consists of the p-type base region 105, the n-type high-concentration region layer 108, and the p-type sub-trench described later. + It is in contact with the mold subregion 103. Trench below p + The mold portion area 103 is provided to cover the bottom of the trench 125. +The mold portion region 103 is provided separately from the p-type base region 105. Trench below p + A high-concentration n-type region 108 is provided between the type subregion 103 and the p-type base region 105. + The end of the mold subregion 103 is between the trenches p + It is in contact with the mold subregion 104. The boundary region 155 in Figure 15A is on the side of the trench 125. ++ Type source region 107, trench space p ++ Type subregion 104, below trench p + The type subregion 103 is in contact. Also, the trench space p + Type subregion 104 is below the trench p + It is in contact with type subregion 103.

[0037] The active region 150 in Figure 15B is between the trenches p + Type subregion 104 and p ++ The difference between the active region 150 shown in Figure 15A and the type contact region 106 is that the type contact region 106 is not provided. The boundary region 155 in Figure 15B has the same configuration as the boundary region 155 shown in Figure 15A.

[0038] As shown in Figure 15C, the active region 150 of the conventional silicon carbide semiconductor device 170 is along the stretching direction of the trench 125, and is on the first main surface of the silicon carbide substrate 180. ++ Type contact area 106 and n ++ Type source regions 107 are provided alternately. ++ Contacting the lower surface of the type contact region 106, between the trenches p + A type region 104 is provided, n ++ A p-type base region 105 is provided in contact with the lower surface of the type source region 107. The gate electrode 113 is connected to the gate pad 112 via a polysilicon layer 115 and a gate runner (not shown).

[0039] As shown in Figure 14, the edge termination region 160 of the conventional silicon carbide semiconductor device 170 has n + Silicon carbide substrate 101, n -Type drift region 102, field oxide film 141, polyimide film 142, FLR structure 130, drain electrode 117, n ++ A channel stopper region 140 is provided. In the edge termination region 160 of the conventional silicon carbide semiconductor device 170, an FLR structure 130 and n are provided on the first main surface of the silicon carbide substrate 180. ++ A channel stopper region 140 is provided. In the edge termination region of the conventional silicon carbide semiconductor device 170, a field oxide film 141 and a polyimide film 142 are provided on the first main surface of the silicon carbide substrate 180. + A drain electrode 117 is provided on the lower surface of the silicon carbide substrate 101 (hereinafter referred to as the second main surface of the silicon carbide substrate 180).

[0040] In conventional silicon carbide semiconductor devices, the FLR structure 130 has multiple p-type FLRs 131 arranged on the first main surface side of the silicon carbide substrate. A shallow, high-density p-type FLR region 132 is provided in the central part of the surface side of the FLR 131. On the surface side of the FLR 131, there is a space between the side surface of the high-density p-type FLR region 132 and the side surface of the FLR 131, and the n + The region on the silicon carbide substrate 101 side is a low-concentration p-type FLR region 133 with a lower impurity concentration than the high-concentration p-type FLR region 132. The high-concentration p-type FLR region 132 is p ++ The depth and impurity concentration can be the same as that of the contact area 106.

[0041] In this way, under the trench coat + In the edge termination structure 160 using an FLR 131 that is shallower than the type subregion 103, the electric field is dispersed to the maximum extent in the FLR region 130, and then the trench below p + Dielectric breakdown is ensured at the end of the mold portion region 103 to guarantee withstand voltage.

[0042] In the conventional silicon carbide semiconductor device 170 voltage breakdown structure, the p of the active region 150 ++Having a high-concentration p-type FLR region 132 with the same depth and impurity concentration as the type contact region 106 presents the following challenges. Firstly, the electric field concentrates in the high-concentration p-type FLR region 132 on the surface of the silicon carbide substrate 180, which lowers the breakdown voltage of the edge termination region 160. Therefore, depending on the design conditions and process variations of the active region 150, there is a risk that the breakdown voltage of the edge termination region 160 will fall below that of the active region 150. In this case, dielectric breakdown occurs in the edge termination region 160, which has a smaller area than the active region 150, increasing the risk of device failure due to heat generation and deterioration of surrounding components. Secondly, when charge accumulates on the surface of the edge termination region 160 due to use under high temperature and high humidity conditions, the electric field strength on the surface of the edge termination region 160 increases, raising the risk of discharge.

[0043] Thus, conventional silicon carbide semiconductor devices 170 have a breakdown voltage structure that cannot balance manufacturing cost and breakdown voltage fluctuations. In this disclosure, in order to solve the above problems, an FLR structure is adopted, which requires only one ion implantation and enables simultaneous formation with the p-type region of the active region, resulting in relatively low manufacturing costs. Furthermore, a semiconductor device is provided that reduces breakdown voltage fluctuations due to dimensional variations and edge surface charges.

[0044] Preferred embodiments of the semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. It is preferable to include up to 5% in the description of the same or equivalent components to account for manufacturing variations.

[0045] (Embodiment) The semiconductor device according to this disclosure is constructed using a wide-bandgap semiconductor. In the embodiment, a silicon carbide semiconductor device fabricated using silicon carbide (SiC) as the wide-bandgap semiconductor will be described using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example. Figure 1 is a top view of the silicon carbide semiconductor device 70 according to the embodiment. Figure 2 is an enlarged view of region Z shown in Figure 1 of the silicon carbide semiconductor device 70 according to the embodiment.

[0046] The silicon carbide semiconductor device 70 according to the embodiment shown in Figure 1 has an active region 50, an edge termination region 60 surrounding the active region 50, and a boundary region 55 between the active region 50 and the edge termination region 60. The active region 50 is the region through which current flows when it is in the ON state, and the edge termination region 60 is n - This region is the area that mitigates the electric field on the front side of the drift region 2 and maintains the breakdown voltage. The boundary region 55 is the region that connects the active region 50 and the edge termination region 60. In this example, an FLR structure 30 composed of multiple FLRs 31 is provided in the edge termination region 60 so as to surround the boundary region 55. Gate wiring (not shown) is provided in the boundary region 55 and is connected to the gate pad 12. Various sense elements such as current sense and temperature sense may also be provided. The hatched area is the source electrode 16. The source electrode 16 is provided extending from the active region 50 to the boundary region 55.

[0047] Figure 2 is an enlarged view of region Z in Figure 1, and is a plan view at the depth position of the E-E' line in Figures 4A to 4C, which will be described later. The active region 50 has trenches 125 arranged in a stripe pattern and gate electrodes 13, n provided inside them via a gate insulating film (not shown). ++ Type source area 7, p ++ A type contact region 6 is provided. The boundary between the active region 50 and the boundary region 55 in the extension direction of the trench 25 is, for example, the n on the edge terminal region 60 side. ++This is the end of the type source region 7. The boundary between the active region 50 and the boundary region 55 in a direction perpendicular to the extension direction of the trench 25 is, for example, the center of the trench 25 located on the side closest to the edge terminal region 60.

[0048] Figure 3 is a cross-sectional view taken along line A-A' showing the edge termination structure of a silicon carbide semiconductor device according to an embodiment. Figure 4A is a cross-sectional view taken along line B-B' showing the active structure of a silicon carbide semiconductor device according to an embodiment. Figure 4B is a cross-sectional view taken along line C-C' showing the active structure of a silicon carbide semiconductor device according to an embodiment. Figure 4C is a cross-sectional view taken along line D-D' showing the active structure of a silicon carbide semiconductor device according to an embodiment.

[0049] Figure 3 shows the A-A' section shown in Figure 1, illustrating the boundary region 55 and the edge termination region 60. The boundary between the boundary region 55 and the edge termination region 60 is, for example, between trenches p + This is the end of the mold portion region 4 on the edge termination region 60 side. Figure 4A is a cross section B-B' shown in Figure 2, and in a direction perpendicular to the extension direction of the trench 25, p ++ Figure 4B shows a cross-sectional view of the boundary region 55 and the active region 50 at the location where the type contact region 6 is provided. Figure 4B is a cross-section of C-C' shown in Figure 2, and in the direction perpendicular to the extension direction of the trench 25, n ++ Figure 4C shows a cross-sectional view of the boundary region 55 and the active region 50 at the location where the type source region 7 is provided. Figure 4C is the D-D' section shown in Figure 2, and shows a cross-sectional view of the boundary region 55 and the active region 50 in the extension direction of the trench 25.

[0050] As shown in Figures 3, 4A, 4B, and 4C, the boundary region 55 of the silicon carbide semiconductor device 70 according to the embodiment contains n + Silicon carbide substrate 1, n - Type drift region 2, below trench p + Type subregion 3, trench space p + Type subregion 4, p ++ A type contact region 6, an n-type high-density region layer 8, a gate insulating film 11, a gate electrode 13, an interlayer insulating film 14, a source electrode 16, a drain electrode 17, and a trench 25 are provided. The silicon carbide semiconductor device 70 according to this embodiment is n +Type silicon carbide substrate 1 and n + On the upper surface of the n-type silicon carbide substrate 1, n - type drift region 2 is provided. Hereinafter, n + type silicon carbide substrate 1 and n - type drift region 2 are combined to form a silicon carbide substrate 80. n + Type silicon carbide substrate 1 is a single crystal silicon carbide substrate. n - Type drift region 2 is n + at an impurity concentration lower than that of the n-type silicon carbide substrate 1. n - Type drift region 2, for example, has an impurity concentration of 5×10 16 cm -3 or less and a thickness of 5.0 μm or more. n + Type silicon carbide substrate 1 functions as a drain region. n + On the back surface of the n-type silicon carbide substrate 1 (the second main surface of the silicon carbide substrate 80), a drain electrode 17 serving as a back surface electrode is provided. Also, n - type drift region 2 and n + type silicon carbide substrate 1, for example, n + a buffer layer or the like for suppressing the growth of crystal defects from the n-type silicon carbide substrate 1 may be provided.

[0051] As shown in FIGS. 4A and 4B, in the active region 50 of the silicon carbide semiconductor device 70 according to the embodiment, n + type silicon carbide substrate 1, n​​​​​​​​​​​​​​​​​An n-type high-concentration region 8 is provided on the surface layer of the n-type drift region 2, a p-type base region 5 is provided on the upper surface of the n-type high-concentration region 8, and an n-type high-concentration region 8 is provided on the upper surface of the p-type base region 5 ++ It has a type source region 7 and a plurality of trenches 25 on the first main surface side of the silicon carbide substrate 80. The trenches 25 are on the first main surface (n ++ From the surface of type source region 7) n ++ The impurity concentration in the n-type high-concentration region 8 is n, which penetrates the p-type source region 7 and the p-type base region 5. + Lower n than type silicon carbide substrate 1 - It is higher than the n-type drift region 2. If the n-type high-concentration region 8 cannot be provided, the trench 25 is from the first main surface of the silicon carbide substrate 80 to n - It may be provided so as to reach the type drift region 2. Along the inner wall of the trench 25, a gate insulating film 11 is provided at the bottom and side walls of the trench 25, and a gate electrode 13 is provided inside the gate insulating film 11 in the trench 25. The gate insulating film 11 makes the gate electrode 13 n - It is insulated from the type drift region 2. A portion of the gate electrode 13 may protrude from the first main surface of the silicon carbide substrate 80 toward the source electrode 16. Below the trench p + The mold portion area 3 is provided to cover the bottom of the trench 25. Below the trench p + The upper surface of the mold portion region 3 is provided separately from the p-type base region 5. The side surface of the trench 25 is n ++ Type source region 7, p-type base region 5, n-type high-concentration region 8, p-type below trench + It is in contact with type subregion 3. Between adjacent trenches 25, p ++ Type contact area 6 is n ++ It is provided sandwiched between the type source region 7, p ++ The side surface of the type contact area 6 is n ++ It is adjacent to type source region 7. ++ The contact region 6 extends from the first main surface of the silicon carbide substrate 80 to n ++ It may be provided to the same depth as the bottom surface of the type source area 7. ++The impurity concentration in the type contact region 6 is 5 × 10¹⁶ in the region from the first main surface of the silicon carbide semiconductor substrate 80 to a depth of 0.5 μm. 19 cm -3 The above 2 x 10 20 cm -3 The following applies. The boundary region 55 in Figure 4A is on the side of the trench 25. ++ Type source region 7, trench space p ++ Type subregion 4, below trench p + Type subregion 3 is in contact. Also, trench space p + The lower surface of mold subregion 4 is below the trench p + It is in contact with type subregion 3.

[0053] In Figure 4B, the active region 50 does not have a p-type base region 5, and the trench-interval p + The point where type subregion 4 is provided and p ++ The difference from the cross-section of the active region 50 shown in Figure 4A is that a type contact region 6 is provided. The active region 50 in Figure 4B is n - An n-type high-concentration region 8 is provided on the surface layer of the n-type drift region 2, and a trench space p is provided on the upper surface of the n-type high-concentration region 8. + Type subregion 4 and trench space p + n provided on the upper surface of the mold subregion 4 ++ It has a type source region 7. Multiple trenches 25 are provided on the first main surface side of the silicon carbide substrate 80. The trenches 25 are on the first main surface (n ++ From the surface of type source region 7) n ++ Type source region 7 and trench space p + The n-type high-concentration region 8 is reached by penetrating the type subregion 4. If the n-type high-concentration region 8 is not provided, the trench 25 extends from the first main surface of the silicon carbide substrate 80 to the n - It may be provided so as to reach the type drift region 2. Along the inner wall of the trench 25, a gate insulating film 11 is provided at the bottom and side walls of the trench 25, and a gate electrode 13 is provided inside the gate insulating film 11 in the trench 25. The gate insulating film 11 makes the gate electrode 13 n -It is insulated from the type drift region 2. A portion of the gate electrode 13 may protrude from the first main surface of the silicon carbide substrate 80 toward the source electrode 16. Below the trench p + The mold portion area 3 is provided to cover the bottom of the trench 25. Below the trench p + The upper surface of the type subregion 3 is between the trenches p + It is provided adjacent to the mold portion region 4. Trench below p + Type subregion 3 is between trenches p + By connecting to the type subregion 4, it is electrically connected to the source electrode 16. The side of the trench 25 is n ++ Type source region 7, trench space p + Type subregion 4, below trench p + It is in contact with type subregion 3. Between adjacent trenches 25, there is a trench interval p. + Type subregion 4 and n ++ A type source region 7 is provided. Between the trenches p + Type subregions 4 and n ++ The side surface of the type source region 7 is in contact with the trench 25. The boundary region 55 in Figure 4B has the same structure as the boundary region 55 in Figure 4A.

[0054] As shown in Figure 4C, the active region 50 of the silicon carbide semiconductor device 70 of the embodiment is along the stretching direction of the trench 25, and is on the first main surface of the silicon carbide substrate 80. ++ Type contact area 6 and n ++ Type source regions 7 are provided alternately. ++ A p-type base region 5 is provided in contact with the lower surface of the type contact region 6, n ++ The trench space p is adjacent to the lower surface of the type source region 7. + A type subregion 4 and a p-type base region 5 are provided. Trench space p + The lower surface of the mold subregion 4 is located deeper than the lower surface of the p-type base region 5. The gate electrode 13 is connected to the polysilicon layer 15 at the boundary region 55. The polysilicon layer 15 is connected to the gate pad 12 via a gate runner (not shown).

[0055] Trench bottoms + Type subregion 3 and trench space p+ The type subregion 4 is fixed at the potential of the source electrode 16 and has the function of depleting (or depleting the n-type high-concentration region layer 8, or both) when the MOSFET (silicon carbide semiconductor device 70) is turned off, thereby mitigating the electric field applied to the gate insulating film 11.

[0056] Also, trench coat bottoms + The peak of impurity concentration in the mold subregion 3 is located in the region at a depth of 1.0 μm or more from the first main surface of the silicon carbide substrate 80, and it is preferable that the maximum value of the impurity concentration is higher than the impurity concentration peak of FLR31 described later. Also, the p below the trench in the active region 50 + Type subregion 3 and trench space p + In the cross-sectional region (Figure 4A) that forms both of the mold subregions 4, the impurity concentration peak of FLR31 is below the trench p + Trench-down p in the depth region up to the impurity concentration peak of subregion 3 of type subregion 3 + Type subregion 3 and trench space p + The superposition impurity concentration in type subregion 4 is always n - It is preferable that the impurity concentration exceeds that of the mold drift layer 2.

[0057] Furthermore, as shown in Figures 3, 4A, 4B, and 4C, below the trench p + Type subregion 3, trench space p + Type subregions 4 and p ++ The type contact region 6 extends from the edge of the active region 50 to the boundary region 55. As shown in Figure 3, in the boundary region 55, below the trench p + The edge of type subregion 3 is between trenches p + It is located at least 3.0 μm on the active region 50 side of the edge of the type subregion 4. Furthermore, in the boundary region 55, p ++ The edge of the type contact region 6 is between the trenches p + It is located at least 1.0 μm closer to the active region 50 than the edge of the type subregion 4.

[0058] The interlayer insulating film 14 is provided so as to cover the entire surface of the first main surface side of the silicon carbide substrate 80, and the gate electrode 13 embedded in the trench 25. The source electrode 16 is connected through a contact hole opened in the interlayer insulating film 14, n ++ Type source region 7 and p ++ It contacts the type contact region 6. The source electrode 16 is electrically insulated from the gate electrode 13 by the interlayer insulating film 14. A source electrode pad (not shown) is provided on the source electrode 16. A barrier metal (not shown) may be provided between the source electrode 16 and the interlayer insulating film 14 to prevent the diffusion of metal atoms from the source electrode 16 to the gate electrode 13. A polyimide film 42, which functions as a protective film, is provided on the surface of the silicon carbide semiconductor device 70. In Figures 4A and 4B, only two MOS gate (insulating gate consisting of metal-oxide-semiconductor) structures are shown in the active region 50, but many more MOS gate structures may be arranged in parallel.

[0059] As shown in Figure 3, an FLR structure 30 is provided in the edge termination region 60 of the semiconductor device according to the embodiment. Furthermore, the n outside the FLR structure 30 (on the chip end side) - n, which functions as a channel stopper, is located on the surface of the type drift region 2 (the first main surface of the silicon carbide substrate 80). ++ A channel stopper region 40 is provided. ++ The type channel stopper region 40 is p ++ A type is also acceptable. FLR structure 30 and n - The pn junction with the mold drift region 2 maintains high lateral breakdown voltage. The edge termination region 60 is covered with a field oxide film 41, on which an HTO film (not shown), an interlayer insulating film (not shown), and a polyimide film 42 are deposited in sequence.

[0060] The FLR structure 30 has multiple p-type FLRs (second semiconductor regions of the second conductivity type) 31 arranged on the first main surface side of the silicon carbide substrate 80. The FLRs 31 are n - It is provided on the surface layer of the drift region 2. The surface layer of FLR31 has n inside FLR -A type region (third semiconductor region of the first conductivity type) 32 is provided. FLR31 and FLR inside n - The surface of the mold region 32 is exposed to the first main surface of the silicon carbide substrate 180. FLR31 and FLR inside n - The mold region 32 is provided in an annular shape so as to surround the active region 50 in a plan view. Multiple FLRs 31 are provided spaced apart, and their width narrows towards the end of the edge termination region 60. Inside the FLR n - The mold region 32 narrows in width towards the end of the edge termination region 60. The FLR 31 provided on the outside of the FLR structure 30 has n inside the FLR - A type region 32 does not necessarily have to be provided. (FLR n) - The FLR31, which is provided with the type region 32, has n within the FLR. - The central region is in contact with the lower surface of the mold region 32, and the sides of the central region are sandwiched between the FLR n - It includes p-type regions (hereinafter referred to as the p-type regions at both ends of the FLR31) that are in contact with the side surface of the type region 32. - Type region 32 is the original n that has not been ion-implanted. - The doping concentration distribution may be the same as that of type drift region 2. (Within FLR n) - The mold region 32 may be provided by injecting n-type impurities into the p-type FLR 31.

[0061] FLR inside n - The mold region 32 is the first main surface (n - It is in contact with the surface of the type drift region 2. From the first main surface of the silicon carbide substrate 80 to the inside of the FLR n - The depth to the lower surface of the mold region 32 is set within the range of 1 / 5 to 1 / 2 of the depth from the first main surface of the silicon carbide substrate 80 to the lower surface of the FLR31. The p-type regions at both ends of the FLR31 are set to ensure the formation of a depletion layer. - It is in contact with the surface of the drift region 2. n inside the FLR - The impurity concentration in type region 32 is n - The impurity concentration in the type drift region 2 may be lower. - The mold region 32 may be formed by injecting n-type impurities into the p-type FLR 31. In that case, the n-type impurities within the FLR -The impurity concentration in type region 32 is n - It may be higher than the type drift region 2. In the A-A' cross-sectional view of Figure 3, the direction from the first main surface of the silicon carbide substrate 80 toward the drain electrode 17 is defined as the depth direction, and the direction from the boundary region 55 toward the outside of the edge termination region 60 is defined as the width direction. Here, within the FLR n - The width of the mold region is within the FLR that is in contact with the first main surface of the silicon carbide substrate 80 in the width direction. - The width of the type region 32 is set to n within the FLR. - Both ends of the mold region 32 are in contact with the first main surface of the silicon carbide substrate 80 in the width direction within the FLR n - These are the ends of the surface of the mold region 32. Furthermore, n within the FLR - The depth of the mold region 32 is measured from the first main surface of the silicon carbide substrate 80 to the inside of the FLR in the depth direction. - The depth is defined as the depth up to the bottom surface of the mold region 32. (FLR inside n) - The center of the depth of type region 32, and within the FLR n - At the center of the width of type region 32, within FLR n - The impurity concentration in type region 32 is n - The impurity concentration in type drift region 2 should be between 1 / 10 and 10 times the original concentration. - The center of the depth of type region 32, and within the FLR n - At the center of the width of type region 32, within FLR n - The impurity concentration in type region 32 is 1 × 10⁻⁶ 15 cm -3 The above 1 x 10 17 cm -3 The following is sufficient. (n within FLR) - The impurity concentration in type region 32 is n at a predetermined position. - The impurity concentration in type drift region 2 should be between 1 / 10 and 10 times the original concentration. - The impurity concentration in type region 32 is 1 × 10⁻⁶ at a given position. 15 cm -3 The above 1 x 10 17 cm -3 The following is acceptable. Here, the designated position is n within the FLR. - At the center of the depth of type region 32, and within the FLR n - When the width of type region 32 is set to 100%, the number of FLR units n -This is a position 20% inward from both ends of type region 32. (Within FLR n) - Type region 32 is within FLR n - From the center of the depth of type region 32, within the FLR n - The impurity concentration on the surface of the mold region 32 (the first main surface of the silicon carbide substrate 80) may be high. FLR31 and n inside FLR - The type region 32 is not electrically connected to any of the device's electrodes and is at a floating potential. Thus, on the surface of the central region of FLR31, the n inside the FLR - A type region 32 exists, and both ends of FLR31 are n - It is connected to the surface of the drift region 2. However, for multiple FLR31 with a width of 1.5 μm or less, n within the FLR - Type region 32 is not provided.

[0062] Also, within FLR n - The type region 32 must be located at least in the FLR 31 closest to the active region 50. - The type region 32 is preferably provided in 1 / 4 or more of each FLR31 from the FLR31 closest to the active region 50, more preferably in 1 / 2 or more of each FLR31, and most preferably in 2 / 3 or more of each FLR31. Also, within the FLR n - The width of the type region 32 should be between 50% and 80% of the width of the FLR 31.

[0063] The p-type regions at both ends of the FLR31 are n - It is in contact with the surface of the type drift region 2. The width of the p-type regions at both ends of this FLR31 should be between 10% and 25% of the width of each FLR31. In other words, within the FLR n - The type region 32 is located at a distance of 10% to 25% of the width of the FLR31 from the edge of the FLR31. For example, the widths of the p-type regions at both ends of the FLR31 are 0.5 μm to 1.5 μm, respectively.

[0064] FLR31 is located between the trenches in the active region 50 and the boundary region 55. + Since it is formed under the same ion implantation conditions as type subregion 4, the trench space p +The depth can be the same as type subregion 4, and the concentration distribution in the depth direction is between trenches p + It is common with type subregion 4. Also, FLR31 is below the trench of the active region 50 and boundary region 55. + It is shallower than type subregion 3.

[0065] Each FLR31 decreases in width and widens from the active region 50 side toward the tip end. For example, when 17 FLR31s are arranged as shown in Figure 3 (F1 to F17, only F1 to F4 are shown in Figure 3), the width of each FLR31, the width between each FLR31 (W2 to W17, only W2 to W4 are shown in Figure 3), and the FLR31 closest to the active region 50 (F1) and p ++ The width W1 of the contact area 6 is as shown in Table 1 below. The unit in Table 1 is μm.

[0066] [Table 1]

[0067] As shown in Table 1, F1 to F15 of FLR31 have a width greater than 1.5 μm, and within the FLR n - A mold region 32 is provided. On the other hand, F16 and F17 of FLR31 have a width of 1.5 μm or less, and within the FLR n - Type region 32 is not provided. - The width of the FLR31 on the outermost surface of the drift region 2 is 6.0 μm or more on the side closest to the active region 50 and 2.0 μm or less on the outer edge of the chip, and the width of each FLR31 is less than or equal to the width of the FLR31 adjacent to the active region 50. As shown in Table 1, n -At the outermost surface of the mold drift region 2, the spacing between the sides of adjacent FLR31s is 2.0 μm or less on the side closest to the active region 50 and 3.0 μm or more on the outer edge of the chip. The spacing between each FLR31 is greater than or equal to the spacing between FLR31s adjacent to the active region 50. It is preferable that there be 10 or more FLRs. In the silicon carbide semiconductor device shown in Table 1, the spacing between the centers of adjacent FLR31s is not constant, but the width of the FLR31s and the spacing between the sides of adjacent FLR31s may be adjusted so that the spacing between the centers of the FLR31s is constant.

[0068] In this embodiment, edge pressure resistance is ensured by the p-type FLR31, while the surface layer of the FLR31 contains n - By providing the type region 32, the concentration of the electric field is mitigated. This further improves the breakdown voltage compared to the conventional structure, reducing the risk of dielectric breakdown at the edge, and suppresses the increase in surface electric field strength when charge accumulates on the edge surface, thereby reducing the risk of discharge. In addition, the FLR31 and the inside of the FLR n - By not using SiC etching or high-acceleration ion implantation to form the mold region 32, manufacturing costs can be reduced.

[0069] Figure 5A is a graph showing the depth distribution of Al concentration in the FLR of a conventional silicon carbide semiconductor device. Figure 5B is a graph showing the depth distribution of Al concentration in the FLR of a silicon carbide semiconductor device according to an embodiment. In Figures 3A and 3B, the vertical axis represents the concentration of impurities in FLR31, in this case aluminum (Al), and the unit is cm. -3 The horizontal axis is n. - This indicates the depth from the surface of the drift region 2, in units of μm. In Figures 3A and 3B, n - For example, the impurity concentration in the drift region 2 is 1 × 10⁻⁶. 16 cm -3 This is illustrated with a dashed line.

[0070] Figure 5A shows the impurity concentration in the X-X' section of Figure 14, and in Figure 5B, the dotted line represents the impurity concentration in the X-X' section of Figure 3, and the solid line represents the impurity concentration in the Y-Y' section of Figure 3. As shown by the dotted line in Figure 5B, the FLR inside n provided in the surface layer of FLR31 - Type region 32 and n within FLR - In the central region of the FLR31 that is in contact with the lower surface of the mold region 32, n - The concentration of Al on the surface of type drift region 2 is n - The impurity concentration is lower than that of the n-type drift region 2, and it is an n-type region. As shown by the solid line in Figure 5B, in the p-type regions at both ends of FLR31, n - The concentration of Al on the surface of type drift region 2 is n - The impurity concentration is higher than that of type drift region 2, resulting in a p-type.

[0071] Furthermore, as shown in Figure 5B, the impurity concentration in FLR31 has a distribution with one peak in the depth direction. The peak of the impurity concentration is n - Type drift region 2 is present in the region from the surface to a depth of 0.5 to 1.5 μm. The maximum impurity concentration is 5 × 10⁻¹⁶. 17 cm -3 The above 2 x 10 18 cm -3 The range is as follows: The deepest point of FLR31 is located in the region from 1.0 μm to 2.0 μm in depth. Also, the peak of impurity concentration in FLR31 is n - The maximum value may be taken within the range of 1 / 2 to 3 / 4 of the distance from the surface of the mold drift region 2 to the bottom surface of the FLR31.

[0072] Figure 6A is a graph showing the edge breakdown voltage of conventional and embodiment silicon carbide semiconductor devices. Figure 6B is a graph showing the horizontal electric field strength at the edge surface of conventional and embodiment silicon carbide semiconductor devices. In Figure 6A, the vertical axis represents breakdown voltage, and the unit is V. The horizontal axis represents n. - This shows the charge density on the surface of type drift region 2, in units of cm. -2 In Figure 6B, the vertical axis represents the surface charge intensity, in units of MV / cm. The horizontal axis represents n -This shows the charge density on the surface of type drift region 2, in units of cm. -2 That is the case.

[0073] In Figures 6A and 6B, the solid lines ○ represent simulation results for the silicon carbide semiconductor device according to the embodiment, and the dotted lines ● represent simulation results for a conventional silicon carbide semiconductor device. As shown in Figure 6A, the silicon carbide semiconductor device according to the embodiment has a higher breakdown voltage than a conventional silicon carbide semiconductor device, regardless of the surface charge density. As shown in Figure 6B, the silicon carbide semiconductor device according to the embodiment has a lower electric field strength at the edge surface than a conventional silicon carbide semiconductor device, thus reducing the risk of discharge. In particular, the electric field increase when surface charge is applied can be suppressed in this embodiment.

[0074] Figures 7A to 10B are graphs showing the change in edge breakdown voltage due to variations in the dimensions of the FLR31 and the dose amount of the FLR31 in a silicon carbide semiconductor device. In Figures 7A to 10B, the solid line ○ shows the simulation results for a silicon carbide semiconductor device according to the embodiment, and the dotted line ● shows the simulation results for a conventional silicon carbide semiconductor device. In Figures 7A, 8A, 9A, and 10A, the vertical axis represents breakdown voltage, and the unit is V. The horizontal axis represents n. - This shows the charge density on the surface of type drift region 2, in units of cm. -2 In Figures 7B, 8B, 9B, and 10B, the vertical axis represents the surface charge intensity, in units of MV / cm. The horizontal axis represents n - This shows the charge density on the surface of type drift region 2, in units of cm. -2 That is the case.

[0075] Figure 7A is a graph showing the edge breakdown voltage when the dose amounts of FLR31 and FLR131 in the conventional and embodiment silicon carbide semiconductor devices are increased by +10%. Figure 7B is a graph showing the horizontal electric field strength on the edge surface when the dose amounts of FLR31 and FLR131 in the conventional and embodiment silicon carbide semiconductor devices are increased by +10%. Figure 8A is a graph showing the edge breakdown voltage when the dose amounts of FLR31 and FLR131 in the conventional and embodiment silicon carbide semiconductor devices are decreased by -10%. Figure 8B is a graph showing the horizontal electric field strength on the edge surface when the dose amounts of FLR31 and FLR131 in the conventional and embodiment silicon carbide semiconductor devices are decreased by -10%. Figure 9A is a graph showing the edge breakdown voltage when the widths of FLR31 and FLR131 in the conventional and embodiment silicon carbide semiconductor devices are increased by 0.3 μm. Figure 9B is a graph showing the horizontal electric field strength at the edge surface when the widths of FLR31 and FLR131 of the conventional and embodiment silicon carbide semiconductor device are increased by 0.3 μm, respectively. Figure 10A is a graph showing the edge breakdown voltage when the widths of FLR31 and FLR131 of the conventional and embodiment silicon carbide semiconductor device are decreased by 0.3 μm, respectively. Figure 10B is a graph showing the horizontal electric field strength at the edge surface when the widths of FLR31 and FLR131 of the conventional and embodiment silicon carbide semiconductor device are decreased by 0.3 μm, respectively.

[0076] As shown in Figures 7A, 8A, 9A, and 10A, even when the dose (±10%) and width (±0.3 μm) of FLR31 fluctuate, the silicon carbide semiconductor device according to this embodiment has a higher breakdown voltage than conventional silicon carbide semiconductor devices. As shown in Figures 7B, 8B, 9B, and 10B, even when the dose (±10%) and width (±0.3 μm) of FLR31 fluctuate, the silicon carbide semiconductor device according to this embodiment has a lower electric field strength at the edge surface than conventional silicon carbide semiconductor devices, thus reducing the risk of discharge. In particular, the electric field increase when surface charge is applied can be suppressed in this embodiment.

[0077] Figure 11 is a graph showing the edge surface electric field distribution of conventional and embodiment silicon carbide semiconductor devices. In Figure 11, the solid line shows the simulation results for the embodiment silicon carbide semiconductor device, and the dotted line shows the simulation results for the conventional silicon carbide semiconductor device. In Figure 11, the vertical axis represents the surface charge intensity of the polyimide film 42, in units of MV / cm. The horizontal axis represents the distance X from the edge of the polyimide film 42 on the active region 50 side at the edge termination region 60, in units of μm.

[0078] In Figure 11, n - If a positive charge accumulates on the surface of type drift region 2 (2.0 × 10 12 cm -2 This shows the electric field distribution at the edge termination region 60 of the silicon carbide semiconductor device. As shown in Figure 11, the silicon carbide semiconductor device according to this embodiment has a more leveled electric field distribution on the surface of the edge termination region 60 and a lower peak electric field intensity compared to conventional silicon carbide semiconductor devices.

[0079] Furthermore, in the semiconductor device manufacturing method according to the embodiment, for example, n - When forming FLR31 inside the drift region 2 by ion implantation, the mask is changed to n in the central region of FLR31. - To prevent ions from being implanted on the surface of type drift region 2, n within the FLR - A mold region 32 can be formed. Other structures can be fabricated in the same way as when fabricating a MOSFET with a voltage rating of 1200V, for example.

[0080] As described above, according to the embodiment, edge pressure resistance is ensured by the p-type FLR, and n is formed on the surface of the central region of the FLR. - n within the FLR with type drift region remaining - By providing a type region, the concentration of the electric field is mitigated. This further improves the withstand voltage compared to conventional structures, reducing the risk of dielectric breakdown at the edge, and suppresses the increase in surface electric field strength when charge accumulates on the edge surface, thereby reducing the risk of discharge. In addition, FLR and FLR internal n -By not using SiC etching or high-acceleration ion implantation to form the mold region, manufacturing costs can be reduced.

[0081] In summary, this disclosure can be modified in various ways without departing from the spirit of this disclosure, and in each of the embodiments described above, for example, the dimensions of each part, the impurity concentration, etc., can be set in various ways according to the required specifications. Furthermore, although the embodiments described above use silicon carbide as the wide bandgap semiconductor as an example, it is also applicable to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). In addition, although the first conductivity type is set to n type and the second conductivity type to p type in each embodiment, this disclosure is also valid even if the first conductivity type is p type and the second conductivity type is n type. [Industrial applicability]

[0082] As described above, the semiconductor device according to this disclosure is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, and igniters for automobiles. [Explanation of Symbols]

[0083] 1, 101 n + Silicon carbide substrate 2, 102 n - Type drift region 3, 103 Trench bottoms p + type subregion 4, 104 trenches between p + type subregion 5. 105 p-type base region 6, 106 p ++ Type Contact Area 7, 107 n ++ Type source area 8, 108 n-type high concentration region layer 11, 111 Gate insulating film 12, 112 gate pads 13, 113 gates 14, 114 Interlayer insulating film 15, 115 Polysilicon layer 16, 116 source electrodes 17, 117 Drain electrodes 25, 125 Trench 30, 130 FLR structure 31, 131 FLR 32 FLR inside n - type area 40, 140 n ++ Type channel stopper region 41, 141 Field oxide film 42, 142 Polyimide film 50, 150 active area 55, 155 boundary area 60, 160 edge termination region 70, 170 Silicon Carbide Semiconductor Devices 80, 180 silicon carbide substrate 132 High concentration p-type FLR region 133 Low concentration p-type FLR region

Claims

1. A semiconductor substrate of the first conductivity type comprises an active region through which a main current flows and a termination region surrounding the active region. In the aforementioned active region, A first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate is provided on the semiconductor substrate, A first semiconductor region of a second conductivity type is provided on the surface of the first semiconductor layer opposite to the semiconductor substrate side, It has, In the aforementioned terminal region, The first semiconductor layer and, A plurality of second semiconductor regions of a second conductivity type are provided in contact with and spaced apart from the surface of the first semiconductor layer, It has, The plurality of second semiconductor regions are arranged in a ring shape so as to surround the first semiconductor region. A semiconductor device characterized in that a third semiconductor region of a first conductivity type is provided at the center of the surface of a predetermined number of second semiconductor regions from the edge of the first semiconductor region.

2. The semiconductor device according to claim 1, characterized in that the third semiconductor region is provided within a range of 1 / 5 to 1 / 2 of the distance from the surface of the first semiconductor layer to the lower surface of the second semiconductor region.

3. The semiconductor device according to claim 1, characterized in that the third semiconductor region is located at a distance of 10% to 25% of the width of the second semiconductor region from the edge of the second semiconductor region.

4. The semiconductor device according to claim 1, characterized in that the width of the third semiconductor region is 50% or more and 80% or less of the width of the second semiconductor region.

5. The semiconductor device according to claim 1, characterized in that the impurity concentration of the third semiconductor region is 1 / 10 to 10 times the impurity concentration of the first semiconductor layer at a predetermined location in the third semiconductor region.

6. The semiconductor device according to claim 5, characterized in that the predetermined position of the third semiconductor region is the center of the depth of the third semiconductor region and the center of the width of the third semiconductor region.

7. The semiconductor device according to claim 5, characterized in that the predetermined position of the third semiconductor region is the center of the depth of the third semiconductor region and is a region 20% inward from both ends of the third semiconductor region when the width of the third semiconductor region is taken as 100%.

8. The semiconductor device according to claim 1, characterized in that the impurity concentration of the third semiconductor region is higher towards the surface of the third semiconductor region than towards the center of the depth of the third semiconductor region.

9. The semiconductor device according to claim 1, characterized in that the third semiconductor region is provided in the second semiconductor region closest to the active region.

10. The semiconductor device according to claim 1, characterized in that the third semiconductor region is provided in the second semiconductor region, which extends at least one-quarter of the way from the active region side.

11. The semiconductor device according to claim 1, characterized in that the third semiconductor region is not provided in the second semiconductor region having a width of 1.5 μm or less.

12. The semiconductor device according to claim 1, characterized in that the second semiconductor region is provided to a depth of 1.0 μm or more and 2.0 μm or less from the surface of the first semiconductor layer.

13. The semiconductor device according to claim 1, characterized in that the second semiconductor region takes the maximum value of the impurity concentration within a range of 1 / 2 to 3 / 4 of the distance from the surface of the first semiconductor layer to the bottom surface of the second semiconductor region.

14. The semiconductor device according to claim 1, characterized in that the second semiconductor region is not electrically connected to the electrodes of the semiconductor device and is at a floating potential.

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