Semiconductor equipment

Abstract

To improve the performance of semiconductor devices. [Solution] The semiconductor substrate SUB has an n-type substrate body SB and an n-type semiconductor layer EP. An LDMOSFET 2 and a trench gate type power MOSFET 1 are formed on the main surface of the semiconductor substrate SUB. A back electrode BE is formed on the back surface of the semiconductor substrate SUB. The LDMOSFET 2 has an n-type drain region DR2, an n-type source region SR2, an n-type drift region ND, a p-type well region PW1, and a p-type well PW2 formed within the n-type semiconductor layer EP. The n-type drift region ND is in contact with the bottom surface of the n-type drain region DR2, the p-type well region PW2 is in contact with the bottom surface of the n-type source region SR2, and the p-type well region PW1 is in contact with the bottom surface of the n-type drift region ND and the bottom surface of the p-type well region PW2. The p-type impurity concentration in the p-type well region PW1 is lower than the p-type impurity concentration in the p-type well region PW2, and also lower than the n-type impurity concentration in the n-type semiconductor layer EP.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and can be suitably used, for example, for a semiconductor device having a transistor as a power switching element.

Background Art

[0002] In some cases, transistors constituting other circuits are also formed together on a semiconductor substrate on which a power switching element is formed.

[0003] Patent Document 1 (Japanese Patent Application Laid-Open No. 2015-23451) discloses a technique related to a semiconductor device including an output MOS transistor and a short-circuit transistor.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] It is desired to improve the performance of a semiconductor device having a power switching element.

[0006] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0007] According to one embodiment, the semiconductor device includes a semiconductor substrate, a first MOSFET and a second MOSFET formed on the main surface of the semiconductor substrate, and a back electrode formed on the back surface of the semiconductor substrate. The semiconductor substrate has a substrate region of a first conductivity type and a semiconductor layer of the first conductivity type formed on the substrate region. The first MOSFET has a gate electrode formed on the semiconductor layer via a gate insulating film, a first source region and a first drain region of the first conductivity type formed within the semiconductor layer, a drift region of the first conductivity type formed within the semiconductor layer, and a first well region and a second well region of the second conductivity type formed within the semiconductor layer. The drift region is in contact with the bottom surface of the first drain region, the first well region is in contact with the bottom surface of the first source region, and the second well region is in contact with the bottom surface of the drift region and the bottom surface of the first well region. The second MOSFET has a trench gate electrode formed in a groove of the semiconductor layer via a second gate insulating film, and a second source region of the first conductivity type formed within the semiconductor layer. The impurity concentration of the second conductivity type in the first well region is higher than the impurity concentration of the second conductivity type in the second well region. The impurity concentration of the second conductivity type in the second well region is lower than the impurity concentration of the first conductivity type in the semiconductor layer. [Effects of the Invention]

[0008] According to one embodiment, the performance of a semiconductor device can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] This is a circuit diagram showing an example of a circuit using a power switching element. [Figure 2] This is a cross-sectional view of the main part of the semiconductor device according to Embodiment 1. [Figure 3] This is a cross-sectional view of the main part of the semiconductor device according to Embodiment 1. [Figure 4] This graph shows the p-type impurity concentration distribution in the p-type well region of the semiconductor device according to Embodiment 1. [Figure 5]This graph shows the p-type impurity concentration distribution in the p-type well region of the semiconductor device according to Embodiment 1. [Figure 6] This graph shows the p-type impurity concentration distribution in the p-type well region of the semiconductor device according to Embodiment 2. [Figure 7] This graph shows the p-type impurity concentration distribution in the p-type well region of the semiconductor device according to Embodiment 2. [Modes for carrying out the invention]

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. Unless otherwise specified, these are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, when referring to the number of elements, etc. (including number, numerical value, quantity, range, etc.) in the following embodiments, unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and may be greater than or less than that number. Moreover, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered essential in principle. Similarly, when referring to the shape, positional relationship, etc. of constituent elements, etc. in the following embodiments, unless otherwise specified or clearly considered not to be so in principle, it shall include those that substantially approximate or resemble that shape, etc. The same applies to the numerical values ​​and ranges mentioned above.

[0011] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0012] Furthermore, in the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to improve readability. Conversely, hatching may be added to plan views to improve readability.

[0013] Furthermore, a planar view refers to viewing the semiconductor substrate (SUB) from a plane approximately parallel to its main or back surface. Also, "bottom surface" and "bottom surface" have the same meaning.

[0014] Furthermore, in this application, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or LDMOSFET (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor) includes not only MOSFETs using an oxide film as the gate insulating film, but also MOSFETs using insulating films other than oxide films as the gate insulating film. In addition, LDMOSFETs are sometimes called HV-MOSFET (High Voltage Metal Oxide Semiconductor Field Effect Transistor) or DEMOSFET (Drain Extended Metal Oxide Semiconductor Field Effect Transistor).

[0015] Furthermore, in this application, the n-type impurity concentration is the effective n-type impurity concentration, and the p-type impurity concentration is the effective p-type impurity concentration. In a semiconductor region containing both n-type and p-type impurities, when the majority carrier is electrons (n-type impurities), the difference between the number of n-type impurities and the number of p-type impurities per unit volume is the effective n-type impurity concentration. In a semiconductor region containing both n-type and p-type impurities, when the majority carrier is holes (p-type impurities), the difference between the number of n-type impurities and the number of p-type impurities per unit volume is the effective p-type impurity concentration.

[0016] (Embodiment 1) <Circuit example> As shown in Fig. 1, a power MOSFET 1 is interposed between a power supply potential VB and a load LD. The power supply potential VB is supplied from a battery or the like. Specifically, the drain of the power MOSFET 1 is connected to the power supply potential VB, and the source of the power MOSFET 1 is connected to the load LD. The load LD is also connected to the ground potential GND. The load LD is interposed between the ground potential GND and the power MOSFET 1.

[0017] Both the power supply potential VB and the ground potential GND are fixed potentials, but the power supply potential VB is higher than the ground potential GND. For example, the ground potential GND is 0 V, and the power supply potential VB is a positive fixed potential.

[0018] The power MOSFET 1 is a transistor that constitutes a power switching element. When the gate voltage of the power MOSFET 1 is lower than the threshold voltage (e.g., 0 V), the power MOSFET 1 is in an off state (non-conducting state), and no current flows through the load LD. When a gate voltage equal to or higher than the threshold voltage is supplied to the gate of the power MOSFET 1, the power MOSFET 1 is in an on state (conducting state). When the power MOSFET 1 is in the on state, current flows through the power MOSFET 1 to the load LD.

[0019] <Regarding the structure of the semiconductor device> The semiconductor device of Embodiment 1 will be described with reference to Figs. 2 and 3. Fig. 3 is a partial cross-sectional view in which a part of Fig. 2 is enlarged. In Fig. 3, the hatching is omitted.

[0020] As shown in Figs. 2 and 3, the semiconductor device of Embodiment 1 includes a semiconductor substrate SUB, a power MOSFET 1, an LDMOSFET 2, a STI region 3, an insulating film IL, and a back surface electrode BE.

[0021] As shown in Figs. 2 and 3, the semiconductor substrate SUB is an n-type semiconductor substrate and has an n-type substrate body (substrate region) SB and an n-type semiconductor layer EP formed on the n-type substrate body SB.

[0022] The n-type substrate body SB is made of n-type single-crystal silicon into which n-type impurities such as phosphorus (P) or arsenic (As) have been introduced. The thickness of the n-type substrate body SB is almost uniform. The n-type semiconductor layer EP is made of n-type single-crystal silicon formed on the n-type substrate body SB. The n-type impurity concentration of the n-type substrate body SB is higher than that of the n-type semiconductor layer EP. The n-type semiconductor layer EP and the n-type substrate body SB are in contact with each other.

[0023] The main surface of the semiconductor substrate SUB is synonymous with the main surface of the n-type semiconductor layer EP. Similarly, the back surface of the semiconductor substrate SUB is synonymous with the back surface of the n-type substrate body SB. The main surface and back surface of the semiconductor substrate SUB are located on opposite sides of each other. A back surface electrode BE is formed on the back surface of the semiconductor substrate SUB. The n-type substrate body SB and the back surface electrode BE are in contact with each other. The thickness direction of the semiconductor substrate corresponds to the direction from one side of the semiconductor substrate SUB (main surface or back surface) to the other, and is approximately perpendicular to either the main surface or the back surface of the semiconductor substrate SUB.

[0024] The STI (Shallow Trench Isolation) region 3 consists of an insulating film embedded in a groove formed within the semiconductor substrate SUB. Instead of the STI region 3, a LOCOS (Local Oxidation of Silicon) region can also be applied.

[0025] The main surface of the semiconductor substrate SUB includes an element region 1A on which a transistor (here, a power MOSFET 1) that functions as a power switching element is formed, and an element region 1B on which an LDMOSFET 2 that constitutes another circuit (e.g., a control circuit) is formed. In a plan view, element region 1A and element region 1B are separated from each other.

[0026] Next, the configuration of the power MOSFET 1 formed within the element region 1A will be described.

[0027] Power MOSFET 1 is a trench gate type MOSFET. Power MOSFET 1 has a trench gate electrode TG, a gate insulating film GF1, an n-type source region SR1, a p-type semiconductor region PR1, a p-type semiconductor region PR2, and a gate wiring region TGL.

[0028] The trench gate electrode TG is formed within a groove TR formed on the main surface of the semiconductor substrate SUB, via a gate insulating film GF1. The groove TR extends from the main surface of the semiconductor substrate SUB toward the back surface of the semiconductor substrate SUB. The bottom surface of the groove TR is deeper than the bottom surface of the p-type semiconductor region PR1. The gate insulating film GF1 is formed on the bottom surface and the sides of the groove TR. The trench gate electrode TG is made of, for example, a polycrystalline silicon film into which n-type impurities have been introduced.

[0029] The n-type source region SR1 and the p-type semiconductor region (p-type body region) PR1 and p-type semiconductor region PR2 are formed within the n-type semiconductor layer EP. The n-type source region SR1 and the p-type semiconductor region PR2 are formed on and in contact with the p-type semiconductor region PR1. The p-type impurity concentration in the p-type semiconductor region PR2 is higher than that in the p-type semiconductor region PR1. The n-type impurity concentration in the n-type source region SR1 is higher than that in the n-type semiconductor layer EP.

[0030] The n-type source region SR1 and the p-type semiconductor region PR1 are in contact with the gate insulating film GF1 formed on the side surface of the groove TR. The n-type source region SR1 is interposed between the p-type semiconductor region PR2 and the groove TR. The n-type source region SR1 is adjacent to the trench gate electrode TG via the gate insulating film GF1. The p-type semiconductor region PR1 is located below the n-type source region SR1 and is also adjacent to the trench gate electrode TG via the gate insulating film GF1. The bottom surface of the n-type source region SR1 is the boundary between the n-type source region SR1 and the p-type semiconductor region PR1. Therefore, a PN junction is formed on the bottom surface of the n-type source region SR1. A part of the n-type semiconductor layer EP (n-type semiconductor region) exists below the bottom surface of the p-type semiconductor region PR1. Therefore, a PN junction is formed on the bottom surface of the p-type semiconductor region PR1.

[0031] The n-type semiconductor layer EP located below the p-type semiconductor region PR1 and the n-type substrate body SB also located below the p-type semiconductor region PR1 function as the n-type drain region of the power MOSFET 1. The channel of the power MOSFET 1 is formed along the groove TR within the p-type semiconductor region PR1. The operating current of the power MOSFET 1 flows between the n-type source region SR1 and the n-type substrate body SB through the channel formed within the p-type semiconductor region PR1 and the n-type semiconductor layer EP. Therefore, the operating current of the power MOSFET 1 flows along the thickness direction of the semiconductor substrate SUB.

[0032] The back electrode BE can function as a drain electrode electrically connected to the drain of the power MOSFET 1. The back electrode BE is formed on the entire back surface of the semiconductor substrate SUB. The power MOSFET 1 may be configured by connecting multiple unit transistor cells in parallel.

[0033] The gate wiring section TGL is integrally formed with the trench gate electrode TG and is electrically connected to the trench gate electrode TG. The trench gate electrode TG is formed within the groove TR. On the other hand, the gate wiring section TGL is located on the semiconductor substrate SUB outside the groove TR. A portion of the gate wiring section TGL is located on the STI region 3.

[0034] The insulating film IL is formed on the main surface of the semiconductor substrate SUB and covers the power MOSFET 1.

[0035] Next, the configuration of the LDMOSFET2 formed within the element region 1B will be described.

[0036] The LDMOSFET2 has a p-type well region PW1, a p-type well region PW2, an n-type drift region ND, an n-type drain region DR2, an n-type source region SR2, a p-type semiconductor region PC, a gate electrode GE, and a gate insulating film GF2.

[0037] The p-type well region (p-type semiconductor region) PW1, the p-type well region (p-type semiconductor region) PW2, the n-type drift region (n-type semiconductor region) ND, the n-type drain region (n-type semiconductor region) DR2, the n-type source region (n-type semiconductor region) SR2, and the p-type semiconductor region (p-type semiconductor region) PC are formed within the n-type semiconductor layer EP. The gate electrode GE is formed on the n-type semiconductor layer EP via a gate insulating film GF2. The insulating film IL is formed on the main surface of the semiconductor substrate SUB and covers the LDMOSFET2.

[0038] The p-type well region PW1 is formed within the upper part of the n-type semiconductor layer EP. A portion of the n-type semiconductor layer EP (the n-type semiconductor region) exists beneath the bottom surface 6 of the p-type well region PW1. Therefore, a PN junction is formed at the bottom surface 6 of the p-type well region PW1.

[0039] The p-type well region PW1 encloses the p-type well region PW2 and the n-type drift region ND. That is, in a plan view, the p-type well region PW2 and the n-type drift region ND are contained within the p-type well region PW1. The bottom surface 7 of the p-type well region PW2 is shallower than the bottom surface 6 of the p-type well region PW1, and the bottom surface 5 of the n-type drift region ND is shallower than the bottom surface 6 of the p-type well region PW1. A part of the p-type well region PW1 exists below the bottom surface 5 of the n-type drift region ND and below the bottom surface 7 of the p-type well region PW2. The bottom surface 7 of the p-type well region PW2 is in contact with the p-type well region PW1, and the bottom surface 5 of the n-type drift region ND is in contact with the p-type well region PW1. The p-type impurity concentration in the p-type well region PW2 is higher than that in the p-type well region PW1. The n-type impurity concentration in the n-type drift region ND is higher than that in the n-type semiconductor layer EP. The bottom surface 5 of the n-type drift region ND is the boundary between the n-type drift region ND and the p-type well region PW1. Therefore, a PN junction is formed at the bottom surface 5 of the n-type drift region ND.

[0040] The p-type well region PW2 surrounds the n-type source region SR2 and the p-type semiconductor region PC. That is, in a plan view, the n-type source region SR2 and the p-type semiconductor region PC are contained within the p-type well region PW2. The bottom surface of the n-type source region SR2 is shallower than the bottom surface 7 of the p-type well region PW2, and the bottom surface of the p-type semiconductor region PC is shallower than the bottom surface 7 of the p-type well region PW2. A portion of the p-type well region PW2 exists below the bottom surface of the n-type source region SR2 and below the bottom surface of the p-type semiconductor region PC. The bottom surfaces of the n-type source region SR2 and the p-type semiconductor region PC are in contact with the p-type well region PW2. The top surfaces of the n-type source region SR2 and the p-type semiconductor region PC reach the main surface of the semiconductor substrate SUB. The n-type impurity concentration in the n-type source region SR2 is higher than the n-type impurity concentration in the n-type drift region ND. The p-type impurity concentration in the p-type semiconductor region PC is higher than that in the p-type well region PW2. The p-type semiconductor region PC can function as a contact area for the p-type well region PW2. The bottom surface of the n-type source region SR2 is the boundary between the n-type source region SR2 and the p-type well region PW2. Therefore, a PN junction is formed on the bottom surface of the n-type source region SR2.

[0041] The n-type drift region ND surrounds the n-type drain region DR2. That is, in a plan view, the n-type drain region DR2 is contained within the n-type drift region ND. The bottom surface of the n-type drain region DR2 is shallower than the bottom surface of the n-type drift region ND. A portion of the n-type drift region ND exists below the bottom surface of the n-type drain region DR2. The bottom surface of the n-type drain region DR2 is in contact with the n-type drift region ND. The top surface of the n-type drain region DR2 reaches the main surface of the semiconductor substrate SUB. The n-type impurity concentration in the n-type drain region DR2 is higher than the n-type impurity concentration in the n-type drift region ND.

[0042] The n-type drift region ND and the p-type well region PW2 are adjacent to each other in the gate length direction of the LDMOSFET2. The gate length direction of the LDMOSFET2 corresponds to the gate length direction of the gate electrode GE, and the gate width direction of the LDMOSFET2 corresponds to the gate width direction of the gate electrode GE.

[0043] The p-type well region PW2 can function as a back gate. The p-type well region PW2 can also function as a punch-through stopper to suppress the extension of the depletion layer from the drain to the source of the LDMOSFET2. The channel of the LDMOSFET2 is formed in the upper part of the p-type well region PW2, which is located between the n-type source region SR2 and the n-type drain region DR2 and below the gate electrode GE. Hereinafter, the region in which the channel of the LDMOSFET2 is formed will be referred to as the channel formation region. The n-type source region SR2 is adjacent to the channel formation region of the LDMOSFET2. The n-type drain region DR2 and the n-type source region SR2 are separated from each other in the gate length direction of the LDMOSFET2.

[0044] In Figures 2 and 3, the p-type semiconductor region PC and the n-type source region SR2 are adjacent to each other in the gate length direction of the LDMOSFET2. In this case, in a plan view, the n-type source region SR2 is positioned between the gate electrode GE and the p-type semiconductor region PC. It is also possible that the p-type semiconductor region PC and the n-type source region SR2 are not adjacent to each other in the gate length direction of the LDMOSFET2, and that the p-type semiconductor region PC and the n-type source region SR2 are arranged alternately in the gate width direction of the LDMOSFET2.

[0045] The gate electrode GE is formed on the main surface of the semiconductor substrate SUB, located between the n-type source region SR2 and the n-type drain region DR2, via a gate insulating film GF2. The gate insulating film GF2 is made of, for example, a silicon oxide film. The gate electrode GE is made of, for example, a single polycrystalline silicon film (doped polysilicon film) or a multilayer film of a polycrystalline silicon film and a metal silicide layer. In a plan view, a portion of the gate electrode GE overlaps with the n-type drift region ND, and another portion of the gate electrode GE overlaps with the p-type well region PW2.

[0046] In a plan view, an STI region 3 is positioned between the channel formation region and the n-type drain region DR2 of the LDMOSFET2, and a portion of the gate electrode GE is located on this STI region 3. Below the STI region 3, which is interposed between the channel formation region and the n-type drain region DR2 of the LDMOSFET2, there is an n-type drift region ND. The bottom surface of the n-type drain region DR2 is in contact with the n-type drift region ND, and the side surface of the n-type drain region DR2 is in contact with the STI region 3. Therefore, the n-type drift region ND below the STI region 3 can also function as a conduction path between the channel and the n-type drain region DR2 of the LDMOSFET2.

[0047] Although Figures 2 and 3 show the case where the gate insulating film GF2 is interposed between the STI region 3 and the gate electrode GE, there may also be cases where the gate insulating film GF2 is not interposed between the STI region 3 and the gate electrode GE. Furthermore, a sidewall spacer (not shown) made of an insulating film may be formed on the side surface of the gate electrode GE.

[0048] A portion of the p-type well region PW2 is located below the gate electrode GE, and a portion of the n-type drift region ND is also located below the gate electrode GE. A PN junction is formed at the boundary between the p-type well region PW2 and the n-type drift region ND. The boundary between the p-type well region PW2 and the n-type drift region ND is located below the gate electrode GE and extends in the gate width direction of the LDMOSFET2.

[0049] In a plan view, the gate electrode GE is positioned between the n-type source region SR2 and the n-type drain region DR2. When a voltage above the threshold voltage is applied to the gate electrode GE, a channel is formed in the upper part of the p-type well region PW2 located below the gate electrode GE. The n-type source region SR2 and the n-type drain region DR2 become conductive to each other through the channel and the n-type drift region ND.

[0050] In the gate length direction of LDMOSFET2, an n-type drift region ND is interposed between the p-type well region PW2 and the n-type drain region DR2. Therefore, an n-type drift region ND exists between the channel formation region and the n-type drain region DR2 of LDMOSFET2. Consequently, in the gate length direction of LDMOSFET2, the channel formation region and the n-type drift region ND exist between the n-type source region SR2 and the n-type drain region DR2, with the channel formation region located between the n-type source region SR2 and the n-type drift region ND.

[0051] Furthermore, metal silicide layers (not shown) may be formed on the n-type drain region DR2, the n-type source region SR2, and the p-type semiconductor region PC, respectively. These metal silicide layers can be formed using salicide (self-aligned silicide) technology.

[0052] Next, we will describe the structure on the semiconductor substrate SUB.

[0053] As shown in Figures 2 and 3, the semiconductor device of Embodiment 1 further comprises a plug (contact plug) PG1, a plug (contact plug) PG2, a plug (contact plug) PGD, a plug (contact plug) PGP, a plug (contact plug) PGS, wiring M1A, wiring M1B, wiring M1D, and wiring M1S.

[0054] The insulating film IL is formed on the main surface of the semiconductor substrate SUB and covers the trench gate electrode TG, the gate wiring portion TGL, and the gate electrode GE. The insulating film IL includes, for example, a silicon nitride film and a silicon oxide film on the silicon nitride film. The upper surface of the insulating film IL is flattened.

[0055] Multiple contact holes (through-holes) are formed within the insulating film IL, and multiple conductive plugs are formed within the multiple contact holes. The multiple plugs include plugs PG1, PG2, PGD, PGP, and PGS. Plugs PG1, PG2, PGD, PGP, and PGS each penetrate the insulating film IL.

[0056] Plug PGD is located on the n-type drain region DR2 and is electrically connected to the n-type drain region DR2. Plug PGS is located on the n-type source region SR2 and is electrically connected to the n-type source region SR2. Plug PGP is located on the p-type semiconductor region PC and is electrically connected to the p-type semiconductor region PC. Therefore, plug PGP is electrically connected to the p-type well region PW2 via the p-type semiconductor region PC.

[0057] Plug PG1 is positioned across the p-type semiconductor region PR2 and the n-type source region SR1, and is electrically connected to both the p-type semiconductor region PR2 and the n-type source region SR1. Plug PG2 is positioned on the gate wiring section TGL and is electrically connected to the gate wiring section TGL.

[0058] Furthermore, a plug is also placed on the gate electrode GE, but the plug on the gate electrode GE is not shown in Figures 2 and 3.

[0059] Multiple wirings are formed on the insulating film IL. These multiple wirings include wiring M1A, wiring M1B, wiring M1D, and wiring M1S.

[0060] Wiring M1A is electrically connected to both the n-type source region SR1 and the p-type semiconductor region PR2 via plug PG1. Therefore, the source potential of power MOSFET 1 is supplied from plug PG1 to the n-type source region SR1 and also supplied from plug PG1 to the p-type semiconductor region PR1 via the p-type semiconductor region PR2. Wiring M1A is connected to the load LD (see Figure 1) via a conductive path outside the semiconductor device.

[0061] The back electrode BE is electrically connected to the n-type substrate body SB, and through the n-type substrate body SB, it is electrically connected to the n-type semiconductor layer EP. Therefore, the drain potential of the power MOSFET 1 is supplied from the back electrode BE to the drain region of the power MOSFET 1 (n-type substrate body SB and n-type semiconductor layer EP). The back electrode BE is connected to the power supply potential VB (see Figure 1) via a conductive path outside the semiconductor device. Therefore, the drain potential of the power MOSFET 1 is the power supply potential VB.

[0062] Wiring M1B is electrically connected to the gate wiring section TGL via plug PG2. The gate potential of power MOSFET 1 is supplied from wiring M1B to the trench gate electrode TG via plug PG2 and the gate wiring section TGL. Wiring M1B is connected to the control circuit within the semiconductor device via wiring within the semiconductor device, etc.

[0063] Wiring M1D is electrically connected to the n-type drain region DR2 via plug PGD. The drain potential of LDMOSFET2 is supplied from wiring M1D to the n-type drain region DR2 via plug PGD. The drain potential of LDMOSFET2 is, for example, the power supply potential VB.

[0064] Wiring M1S is electrically connected to the n-type source region SR2 via plug PGS, and is also electrically connected to the p-type semiconductor region PC via plug PGP. In other words, wiring M1S is electrically connected to both plug PGS located on the n-type source region SR2 and plug PGP located on the p-type semiconductor region PC.

[0065] Therefore, the potential supplied from plug PGS to the n-type source region SR2 (the source potential of LDMOSFET2) and the potential supplied from plug PGP to the p-type semiconductor region PC are the same. Consequently, the source potential of LDMOSFET2 is supplied from plug PGS to the n-type source region SR2 and also supplied from plug PGP to the p-type well region PW2 via the p-type semiconductor region PC. The source potential of LDMOSFET2 is, for example, the ground potential GND.

[0066] Gate wiring, which is electrically connected to the gate electrode GE via a plug, is formed on the insulating film IL, but the gate wiring is not shown in Figures 2 and 3.

[0067] Wires M1A, M1B, M1D, and M1S are not connected to each other and are isolated from one another.

[0068] In Figures 2 and 3, plug PGS and plug PGP are connected to a common wiring M1S. It is also possible to connect plug PGS to wiring M1S and plug PGP to another wiring (not shown) formed on the insulating film IL. In that case, since wiring M1S to which plug PGS is connected and wiring (not shown) to which plug PGP is connected are isolated from each other, the potential supplied from plug PGS to the n-type source region SR2 and the potential supplied from plug PGP to the p-type semiconductor region PC can be controlled independently of each other.

[0069] The diagrams and descriptions of the structures above the insulating film IL, wiring M1A, wiring M1B, wiring M1D, and wiring M1S are omitted.

[0070] <Regarding the background of the consideration> The inventors are investigating a semiconductor device having a power MOSFET 1 and an LDMOSFET 2.

[0071] Power MOSFET 1 is used as a power switching element. Therefore, it is desirable to reduce the on-resistance (resistance when conducting) of power MOSFET 1.

[0072] When power MOSFET1 is turned off, a surge voltage may be superimposed on the drain voltage. Therefore, it is desirable to improve the voltage rating of LDMOSFET2 so that LDMOSFET2 can withstand (be not destroyed by) a voltage higher than the power supply potential VB applied to its drain.

[0073] Therefore, in order to improve the performance of a semiconductor device having a power MOSFET 1 and an LDMOSFET 2, it is desirable to achieve both a reduction in the on-resistance of the power MOSFET 1 and an improvement in the breakdown voltage of the LDMOSFET 2.

[0074] <Main Features and Effects> To reduce the on-resistance of the power MOSFET 1, it is effective to increase the concentration of n-type impurities in the n-type semiconductor layer EP. The operating current (on-current) of the power MOSFET 1 flows between the back electrode BE and the wiring M1A, through the n-type substrate body SB, the n-type semiconductor layer EP, the channel formed in the p-type semiconductor region PR1, the n-type source region SR1, and the plug PG1. Therefore, by increasing the concentration of n-type impurities in the n-type semiconductor layer EP, the electrical resistance of the n-type semiconductor layer EP can be reduced, thereby reducing the on-resistance of the power MOSFET 1.

[0075] In Figure 1, wiring M1A is connected to the load LD located outside the semiconductor device, and the back electrode BE is connected to the power supply potential VB. The power supply potential VB supplied to the back electrode BE is supplied to the n-type semiconductor layer EP via the n-type substrate body SB. The drain potential (power supply potential VB) of LDMOSFET2 is supplied from wiring M1D to the n-type drain region DR2 via plug PGD, and further supplied to the n-type drift region ND via the n-type drain region DR2. The source potential of LDMOSFET2 is supplied to the n-type source region SR2 via plug PGS, and also supplied to the p-type semiconductor region PC via plug PGP, and further supplied to the p-type well region PW1 via the p-type semiconductor region PC and the p-type well region PW2.

[0076] Therefore, a potential difference equivalent to the difference between the drain voltage (power supply potential VB) and the source voltage (ground potential GND) is generated between the p-type well region PW1 and the n-type semiconductor layer EP below the p-type well region PW1. In addition, a potential difference equivalent to the difference between the drain voltage (power supply potential VB) and the source voltage (ground potential GND) of the LDMOSFET2 is generated between the n-type drift region ND and the p-type well region PW1.

[0077] Therefore, when a surge voltage is superimposed on the drain voltage (power supply potential VB) of LDMOSFET2 during the turn-off of power MOSFET1, the breakdown voltage of LDMOSFET2 is largely determined by the breakdown voltage of the PN junction formed at the bottom surface 5 of the n-type drift region ND (the boundary between the n-type drift region ND and the p-type well region PW1) and the breakdown voltage of the PN junction formed at the bottom surface 6 of the p-type well region PW1 (the boundary between the p-type well region PW1 and the n-type semiconductor layer EP). Increasing the n-type impurity concentration of the n-type semiconductor layer EP acts to decrease the breakdown voltage of the PN junction formed at the bottom surface 6 of the p-type well region PW1.

[0078] Here, the bottom surface 6 of the p-type well region PW1 has a bottom surface 6a located below the n-type drift region ND and a bottom surface 6b located below the p-type well region PW2.

[0079] Therefore, in Embodiment 1, the p-type impurity concentration in the p-type well region PW1 is reduced. That is, the n-type impurity concentration in the n-type semiconductor layer EP is increased, and the p-type impurity concentration in the p-type well region PW1 is reduced.

[0080] By lowering the p-type impurity concentration in the p-type well region PW1, the depletion layer tends to spread more easily within the p-type well region PW1 downwards from the bottom surface 5 of the n-type drift region ND, and also tends to spread more easily within the p-type well region PW1 upwards from the bottom surface 6 of the p-type well region PW1. As a result, the depletion layer spreading downwards from the bottom surface 5 of the n-type drift region ND and the depletion layer spreading upwards from the bottom surface 6 of the p-type well region PW1 connect, allowing almost the entire p-type well region PW1 below the n-type drift region ND to be depleted. This prevents failure at the PN junction formed on the bottom surface 5 of the n-type drift region ND, and also prevents failure at the PN junction formed on the bottom surface 6a of the p-type well region PW1, when a surge voltage is superimposed on the drain voltage (power supply potential VB) of the LDMOSFET2.

[0081] As a result, when a surge voltage is superimposed on the drain voltage (power supply potential VB) of LDMOSFET2, the breakdown voltage of LDMOSFET2 is not determined by the breakdown voltage of the PN junction formed on the bottom surface 5 of the n-type drift region ND, nor by the breakdown voltage of the PN junction formed on the bottom surface 6a of the p-type well region PW1, but is almost entirely determined by the breakdown voltage of the PN junction formed on the bottom surface 6b of the p-type well region PW1. Since the n-type impurity concentration in the n-type drift region ND is higher than the n-type impurity concentration in the n-type semiconductor layer EP, the breakdown voltage of the PN junction formed on the bottom surface 6b of the p-type well region PW1 is higher than the breakdown voltage of the PN junction formed on the bottom surface 5 of the n-type drift region ND. Therefore, the breakdown voltage of LDMOSFET2 is not affected by the breakdown voltage of the PN junction formed on the bottom surface 5 of the n-type drift region ND, nor by the breakdown voltage of the PN junction formed on the bottom surface 6a of the p-type well region PW1, but is determined by the breakdown voltage of the PN junction formed on the bottom surface 6b of the p-type well region PW1. As a result, the breakdown voltage of LDMOSFET2 can be improved.

[0082] Therefore, the technical concept of Embodiment 1 is to increase the n-type impurity concentration in the n-type semiconductor layer EP and decrease the p-type impurity concentration in the p-type well region PW1. For this reason, in Embodiment 1, the p-type impurity concentration in the p-type well region PW1 is lower than that of the n-type impurity concentration in the n-type semiconductor layer EP. More specifically, the p-type impurity concentration in the p-type well region PW1 is lower than that of the n-type impurity concentration in the n-type semiconductor layer EP below the p-type well region PW1. This makes it possible to achieve both a reduction in the on-resistance of the power MOSFET 1 and an improvement in the breakdown voltage of the LDMOSFET 2. Consequently, the performance of the semiconductor device can be improved.

[0083] To effectively reduce the on-resistance of power MOSFET 1, the n-type impurity concentration of the n-type semiconductor layer EP is set to 1.0E16 / cm³. 3 The above, and 1.0E17 / cm 3 The following is preferable: In order to accurately obtain the effect of improving the breakdown voltage of LDMOSFET2, the p-type impurity concentration in the p-type well region PW1 is 1.0E16 / cm³. 3 The above, and 1.0E17 / cm 3 The following is preferable:

[0084] It is preferable to set the p-type impurity concentration in the p-type well region PW1 such that the entire p-type well region PW1 is depleted below the n-type drift region ND.

[0085] (Embodiment 2) Figures 4 and 5 are graphs showing the p-type impurity concentration distribution within the p-type well region PW1 in the semiconductor device of Embodiment 1, and Figures 6 and 7 are graphs showing the p-type impurity concentration distribution within the p-type well region PW1 in the semiconductor device of Embodiment 2. The vertical axis of each graph represents the p-type impurity concentration, and the horizontal axis of each graph represents the depth position.

[0086] Figures 4 and 6 show the p-type impurity concentration distribution within the p-type well region PW1 below the n-type drain region DR2. Specifically, Figures 4 and 6 show the p-type impurity concentration distribution within the p-type well region PW1 at a position along the dotted line L1 shown in Figure 3. Figures 5 and 7 show the p-type impurity concentration distribution within the p-type well region PW1 below the side surface 8 of the n-type drift region ND. Specifically, Figures 5 and 7 show the p-type impurity concentration distribution at a position along the dotted line L2 shown in Figure 3. The side surface (end) 8 of the n-type drift region ND overlaps with the gate electrode GE2 in a plan view and is in contact with the channel of the LDMOSFET2.

[0087] The difference between the semiconductor device of Embodiment 1 and the semiconductor device of Embodiment 2 lies in the distribution of p-type impurity concentrations within the p-type well region PW1.

[0088] In Embodiment 1, as shown in Figure 4, below the n-type drain region DR2, the p-type impurity concentration in the p-type well region PW1 is almost constant regardless of the depth within the p-type well region PW1. Furthermore, in Embodiment 1, as shown in Figure 5, below the side surface 8 of the n-type drift region ND, the p-type impurity concentration in the p-type well region PW1 gradually decreases with increasing depth (gradually decreasing towards the bottom surface 6). For this reason, in Embodiment 1, the trend of the p-type impurity concentration distribution in the p-type well region PW1 below the side surface 8 of the n-type drift region ND differs from the trend of the p-type impurity concentration distribution in the p-type well region PW1 below the n-type drain region DR2. Consequently, when the depletion layer expands downward from the bottom surface 5 of the n-type drift region ND, the expansion of the depletion layer tends to differ between below the n-type drain region DR2 and below the side surface 8 of the n-type drift region ND.

[0089] In contrast, in Embodiment 2, as shown in Figure 6, below the n-type drain region DR2, the p-type impurity concentration in the p-type well region PW1 gradually decreases with increasing depth (gradually decreasing towards the bottom surface 6). Furthermore, in Embodiment 2, as shown in Figure 7, below the side surface 8 of the n-type drift region ND, the p-type impurity concentration in the p-type well region PW1 gradually decreases with increasing depth (gradually decreasing towards the bottom surface 6). Therefore, in Embodiment 2, the trend of the p-type impurity concentration distribution in the p-type well region PW1 below the side surface 8 of the n-type drift region ND is the same as the trend of the p-type impurity concentration distribution in the p-type well region PW1 below the n-type drain region DR2. As a result, when the depletion layer expands downward from the bottom surface 5 of the n-type drift region ND, the expansion of the depletion layer below the n-type drain region DR2 and below the side surface 8 of the n-type drift region ND are almost the same. As a result, the depletion layer can spread evenly downward from the bottom surface 5 of the n-type drift region ND, making it easier to deplete the entire p-type well region PW1 below the n-type drift region ND. This effectively prevents failure at the PN junction formed on the bottom surface 5 of the n-type drift region ND when a surge voltage is superimposed on the drain voltage (power supply potential VB) of the LDMOSFET2, and also effectively prevents failure at the PN junction formed on the bottom surface 6a of the p-type well region PW1. Therefore, the breakdown voltage of the LDMOSFET2 can be further improved.

[0090] The present invention has been described in detail above based on its embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0091] 1 Power MOSFET 2 LDMOSFET 3 STI area 5,6,6a,6b,7 Bottom 8 Sides BE back electrode EP n-type semiconductor layer DR2 n-type drain region GF1, GF2 gate insulating film IL insulating film LD load M1A, M1B, M1D, M1S wiring ND n-type drift region PC p-type semiconductor area PG1, PG2, PGD, PGP, PGS plugs PR1,PR2 p-type semiconductor region PW1, PW2 p-type well region SB n-type circuit board main unit SR1, SR2 n-type source region SUB Semiconductor Substrate TG Trench Gridgate TGL gate wiring section TR groove VB power supply potential

Claims

1. A semiconductor substrate having a main surface and a back surface opposite to the main surface, A first MOSFET formed on the main surface of the semiconductor substrate, A second MOSFET formed on the main surface of the semiconductor substrate, A back electrode formed on the back surface of the semiconductor substrate, Includes, The aforementioned semiconductor substrate is First conductivity type substrate region, The first conductivity type semiconductor layer formed on the substrate region, It has, The first MOSFET is, A gate electrode formed on the semiconductor layer via a gate insulating film, A first source region of the first conductivity type formed within the semiconductor layer, The first drain region of the first conductivity type formed within the semiconductor layer, A drift region of the first conductivity type formed within the semiconductor layer and in contact with the bottom surface of the first drain region, A first well region of a second conductivity type opposite to the first conductivity type is formed within the semiconductor layer and is in contact with the bottom surface of the first source region, A second well region of the second conductivity type is formed within the semiconductor layer and is in contact with the bottom surface of the drift region and the bottom surface of the first well region, It has, The second MOSFET is, A trench gate electrode formed in the groove of the semiconductor layer via a second gate insulating film, A second source region of the first conductivity type is formed within the semiconductor layer and is adjacent to the trench gate electrode via the second gate insulating film, A first semiconductor region of the second conductivity type is formed within the semiconductor layer, located below the second source region, and adjacent to the trench gate electrode via the second gate insulating film, It has, The bottom surface of the drift region is shallower than the bottom surface of the second well region. The bottom surface of the first well region is shallower than the bottom surface of the second well region. The bottom surface of the first drain region is shallower than the bottom surface of the drift region. The bottom surface of the first source region is shallower than the bottom surface of the first well region. The impurity concentration of the first conductivity type in the first source region is higher than the impurity concentration of the first conductivity type in the drift region. The impurity concentration of the second conductivity type in the first well region is higher than the impurity concentration of the second conductivity type in the second well region. A semiconductor device wherein the impurity concentration of the second conductivity type in the second well region is lower than the impurity concentration of the first conductivity type in the semiconductor layer.

2. In the semiconductor device described in claim 1, A semiconductor device wherein the semiconductor layer located below the first semiconductor region and the substrate region located below the first semiconductor region function as the second drain region of the second MOSFET.

3. In the semiconductor device described in claim 1, The first MOSFET further comprises a second semiconductor region of the second conductivity type formed within the semiconductor layer, The impurity concentration of the second conductivity type in the second semiconductor region is higher than the impurity concentration of the second conductivity type in the first well region. The first well region is a semiconductor device in contact with the bottom surface of the first source region and the bottom surface of the second semiconductor region.

4. In the semiconductor device according to claim 3, An insulating film formed on the main surface of the semiconductor substrate and covering the gate electrode, A first contact plug that penetrates the insulating film and is electrically connected to the first drain region, A second contact plug penetrates the insulating film and is electrically connected to the first source region, A third contact plug that penetrates the insulating film and is electrically connected to the second semiconductor region, A semiconductor device, further including the following.

5. In the semiconductor device according to claim 4, A first fixed potential is supplied from the first contact plug to the first drain region. A second fixed potential, different from the first fixed potential, is supplied from the second contact plug to the first source region. The second fixed potential is supplied from the third contact plug to the second semiconductor region. A semiconductor device in which the first fixed potential is supplied from the back electrode to the substrate region.

6. In the semiconductor device according to claim 5, The first conductivity type is n-type, The second conductivity type is p-type, A semiconductor device in which the first fixed potential is higher than the second fixed potential.

7. In the semiconductor device according to claim 6, The second MOSFET is a power switching element, which is a semiconductor device.

8. In the semiconductor device described in claim 1, In a plan view, a portion of the gate electrode overlaps with the drift region. A semiconductor device in which, in a plan view, the other part of the gate electrode overlaps with the first well region.

9. In the semiconductor device described in claim 1, A semiconductor device wherein the impurity concentration of the first conductivity type in the drift region is higher than the impurity concentration of the first conductivity type in the semiconductor layer.

10. In the semiconductor device described in claim 1, Below the first drain region, the impurity concentration of the second conductivity type in the second well region gradually decreases toward the bottom surface of the second well region. Below the side surface of the drift region, the impurity concentration of the second conductivity type in the second well region gradually decreases toward the bottom surface of the second well region. The side surface of the drift region overlaps with the gate electrode in a plan view, wherein the semiconductor device is a semiconductor device.

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