Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can improve the lifespan of an element while reducing current collapse. [Solution] The semiconductor device comprises a compound semiconductor layer provided on a substrate, a first insulating film disposed on the compound semiconductor layer, a first gate electrode disposed on the first insulating film, a second gate electrode disposed above the first gate electrode, a second insulating film disposed between the first gate electrode and the second gate electrode, and a third insulating film disposed around the first gate electrode, the second gate electrode, and the second insulating film, having a higher dielectric constant than the first and second insulating films.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] Electronic devices using nitride semiconductors are used in switching devices such as high-speed electronic devices and power devices.

[0003] Switching devices require high voltage resistance and low on-resistance. While there is a trade-off relationship between voltage resistance and on-resistance determined by the device material, using wide-bandgap semiconductors such as nitride semiconductors and silicon carbide (SiC) as device materials can improve this trade-off relationship compared to silicon, enabling higher voltage resistance and lower on-resistance. Furthermore, devices using nitride semiconductors such as GaN and AlGaN have excellent material properties, enabling the realization of high-performance switching devices. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2013-8836 [Overview of the project] [Problems that the invention aims to solve]

[0005] The embodiment provides a semiconductor device that can improve device lifetime while reducing current collapse, which increases on-resistance. [Means for solving the problem]

[0006] The semiconductor device according to the embodiment comprises a compound semiconductor layer provided on a substrate, a first insulating film disposed on the compound semiconductor layer, a first gate electrode disposed on the first insulating film, a second gate electrode disposed above the first gate electrode, a second insulating film disposed between the first gate electrode and the second gate electrode, and a third insulating film disposed around the first gate electrode, the second gate electrode, and the second insulating film, having a higher dielectric constant than the first insulating film and the second insulating film. [Brief explanation of the drawing]

[0007] [Figure 1] This is a cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2] This is a schematic cross-sectional view illustrating the effects of a semiconductor device. [Figure 3] This is a cross-sectional view showing a method for manufacturing a semiconductor device. [Figure 4] This is a cross-sectional view showing a method for manufacturing a semiconductor device. [Figure 5] This is a cross-sectional view of a semiconductor device according to a modified example of the first embodiment. [Figure 6] This is a cross-sectional view of a semiconductor device according to the second embodiment. [Figure 7] This is a cross-sectional view of a semiconductor device according to a modified example of the second embodiment. [Modes for carrying out the invention]

[0008] Embodiments will be described below with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions and proportions of each drawing are not necessarily the same as those of reality. The following embodiments are illustrative examples of devices and methods for realizing the technical concept of the present invention, and the technical concept of the present invention is not defined by the shape, structure, arrangement of the components, etc. In the following description, elements having the same function and configuration will be denoted by the same reference numerals, and redundant explanations will be given only when necessary. In this disclosure, "lamination" includes not only cases where layers are stacked in contact with each other, but also cases where other layers are inserted between them.

[0009] <1. First Embodiment> (1.1. Semiconductor device 1) Figure 1(a) is a cross-sectional view of the semiconductor device 1 according to this embodiment. Figure 1(b) is an enlarged cross-sectional view of portion D1 in Figure 1(a). The semiconductor device 1 according to this embodiment is composed of a heterojunction field effect transistor (HFET) or a high electron mobility transistor (HEMT). The semiconductor device 1 comprises a channel layer 13, a barrier layer 14, and various electrodes sequentially stacked on a substrate 10.

[0010] The substrate 10 is composed of, for example, a silicon (Si) substrate with the (111) plane as its main surface. The substrate 10 may also be made of sapphire (Al2O3), silicon carbide (SiC), gallium phosphide (GaP), indium phosphide (InP), or gallium arsenide (GaAs). Furthermore, the substrate 10 may include an insulating layer. For example, an SOI (Silicon On Insulator) substrate can be used as the substrate 10. The substrate 10 is not limited to those listed above, as it is a single-crystal substrate on which an epitaxial layer can be grown.

[0011] The channel layer 13 is the layer in which the transistor's channel (current path) is formed. X Al Y Ga (1-x-y) It is composed of N(0≦X<1, 0≦Y<1, 0≦X+Y<1). The channel layer 13 is preferably composed of a nitride semiconductor layer with good crystallinity (high quality). In this embodiment, the channel layer 13 is composed of GaN.

[0012] The barrier layer 14 forms a heterojunction with the channel layer 13. The barrier layer 14 is composed of a nitride semiconductor layer with a band gap larger than that of the channel layer 13. The barrier layer 14 is made of In X Al Y Ga(1-x-y) It is composed of N(0≦X<1, 0≦Y<1, 0≦X+Y<1). In this embodiment, the barrier layer 14 is composed of undoped AlGaN. Note that undoped means that impurities are not intentionally doped. For example, the amount of impurities that enter during the manufacturing process, etc. is included in undoped.

[0013] In the heterojunction structure of the channel layer 13 and the barrier layer 14, since the lattice constant of the barrier layer 14 is smaller than that of the channel layer 13, strain occurs in the barrier layer 14. Due to the piezoelectric effect caused by this strain, piezoelectric polarization occurs in the barrier layer 14, and a two-dimensional electron gas (2DEG: two-dimensional electron gas) is generated near the interface between the channel layer 13 and the barrier layer 14. This two-dimensional electron gas becomes the channel between the source electrode 15 and the drain electrode 16.

[0014] The source electrode 15 and the drain electrode 16 are provided spaced apart from each other on the barrier layer 14. The source electrode 15 and the 2DEG are in ohmic contact through the barrier layer 14. Similarly, the drain electrode 16 and the 2DEG are in ohmic contact through the barrier layer 14. That is, each of the source electrode 15 and the drain electrode 16 is configured to include a material that is in ohmic contact with the 2DEG. As the source electrode 15 and the drain electrode 16, titanium (Ti), or a stacked structure of Al (aluminum) / Ti, etc. is used. " / " represents that the right side is the lower layer and the left side is the upper layer.

[0015] A first insulating film 20 is provided on the barrier layer 14. As an example of the material of the first insulating film 20, silicon oxide such as SiO2 is used.

[0016] On the first insulating film 20 and between the source electrode 15 and the drain electrode 16, a gate electrode 17 (first gate electrode) is provided. In order to improve the breakdown voltage between the gate and the drain, the distance between the gate electrode 17 and the drain electrode 16 is set longer than the distance between the gate electrode 17 and the source electrode 15. The gate electrode 17 and the barrier layer 14 are in Schottky contact. That is, the gate electrode 17 is configured to include a material that forms a Schottky contact with the barrier layer 14. The semiconductor device 1 shown in FIG. 1 is a Schottky barrier type HEMT. As the gate electrode 17, nickel (Ni), or a stacked structure of Au / Ni, etc. is used.

[0017] Due to the Schottky barrier formed by the junction between the gate electrode 17 and the barrier layer 14, the control of the drain current becomes possible. Also, since the mobility of the carriers flowing in the two-dimensional electron gas is fast, the semiconductor device 1 can perform a very fast switching operation.

[0018] Note that the semiconductor device 1 is not limited to a Schottky barrier type HEMT, and may be a MIS (Metal Insulator Semiconductor) type HEMT in which a gate insulating film is interposed between the barrier layer 14 and the gate electrode 17. Also, a junction gate structure may be applied to the HEMT. The junction gate structure is configured by providing a p-type nitride semiconductor layer (for example, a GaN layer) on the barrier layer 14 and providing the gate electrode 17 on this p-type nitride semiconductor layer.

[0019] Above the gate electrode 17, a gate field plate electrode 21 (second gate electrode) is disposed. The gate electrode 17 and the gate field plate electrode 21 are connected via a contact portion 17a. The gate field plate electrode 21 protrudes in the direction of the source electrode 15 and the drain electrode 16 from the connection portion with the contact portion 17a.

[0020] Above the source electrode 15, a source field plate electrode 24 is provided. The source field plate electrode 24 protrudes from above the source electrode 15 toward the drain electrode 16.

[0021] A drain field plate electrode 25 is provided above the drain electrode 16. The drain field plate electrode 25 protrudes from above the drain electrode 16 toward the source electrode 15.

[0022] A second insulating film 22 is placed between the gate electrode 17 and the gate field plate electrode 21. For example, as shown in Figure 1(b), the second insulating film 22 is placed directly beneath the gate field plate electrode 21. More specifically, the side surface of the second insulating film 22 may be flush with the side surface of the gate field plate electrode 21. A silicon oxide such as SiO2 is used as the material for the second insulating film 22.

[0023] A third insulating film 23 is disposed on the first insulating film 20, surrounding the gate electrode 17, the gate field plate electrode 21, and the second insulating film 22. The third insulating film 23 has a higher relative permittivity than the first insulating film 20 and the second insulating film 22. Silicon nitride such as SiN is used as the material for the third insulating film 23.

[0024] An insulating layer 28 is provided on the drain electrode 16, the source electrode 15, and the third insulating film 23. SiO2 or the like is used as the material for the insulating layer 28.

[0025] A protective layer 27 is provided on top of the insulating layer 28. The protective layer 27 is also called a passivation layer. The protective layer 27 is composed of an insulator, such as SiN or SiO2.

[0026] Referring to Figure 2, the effects of the semiconductor device 1 will be explained. In the semiconductor device 1, as shown in Figure 2, when some of the holes H generated in the barrier layer 14 below the first insulating film 20 flow out into the region R1 of the gate electrode 17, the third insulating film 23 has a higher relative permittivity than the first insulating film 20, so electric field lines are drawn out to the third insulating film 23 side, and more holes H flow out to the side of the gate electrode 17. Similarly, when some of the holes H generated in the barrier layer 14 flow out into the region R2 of the gate field plate electrode 21, the third insulating film 23 has a higher relative permittivity than the second insulating film 22, so electric field lines are drawn out to the third insulating film 23 side, and more holes H flow out to the side of the gate field plate electrode 21.

[0027] Thus, the semiconductor device 1 includes a gate electrode 17, a gate field plate electrode 21, and a second insulating film 22, and is equipped with a third insulating film 23 having a higher relative permittivity than the first insulating film 20 and the second insulating film 22. By drawing electric field lines to the third insulating film 23, which is a high-dielectric-constant material, the electric field at the electrode ends can be relaxed, current collapse can be suppressed, and ultimately, the device lifespan can be improved.

[0028] (1.2. Manufacturing method) Figures 3(a) to 3(d) and 4(a) to 4(d) are cross-sectional views showing a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device 1 will be explained with reference to Figures 3 and 4. Note that the substrate 10 is not shown in Figures 3 and 4.

[0029] As shown in Figure 3(a), a silicon oxide film 30 (e.g., SiO2) is deposited on a wafer that will become the barrier layer 14 placed on a substrate, for example, by CVD (Chemical Vapor Deposition). Next, as shown in Figure 3(b), a metal layer 31 (e.g., Al) is formed on the upper surface of the silicon oxide film 30 by sputtering.

[0030] Next, as shown in Figure 3(c), a resist 32 is applied to the metal layer 31 and a pattern is formed on the metal layer 31 by RIE (Reactive Ion Etching). Then, as shown in Figure 3(d), a silicon nitride film 33 (e.g., SiN) is deposited, for example, by CVD.

[0031] Next, as shown in Figure 4(a), a silicon oxide film 34 (e.g., SiO2) is formed on the upper surfaces of the metal layer 31 and the silicon nitride film 33, for example by CVD. Then, as shown in Figure 4(b), a metal layer 35 (e.g., Al) is formed on the upper surface of the silicon oxide film 34 by sputtering.

[0032] Next, as shown in Figure 4(c), a resist 36 is applied to the metal layer 35 and RIE is performed to form a pattern on the metal layer 35 and the silicon oxide film 34. Then, as shown in Figure 4(d), a silicon nitride film (e.g., SiN) is deposited around the silicon oxide film 34 and the metal layer 35, for example by CVD. As a result, the metal layer 31 becomes the gate electrode 17, the silicon oxide film 30 becomes the first insulating film 20, the silicon oxide film 34 becomes the second insulating film 22, the metal layer 35 becomes the gate field plate electrode 21, and a third insulating film 23 is formed around the gate field plate electrode 21 and the second insulating film 22.

[0033] (1.3. Variant) Figures 5(a) and 5(b) are cross-sectional views of a modified semiconductor device according to the first embodiment. A modified example of the semiconductor device 1 according to the first embodiment will be described with reference to Figure 5. As an example, as shown in Figure 5(a), in the modified semiconductor device 1, the side surface of the second insulating film 22 may not be flush with the side surface of the gate field plate electrode 21. More specifically, the second insulating film 22 may be located directly above the first insulating film 20 so as to be connected to the source electrode 15 and the drain electrode 16, respectively.

[0034] As another example, as shown in Figure 5(b), the second insulating film 22 may be positioned only in a portion of the region between the gate electrode 17 and the gate field plate electrode 21. More specifically, the second insulating film 22 may be positioned only on the gate field plate electrode 21 side of the region between the gate electrode 17 and the gate field plate electrode 21.

[0035] As another example, as shown in Figure 5(c), the side surface of the second insulating film 22 may not be flush with the side surface of the gate field plate electrode 21, and may be positioned only in a portion of the region between the gate electrode 17 and the gate field plate electrode 21. More specifically, the second insulating film 22 may be positioned directly above the first insulating film 20 so as to connect to the source electrode 15 and the drain electrode 16, respectively, and may be positioned only on the gate field plate electrode 21 side in the region between the gate electrode 17 and the gate field plate electrode 21.

[0036] In the semiconductor device 1 according to this modified example, as in the first embodiment, electric field lines can be drawn to the third insulating film 23, which is a high dielectric constant material, thereby mitigating the electric field at the electrode end and suppressing current collapse, and ultimately improving the device lifespan.

[0037] <2. Second Embodiment> (2.1. Semiconductor Devices 2) Figure 6(a) is a cross-sectional view of the semiconductor device according to the second embodiment. Figure 6(b) is an enlarged cross-sectional view of portion D2 in Figure 6(a). The semiconductor device 2 according to the second embodiment will be described with reference to Figure 6. In the semiconductor device 2, the shape of the second insulating film 22 differs from that of the first embodiment. The differences will be described below.

[0038] As shown in Figure 6, in the semiconductor device 2, the second insulating film 22 is positioned between the gate electrode 17 and the gate field plate electrode 21, and around the gate field plate electrode 21. As shown in Figure 6(b), the second insulating film 22 is positioned so that its outer edge aligns with the outer edge of the gate field plate electrode 21. This configuration allows for the effects of the first embodiment described above to be obtained. Furthermore, since the second insulating film 22 containing SiO2 has a higher band offset than the third insulating film 23 containing SiN, electron injection into the gate field plate electrode 21 is further hindered, and the increase in on-resistance can be further suppressed.

[0039] (2.2. Variant) Figures 7(a) to 7(c) are cross-sectional views of a modified semiconductor device according to the second embodiment. A modified example of the semiconductor device 2 according to the second embodiment will be described with reference to Figure 7. As an example, as shown in Figure 7(a), in the modified semiconductor device 2, the outer edge of the second insulating film 22 may not be aligned with the outer edge of the gate field plate electrode 21. More specifically, the second insulating film 22 may be located directly above the first insulating film 20 so as to be connected to the source electrode 15 and the drain electrode 16, respectively.

[0040] As another example, as shown in Figure 7(b), a first insulating film 20 may be arranged around the gate electrode 17, and a second insulating film 22 may be arranged around the gate field plate electrode 21. More specifically, the second insulating film 22 may be arranged so that its outer edge is aligned with the outer edge of the gate field plate electrode 21, and a gap may be provided between the first insulating film 20 and the second insulating film 22.

[0041] As another example, as shown in FIG. 7(c), a first insulating film 20 is disposed around the gate electrode 17, a second insulating film 22 is disposed around the gate field plate electrode 21, and the outer edge of the second insulating film 22 may not follow the outer edge of the gate field plate electrode 21. More specifically, a gap may be provided between the first insulating film 20 and the second insulating film 22, and the second insulating film 22 may be located directly above the first insulating film 20 so as to be connected to the source electrode 15 and the drain electrode 16, respectively.

[0042] Even in the semiconductor device 2 according to such a modified example, similarly to the first embodiment, the electric lines of force can be drawn out to the side of the third insulating film 23 which is a high dielectric constant material, the electric field at the electrode end can be relaxed, and current collapse can be suppressed. As a result, improvement of the element lifetime can be realized.

[0043] <3. Other Embodiments> As described above, the semiconductor device 1 according to the present embodiment has been described. However, the application of the technical idea of the present disclosure is not limited to the above embodiment. For example, in the above embodiment, the first insulating film 20 and the second insulating film 22 contain SiO2, and the third insulating film 23 contains SiN. However, the technical idea of the present disclosure may be realized using other materials.

[0044] Note that the present embodiment constitutes a semiconductor device using a nitride semiconductor. However, the present invention is not limited to this, and it is also applicable to compound semiconductors other than nitride semiconductors.

[0045] In addition, in this specification, the "nitride semiconductor" refers to In x Al y Ga (1-x-y) It shall include semiconductors of all compositions in which the composition ratios x and y are changed within their respective ranges in the chemical formula N(0≦x≦1, 0≦y≦1, 0≦x + y≦1). Further, in the above chemical formula, those further including group V elements other than N (nitrogen), those further including various elements added to control various physical properties such as conductivity type, and those further including various elements contained unintentionally shall also be included in the "nitride semiconductor".

[0046] This disclosure may include the following features: (Note 1) A compound semiconductor layer provided on a substrate, A first insulating film disposed on the compound semiconductor layer, A first gate electrode disposed on the first insulating film, A second gate electrode positioned above the first gate electrode, A second insulating film is disposed between the first gate electrode and the second gate electrode, A semiconductor device comprising a first gate electrode, a second gate electrode, and a second insulating film, the third insulating film being disposed around the first insulating film and the second insulating film, and having a higher relative permittivity than the first insulating film and the second insulating film. (Note 2) The semiconductor device according to Appendix 1, wherein the side surface of the second insulating film is flush with the side surface of the second gate electrode. (Note 3) A compound semiconductor layer provided on a substrate, A first insulating film disposed on the compound semiconductor layer, A first gate electrode disposed on the first insulating film, A second gate electrode positioned above the first gate electrode, A second insulating film is disposed between the first gate electrode and the second gate electrode, and around the second gate electrode. A semiconductor device comprising a first gate electrode and a second insulating film, and a third insulating film disposed around them, having a higher relative permittivity than the first insulating film and the second insulating film. (Note 4) The semiconductor device according to Appendix 3, wherein the second insulating film is arranged such that its outer edge aligns with the outer edge of the second gate electrode. (Note 5) A semiconductor device according to any one of appendices 1 to 4, wherein the first insulating film and the second insulating film contain SiO2, and the third insulating film contains SiN.

[0047] While several embodiments of this disclosure have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of Symbols]

[0048] 1, 2: Semiconductor device, 10: Substrate, 13: Channel layer, 14: Barrier layer, 15: Source electrode, 16: Drain electrode, 17: Gate electrode, 17a: Contact area, 20: First insulating film, 21: Gate field plate electrode, 22: Second insulating film, 23: Third insulating film, 24: Source field plate electrode, 25: Drain field plate electrode, 27: Protective layer, 28: Insulating layer, 30: Silicon oxide film, 31: Metal layer, 32: Resist, 33: Silicon nitride film, 34: Silicon oxide film, 35: Metal layer, 36: Resist

Claims

1. A compound semiconductor layer provided on a substrate, A first insulating film disposed on the compound semiconductor layer, A first gate electrode disposed on the first insulating film, A second gate electrode positioned above the first gate electrode, A second insulating film disposed between the first gate electrode and the second gate electrode, A semiconductor device comprising a first gate electrode, a second gate electrode, and a second insulating film, the third insulating film being disposed around the first insulating film and the second insulating film, and having a higher relative permittivity than the first insulating film and the second insulating film.

2. The semiconductor device according to claim 1, wherein the side surface of the second insulating film is flush with the side surface of the second gate electrode.

3. A compound semiconductor layer provided on a substrate, A first insulating film disposed on the compound semiconductor layer, A first gate electrode disposed on the first insulating film, A second gate electrode positioned above the first gate electrode, A second insulating film is disposed between the first gate electrode and the second gate electrode, and around the second gate electrode. A semiconductor device comprising a first gate electrode and a second insulating film, and a third insulating film disposed around them, having a higher relative permittivity than the first insulating film and the second insulating film.

4. The semiconductor device according to claim 3, wherein the second insulating film is arranged such that its outer edge aligns with the outer edge of the second gate electrode.

5. The first insulating film and the second insulating film are SiO ２ A semiconductor device according to any one of claims 1 to 4, wherein the third insulating film comprises SiN.

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