Wiring board

Abstract

Providing high-quality wiring boards. [Solution] The wiring board of the embodiment has a first resin insulating layer having a first surface, a second surface, and a cavity extending from the first surface to the second surface; a second resin insulating layer having a third surface and a fourth surface, formed on the first resin insulating layer such that the fourth surface faces the first surface; a component having an electrode facing the fourth surface and housed within the cavity; and a third resin insulating layer having a fifth surface and a sixth surface, formed on the first resin insulating layer such that the fifth surface faces the second surface. The cavity has an opening on the first surface side and an opening on the second surface side. The second resin insulating layer closes the opening on the first surface side, and the third resin insulating layer closes the opening on the second surface side. The second resin insulating layer is closer to the mounting surface for mounting electronic components than the third resin insulating layer. A portion of the third resin insulating layer fills the gap between the inner wall of the cavity and the component. The cross-sectional shape of the cavity is substantially trapezoidal, and the distance between opposing legs decreases substantially from the second surface to the first surface.

Description

Technical Field

[0001] The technology disclosed by this specification relates to a wiring board.

Background Art

[0002] Patent Document 1 discloses an electronic component built-in substrate in which an electronic component is built in a cavity formed in a resin insulating layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] [Problems of Patent Document 1] As shown in FIG. 1 of Patent Document 1, the electronic component built-in substrate of Patent Document 1 has a core substrate and an upper build-up layer. The electronic component is accommodated in a cavity in the upper build-up layer. The cross-sectional shape of the cavity is shown in FIG. 5(B) of Patent Document 1. According to FIG. 5(B) of Patent Document 1, the wall surface of the cavity of Patent Document 1 is inclined. And the distance between the opposing wall surfaces becomes smaller toward the core substrate. Therefore, as an explanation of the cross-sectional shape of the cavity of Patent Document 1, an inverted trapezoid is considered appropriate. When the electronic component built-in substrate of Patent Document 1 receives a thermal shock, it is considered that the flatness of the upper surface of the upper build-up layer decreases.

Means for Solving the Problems

[0005] The wiring board of the present invention comprises: a first resin insulating layer having a first surface, a second surface opposite to the first surface, and a cavity extending from the first surface to the second surface; a second resin insulating layer having a third surface and a fourth surface opposite to the third surface, formed on the first resin insulating layer such that the fourth surface faces the first surface; a component having an electrode facing the fourth surface and housed within the cavity; and a third resin insulating layer having a fifth surface and a sixth surface opposite to the fifth surface, formed on the first resin insulating layer such that the fifth surface faces the second surface. The cavity has an opening on the first surface side located on the first surface and an opening on the second surface side located on the second surface. The second resin insulating layer closes the opening on the first surface side, and the third resin insulating layer closes the opening on the second surface side. The second resin insulating layer is closer to the mounting surface for mounting electronic components than the third resin insulating layer. A portion of the third resin insulating layer fills the gap between the inner wall of the cavity and the component within the cavity. The cross-sectional shape of the cavity is substantially trapezoidal, and the distance between opposing legs decreases substantially from the second surface to the first surface.

[0006] In the wiring board of the embodiment of the present invention, the cross-sectional shape of the cavity is substantially trapezoidal, and the distance between opposing legs decreases substantially from the second surface to the first surface of the first resin insulating layer. The space between the inner wall of the cavity and the components within the cavity decreases substantially from the second surface to the first surface. The size of the exit of the space on the second surface side is larger than the size of the exit of the space on the first surface side. Even if the resin in the space expands due to thermal shock, etc., the expanded resin is less likely to exit the space through the exit on the first surface side. The expanded resin is less likely to press against the second resin insulating layer. The flatness of the mounting surface is less likely to decrease. When electronic components are mounted on the wiring board of the embodiment, the electronic components are easily mounted. The embodiment can improve the connection reliability between the wiring board of the embodiment and the electronic components mounted on the wiring board of the embodiment. The connection reliability between the wiring board of the embodiment and the electronic components mounted on the wiring board of the embodiment is less likely to decrease due to thermal shock. The embodiment can provide a wiring board with stable performance. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic cross-sectional view showing the wiring board of the embodiment. [Figure 2A] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2B] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2C] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2D] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2E] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2F] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2G] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2H] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2I] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 2J] A schematic cross-sectional view illustrating the manufacturing method of the wiring board according to the embodiment. [Figure 3] A schematic cross-sectional view showing the wiring board of a modified example. [Modes for carrying out the invention]

[0008] [Embodiment] Figure 1 is a cross-sectional view showing a wiring board 2 of an embodiment. As shown in Figure 1, the wiring board 2 has an upper surface 2a and a lower surface 2b. The upper surface 2a is the mounting surface, on which electronic components are mounted. Examples of electronic components include logic ICs and memory. The wiring board 2 includes a first resin insulating layer 20, a second resin insulating layer 200, a third resin insulating layer 80, a fourth resin insulating layer 110, and a second solder resist layer 140. An example of the second resin insulating layer 200 is the first solder resist layer. The second resin insulating layer 200 is the outermost resin insulating layer.

[0009] The first resin insulating layer 20 has a first surface 20a and a second surface 20b opposite to the first surface 20a. The second resin insulating layer 200 has a third surface 200a and a fourth surface 200b opposite to the third surface 200a. The third resin insulating layer 80 has a fifth surface 80a and a sixth surface 80b opposite to the fifth surface 80a. The fourth resin insulating layer 110 has a seventh surface 110a and an eighth surface 110b opposite to the seventh surface 110a. The second solder resist layer 140 has a ninth surface 140a and a tenth surface 140b opposite to the ninth surface 140a. The top surface 2a of the wiring board 2 and the third surface 200a of the second resin insulating layer 200 are the same surface. The bottom surface 2b of the wiring board 2 and the tenth surface 140b of the second solder resist layer 140 are the same surface. The first surface 20a faces the fourth surface 200b of the second resin insulating layer 200. The second surface 20b faces the fifth surface 80a of the third resin insulating layer 80. The first resin insulating layer 20 includes an uppermost first resin insulating layer 22 and a lowermost first resin insulating layer 24. The surface of the uppermost first resin insulating layer 22 that is in contact with the second resin insulating layer 200 is the first surface 20a. The surface of the lowermost first resin insulating layer 24 that is in contact with the third resin insulating layer 80 is the second surface 20b. The first resin insulating layer 20 may include another resin insulating layer between the uppermost first resin insulating layer 22 and the lowermost first resin insulating layer 24. The number of resin insulating layers forming the first resin insulating layer 20 may be three or more. The resin insulating layers forming the first resin insulating layer 20 are made of resin and inorganic particles dispersed within the resin. An example of the resin is a thermosetting resin. The inorganic particles are, for example, silica or alumina. The resin insulating layer forming the first resin insulating layer 20 does not have a reinforcing material made of fibers. An example of a reinforcing material is glass cloth. The second resin insulating layer 200 and the third resin insulating layer 80 do not have a reinforcing material.

[0010] The wiring board 2 further has conductor layers 10, 30 and via conductors 40. The conductor layers 10, 30 and resin insulating layers 22, 24 are stacked alternately. The via conductor 40 penetrates the resin insulating layer 22 sandwiched between adjacent conductor layers 10, 30 and connects adjacent conductor layers 10, 30. Conductor layer 10 is formed between the first surface 20a of the first resin insulating layer 20 and the fourth surface 200b of the second resin insulating layer 200. Conductor layer 10 is sandwiched between the second resin insulating layer 200 and the topmost first resin insulating layer 22. Conductor layer 10 includes a frame-shaped cavity conductor circuit 14a. Conductor layer 30 is formed between the topmost first resin insulating layer 22 and the bottommost first resin insulating layer 24. Conductor layer 30 is sandwiched between the topmost first resin insulating layer 22 and the bottommost first resin insulating layer 24. The via conductor 40 connects conductor layer 10 and conductor layer 30. The via conductor 40 is formed within an opening 42 that penetrates the uppermost first resin insulating layer 22.

[0011] The first resin insulating layer 20 has a cavity 50 extending from the first surface 20a to the second surface 20b. The cavity 50 penetrates the first resin insulating layer 20 and the cavity conductor circuit 14a. The cavity 50 has an opening 50a on the first surface 20a side located on the first surface 20a and an opening 50b on the second surface 20b side located on the second surface 20b. A component 60 is housed within the cavity 50. An adhesive film 70 is formed between the component 60 and the fourth surface 200b of the second resin insulating layer 200. The component 60 is fixed to the fourth surface 200b of the second resin insulating layer 200 by the adhesive film 70. The component 60 has an electrode 62 facing the fourth surface 200b. The second resin insulating layer 200 closes the opening 50a on the first surface 20a side. The third resin insulating layer 80 closes the opening 50b on the second surface 20b side. A portion of the third resin insulating layer 80 fills the gap 52 between the inner wall of the cavity 50 and the component 60.

[0012] The cross-sectional shape of the cavity 50 is substantially trapezoidal. The distance between opposite legs (leg distance) decreases substantially from the second surface 20b towards the first surface 20a. Of the four sides of the trapezoid, the legs are the sides other than the top and bottom bases. The leg distance decreases substantially towards the mounting surface. In Patent Document 1 and the embodiment, the leg distance is reversed. In Patent Document 1, the leg distance increases towards the mounting surface. The size of the opening 50a on the first surface 20a side of the cavity 50 is smaller than the size of the opening 50b on the second surface 20b side.

[0013] The third resin insulating layer 80 is formed on the second surface 20b of the first resin insulating layer 20. The fifth surface 80a faces the second surface 20b of the first resin insulating layer 20. The sixth surface 80b faces the seventh surface 110a of the fourth resin insulating layer 110. The third resin insulating layer 80 is formed of resin and inorganic particles dispersed within the resin.

[0014] The wiring board 2 further has a conductor layer 90 and a via conductor 100. The conductor layer 90 is formed on the sixth surface 80b of the third resin insulating layer 80. The via conductor 100 connects the conductor layer 30 and the conductor layer 90. The via conductor 100 is formed in an opening 102 that penetrates the third resin insulating layer 80 and the bottommost first resin insulating layer 24. The opening 102 penetrates only the third resin insulating layer 80 and the bottommost first resin insulating layer 24. The via conductor 100 is an example of a second via conductor.

[0015] The fourth resin insulating layer 110 is formed on the sixth surface 80b of the third resin insulating layer 80 and on the conductor layer 90. The fourth resin insulating layer 110 is in contact with the second solder resist layer 140 and is formed inside the second solder resist layer 140. The seventh surface 110a faces the sixth surface 80b of the third resin insulating layer 80. The eighth surface 110b faces the ninth surface 140a of the second solder resist layer 140. The fourth resin insulating layer 110 is formed of a resin and inorganic particles dispersed in the resin. The fourth resin insulating layer 110 may further have a reinforcing material 112. The reinforcing material 112 is included only in the fourth resin insulating layer 110, and the first resin insulating layer 20, the third resin insulating layer 80, the second resin insulating layer 200, and the second solder resist layer 140 do not include the reinforcing material. The fourth resin insulating layer 110 is formed using, for example, a prepreg. The thickness of the resin insulating layer including the reinforcing material 112 is larger than the distance between the first surface 20a and the second surface 20b of the first resin insulating layer 20 (the thickness of the first resin insulating layer 20) (Relationship 1). An example of the resin insulating layer including the reinforcing material 112 is the fourth resin insulating layer 110. The resin insulating layer including the reinforcing material 112 is in contact with the second solder resist layer 140. The thickness of the first resin insulating layer 20 may be the distance between the conductor layer 10 in contact with the first surface 20a and the second surface 20b (K1 in FIG. 1). The thickness of the fourth resin insulating layer 110 is represented by the distance between the conductor layers sandwiching the fourth resin insulating layer 110. The thickness of the resin insulating layer including the reinforcing material 112 is represented by the distance between the conductor layers sandwiching the resin insulating layer including the reinforcing material 112 (K2 in FIG. 1). When there are a plurality of resin insulating layers including the reinforcing material, one layer satisfies Relationship 1. Alternatively, two layers satisfy Relationship 1. Alternatively, all layers satisfy Relationship 1. The wiring board 2 further has a conductor layer 120 and a via conductor 130. The conductor layer 120 is formed on the eighth surface 110b of the fourth resin insulating layer 110. The via conductor 130 is formed in an opening 132 penetrating the fourth resin insulating layer 110. The via conductor 130 connects the conductor layer 90 and the conductor layer 120.

[0016] The second solder resist layer 140 is formed on the eighth surface 110b of the fourth resin insulating layer 110 and on the conductor layer 120. The second solder resist layer 140 is formed at a position farthest from the second resin insulating layer 200. The ninth surface 140a faces the eighth surface 110b of the fourth resin insulating layer 110. The tenth surface 140b forms the lower surface 2b of the wiring substrate 2. The second solder resist layer 140 has an opening 162 that exposes the conductor layer 120.

[0017] The second resin insulating layer 200 is formed on the first surface 20a of the first resin insulating layer 20. The second resin insulating layer 200 is formed on the first resin insulating layer 20 such that the fourth surface 200b faces the first surface 20a. The wiring substrate 2 further includes a conductor layer 210 and via conductors 220, 230. The conductor layer 210 is formed on the third surface 200a of the second resin insulating layer 200. The conductor layer 210 includes mounting electrodes 212, 213. An alignment mark (first alignment mark) 8 is formed on the third surface 200a of the second resin insulating layer 200. The conductor layer 210 and the alignment mark 8 are not formed simultaneously. They are formed separately. The alignment mark 8 is embedded in the second resin insulating layer 200. The conductor layer 210 including the mounting electrodes 212, 213 is not embedded in the second resin insulating layer 200. The conductor layer 210 protrudes from the second resin insulating layer 200. A conductor 9 is formed in an opening 9a that penetrates the second resin insulating layer 200. The conductor 9 connects the first alignment mark 8 and the conductor layer 10. The via conductor 220 is formed in an opening 222 that penetrates the second resin insulating layer 200. The opening 222 exposes the conductor layer 10. The via conductor 220 connects the mounting electrode 212 and the conductor layer 10. The via conductor 230 is formed in an opening 232 that penetrates the second resin insulating layer 200 and the adhesive film 70. The opening 232 exposes the electrode 62 of the component 60. The via conductor 230 connects the mounting electrode 213 and the electrode 62. The via conductor 230 is an example of a first via conductor. A tin plating layer may be formed on the upper surface of the conductor layer 210. The mounting electrodes 212, 213 function as bumps for mounting electronic components.

[0018] The second resin insulating layer 200 has openings 222, 232, and 9a that penetrate the second resin insulating layer 200. The lengths of each opening 222, 232, and 9a are different. The length of opening 232 is longer than the length of opening 222. The length of opening 222 is longer than the length of opening 9a. The length of opening 222 is the distance between the third surface 200a and the fourth surface 200b. The length of opening 232 is the distance between the third surface 200a and the electrode 62. The length of opening 9a is the distance between the alignment mark 8 and the fourth surface 200b. Thus, the second resin insulating layer 200 has three types of openings 222, 232, and 9a, and the lengths of the three types of openings 222, 232, and 9a are different from each other.

[0019] [Manufacturing method for the wiring board 2 of the embodiment] Figures 2A to 2J show the manufacturing method of the wiring board 2 according to the embodiment. Figures 2A to 2J are cross-sectional views. In Figures 2A to 2I, the vertical direction in the figures is reversed compared to Figures 1 and 2J. Figure 2A shows a support plate 4, a metal layer 6 formed on the support plate 4, and alignment marks (first alignment marks) 8 formed on the metal layer 6. The metal layer 6 is, for example, copper foil. The metal layer 6 is formed on the support plate 4 in advance. A plating resist is formed on the metal layer 6. Alignment marks 8 are formed on the metal layer 6 exposed from the plating resist by electrolytic copper plating. It is preferable that no conductive circuits other than the alignment marks 8 are formed on the metal layer 6. The metal layer 6 acts as a seed layer for forming the alignment marks 8. After that, the plating resist is removed.

[0020] A second resin insulating layer 200 is formed on the metal layer 6 and the alignment mark 8. The second resin insulating layer 200 has a third surface 200a and a fourth surface 200b opposite to the third surface 200a. The third surface 200a of the second resin insulating layer 200 faces the metal layer 6. An opening 9a is formed in the second resin insulating layer 200, penetrating it and exposing the alignment mark 8. The opening 9a is formed with respect to the alignment mark 8. The opening 9a is formed by laser light or photographic technology. The opening 9a penetrates only the second resin insulating layer 200. A seed layer is formed on the fourth surface 200b of the second resin insulating layer 200 and within the opening 9a. A plating resist is formed on the seed layer with respect to the alignment mark 8. A plating resist may also be formed on the seed layer with respect to the opening 9a. An electrolytic copper plating layer is formed on the seed layer exposed from the plating resist. The plating resist is removed. The seed layer exposed from the electrolytic copper plating layer is removed. As shown in Figure 2B, a conductor layer 10 is formed on the fourth surface 200b of the second resin insulating layer 200. The conductor layer 10 includes a cavity conductor circuit 14. The conductor layer 10 may have alignment marks (second alignment marks). The position of each conductor circuit in the conductor layer 10 is related to the position of the first alignment mark 8. The cavity conductor circuit 14 and the second alignment marks are included in the conductor circuits within the conductor layer 10. The position of the first alignment mark 8 and the position of the second alignment mark are related. The position of the first alignment mark 8 and the position of the cavity conductor circuit 14 are related. The cavity conductor circuit 14 acts as a stopper for forming the cavity 50. The size of the cavity conductor circuit 14 is preferably larger than the size of the opening 50a on the first surface 20a side of the cavity 50. A conductor 9 that fills the opening 9a is formed simultaneously with the conductor layer 10. Conductor 9 connects alignment mark 8 and conductor layer 10.

[0021] An uppermost first resin insulating layer 22 is formed on the conductor layer 10 and the fourth surface 200b of the second resin insulating layer 200. A laser beam is shone onto the uppermost first resin insulating layer 22. The laser beam is shone based on the position of the conductor circuit in the conductor layer 10. For example, the laser beam is shone based on the second alignment mark. The laser beam penetrates the uppermost first resin insulating layer 22. An opening 42 for via conductors 40 is formed in the uppermost first resin insulating layer 22, penetrating the uppermost first resin insulating layer 22 and exposing the conductor layer 10. The position of the opening 42 for via conductors 40 is related to the position of the first alignment mark 8. A seed layer is formed on the uppermost first resin insulating layer 22 and within the opening 42. A plating resist is formed on the seed layer based on the position of the conductor circuit in the conductor layer 10. For example, the plating resist is formed based on the second alignment mark. An electrolytic copper plating layer is formed on the seed layer exposed from the plating resist. The plating resist is removed. The seed layer exposed from the electrolytic copper plating layer is removed. Conductor layer 30 and via conductor 40 are formed simultaneously. Conductor layer 30 may have a third alignment mark. The position of each conductor circuit within conductor layer 30 is related to the position of the first alignment mark 8. The position of the third alignment mark is related to the position of the first alignment mark 8. The position of the via conductor 40 is related to the position of the first alignment mark 8. The via conductor 40 fills the opening 42. The via conductor 40 connects conductor layer 10 and conductor layer 30. The topmost first resin insulating layer 22 and the bottommost first resin insulating layer 24 are formed on conductor layer 30. As shown in Figure 2C, the fourth surface 200b of the second resin insulating layer 200 and the first resin insulating layer 20 are formed on conductor layer 10. The first resin insulating layer 20 has a first surface 20a and a second surface 20b opposite to the first surface 20a. The first surface 20a of the first resin insulating layer 20 faces the fourth surface 200b of the second resin insulating layer 200. The first resin insulating layer 20 is formed from an uppermost first resin insulating layer 22 and a lowermost first resin insulating layer 24. The conductor layer 30 is sandwiched between the uppermost first resin insulating layer 22 and the lowermost first resin insulating layer 24. The uppermost first resin insulating layer 22 and the lowermost first resin insulating layer 24 have a first surface and a second surface opposite to the first surface. The first surface of the uppermost first resin insulating layer 22 faces the fourth surface 200b of the second resin insulating layer 200.The first surface of the uppermost first resin insulating layer 22 and the first surface 20a of the first resin insulating layer 20 form the same surface. The first surface of the bottommost first resin insulating layer 24 faces the second surface of the uppermost first resin insulating layer 22. The second surface of the bottommost first resin insulating layer 24 and the second surface 20b of the first resin insulating layer 20 form the same surface. It is preferable that the thickness of the uppermost first resin insulating layer 22 is greater than the thickness of the bottommost first resin insulating layer 24. The ratio of the thickness of the uppermost first resin insulating layer 22 to the thickness of the bottommost first resin insulating layer 24 (thickness of the uppermost first resin insulating layer 22 / thickness of the bottommost first resin insulating layer 24) is preferably 1.2 or more and 1.5 or less. The thickness of the uppermost first resin insulating layer 22 is the distance between the conductor layer 10 and the conductor layer 30. The uppermost first resin insulating layer 22 is sandwiched between the conductor layer 10 and the conductor layer 30. The thickness of the bottommost first resin insulating layer 24 is the distance between the conductor layer 30 and the second surface of the bottommost first resin insulating layer 24. The conductor layer 30 is sandwiched between the topmost first resin insulating layer 22 and the bottommost first resin insulating layer 24.

[0022] A laser beam is shone from the second surface 20b of the first resin insulating layer 20. The laser beam is shone based on the position of the conductor circuit in the conductor layer 30. For example, the laser beam is shone based on the third alignment mark. The laser beam penetrates the first resin insulating layer 20. As shown in Figure 2D, an opening 51 is formed that penetrates the first resin insulating layer 20 and leads to the first aperture conductor circuit 14. The laser beam penetrates all the resin insulating layers 22 and 24 belonging to the first resin insulating layer 20 and reaches the cavity conductor circuit 14. The cavity conductor circuit 14 is exposed through the opening 51. The position of the opening 51 is related to the position of the first alignment mark 8. The cavity conductor circuit 14 prevents the laser beam from reaching the second resin insulating layer 200. For example, the laser beam may be shone obliquely to the cavity conductor circuit 14 so that the wall surface of the opening 51 is formed obliquely to the cavity conductor circuit 14. The cross-sectional shape of the opening 51 is formed to be substantially trapezoidal. The cross-sectional shape of the opening 51 shown in Figure 2D is approximately an inverted trapezoid. The distance between opposing legs decreases substantially from the second surface 20b to the first surface 20a.

[0023] The cavity conductor circuit 14 exposed from the opening 51 is removed by etching. The planar shape of the cavity conductor circuit 14a after etching is frame-shaped. The frame-shaped cavity conductor circuit 14a is covered with the uppermost first resin insulating layer 22. As shown in Figure 2E, a cavity 50 is formed that simultaneously penetrates the first resin insulating layer 20 and the cavity conductor circuit 14a. The cross-sectional shape of the cavity 50 is substantially trapezoidal. The cross-sectional shape of the cavity 50 depicted in Figure 2E is approximately an inverted trapezoid. The distance between opposing legs substantially decreases from the second surface 20b toward the first surface 20a. The size of the opening 50a on the first surface 20a side is smaller than the size of the opening 50b on the second surface 20b side. The fourth surface 200b of the second resin insulating layer 200 is exposed from the cavity 50. The second resin insulating layer 200 closes the opening 50a on the first surface 20a side of the cavity 50. The opening 50a of the cavity 50 is closed by the fourth surface 200b of the second resin insulating layer 200. The second resin insulating layer 200 is an example of a component for closing the opening 50a.

[0024] As shown in Figure 2F, part 60 is fixed to the fourth surface 200b of the second resin insulating layer 200, which is exposed from the cavity 50, via the adhesive film 70. For example, part 60 is fixed to the fourth surface 200b of the second resin insulating layer 200 based on the third alignment mark. Alternatively, part 60 is fixed to the fourth surface 200b of the second resin insulating layer 200 based on the position of the cavity 50. The position of part 60 is related to the position of the first alignment mark 8. The adhesive film 70 is pre-attached to part 60. Part 60 with the adhesive film 70 attached is fixed to the fourth surface 200b exposed from the cavity 50. Part 60 is fixed within the cavity 50. As part 60 is fixed, part 60 is surrounded by the first resin insulating layer 20. Part 60 is protected by the first resin insulating layer 20. The top surface 601 of part 60 does not protrude from the opening 50b. The upper surface 601 of component 60 is located below the second surface 20b of the first resin insulating layer 20. The upper surface 601 of component 60 is not located above the second surface 20b of the first resin insulating layer 20. Preferably, the upper surface 601 of component 60 is located above the first surface of the lowest first resin insulating layer 24. The upper surface 601 of component 60 is located between the first surface and the second surface of the lowest first resin insulating layer 24. A gap 52 is formed between component 60 and the inner wall surface of the cavity 50.

[0025] As shown in Figure 2G, a third resin insulating layer 80 is formed on the second surface 20b of the first resin insulating layer 20. The third resin insulating layer 80 has a fifth surface 80a and a sixth surface 80b opposite to the fifth surface 80a. The fifth surface 80a of the third resin insulating layer 80 faces the second surface 20b. The third resin insulating layer 80 closes the opening 50b of the cavity 50 on the second surface 20b side. The opening 50b of the cavity 50 is closed by the fifth surface 80a of the third resin insulating layer 80. The third resin insulating layer 80 fills the gap 52.

[0026] A laser beam (first laser beam) is irradiated from the sixth surface 80b of the third resin insulating layer 80 based on the position of the conductor circuit within the conductor layer 30. For example, the first laser beam is irradiated based on the third alignment mark. The first laser beam simultaneously penetrates the third resin insulating layer 80 and the bottommost first resin insulating layer 24. An opening 102 is formed that penetrates the third resin insulating layer 80 and the bottommost first resin insulating layer 24 and leads to the conductor layer 30. As shown in Figure 2H, a conductor layer 90 is formed on the sixth surface 80b of the third resin insulating layer 80. A via conductor 100 is formed simultaneously with the conductor layer 90. For example, the conductor layer 90 and the via conductor 100 are formed by a semi-additive method. The via conductor 100 fills the opening 102. The via conductor 100 connects the conductor layer 30 and the conductor layer 90.

[0027] If component 60 has electrodes on both sides, a laser beam (second laser beam) is irradiated from the sixth surface 80b of the third resin insulating layer 80 toward component 60 based on the position of the conductor circuit in the conductor layer 30. For example, the second laser beam is irradiated based on the third alignment mark. The second laser beam penetrates only the third resin insulating layer 80. The second laser beam does not penetrate the bottommost first resin insulating layer 24. An opening for a via conductor is formed in the third resin insulating layer 80 that penetrates the third resin insulating layer 80 and leads to component 60. The via conductor opening that penetrates only the third resin insulating layer 80 leads to the electrodes of component 60. The third resin insulating layer 80 can have two types of via conductor openings. The depths of the two openings (an opening leading to the conductor layer 30 and an opening leading to the electrodes of the component) are different. When the via conductor 100 is formed, a via conductor connecting component 60 and the conductor layer 90 is formed within the via conductor opening that exposes the electrodes of component 60.

[0028] A fourth resin insulating layer 110 is formed on the sixth surface 80b of the third resin insulating layer 80 and on the conductor layer 90. The seventh surface 110a of the fourth resin insulating layer 110 faces the sixth surface 80b. The fourth resin insulating layer 110 includes a reinforcing material 112. An opening 132 is formed in the fourth resin insulating layer 110. As shown in Figure 2I, a conductor layer 120 is formed on the eighth surface 110b of the fourth resin insulating layer 110. For example, the conductor layer 120 and the via conductor 130 are formed by a semi-additive method. The via conductor 130 is formed simultaneously with the conductor layer 120. The via conductor 130 fills the opening 132. The via conductor 130 connects the conductor layer 90 and the conductor layer 120.

[0029] In this embodiment, a resin insulating layer having a reinforcing material (an additional resin insulating layer) can be added between the third resin insulating layer 80 and the fourth resin insulating layer 110. A conductor layer is formed between the additional resin insulating layer and the fourth resin insulating layer 110. Via conductors are formed penetrating the additional resin insulating layer. Preferably, the thickness of the resin insulating layer having a reinforcing material, such as the fourth resin insulating layer 110, is greater than the thickness of the first resin insulating layer 20.

[0030] The support plate 4 and the metal layer 6 are removed. The third surface 200a of the second resin insulating layer 200 is exposed. The alignment mark 8 is exposed. The second solder resist layer 140 is formed on the eighth surface 110b of the fourth resin insulating layer 110. Preferably, the second solder resist layer 140 is formed directly above the fourth resin insulating layer 110. The ninth surface 140a and the eighth surface 110b are in contact. The ninth surface 140a of the second solder resist layer 140 faces the eighth surface 110b. As shown in Figure 2J, an opening 162 is formed in the second solder resist layer 140 to expose the conductor layer 120. For example, the opening 162 is formed by photographic technology.

[0031] A laser beam (third laser) is shone from the third surface 200a of the second resin insulating layer 200. The third laser beam is shone based on the first alignment mark 8. The third laser beam penetrates both the second resin insulating layer 200 and the adhesive film 70 simultaneously. An opening 232 is formed. The position of the opening 232 is related to the position of the first alignment mark 8. The opening 232 penetrates both the second resin insulating layer 200 and the adhesive film 70, exposing the electrodes 62 of the component 60. The position of the opening 232 is related to the position of the component 60. Therefore, the position of the electrodes 62 of the component 60 and the position of the opening 232 are aligned with high precision. Furthermore, a laser beam (fourth laser) is shone from the third surface 200a of the second resin insulating layer 200. The fourth laser beam is shone based on the first alignment mark 8. The fourth laser beam penetrates the second resin insulating layer 200. The fourth laser beam penetrates only the second resin insulating layer 200. An opening 222 is formed. The opening 222 penetrates only the second resin insulating layer 200. The position of the opening 222 is related to the position of the first alignment mark 8. The opening 222 penetrates the second resin insulating layer 200 and exposes the conductor layer 10. A conductor layer 210 is formed on the third surface 200a. The conductor layer 210 includes mounting electrodes 212 and 213. Via conductors 220 and 230 are formed simultaneously with the conductor layer 210. At this time, the alignment mark 8 has already been formed. The conductor layer 210 and the alignment mark 8 are not formed at the same time. The conductor layer 210 and the alignment mark 8 are formed separately. The via conductor 220 fills the opening 222. The via conductor 220 connects the conductor layer 10 and the mounting electrode 212. The via conductor 230 fills the opening 232. The via conductor 230 connects electrode 62 and mounting electrode 213. The position of the opening 232 and the position of the component 60 are related to the position of the first alignment mark 8. Therefore, the wiring board 2 of the embodiment can achieve high connection reliability between the via conductor 230 and the electrode 62 of the component 60. The wiring board 2 manufactured in the embodiment can achieve high connection reliability between the mounting electrode 213 and the electronic component and the component 60 via the via conductor 230. A tin plating layer is formed on the upper surface of the conductor layer 210. The wiring board 2 of the embodiment is obtained.

[0032] In the wiring board 2 of the embodiment, the cross-sectional shape of the cavity 50 is substantially trapezoidal, and the distance between opposing legs substantially decreases from the second surface 20b to the first surface 20a of the first resin insulating layer 20. The space between the inner wall of the cavity 50 and the components 60 inside the cavity 50 substantially decreases from the second surface 20b to the first surface 20a. The size of the exit of the space on the second surface 20b side is larger than the size of the exit of the space on the first surface 20a side. Even if the resin in the space expands due to thermal shock, etc., the expanded resin is unlikely to exit the space through the exit on the first surface 20a side. The expanded resin is unlikely to exit the space through the opening 50a on the first surface 20a side. The expanded resin is unlikely to press against the second resin insulating layer 200. The flatness of the mounting surface is unlikely to decrease. When electronic components are mounted on the wiring board 2 of the embodiment, the electronic components are easily mounted. The embodiment can improve the connection reliability between the wiring board 2 of the embodiment and the electronic components mounted on the wiring board 2 of the embodiment. Thermal shock is less likely to degrade the connection reliability between the wiring board 2 of the embodiment and the electronic components mounted on the wiring board 2 of the embodiment. The embodiment can provide a wiring board 2 with stable performance.

[0033] The via conductors 220 and 230 that penetrate the second resin insulation 200 are tapered toward the lower surface 2b of the wiring board 2. The via conductors 40, 100 and 130 that penetrate the resin insulation layers 22, 24, 80, and 110 other than the second resin insulation 200 are tapered toward the upper surface 2a of the wiring board 2. The orientation of the via conductors that penetrate the second resin insulation is opposite to the orientation of the via conductors that penetrate the resin insulation layers other than the second resin insulation.

[0034] [Modified example wiring board 2x and manufacturing method] Figure 3 is a cross-sectional view showing a modified wiring board 2x. If the elements forming the modified wiring board 2x are the same as those forming the wiring board 2 of the embodiment, the reference numerals in the figure are the same. Detailed explanations of elements common to the embodiment are omitted. The modified wiring board 2x is obtained by adding a first solder resist layer 350, a conductor layer 360, and a via conductor 370 to the wiring board 2 of the embodiment. The first solder resist layer 350 is formed on the second resin insulating layer 200, the conductor layer 210, and the alignment marks 8. No tin plating layer is formed on the conductor layer 210. The conductor layer 360 is formed on the first solder resist layer 350. A via conductor 370 is formed that penetrates the first solder resist layer 350 and connects the conductor layer 210 and the conductor layer 360. The conductor layer 360 and the via conductor 370 are formed simultaneously by a semi-additive method. In the embodiment, the second resin insulating layer 200 also serves as the first solder resist layer, but in the modified example, the first solder resist layer 350 exists separately from the second resin insulating layer 200. The conductor layer 210 in the embodiment includes a conductor circuit for mounting electronic components, but the conductor layer 210 in the modified example does not include a conductor circuit for mounting electronic components. In the modified example, the conductor layer 360 includes a conductor circuit for mounting electronic components. In the embodiment, the second resin insulating layer 200 is one of the outermost resin insulating layers, but in the modified example, the first solder resist layer 350 is one of the outermost resin insulating layers.

[0035] The first solder resist layer 350 is formed on the third surface 200a of the second resin insulating layer 200. The first solder resist layer 350 has an eleventh surface 350a and a twelfth surface 350b opposite to the eleventh surface 350a. The twelfth surface 350b faces the third surface 200a. In the modified example, the top surface 2a of the wiring board 2x is the same surface as the eleventh surface 350a of the first solder resist layer 350. The first solder resist layer 350 does not contain reinforcing material. Reinforcing material 112 is included only in the fourth resin insulating layer 110, and the first resin insulating layer 20, the third resin insulating layer 80, the second resin insulating layer 200, the first solder resist layer 350, and the second solder resist layer 140 do not contain reinforcing material. The conductor layer 360 is formed on the eleventh surface 350a of the first solder resist layer 350. The conductor layer 360 includes mounting electrodes 362 and 363. The via conductor 370 is formed within an opening 372 that penetrates the first solder resist layer 350. The opening 372 exposes the conductor layer 210. A tin plating layer may be formed on the upper surface of the conductor layer 360. The mounting electrodes 362 and 363 function as bumps for mounting electronic components.

[0036] In the modified wiring board 2, the cross-sectional shape of the cavity 50 is substantially trapezoidal, and the distance between opposing legs decreases substantially from the second surface 20b to the first surface 20a of the first resin insulating layer 20. The modified wiring board 2x has the same effect as the wiring board 2 of the embodiment.

[0037] In the embodiment and the modified example, the orientation of the via conductors is the same. The via conductor 370 that penetrates the first solder resist layer 350 tapers toward the lower surface 2b of the wiring board 2x. In the embodiment and the modified example, the orientation of the via conductors located above the first surface 20a of the first resin insulating layer 20 is reversed compared to the orientation of the via conductors located below the first surface 20a of the first resin insulating layer 20.

[0038] The details regarding thickness and length are the same in the embodiment and the modified example. The relationships regarding thickness and length are the same in the embodiment and the modified example. [Explanation of Symbols]

[0039] 2, 2x: Wiring board 20: First resin insulating layer 20a: Page 1 20b: 2nd side 22: The finest first resin insulating layer 24: The bottommost first resin insulating layer 50: Cavity 50a: Opening on the first side 50b: Opening on the second side 52: Gap 60: Parts 62: Electrode 70: Adhesive film 80: Third resin insulating layer 80a:Side 5 80b:Side 6 100: Via conductor 102:Aperture 110: Fourth resin insulating layer 110a:Side 7 110b:Side 8 112: Reinforcement material 140: Second solder resist layer 200: Second resin insulating layer 200a: 3rd side 200b: 4th side 210: Conductor layer 220: Via conductor 230: Via conductor 350: First solder resist layer

Claims

1. A first resin insulating layer having a first surface, a second surface opposite to the first surface, and a cavity extending from the first surface to the second surface, A second resin insulating layer having a third surface and a fourth surface opposite to the third surface, formed on the first resin insulating layer such that the fourth surface faces the first surface, A component having an electrode facing the fourth surface and housed within the cavity, A wiring substrate having a fifth surface and a sixth surface opposite to the fifth surface, and a third resin insulating layer formed on the first resin insulating layer such that the fifth surface faces the second surface, The cavity has an opening on the first surface side located on the first surface and an opening on the second surface side located on the second surface. The second resin insulating layer closes the opening on the first surface side, and the third resin insulating layer closes the opening on the second surface side. The second resin insulating layer is closer to the mounting surface for mounting electronic components than the third resin insulating layer. A portion of the third resin insulating layer fills the gap between the inner wall of the cavity and the component inside the cavity. The cross-sectional shape of the cavity is substantially trapezoidal, and the distance between opposing legs decreases substantially from the second surface to the first surface.

2. A wiring board according to claim 1, wherein the first resin insulating layer comprises a plurality of resin insulating layers, the resin insulating layer in contact with the second resin insulating layer is the uppermost first resin insulating layer, the resin insulating layer in contact with the third resin insulating layer is the lowest first resin insulating layer, the surface of the uppermost first resin insulating layer in contact with the second resin insulating layer is the first surface, the surface of the lowest first resin insulating layer in contact with the third resin insulating layer is the second surface, and the cavity penetrates the plurality of resin insulating layers.

3. The wiring board according to claim 1, wherein the second resin insulating layer also serves as the outermost resin insulating layer.

4. The wiring board according to claim 3, wherein the outermost resin insulating layer is a first solder resist layer.

5. A wiring board according to claim 1, further comprising an outermost resin insulating layer formed on the third surface of the second resin insulating layer, wherein the outermost resin insulating layer is in contact with the third surface.

6. The wiring board according to claim 5, wherein the outermost resin insulating layer also serves as the first solder resist layer.

7. A wiring board according to claim 1, further comprising an adhesive film formed between the second resin insulating layer and the electrode, and a first via conductor that simultaneously penetrates the second resin insulating layer and the adhesive film and reaches the electrode.

8. A wiring board according to claim 2, further comprising a second via conductor that simultaneously penetrates the third resin insulating layer and the bottommost first resin insulating layer.

9. A wiring board according to claim 1, further comprising an adhesive film formed between the second resin insulating layer and the electrode, wherein the component is fixed to the fourth surface of the second resin insulating layer by the adhesive film.

10. A wiring board according to claim 2, wherein the plurality of resin insulating layers do not include any resin insulating layers other than the uppermost first resin insulating layer and the lowermost first resin insulating layer.

11. The wiring board according to claim 8, wherein the second via conductor penetrates only the third resin insulating layer and the bottommost first resin insulating layer.

12. A wiring board according to claim 6, further comprising a second solder resist layer formed at the position furthest from the first solder resist layer and a fourth resin insulating layer in contact with the second solder resist layer and formed inside the second solder resist layer, wherein the fourth resin insulating layer includes a reinforcing material, and the first resin insulating layer, the second resin insulating layer and the third resin insulating layer do not include a reinforcing material.

13. A wiring board according to claim 12, wherein the first solder resist layer and the second solder resist layer do not contain reinforcing material, and the thickness of the fourth resin insulating layer is greater than the thickness of the first resin insulating layer.

14. A wiring board according to claim 4, further comprising a second solder resist layer formed at the position furthest from the first solder resist layer and a fourth resin insulating layer in contact with the second solder resist layer and formed inside the second solder resist layer, wherein the fourth resin insulating layer includes a reinforcing material, and the first resin insulating layer and the third resin insulating layer do not include a reinforcing material.

15. A wiring board according to claim 1, wherein alignment marks are formed on the third surface of the second resin insulating layer.

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