Semiconductor memory device and method for manufacturing a semiconductor memory device

Abstract

The present invention provides a semiconductor memory device and a method for manufacturing a semiconductor memory device that can efficiently supply voltage. [Solution] The semiconductor memory device of this embodiment includes a first stack and a second stack in a first region. It also includes a first via contact electrode disposed in a second region adjacent to the first region and having a height of at least half the height of the first stack in the stacking direction, and a second via contact electrode disposed on the first via contact electrode in the stacking direction of the second region, electrically connected to the first via contact electrode, and having a height of at least half the height of the second stack in the stacking direction. The diameter of the surface of the second via contact electrode facing the first via contact electrode is larger than the diameter of the surface of the first via contact electrode facing the second via contact electrode.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device.

Background Art

[0002] There has been proposed a three-dimensional semiconductor memory device in which a memory hole is formed in a laminate in which a plurality of wiring layers are laminated via an insulating layer on a substrate, and a silicon body is provided in the memory hole. Further, a technique has been proposed in which a control circuit for this three-dimensional memory cell array is provided directly below or directly above the memory cell array.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Summary of the Invention

Problems to be Solved by the Invention

[0004] In one embodiment of the present invention, there is provided a semiconductor memory device and a method for manufacturing a semiconductor memory device that can efficiently supply voltage.

Means for Solving the Problems

[0005] The semiconductor memory device of this embodiment includes a first laminate in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked in a first region, and a second laminate disposed on the first laminate in the stacking direction of the first laminate, in which a plurality of second conductive layers and a plurality of second insulating layers are alternately stacked. It also includes a first via contact electrode disposed in a second region adjacent to the first region and having a height of at least half the height of the first laminate in the stacking direction, and a second via contact electrode disposed on the first via contact electrode in the stacking direction of the second region, electrically connected to the first via contact electrode, and having a height of at least half the height of the second laminate in the stacking direction. The diameter of the surface of the second via contact electrode facing the first via contact electrode is larger than the diameter of the surface of the first via contact electrode facing the second via contact electrode. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example configuration of a semiconductor memory device in the first embodiment. [Figure 2] A perspective view showing an example of the appearance of a semiconductor memory device in the first embodiment. [Figure 3A] A cross-sectional view showing an example of the configuration of a semiconductor memory device in the first embodiment. [Figure 3B] A cross-sectional view showing an example of the configuration of a semiconductor memory device in the first embodiment. [Figure 4A] A cross-sectional view showing an example of the configuration of a semiconductor memory device in the first embodiment. [Figure 4B] A cross-sectional view showing an example of the configuration of a semiconductor memory device in the first embodiment. [Figure 4C] A cross-sectional view showing an example of the configuration of a semiconductor memory device in the first embodiment. [Figure 4D] A cross-sectional view showing an example of the configuration of a semiconductor memory device in the first embodiment. [Figure 5] A cross-sectional view showing an example of the cross-sectional structure of the memory layer during manufacturing in the first embodiment. [Figure 6] A cross-sectional view showing an example of the cross-sectional structure of the memory layer during manufacturing in the first embodiment. [Figure 7] Cross-sectional view showing an example of a cross-sectional structure during the manufacture of the memory layer in the first embodiment. [Figure 8] Cross-sectional view showing an example of a cross-sectional structure during the manufacture of the memory layer in the first embodiment. [Figure 9] Cross-sectional view showing an example of a cross-sectional structure during the manufacture of the memory layer in the first embodiment. [Figure 10] Cross-sectional view showing an example of a cross-sectional structure during the manufacture of the memory layer in the first embodiment. [Figure 11] Cross-sectional view showing an example of a cross-sectional structure during the manufacture of the memory layer in the first embodiment. [Figure 12] Cross-sectional view showing an example of a cross-sectional structure during the manufacture of the memory layer in the first embodiment. [Figure 13] Cross-sectional view showing an example of a cross-sectional structure during the manufacture of the memory layer in the first embodiment. [Figure 14] Cross-sectional view showing an example of a cross-sectional structure during the manufacture of the memory layer in the first embodiment. [Figure 15] Cross-sectional view showing an example of a cross-sectional structure during the manufacture of the memory layer in the first embodiment. [Figure 16] Cross-sectional view showing an example of a cross-sectional structure during the manufacture of the first CMOS layer in the first embodiment. [Figure 17] Cross-sectional view showing an example of a cross-sectional structure during the manufacture of the first CMOS layer in the first embodiment. [Figure 18] Cross-sectional view showing an example of a cross-sectional structure during the manufacture of the first CMOS layer in the first embodiment. [Figure 19] Cross-sectional view showing an example of the bonding process of the memory layer and the first CMOS layer in the first embodiment. [Figure 20] Cross-sectional view showing an example of the bonding process of the memory layer and the first CMOS layer in the first embodiment. [Figure 21] Cross-sectional view showing an example of the bonding process of the memory layer and the first CMOS layer in the first embodiment. [Figure 22] Cross-sectional view showing an example of the bonding process of the memory layer and the first CMOS layer in the first embodiment. [Figure 23] Cross-sectional view showing an example of the bonding process of the first CMOS layer and the second CMOS layer in the first embodiment. [Figure 24] Cross-sectional view showing an example of the bonding process of the first CMOS layer and the second CMOS layer in the first embodiment. [Figure 25] Cross-sectional view showing an example of the bonding process of the first CMOS layer and the second CMOS layer in the first embodiment. [Figure 26] Cross-sectional view showing a configuration example of the semiconductor memory device 1 in the second embodiment. [Figure 27] Cross-sectional view showing an example of the cross-sectional structure during the manufacture of the memory layer in the second embodiment. [Figure 28] Perspective view showing an example of the appearance of the semiconductor memory device in the third embodiment. [Figure 29] Cross-sectional view showing a configuration example of the semiconductor memory device in the third embodiment. [Figure 30] Cross-sectional view showing an example of the cross-sectional structure during the manufacture of the memory layer in the third embodiment. [Figure 31] Cross-sectional view showing an example of the cross-sectional structure during the manufacture of the memory layer in the third embodiment. [Figure 32] Cross-sectional view showing an example of the cross-sectional structure during the manufacture of the memory layer in the third embodiment. [Figure 33] Cross-sectional view showing an example of the cross-sectional structure during the manufacture of the memory layer in the third embodiment. [Figure 34] Cross-sectional view showing an example of the bonding process of the memory layer and the third CMOS layer in the third embodiment. [Figure 35] Cross-sectional view showing an example of the bonding process of the memory layer and the third CMOS layer in the third embodiment. [Figure 36] Cross-sectional view showing a configuration example of the semiconductor memory device in a modified example of the third embodiment. [Figure 37] Perspective view showing an example of the appearance of the semiconductor memory device in the fourth embodiment. [Figure 38] Cross-sectional view showing a configuration example of the semiconductor memory device in the fourth embodiment. [Figure 39]A cross-sectional view showing an example of the bonding process between the second memory layer and the first CMOS layer in the fourth embodiment. [Figure 40] A cross-sectional view showing an example of the bonding process between the second memory layer and the first CMOS layer in the fourth embodiment. [Figure 41] A cross-sectional view showing an example of the bonding process between the second memory layer and the first CMOS layer in the fourth embodiment. [Figure 42] A cross-sectional view showing an example of the bonding process between the second memory layer and the first CMOS layer in the fourth embodiment. [Figure 43] A cross-sectional view showing an example of the bonding process between the second memory layer and the memory layer in the fourth embodiment. [Figure 44] A cross-sectional view showing an example of the bonding process between the second memory layer and the memory layer in the fourth embodiment. [Figure 45] A cross-sectional view showing an example of the bonding process between the second memory layer and the memory layer in the fourth embodiment. [Figure 46] A cross-sectional view showing an example of the bonding process between the second memory layer and the memory layer in the fourth embodiment. [Figure 47] A cross-sectional view showing an example of the configuration of a semiconductor memory device in the fourth embodiment. [Figure 48] A perspective view showing an example of the appearance of a semiconductor memory device in the fifth embodiment. [Figure 49] A cross-sectional view showing an example configuration of a semiconductor memory device in the fifth embodiment. [Figure 50] A cross-sectional view showing an example of the bonding process between the memory layer and the second memory layer in the fifth embodiment. [Figure 51] A cross-sectional view showing an example of the bonding process between the memory layer and the second memory layer in the fifth embodiment. [Figure 52] A cross-sectional view showing an example of the bonding process between the memory layer and the second memory layer in the fifth embodiment. [Figure 53] A cross-sectional view showing an example of the bonding process between the second memory layer and the third CMOS layer in the fifth embodiment. [Figure 54] A cross-sectional view showing an example of the bonding process between the second memory layer and the third CMOS layer in the fifth embodiment. [Figure 55]A cross-sectional view showing an example of the bonding process between the second memory layer and the third CMOS layer in the fifth embodiment. [Figure 56] A cross-sectional view showing an example of the configuration of a semiconductor memory device in a modified version of the fifth embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] (First Embodiment) The semiconductor memory device in the first embodiment comprises memory cells and CMOS circuits for accessing the memory cells. The semiconductor memory device has a structure in which the CMOS circuits are arranged on a plurality of stacked substrates. Details of the first embodiment will be described below.

[0009] Figure 1 is a block diagram showing an example configuration of the semiconductor memory device 1 in the first embodiment. The semiconductor memory device 1 in this embodiment is controlled by an external controller 2. The semiconductor memory device 1 in this embodiment is, for example, a NAND flash memory capable of storing data non-volatilely.

[0010] The semiconductor memory device 1 includes, for example, a memory cell array 3, an input / output circuit 4, a logic control circuit 5, a register 6, a sequencer 7, a voltage generation circuit 8, a row decoder 9, and a sense amplifier 10.

[0011] The memory cell array 3 includes a plurality of non-volatile memory cells (not shown) associated with word lines and bit lines.

[0012] The input / output circuit 4 transmits and receives signals DQ<7:0> (not shown) and data strobe signals DQS and / DQS to and from the controller 2. The input / output circuit 4 transfers the command and address within the signal DQ<7:0> (not shown) to the register 6. The input / output circuit 4 also transmits and receives write data and read data to and from the sense amplifier 10.

[0013] The logic control circuit 5 receives the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals RE and RE, and write protect signal / WP from the controller 2. The logic control circuit 5 also forwards the ready busy signal / RB to the controller 2 to notify the external system of the state of the semiconductor memory device 1.

[0014] The voltage generation circuit 8 generates the voltages necessary for operations such as writing, reading, and erasing data, based on instructions from the sequencer 7.

[0015] The row decoder 9 receives the block address and row address within the address from register 6, selects the corresponding block based on the block address, and selects the corresponding word line based on the row address.

[0016] When reading data, the sense amplifier 10 senses the read data read from the memory cell onto the bit line and transfers the sensed read data to the input / output circuit 4. When writing data, the sense amplifier 10 transfers the write data to be written to the memory cell via the bit line.

[0017] Figure 2 is a perspective view showing an example of the appearance of the semiconductor memory device 1 in the first embodiment. The semiconductor memory device 1 has a structure in which, for example, a memory layer 200, a first CMOS layer 300, and a second CMOS layer 400 are stacked in order from top to bottom in the Z direction. The memory layer 200 is included in, for example, the first chip. The first CMOS layer 300 is included in, for example, the second chip. The second CMOS layer 400 is included in, for example, the third chip.

[0018] In the Z direction, the first CMOS layer 300 and the second CMOS layer 400 may each have a first substrate 30 and a second substrate 40, respectively, as shown in Figure 3 and later, below the CMOS layer. Also, in the Z direction, the memory layer 200 may have a wiring layer above the memory layer. Note that the wiring layer in the memory layer 200 includes a layer formed on the memory after the bonding process of the memory layer 200 and the first CMOS layer 300, which will be described later. The wiring layer includes, for example, a plurality of external pads PD used to connect the semiconductor memory device 1 and the controller 2. The external pads PD are connected to the input / output circuit 4 and are exposed on the surface of the semiconductor memory device 1.

[0019] The first CMOS layer 300 includes a CMOS circuit formed using a first substrate 30 (not shown). The second CMOS layer 400 includes a CMOS circuit formed using a second substrate 40 (not shown). The combination of the first CMOS layer 300 and the second CMOS layer 400 includes, for example, an input / output circuit 4, a logic control circuit 5, a register 6, a sequencer 7, a voltage generation circuit 8, a row decoder 9, and a sense amplifier 10. The memory layer 200 includes a memory cell array 3. The second CMOS layer 400 includes, for example, a CMOS circuit capable of high-speed operation. The high-speed CMOS circuit is, for example, the input / output circuit 4.

[0020] In the semiconductor memory device 1, the memory layer 200, the first CMOS layer 300, and the second CMOS layer 400 are bonded together. At this time, the contact (boundary) portion between the memory layer 200 and the first CMOS layer 300, and the contact (boundary) portion between the first substrate 30 and the second CMOS layer 400, each form a bonding surface. When the memory layer 200 and the first CMOS layer 300 are bonded together, the memory cell array 3 in the memory layer 200 and the CMOS circuit in the first CMOS layer 300 may be sandwiched between the wiring layer and the first substrate 30. Also, when the first substrate 30 and the second CMOS layer 400 are bonded together, the CMOS circuit in the second CMOS layer 400 may be sandwiched between the first substrate 30 and the second substrate 40. Hereinafter, the bonding of the memory layer 200 to the first CMOS layer 300, or the bonding of the first CMOS layer 300 to the second CMOS layer 400, will be referred to as the "bonding process".

[0021] Figures 3A and 3B are cross-sectional views showing an example configuration of the semiconductor memory device 1 in the first embodiment. Figure 4A is a cross-sectional view showing an example configuration of the semiconductor memory device 1 in the first embodiment, illustrating the peripheral region RP. Figure 4B is a top view of Figure 4A as seen from the Z direction. Figure 4C is an XY plan view of position AA' as seen in the Z direction in the direction of the arrow. Figure 4D is an XY plan view of position BB' as seen in the Z direction in the direction of the arrow.

[0022] The memory layer 200 and the first CMOS layer 300 are bonded together by the contact between the bonding pad 25 and the bonding pad 35, which will be described later. In addition, an oxide film (not shown) may be provided on the bonding surface between the memory layer 200 and the first CMOS layer 300 together with the bonding pad, and the memory layer 200 and the first CMOS layer 300 may be bonded together by the oxide film and the bonding pad.

[0023] The first CMOS layer 300 and the second CMOS layer 400 each have oxide films 39 and 49, described later, on their bonding surfaces. The first CMOS layer 300 and the second CMOS layer 400 may be bonded together by contact between the oxide films 39 and 49. In addition, in the peripheral region RP, described later, the first CMOS layer 300 and the second CMOS layer 400 may be bonded together by contact between the second via contact electrode CP2, described later, and the bonding pad 45 in the second CMOS layer 400, described later.

[0024] The semiconductor memory device 1 includes an insulating film 20, wiring layers 21-24, a bonding pad 25, a conductive layer 26, a diffusion suppression layer 27, an interlayer insulating film 28, a first substrate 30, wiring layers 31-33, a bonding pad 35, a diffusion suppression layer 37, an interlayer insulating film 38, an oxide film 39, a second substrate 40, wiring layers 41-43, a bonding pad 45, an interlayer insulating film 48, an oxide film 49, a first via contact electrode CP1, a second via contact electrode CP2, a third via contact electrode CP3, transistors TR1-2, and external pads PD1-2.

[0025] Furthermore, the semiconductor memory device 1 has a memory area RM and a peripheral area RP. The memory area RM is the area that includes the memory cell array 3. The peripheral area RP is located around the memory area RM and contains external pads PD1-2 and via contact electrodes CP1-3 for supplying voltage from the external pads PD1-2 to the CMOS circuit.

[0026] The memory layer 200 includes external pads PD1-2, insulating film 20, wiring layers 21-24, bonding pad 25, diffusion suppression layer 27, conductive layer 26, interlayer insulating film 28, memory pillar MP, first via contact electrode CP1, second via contact electrode CP2, and third via contact electrode CP3. The storage area RM in the memory layer 200 is included, for example, in the first area. The peripheral area RP in the memory layer 200 is included, for example, in the second area.

[0027] External pads PD1 and PD2 are provided in multiple locations in the peripheral area RP of the memory layer 200. Hereafter, external pads PD1 and PD2 may be collectively referred to as external pad PD.

[0028] The external pad PD is electrically connected to the first via contact electrode CP1 and the second via contact electrode CP2, or the third via contact electrode CP3, as described later. The external pad PD supplies voltage to the CMOS circuit formed on the first CMOS layer 300 and the second CMOS layer 400.

[0029] The insulating film 20 is formed to surround the wiring layer 21, which will be described later, and prevents the external pad PD and the wiring layer 21 from being electrically connected. The insulating film 20 includes, for example, silicon oxide (SiO2).

[0030] The first via contact electrode CP1 is formed in the peripheral region RP of the memory layer 200. The first via contact electrode CP1 is electrically connected to the external pad PD1 and also to the second via contact electrode CP2, which will be described later. Voltage is supplied from the external pad PD1 to the second CMOS layer 400 via the first via contact electrode CP1 and the second via contact electrode CP2. Multiple first via contact electrodes CP1 may be connected to one external pad PD1. When multiple first via contact electrodes CP1 are connected to one external pad PD1, these multiple first via contact electrodes CP1 are connected to one second via contact electrode CP2.

[0031] The first via contact electrode CP1 has a height of at least half the height in the Z direction of the first laminate 29A, which will be described later. More specifically, the first via contact electrode CP1 has a height that is approximately the same as the height in the Z direction of the first laminate 29A.

[0032] The first via contact electrode CP1 contains a conductor, for example, tungsten (W).

[0033] The second via contact electrode CP2 is formed in the peripheral region RP of the memory layer 200. The second via contact electrode CP2 is electrically connected to the first via contact electrode CP1 via the conductive layer 26, and is electrically connected to the external pad PD1 via the first via contact electrode CP1.

[0034] In the second via contact electrode CP2, the diameter of the surface facing the first via contact electrode CP1 is larger than the diameter of the surface facing the second via contact electrode CP2 in the first via contact electrode CP1. In this case, by connecting the second via contact electrode CP2 to the first via contact electrode CP1 via the conductive layer 26, it is possible to simultaneously connect multiple first via contact electrodes CP1, each connected to the conductive layer 26, to a single second via contact electrode CP2.

[0035] The second via contact electrode CP2 may be connected to the first via contact electrode CP1 via the conductive layer 26, or it may be in direct contact with the first via contact electrode CP1 without the conductive layer 26.

[0036] The second via contact electrode CP2 contacts the bonding pad 45 of the second CMOS layer 400, which will be described later, on the surface opposite to the surface that contacts the conductive layer 26. In other words, the second via contact electrode CP2 has a structure that penetrates a portion of the first CMOS layer 300 and the memory layer 200, which will be described later, in the Z direction. Therefore, the second via contact electrode CP2 has a height of at least half the height of the second stacked body 29B in the Z direction, which will be described later. More specifically, the second via contact electrode CP2 has a height in the Z direction that is almost the same as the height from the second stacked body 29B to the bonding surface between the first CMOS layer 300 and the second CMOS layer 400. In other words, the height of the second via contact electrode CP2 is greater than the sum of the height of the second stacked body 29B and the height of the first CMOS layer 300, in the Z direction.

[0037] The second via contact electrode CP2 contains a conductor and is made of a different material than the first via contact electrode CP1. The second via contact electrode CP2 may contain, for example, copper (Cu) or nickel-platinum (NiPt). Alternatively, the second via contact electrode CP2 may contain a material with a lower resistivity than tungsten. The following describes the case where the second via contact electrode CP2 contains copper.

[0038] Multiple third via contact electrodes CP3 are arranged in the memory layer 200. A portion of the third via contact electrodes CP3 are located in the storage area RM, and the wiring layer 22, which will be described later, is electrically connected to the wiring layer 23, which will be described later, via the third via contact electrodes CP3.

[0039] Furthermore, a portion of the third via contact electrode CP3 is located in the peripheral region RP and is electrically connected to the external pad PD2. In this case, multiple third via contact electrodes CP3 may be electrically connected to a single external pad PD2. The third via contact electrodes CP3 located in the peripheral region RP electrically connect the external pad PD2 to the first CMOS layer 300, which will be described later, for example, via the wiring layer 23, wiring layer 24, and bonding pad 25, which will be described later. In other words, voltage is supplied from the external pad PD2 to the first CMOS layer 300 via the third via contact electrode CP3. To put it another way, the third via contact electrodes CP3 in the peripheral region RP can supply voltage to the CMOS layer that is in direct contact with the layer containing the memory cell array.

[0040] The height of the third via contact electrode CP3, located in the peripheral region RP, in the Z direction is greater than the height of the first via contact electrode CP1 in the Z direction.

[0041] The third via contact electrode CP3 contains, for example, tungsten.

[0042] The conductive layer 26 is formed between the first via contact electrode CP1 and the second via contact electrode CP2. In other words, the conductive layer 26 is electrically connected to the first via contact electrode CP1 on one side and to the second via contact electrode CP2 on the side opposite to the side that is electrically connected to the first via contact electrode CP1.

[0043] The size of the conductive layer 26 in the XY plane is the same as or larger than the size of the face of the second via contact electrode CP2 facing the first via contact electrode CP1. More specifically, the conductive layer 26 may be circular or quadrilateral in the XY plane, and the diameter of the face of the conductive layer 26 in the XY plane, or the distance between opposing sides, is larger than the size of the face of the second via contact electrode CP2 facing the first via contact electrode CP1. Also, the diameter of the face of the conductive layer 26 in the XY plane, or the distance between opposing sides, is smaller than the size of the inside of the diffusion suppression layer 27, which will be described later.

[0044] The conductive layer 26 contains, for example, polysilicon (Poly-Si) or tungsten.

[0045] The diffusion suppression layer 27 is provided around the first via contact electrode CP1 and the second via contact electrode CP2. The diffusion suppression layer 27 may be provided at a height approximately the same as the height from the boundary between the wiring layer 21 and the interlayer insulating film 28 (described later) in the Z direction to the lowest wiring layer 22 in the Z direction. The diffusion suppression layer 27 is columnar and has a shape that encloses the inside. Therefore, the inside of the diffusion suppression layer 27 is filled with the interlayer insulating film 28. As shown in Figure 4C, the diffusion suppression layer 27 may be provided in a circular or quadrilateral shape in the XY plane, for example. In other words, the diffusion suppression layer 27 may be provided in a quadrilateral shape with an opening in the XY plane. The diffusion suppression layer 27 is formed so as to minimize gaps or defects that connect the inside of the diffusion suppression layer 27 to the outside of the diffusion suppression layer 27 in the XY plane. This suppresses the diffusion of metals such as copper contained in the second via contact electrode CP2 from the surrounding region RP to other regions. In other words, the height of the diffusion suppression layer 27 in the Z direction may be approximately the same as the sum of the height of the first stacked body 29A in the Z direction and the height of the second stacked body 29B in the Z direction, as described later. By forming the diffusion suppression layer 27 in a shape that surrounds the second via contact electrode CP2, the diffusion of metals such as copper into the wiring layer 21 and wiring layer 22 of the memory area RM can be suppressed. Note that the diffusion suppression layer 27 in the memory layer 200 can be omitted.

[0046] The diffusion suppression layer 27 contains, for example, tungsten.

[0047] Furthermore, as shown in Figure 3B, the diffusion suppression layer 27 may be provided in contact with the bonding pad 25. In this case, the diffusion suppression layer 27 is connected to the bonding pad 25 in the peripheral region RP via the wiring layer 23 and the wiring layer 24.

[0048] The wiring layer 21 is electrically connected to the memory pillar MP, which will be described later. The wiring layer 21 functions as part of the source line. The wiring layer 21 may contain, for example, a semiconductor layer such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). Alternatively, the wiring layer 21 may contain a metal such as tungsten, or a silicide such as tungsten silicide (WSi). Furthermore, an interlayer insulating film 28, which will be described later, is formed between the wiring layer 21 and the wiring layer 22 adjacent to the wiring layer 21.

[0049] The wiring layer 22 is formed in a position that overlaps with a portion of the first via contact electrode CP1 and the second via contact electrode CP2 when viewed from the X direction. The multiple wiring layers 22 are spaced apart from each other, and an interlayer insulating film 28, described later, is formed between adjacent wiring layers 22. In the memory area RM, the first laminate 29A is a structure in which multiple insulating layers and multiple wiring layers 22 are alternately stacked from the interlayer insulating film 28 that is formed below the wiring layer 21 in the Z direction and is in contact with the wiring layer 21. The second laminate 29B is a structure in which multiple insulating layers and multiple wiring layers 22 are alternately stacked below the first laminate 29A in the Z direction. The first laminate 29A and the second laminate 29B may have the same height or different heights in the Z direction. The wiring layer 22 is included, for example, in the first conductive layer and the second conductive layer.

[0050] The wiring layer 22, as one of the multiple electrode layers in the memory cell array 3, comprises multiple word lines and multiple select gate lines. In other words, the wiring layer 22 is formed in the memory area RM of the memory layer 200. The wiring layer 22 has a stepped structure, and each wiring layer 22 is electrically connected to the wiring layer 23 via a third via contact electrode CP3. In addition, each memory pillar MP that penetrates the multiple wiring layers 22 is electrically connected to the wiring layer 21 (source line) and the wiring layer 23. Some of the multiple wiring layers 23 are, for example, bit lines, and the bit lines are electrically connected to the memory pillar MP.

[0051] The memory pillar MP is provided in the storage area RM of the memory layer 200 so as to penetrate the wiring layer 22. The memory pillar MP is cylindrical and includes a cylindrical channel film CHL. In addition, a memory film MRL is formed around the channel film CHL in the memory pillar MP. That is, the memory film MRL has a shape in which the outer wall of the cylindrical channel film CHL is surrounded by the memory film MRL. The memory film MRL is in contact with the wiring layer 21, the wiring layer 22, and the interlayer insulating film 28, which will be described later. The channel film CHL may include a cylindrical core film containing silicon oxide (SiO2) and a channel film formed to surround the cylindrical core film. The memory film MRL may include a configuration in which a tunnel insulating film, a charge storage film, and a block insulating film, which are films in contact with the channel film CHL, are stacked.

[0052] Multiple wiring layers 23-24 are formed in the memory layer 200 in the storage area RM and the peripheral area RP.

[0053] A portion of the wiring layer 23 formed in the memory area RM is electrically connected to the memory pillar MP and functions as a bit line. Other wiring layers 23, i.e., wiring layers 23 formed throughout the entire memory layer 200, electrically connect the third via contact electrode CP3 (described later) to the bonding pad of the bonding pad 25 (described later). These multiple wiring layers 23 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper.

[0054] Multiple wiring layers 24 are provided to electrically connect the wiring layers 23 to the adhesive pads 25, which will be described later. The wiring layers 24 may include, for example, a laminated film of a barrier conductive film such as titanium nitride and a metal film such as tungsten.

[0055] Multiple wirings included in the bonding pad 25 are electrically connected to, for example, the configuration in the memory layer 200 and the configuration in the first CMOS layer 300. The bonding pad 25 includes multiple bonding pads. These multiple bonding pads 25 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper. In the following description, one bonding pad included in the memory layer 200 may be described as bonding pad 25, or multiple bonding pads included in the memory layer 200 may be described as bonding pad 25.

[0056] The interlayer insulating film 28 fills the memory layer 200 and insulates it from other elements. A portion of the interlayer insulating film 28 is formed between the wiring layer 21 and multiple wiring layers 22, preventing electrical connection between adjacent wiring layers 21 and 22, and between adjacent wiring layers 22. The interlayer insulating film 28 formed between the wiring layers 21 and 22 is layered and functions as an insulating layer.

[0057] The interlayer insulating film 28 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 28 is, for example, a silicon oxide film, or a multilayer film including a silicon oxide film and other insulating films.

[0058] The first CMOS layer 300 includes a first substrate 30, wiring layers 31-33, bonding pads 35, a diffusion suppression layer 37, an interlayer insulating film 38, an oxide film 39, and a transistor TR1. The first CMOS layer 300 includes a first CMOS circuit.

[0059] The first substrate 30 is a silicon wafer and contains, for example, p-type silicon containing p-type impurities such as boron. The surface of the first substrate 30 is provided with, for example, an N-type well region containing an N-type impurity such as phosphorus, a p-type well region containing a p-type impurity such as boron, a semiconductor substrate region without an N-type well region or a p-type well region, and an insulating region. The N-type well region and the p-type well region each function as part of a CMOS circuit, such as multiple transistors and multiple capacitors.

[0060] The wiring layers 31 to 33 are provided within the interlayer insulating film 38, which will be described later. The wiring layers 31, 32, and 33 are formed in order from the first substrate 30 side. Wiring for the first CMOS layer 300 is provided in the wiring layers 31 to 33.

[0061] In the semiconductor memory device 1, the wiring layers 31 to 33 provided in the memory area RM are electrically connected to the wiring layers 23, 24, etc. of the memory layer 200 via adhesive pads 25, 35.

[0062] The multiple wiring layers 31 to 33 may include, for example, a barrier conductive film such as titanium nitride and a laminated film of a metal film such as tungsten. Alternatively, the multiple wiring layers 31 to 33 may include, for example, a barrier conductive film such as titanium nitride, a laminated film of tantalum nitride (TaN) and tantalum (Ta), and a metal film such as copper.

[0063] Multiple wirings included in the bonding pad 35 are electrically connected to, for example, at least one of the configurations in the first CMOS layer 300 and the configurations in the memory layer 200. The bonding pad 35 includes multiple bonding pads. These multiple bonding pads 35 may include, for example, a laminated film of a barrier conductive film such as titanium nitride and a metal film such as copper. In the following, one bonding pad included in the first CMOS layer 300 may be described as bonding pad 35, or multiple bonding pads included in the first CMOS layer 300 may be described as bonding pad 35.

[0064] The adhesive pad included in the adhesive pad 35 adheres the memory layer 200 and the first CMOS layer 300 by coming into contact with the adhesive pad in the adhesive pad 25 at the bonding surface between the memory layer 200 and the first CMOS layer.

[0065] The diffusion suppression layer 37 is provided around the second via contact electrode CP2. One end of the diffusion suppression layer 37 is in contact with the bonding pad 35, for example, in the Z direction. The end opposite to the end in contact with the bonding pad 35 is in contact with at least the first substrate 30 and may penetrate the first substrate 30.

[0066] The shape of the diffusion suppression layer 37 may be the same as that of the diffusion suppression layer 27. Also, as shown in Figure 4D, in the XY plane, the size of the opening of the diffusion suppression layer 37 is larger than the plane through which the second via contact electrode CP2 penetrates the first substrate 30.

[0067] Similar to the diffusion suppression layer 27, the diffusion suppression layer 37 is formed in such a way that there are as few gaps as possible connecting the inside of the diffusion suppression layer 27 to the outside of the diffusion suppression layer 27 in the XY plane. This suppresses the diffusion of metals such as copper contained in the second via contact electrode CP2 from the surrounding region RP to other regions. In other words, because the diffusion suppression layer 37 is formed in a shape that surrounds the second via contact electrode CP2, it suppresses the diffusion of metals such as copper to the wiring layers 31-33 and transistor TR1.

[0068] The diffusion suppression layer 37 contains, for example, tungsten.

[0069] The interlayer insulating film 38 is provided on the first substrate 30. The interlayer insulating film 38 covers the circuit (for example, wiring layers 31-33) provided on the first substrate 30. The interlayer insulating film 38 may include a plurality of insulating layers.

[0070] The oxide film 39 is located below the first substrate 30 in the Z direction and is in contact with the oxide film 49 included in the second CMOS layer 400, which will be described later. The contact between the oxide film 39 and the oxide film 49, which will be described later, causes the first CMOS layer 300 and the second CMOS layer 400 to bond together. In other words, the boundary between the oxide film 39 and the oxide film 49, which will be described later, corresponds to the bonding surface between the first CMOS layer 300 and the second CMOS layer 400.

[0071] The oxide film 39 includes, for example, silicon oxide.

[0072] The transistor TR1 has a MOSFET structure including a gate electrode and source / drain regions. The source / drain regions of the MOSFET are electrically connected to the bonding pad formed on the bonding pad 35 by wiring layers 31-33.

[0073] The second CMOS layer 400 includes a second substrate 40, wiring layers 41-43, bonding pads 45, interlayer insulating film 48, oxide film 49, and transistor TR2. The second CMOS layer 400 also includes a second CMOS circuit.

[0074] The second CMOS layer 400 may include, for example, a high-speed CMOS circuit. When a high-speed CMOS circuit is included, efficient voltage supply can be achieved by lowering the resistivity of the voltage supplied from the external pad PD.

[0075] The second substrate 40 is a silicon wafer, and for example, it contains p-type silicon containing p-type impurities such as boron. The configuration of the second substrate 40 can be the same as that of the first substrate 30, so a description is omitted.

[0076] The wiring layers 41 to 43 are provided within the interlayer insulating film 48, which will be described later. The wiring layers 41, 42, and 43 are formed in that order from the second substrate 40 side. Wiring for the second CMOS layer 400 is provided in the wiring layers 41 to 43, and they are electrically connected to each other.

[0077] The materials included in the multiple wiring layers 41-43 can be the same as those in wiring layers 31-33, so their explanation is omitted.

[0078] The bonded pad 45 is electrically connected to the external pad PD1 via a first via contact electrode CP1 and a second via contact electrode CP2. The bonded pad 45 may also be electrically connected to the wiring layer 43 via a plurality of via plugs. The bonded pad 45 may include, for example, a laminated film of a barrier conductive film such as titanium nitride and a metal film such as copper. In the following description, one bonded pad included in the second CMOS layer 400 may be described as the bonded pad 45, or a plurality of bonded pads included in the second CMOS layer 400 may be described as the bonded pad 45.

[0079] The bonding pad 45 contacts the second via contact electrode CP2 at the bonding surface between the first CMOS layer 300 and the second CMOS layer 400, thereby bonding the first CMOS layer 300 and the second CMOS layer 400. The bonding pad 45 is embedded in the oxide film 49, with its surface exposed from the oxide film 49.

[0080] In the bonded pad 45, the plane on the oxide film 49 side (XY plane) is greater than or equal to the diameter of the plane on the oxide film 39 side (XY plane) in the 2-via contact electrode CP2.

[0081] The interlayer insulating film 48 is provided on the second substrate 40. The interlayer insulating film 48 can be the same as the interlayer insulating film 38, so its description is omitted.

[0082] The oxide film 49 is located above the second substrate 40 in the Z direction and is in contact with the oxide film 39.

[0083] The oxide film 49 includes, for example, silicon oxide.

[0084] The transistor TR2 has a MOSFET structure with a gate electrode, source / drain regions, etc. The source / drain regions of the MOSFET are electrically connected to the bonding pad 45 by wiring layers 41-43.

[0085] Figures 5 to 15 are cross-sectional views showing an example of the cross-sectional structure of the memory layer 200 during the manufacturing process in the first embodiment.

[0086] As shown in Figure 5, in the memory area RM of the semiconductor memory device 1, sacrificial layers 22' are stacked in a stepped manner on top of the wiring layer 21. A substrate (not shown) may be provided below the wiring layer 21. The sacrificial layer 22' is a layer that will be replaced by the wiring layer 22 in a later process, and contains, for example, silicon nitride. At this time, in the Z direction, there is space between the wiring layer 21 and the sacrificial layer 22', and multiple sacrificial layers 22' are spaced apart, and an interlayer insulating film 28 is formed between them. Also, due to the formation of the interlayer insulating film 28, the peripheral area RP in the Z direction is also aligned to almost the same height as the memory area RM. The laminate formed by the sacrificial layer 22' formed in Figure 5 and the interlayer insulating film 28 formed between the sacrificial layers 22' is referred to as the first laminate 29A. The sacrificial layer 22' formed at this time is included in the first sacrificial layer, for example. At this time, the interlayer insulating film 28 formed between the wiring layer 21 and the sacrificial layer 22', and the interlayer insulating film 28 formed between multiple sacrificial layers 22' are included in the first insulating layer. The interlayer insulating film 28 formed in the peripheral region RP is included, for example, in the first insulator.

[0087] As shown in Figure 6, multiple memory holes MH are formed in the memory region RM, penetrating the first stacked structure 29A. The memory holes MH are formed, for example, by anisotropic etching. At the same time, multiple first via contact holes CP1' are also formed in the peripheral region RP. In other words, the height of the first via contact electrode CP1 in the Z direction is almost the same as the height of the memory holes MH.

[0088] As shown in Figure 7, tungsten or the like is embedded in the first via contact hole CP1' in the peripheral region RP to form the first via contact electrode CP1.

[0089] As shown in Figure 8, a conductive layer 26 is formed on the first via contact electrode CP1 in the peripheral region RP. The conductive layer 26 is deposited, for example, on the entire surface of the memory layer 200, that is, the surface where the first via contact electrode CP1 is exposed. Subsequently, it may be etched by the RIE (Reactive Ion Etching) method and formed on the first via contact electrode CP1 in the peripheral region RP.

[0090] As shown in Figure 9, in the memory area RM of the semiconductor memory device 1, sacrificial layers 22' are stacked in a step-like manner on the first stack 29A. Furthermore, holes are formed that penetrate the second stack 29B so as to overlap with the memory holes MH formed in the first stack 29A when viewed from the Z direction, and the height of the memory holes MH in the Z direction is made greater than the height of the memory holes MH in the process shown in Figure 5. The stacking method of the sacrificial layers 22' can be the same as in the process shown in Figure 5. At this time, the multiple sacrificial layers 22' are spaced apart in the Z direction, and an interlayer insulating film 28 is formed between them. Due to the formation of the interlayer insulating film 28, the peripheral area RP in the Z direction is also aligned to almost the same height as the memory area RM. The stack formed by the sacrificial layers 22' formed in Figure 9 and the insulating layer formed between the sacrificial layers 22' is defined as the second stack 29B. The sacrificial layers 22' formed in the memory area RM in Figure 9 are included in the second sacrificial layer, for example. Furthermore, the interlayer insulating film 28 formed between the multiple sacrificial layers 22' in Figure 9 is included in the second insulating layer. The interlayer insulating film 28 formed in the peripheral region RP is included, for example, in the second insulator.

[0091] As shown in Figure 10, a memory pillar MP is formed by embedding multiple films inside the memory hole MH. The memory pillar MP includes, for example, a block insulating film, an electrostatic storage film, a tunnel insulating film, a channel film, and a core film, starting from the side in contact with the sacrificial layer 22' and the interlayer insulating film 28 and moving inward.

[0092] As shown in Figure 11, a slit 27' is formed in the peripheral region RP so as to surround the first via contact electrode CP1 and the conductive layer 26. The slit 27' is the diffusion suppression layer 27 before the material is embedded. The slit 27' can be any shape that surrounds the first via contact electrode CP1, the conductive layer 26, and the second via contact electrode CP2 formed in a later step when viewed from the Z direction, for example, a quadrilateral or circular shape. The height of the slit 27' in the Z direction is almost equal to the height of the laminate including the first laminate 29A and the second laminate 29B in the Z direction. In this case, the slit 27' is formed in the peripheral region RP when a slit (not shown) is formed in the memory region RM.

[0093] Furthermore, the slit 27' may be formed in the peripheral region RP when forming the third via contact hole CP3', which will be described later. If the slit 27' is formed at the same time as the third via contact hole CP3', the height of the slit 27' in the Z direction will be almost the same as the height of the third via contact hole CP3' in the peripheral region RP. In other words, the slit 27' can be formed at times other than those shown in Figure 12, and the height of the slit 27' formed during the third via contact hole CP3' formation process in the Z direction is greater than the height of the slit 27' in the Z direction in Figure 11.

[0094] As shown in Figure 12, the sacrificial layer 22' is removed in the memory region RM and replaced with the wiring layer 22. In addition, tungsten is embedded in the slit 27' that was formed in the peripheral region RP, forming the diffusion suppression layer 27.

[0095] As shown in Figure 13, an insulating film is formed over the entire surface of the memory layer 200, and a third via contact hole CP3' is formed in the storage area RM and the peripheral area RP. In addition, a hole is formed on the memory pillar MP to form a via plug that electrically connects to the memory pillar MP. The insulating film formed on the memory layer 200 as shown in Figure 13 is included in the interlayer insulating film 28. As mentioned above, when forming the third via contact hole CP3' in Figure 13, a slit 27' may also be formed in the peripheral area RP.

[0096] As shown in Figure 14, a tungsten-containing material is embedded in the third via contact hole CP3' and the hole on the memory pillar MP to form the third via contact electrode CP3 and the via plug.

[0097] As shown in Figure 15, an insulating film, wiring layers 23-24, via plugs, and bonding pads 25 are formed on the interlayer insulating film 28. The insulating film further formed in Figure 15 is included in the interlayer insulating film 28. With the wiring layers 23-24, via plugs, and bonding pads 25 formed in this way, the memory layer 200 becomes electrically connectable to the first CMOS layer 300, which will be described later.

[0098] Furthermore, when forming the diffusion suppression layer 27 as shown in Figure 3B, the diffusion suppression layer 27 is formed in the same way as the third via contact electrode CP3 in the peripheral region RP. In other words, the diffusion suppression layer 27 may be formed at the same time as the third via contact electrode CP3 in the peripheral region RP shown in Figures 13-15. In this case, the diffusion suppression layer 27 is formed to contact the bonding pad 25 via the wiring layers 23 and 24.

[0099] Figures 16 to 18 are cross-sectional views showing an example of the cross-sectional structure of the first CMOS layer 300 during the manufacturing process in the first embodiment.

[0100] As shown in Figure 16, a transistor TR1, wiring layers 31-33, an interlayer insulating film 38, and via plugs connecting the wiring layers 31-33 are formed on the first substrate 30.

[0101] As shown in Figure 17, in the peripheral region RP, an interlayer insulating film 38 and a diffusion suppression layer 37 penetrating the first substrate 30 are formed. The diffusion suppression layer 37 only needs to have a shape that surrounds the second via contact electrode CP2 formed in a later step when viewed from the Z direction, for example, a quadrilateral shape or a circular shape.

[0102] As shown in Figure 18, a bonding pad 35 is formed on the first CMOS layer 300. The bonding pad 35 is in contact with via plugs and a diffusion suppression layer 37. By electrically connecting the wiring layers 31-33 to the bonding pad 35, the first CMOS layer 300 is electrically connected to the memory layer 200 and the external pad PD, which will be described later.

[0103] Figures 19 to 22 are cross-sectional views showing an example of the bonding process between the memory layer 200 and the first CMOS layer 300 in the first embodiment.

[0104] As shown in Figure 19, the memory layer 200 and the first CMOS layer 300 are arranged facing each other. In other words, the memory layer 200 and the first CMOS layer 300 are arranged so that the bonding pad 25 formed on the memory layer 200 and the bonding pad 35 formed on the first CMOS layer 300 face each other.

[0105] As shown in Figure 20, a bonding process is performed to bond the memory layer 200 and the first CMOS layer 300 together. An oxide film 39 is also formed on the side of the first CMOS layer opposite to the bonding surface with the memory layer 200. Bonding pads 25 and 35 correspond to each other and are electrically connected. This electrically connects the memory layer 200 and the first CMOS layer 300.

[0106] As shown in Figure 21, a second via contact hole CP2' is formed in the memory layer 200 and the peripheral region RP of the first CMOS layer 300 after the bonding process. The second via contact hole CP2' is the second via contact electrode CP2 before the copper-containing material is embedded. The second via contact hole CP2' is formed from the oxide film 39 side of the first CMOS layer 300, penetrates the first CMOS layer 300, and is formed up to the conductive layer 26 of the memory layer 200. In other words, the second via contact hole CP2' is formed by anisotropic etching so as to penetrate the oxide film 39, the first substrate 30, the interlayer insulating film 38, and a portion of the interlayer insulating film 28, and reach the conductive layer 26. The conductive layer 26 has a lower etching rate compared to the interlayer insulating film 28 and is less susceptible to anisotropic etching. Thus, the conductive layer 26 also functions as an etching stopper layer. Therefore, the anisotropic etching to form the second via contact hole CP2' can be stopped after reaching the conductive layer 26 but before penetrating it. When viewed from the negative Z direction, the second via contact hole CP2' is formed to overlap with the conductive layer 26 and the first via contact electrode CP1. In other words, when viewed from the negative Z direction, the conductive layer 26 is exposed.

[0107] As shown in Figure 22, a copper-containing material is embedded in the second via contact hole CP2' to form the second via contact electrode CP2. The second via contact electrode CP2 is formed from the oxide film 39 side of the first CMOS layer 300, penetrates the first CMOS layer 300, and extends to the conductive layer 26 of the memory layer 200. In other words, the second via contact electrode CP2 is formed to penetrate the oxide film 39, the first substrate 30, the interlayer insulating film 38, and the interlayer insulating film 28, and contacts the conductive layer 26.

[0108] When a copper-containing material is embedded in the second via contact hole CP2', the diffusion suppression layer 27 is provided so as to surround the second via contact hole CP2', thereby suppressing the diffusion of copper to other areas in the memory layer 200 and the first CMOS layer 300.

[0109] Figures 23 to 25 are cross-sectional views showing an example of the bonding process of the first CMOS layer 300 and the second CMOS layer 400 in the first embodiment.

[0110] As shown in Figure 23, the first CMOS layer 300 and the second CMOS layer 400 are arranged to face each other. In other words, the first CMOS layer 300 and the second CMOS layer 400 are arranged so that the oxide film 39 formed on the first CMOS layer 300 and the second via contact electrode CP2 face each other, and the oxide film 49 formed on the second CMOS layer 400 and the bonding pad 45 face each other.

[0111] As shown in Figure 24, a bonding process is performed to bond the first CMOS layer 300 and the second CMOS layer 400 together. The bonding pad 45 and the second via contact electrode CP2 face each other, and the bonding process electrically connects the bonding pad 45 and the second via contact electrode CP2. This allows the second CMOS layer 400 to be electrically connected to the external pad PD1, which will be described later. In addition, the oxide film 39 and oxide film 49 come into contact, bonding the memory layer 200 and the first CMOS layer 300 to the second CMOS layer 400.

[0112] As shown in Figure 25, an insulating film 20 and external pads PD1 and PD2 are formed on the wiring layer 21 of the memory layer 200 by etching the wiring layer 21 or the like.

[0113] The insulating film 20 is formed so as to surround the external pads PD1 and PD2 when viewed from the Z direction, and the insulating film 20 electrically insulates the wiring layer 21 from the external pads PD1 and PD2.

[0114] External pads PD1 and PD2 are located in the peripheral region RP and are electrically connected to the first via contact electrode CP1 and the third via contact electrode CP3. The second via contact electrode CP2 is also connected to external pad PD1 via the first via contact electrode CP1. The electrical connection between external pad PD1 and the first via contact electrode CP1 and the second via contact electrode CP2 allows voltage to be supplied from external pad PD1 to the second CMOS layer 400. Furthermore, the electrical connection between external pad PD2 and the third via contact electrode CP3 allows voltage to be supplied from external pad PD2 to the first CMOS layer 300.

[0115] According to the first embodiment, after bonding the memory layer 200 and the first CMOS layer 300, a second via contact electrode CP2 is formed from the side of the first CMOS layer 300 opposite to the bonding surface, penetrating the first CMOS layer 300 and partway through the memory layer 200. Furthermore, one second via contact electrode CP2 can be formed corresponding to multiple first via contact electrodes CP1, and a second via contact electrode CP2 with a larger diameter in the XY plane than the first via contact electrode CP1 can be formed. Moreover, by forming the first via contact electrode CP1 and the second via contact electrode CP2 separately, a material with lower resistivity than the first via contact electrode CP1 can be used for the second via contact electrode CP2. In other words, a second via contact hole CP2' that penetrates the first CMOS layer 300 from the first substrate 30 side and reaches partway through the memory layer 200 is formed all at once, and the second via contact electrode CP2 is formed using a material with lower resistivity than tungsten.

[0116] In this embodiment, by forming the second via contact electrode CP2 as described above, the resistance when supplying voltage from the external pad PD1 to the second CMOS layer 400 can be reduced. More specifically, when a high-speed CMOS circuit is provided in the second CMOS layer 400, by providing the low-resistance second via contact electrode CP2, the voltage supply from the external pad PD to the CMOS circuit in the second CMOS layer 400 can be performed efficiently.

[0117] Furthermore, in this embodiment, the first CMOS layer 300 and the external pad PD2 are connected via a third via contact electrode CP3, and the second CMOS layer 400 and the external pad PD1 are connected via a first via contact electrode CP1 and a second via contact electrode CP2. This makes it possible to reduce the space of the peripheral region RP compared to connecting the first via contact electrode CP1 and the second via contact electrode CP2 to all external pads PD. In other words, the connection between the first CMOS layer 300 and the external pad PD2 can also reduce the space of the peripheral region RP in this embodiment compared to the case where the connection is made via a first via contact electrode CP1 and a second via contact electrode CP2.

[0118] Furthermore, the connection between the second CMOS layer 400 and the external pad PD1 may be made not only by the first via contact electrode CP1 and the second via contact electrode CP2, but also via the third via contact electrode CP3.

[0119] In this embodiment, a first laminate 29A is formed in the storage area RM of the memory layer 200, and an interlayer insulating film 28 is also formed in the peripheral area RP. Then, a conductive layer 26 is formed in the peripheral area RP on the interlayer insulating film 28 formed at this time. By forming the conductive layer 26 during the lamination of the wiring layer 22, the impact on the subsequent formation of the wiring layer 21, insulating film 20, and external pad PD can be suppressed.

[0120] In the semiconductor memory device 1, as the stacking of wiring layers 22 in the memory layer 200 increases, the aspect ratio of the via contact electrodes in the peripheral region RP also increases. In this case, the stacking of wiring layers 22 in the memory layer 200 may be divided into multiple stacks, and these multiple stacks may be stacked sequentially. In this embodiment, the first via contact electrode CP1 is formed at the same timing as the process of forming the first stacked stack in the memory layer 200. This allows the first via contact electrode CP1 to be formed without requiring an additional process, even when the stacking of wiring layers 22 in the memory layer 200 increases further. Furthermore, since the second via contact electrode CP2 can be formed with a larger diameter in the XY plane than the first via contact electrode CP1, it is less affected than the first via contact electrode CP1 even when the stacking of wiring layers 22 increases.

[0121] As the number of layers of wiring layers 22 increases, the proportion of the second via contact electrode CP2 used to electrically connect the external pad PD and the second CMOS layer 400 increases. Therefore, as the number of layers of wiring layers 22 increases, the proportion of the second via contact electrode CP2 becomes relatively larger, and the resistance when supplying voltage from the external pad PD to the second CMOS layer 400 becomes relatively lower.

[0122] (Second Embodiment) The configuration of the semiconductor memory device in the second embodiment differs in the configuration of the memory layer 200.

[0123] Figure 26 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 in the second embodiment.

[0124] The semiconductor memory device 1 in the second embodiment differs from the first embodiment in that a third stacked structure 29C is formed in the storage area RM of the memory layer 200.

[0125] The semiconductor memory device 1 includes an insulating film 20, wiring layers 21-24, a bonding pad 25, a conductive layer 26, a diffusion suppression layer 27, an interlayer insulating film 28, a first substrate 30, wiring layers 31-33, an interlayer insulating film 38, an oxide film 39, a second substrate 40, wiring layers 41-43, an interlayer insulating film 48, an oxide film 49, a first via contact electrode CP1, a second via contact electrode CP2, a third via contact electrode CP3, and transistors TR1-2.

[0126] Furthermore, the semiconductor memory device 1 has a memory area RM and a peripheral area RP. The memory area RM is the area that includes the memory cell array 3. The peripheral area RP is located around the memory area RM and contains an external pad PD and via contact electrodes for supplying voltage supplied from the external pad PD to the CMOS circuit.

[0127] The memory layer 200 includes external pads PD1-2, insulating film 20, wiring layers 21-24, bonding pad 25, conductive layer 26, diffusion suppression layer 27, interlayer insulating film 28, memory pillar MP, first via contact electrode CP1, second via contact electrode CP2, and third via contact electrode CP3.

[0128] The external pad PD, insulating film 20, wiring layer 21, wiring layer 23, bonding pad 25, conductive layer 26, interlayer insulating film 28, third via contact electrode CP3, and memory pillar MP may be the same as in the first embodiment, so their description is omitted.

[0129] The first via contact electrode CP1 is formed in the peripheral region RP of the memory layer 200. The first via contact electrode CP1 may be the same as in the first embodiment and has a height of at least half the height in the Z direction of the first stacked body 29A, which will be described later.

[0130] The second via contact electrode CP2 is formed in the peripheral region RP of the memory layer 200. The second via contact electrode CP2 may be the same as in the first embodiment, wherein the diameter of the surface of the second via contact electrode CP2 facing the first via contact electrode CP1 is larger than the diameter of the surface of the first via contact electrode CP1 facing the second via contact electrode CP2.

[0131] The second via contact electrode CP2 has a height of at least half the height of the second laminate 29B in the Z direction, as described later, similar to the first embodiment. More specifically, the second via contact electrode CP2 has a height in the Z direction that is almost the same as the height from the second laminate 29B to the bonding surface between the first CMOS layer 300 and the second CMOS layer 400. In the second embodiment, the wiring layer 22, described later, includes a third laminate 29C. Therefore, the height of the second via contact electrode CP2 in the Z direction is higher compared to the first embodiment.

[0132] The wiring layer 22 may be the same as in the first embodiment, and is formed in a position that overlaps with a portion of the first via contact electrode CP1 and the second via contact electrode CP2 when viewed from the X direction. The multiple wiring layers 22 are spaced apart from each other, and an interlayer insulating film 28, described later, is formed between adjacent wiring layers 22. In the memory area RM, the first laminate 29A is a structure in which multiple insulating layers and multiple wiring layers 22 are alternately stacked from the interlayer insulating film 28 that is formed below the wiring layer 21 in the Z direction and is in contact with the wiring layer 21. The second laminate 29B is a structure in which multiple insulating layers and wiring layers 22 are alternately stacked below the first laminate 29A in the Z direction. In the second embodiment, the third laminate 29C is a structure in which multiple insulating layers and wiring layers 22 are alternately stacked below the second laminate 29B in the Z direction. The first laminate 29A, the second laminate 29B, and the third laminate 29C may have the same height in the Z direction or may have different heights.

[0133] The configurations of the first CMOS layer 300 and the second CMOS layer 400 may be the same as in the first embodiment, so their description will be omitted.

[0134] Figure 27 is a cross-sectional view showing an example of the cross-sectional structure of the memory layer 200 during the manufacturing process in the second embodiment.

[0135] The manufacturing process until the second laminate 29B shown in Figure 27 is formed is the same as the process shown in Figures 5 to 9 of the first embodiment, so the explanation will be omitted. In the second embodiment, a third laminate 29C is further laminated on top of the second laminate 29B.

[0136] As shown in Figure 27, in the memory area RM of the semiconductor memory device 1, sacrificial layers 22' are stacked in a step-like manner on the second stack 29B. The stack formed by the sacrificial layers 22' formed on the second stack 29B and the interlayer insulating film 28 formed between the sacrificial layers 22' is defined as the third stack 29C. Furthermore, holes are formed that penetrate the first stack 29A, the second stack 29B, and the third stack 29C when viewed from the Z direction. The stacking method of the sacrificial layers 22' may be the same as in the first embodiment. In this case, the multiple sacrificial layers 22' are spaced apart in the Z direction, and the interlayer insulating film 28 is formed between them. Due to the formation of the interlayer insulating film 28, the height of the peripheral area RP in the Z direction is the same as the height of the memory area RM.

[0137] From this point onward, the semiconductor memory device 1 of the second embodiment, as shown in Figure 26, can be formed by manufacturing using the same process as shown in Figures 10 to 25.

[0138] In this second embodiment of the semiconductor memory device, the same effects as in the first embodiment can be obtained.

[0139] As the number of layers in the wiring layer 22 increases, the proportion of the second via contact electrode CP2 when electrically connecting the external pad PD and the second CMOS layer 400 increases. Therefore, in this embodiment, since the third layer 29C is included in the wiring layer 22, the proportion of the second via contact electrode CP2 becomes relatively larger, and the resistance when supplying voltage from the external pad PD to the second CMOS layer 400 becomes relatively lower.

[0140] (Third embodiment) The semiconductor memory device in the third embodiment comprises a memory cell and a CMOS circuit for accessing the memory cell. Details of the third embodiment are described below.

[0141] The configuration example of the semiconductor memory device in the third embodiment may be the same as in the first embodiment, so a brief explanation will be given.

[0142] Figure 28 is a perspective view showing an example of the appearance of the semiconductor memory device 1 in the third embodiment. The semiconductor memory device 1 has a structure in which, for example, a memory layer 200 and a third CMOS layer 500 are stacked in order from top to bottom in the Z direction.

[0143] The third embodiment differs from the first embodiment in that it has one third CMOS layer 500 for each memory layer 200.

[0144] Figure 29 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 in the third embodiment.

[0145] In the Z direction, the third CMOS layer 500 may have a third substrate 50 beneath the CMOS layer. Also in the Z direction, the memory layer 200 may have a wiring layer above the memory layer. The wiring layer in the memory layer 200 includes layers formed on the memory after the bonding process between the memory layer 200 and the third CMOS layer 500, which will be described later. The wiring layer includes, for example, a plurality of external pads PD used to connect the semiconductor memory device 1 and the controller 2.

[0146] The third CMOS layer 500 includes a CMOS circuit formed using the third substrate 50. The third CMOS layer 500 includes, for example, an input / output circuit 4, a logic control circuit 5, a register 6, a sequencer 7, a voltage generation circuit 8, a row decoder 9, and a sense amplifier 10. In other words, in the third CMOS layer 500 of the third embodiment, the CMOS circuit that was divided into two in the first embodiment is included in a single CMOS layer. The memory layer 200 includes a memory cell array 3.

[0147] In the semiconductor memory device 1, the memory layer 200 and the third CMOS layer 500 are bonded together. At this time, the contact (boundary) portion between the memory layer 200 and the third CMOS layer 500 is the bonding surface. When the memory layer 200 and the third CMOS layer 500 are bonded together, the memory cell array 3 in the memory layer 200 and the CMOS circuit in the third CMOS layer 500 may be sandwiched between the wiring layer and the third substrate 50. Hereinafter, the process of bonding the memory layer 200 and the third CMOS layer 500 will be referred to as the "bonding process".

[0148] The memory layer 200 and the third CMOS layer 500 are bonded together by the contact between the bonding pad 25 and the bonding pad 55, which will be described later. Alternatively, the memory layer 200 and the third CMOS layer 500 are bonded together by the contact between the second via contact electrode CP2, which will be described later, and the bonding pad 55. Furthermore, an oxide film (not shown) is provided on the bonding surface between the memory layer 200 and the third CMOS layer 500 along with the bonding pad, and the memory layer 200 and the third CMOS layer 500 may be bonded together by the oxide film and the bonding pad.

[0149] The semiconductor memory device 1 includes an insulating film 20, wiring layers 21-24, a bonding pad 25, a conductive layer 26, a diffusion suppression layer 27, an interlayer insulating film 28, a third substrate 50, wiring layers 51-53, a bonding pad 55, an interlayer insulating film 58, a first via contact electrode CP1, a second via contact electrode CP2, a third via contact electrode CP3, a transistor TR3, and an external pad PD3.

[0150] The memory layer 200 includes an external pad PD3, an insulating film 20, wiring layers 21-24, a bonding pad 25, a conductive layer 26, a diffusion suppression layer 27, an interlayer insulating film 28, a memory pillar MP, a first via contact electrode CP1, a second via contact electrode CP2, and a third via contact electrode CP3.

[0151] Multiple external pads PD3 are provided in the peripheral area RP of the memory layer 200.

[0152] The external pad PD3 is electrically connected to the first via contact electrode CP1 and the second via contact electrode CP2, which will be described later, and supplies voltage to the CMOS circuit formed on the third CMOS layer 500.

[0153] The insulating film 20, wiring layers 21-24, bonding pad 25, conductive layer 26, diffusion suppression layer 27, interlayer insulating film 28, and memory pillar MP can be the same as in the first embodiment, so their description is omitted.

[0154] The first via contact electrode CP1 is formed in the peripheral region RP of the memory layer 200. The first via contact electrode CP1 may be the same as in the first embodiment. The first via contact electrode CP1 is electrically connected to the external pad PD3 and is also electrically connected to the second via contact electrode CP2, which will be described later. Voltage is supplied from the external pad PD3 to the third CMOS layer 500 via the first via contact electrode CP1 and the second via contact electrode CP2.

[0155] The first via contact electrode CP1 is formed in the peripheral region RP, similar to the first embodiment, and has a height of at least half the height in the Z direction of the first laminate 29A. More specifically, the first via contact electrode CP1 has a height approximately the same as the height in the Z direction of the first laminate 29A.

[0156] The second via contact electrode CP2 is formed in the peripheral region RP of the memory layer 200.

[0157] In the second via contact electrode CP2, the diameter of the surface facing the first via contact electrode CP1 is larger than the diameter of the surface facing the second via contact electrode CP2 in the first via contact electrode CP1.

[0158] The second via contact electrode CP2 contacts the bonding pad 55 of the third CMOS layer 500, which will be described later, on the surface opposite to the surface that contacts the conductive layer 26. In other words, the second via contact electrode CP2 has a structure that penetrates a portion of the memory layer 200 in the Z direction. That is, the second via contact electrode CP2 has a height of at least half the height of the second stacked body 29B in the Z direction, which will be described later. More specifically, the second via contact electrode CP2 has a height in the Z direction that is almost the same as the height from the second stacked body 29B to the bonding surface between the memory layer 200 and the third CMOS layer 500. In other words, the second via contact electrode CP2 has a height greater than the height of the second stacked body 29B in the Z direction.

[0159] The third via contact electrode CP3 may be the same as in the first embodiment, and multiple electrodes are arranged in the memory area RM.

[0160] The first stacked body 29A and the second stacked body 29B in the memory area RM may be the same as in the first embodiment.

[0161] The third CMOS layer 500 includes a third substrate 50, wiring layers 51-53, bonding pads 55, interlayer insulating film 58, oxide film 59, and transistor TR3.

[0162] The third substrate 50 can be the same as the first substrate 30 or the second substrate 40, so its explanation is omitted.

[0163] The wiring layers 51 to 53 are provided within the interlayer insulating film 58, which will be described later. The wiring layers 51, 52, and 53 are formed in order from the third substrate 50 side. Wiring for the third CMOS layer 500 is provided in the wiring layers 51 to 53.

[0164] In the semiconductor memory device 1, the wiring layers 51 to 53 provided in the memory area RM are electrically connected to the wiring layers 23, 24, etc. of the memory layer 200 via bonding pads 25 and 55.

[0165] The multiple wiring layers 51 to 53 may include, for example, a laminated film of a barrier conductive film such as titanium nitride and a metal film such as tungsten. Alternatively, the multiple wiring layers 51 to 53 may include, for example, a barrier conductive film such as titanium nitride or a laminated film of tantalum nitride and tantalum, and a metal film such as copper.

[0166] Multiple wirings included in the bonding pad 55 are electrically connected to, for example, at least one of the configurations in the third CMOS layer 500 and the configurations in the memory layer 200. The bonding pad 55 includes multiple bonding pads. These multiple bonding pads may include, for example, a barrier conductive film such as titanium nitride and a laminated film of a metal film such as copper. In the following description, one bonding pad included in the third CMOS layer 500 may be described as bonding pad 55, or multiple bonding pads included in the third CMOS layer 500 may be described as bonding pad 55.

[0167] The bonding pad 55 comes into contact with the bonding pad 25 at the bonding surface between the memory layer 200 and the third CMOS layer 500, thereby bonding the memory layer 200 and the third CMOS layer 500 together.

[0168] The interlayer insulating film 58 is provided on the third substrate 50. The interlayer insulating film 58 covers the circuits (for example, wiring layers 51-53) provided on the third substrate 50. The interlayer insulating film 58 may include a plurality of insulating layers.

[0169] The transistor TR3 has a MOSFET structure with a gate electrode, source / drain regions, etc. The source / drain regions of the MOSFET are electrically connected to the bonding pad 55 by wiring layers 51-53.

[0170] Figures 30 to 34 are cross-sectional views showing an example of the cross-sectional structure of the memory layer 200 during the manufacturing process in the third embodiment.

[0171] Note that the manufacturing example up to Figure 30 is the same as in Figures 5 to 12 of the first embodiment, so the explanation will be omitted.

[0172] As shown in Figure 30, a third via contact hole CP3' is formed in the memory region RM. In addition, a hole is formed on the memory pillar MP to form a via plug that electrically connects to the memory pillar MP. The insulating film formed on the memory layer 200 formed in Figure 30 is included in the interlayer insulating film 28.

[0173] As shown in Figure 31, a tungsten-containing material is embedded in the third via contact hole CP3' and the hole on the memory pillar MP to form the third via contact electrode CP3 and via plug. In addition, an insulating film, wiring layers 23-24, via plug, and bonding pad 25 are formed on the interlayer insulating film 28. The insulating film further formed in Figure 31 is included in the interlayer insulating film 28. With the formation of the wiring layers 23-24, via plug, and bonding pad 25 in this way, the memory layer 200 is electrically connected to the third CMOS layer 500, which will be described later.

[0174] As shown in Figure 32, a second via contact hole CP2' is formed in the peripheral region RP of the memory layer 200. The second via contact hole CP2' is formed from the bonding pad 25 side of the memory layer 200 and extends to the conductive layer 26 of the memory layer 200. In other words, the second via contact hole CP2' is formed by anisotropic etching so as to penetrate a portion of the interlayer insulating film 28 and reach the conductive layer 26.

[0175] As shown in Figure 33, a copper-containing material is embedded in the second via contact hole CP2' to form the second via contact electrode CP2.

[0176] When a copper-containing material is embedded in the second via contact hole CP2', the diffusion suppression layer 27 is provided so as to surround the second via contact hole CP2', thereby suppressing the diffusion of copper to other areas in the memory layer 200.

[0177] Figures 34 and 35 are cross-sectional views showing an example of the bonding process between the memory layer 200 and the third CMOS layer 500 in the third embodiment.

[0178] As shown in Figure 34, the memory layer 200 and the third CMOS layer 500 are arranged facing each other. In other words, the memory layer 200 and the third CMOS layer 500 are arranged so that the bonding pad 25 formed on the memory layer 200 and the bonding pad 55 formed on the third CMOS layer 500 face each other.

[0179] As shown in Figure 35, a bonding process is performed to bond the memory layer 200 and the third CMOS layer 500. Bonding pads 25 and 55 correspond to each other, and bonding pads 25 and 35 are electrically connected. This electrically connects the memory layer 200 and the third CMOS layer 500. Alternatively, the memory layer 200 and the third CMOS layer 500 may be bonded by contact between oxide films (not shown) contained in the layer on which bonding pads 25 and 55 are formed. At this time, in the peripheral region RP, the second via contact electrode CP2 contacts and electrically connects with bonding pad 55.

[0180] Subsequently, an insulating film 20 and an external pad PD3 are formed on the wiring layer 21 of the memory layer 200 by etching the wiring layer 21, resulting in the configuration shown in Figure 29.

[0181] The insulating film 20 is formed so as to surround the external pad PD3 when viewed from the Z direction, and the insulating film 20 electrically insulates the wiring layer 21 from the external pad PD3.

[0182] The external pad PD3 is electrically connected to the first via contact electrode CP1 and the second via contact electrode CP2, thereby electrically connecting the external pad PD3 to the third CMOS layer 500. In other words, voltage can be supplied from the external pad PD3 to the third CMOS layer 500.

[0183] In the third embodiment, as in the first embodiment, by using a second via contact electrode CP2 which has lower resistance compared to other via contact electrodes, voltage can be supplied efficiently to the third CMOS layer 500.

[0184] In the third embodiment, the same effects as in the first embodiment can be obtained. Furthermore, in this embodiment, as the number of layers of wiring layer 22 increases, the proportion of the second via contact electrode CP2 increases relatively with increasing layering, so the resistance when supplying voltage from the external pad PD to the third CMOS layer 500 becomes relatively lower.

[0185] (modified version) Figure 36 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 in a modified example of the third embodiment.

[0186] In this modified example, the semiconductor memory device 1 differs from the semiconductor memory device 1 in the third embodiment in that a third via contact electrode CP3 and an external pad PD4 are provided in the peripheral region RP. Other configuration examples are the same as those in the semiconductor memory device 1 of the third embodiment, so their explanation is omitted.

[0187] Multiple external pads PD4 are provided in the peripheral region RP of the memory layer 200 and, like external pads PD3, supply voltage to the CMOS circuit formed on the third CMOS layer 500. Hereafter, external pads PD3 and PD4 may be collectively referred to as external pads PD.

[0188] A portion of the third via contact electrode CP3 is located in the peripheral region RP and is electrically connected to the external pad PD4. In this case, multiple third via contact electrodes CP3 may be electrically connected to a single external pad PD4. The third via contact electrodes CP3 located in the peripheral region RP electrically connect the external pad PD4 and the third CMOS layer 500 via the wiring layer 23, the wiring layer 24, and the bonding pad 25. In other words, voltage is supplied from the external pad PD4 to the third CMOS layer 500 via the third via contact electrode CP3.

[0189] The height of the third via contact electrode CP3, located in the peripheral region RP, in the Z direction is greater than that of the first via contact electrode CP1 in the Z direction.

[0190] In the peripheral region RP of the semiconductor memory device 1 of this modified example, a plurality of external pads PD3 to PD4 are formed. External pad PD3 is electrically connected to the third CMOS layer 500 via a first via contact electrode CP1 and a second via contact electrode CP2, and external pad PD4 is electrically connected to the third CMOS layer 500 via a third via contact electrode CP3. Therefore, voltage supply to the third CMOS layer 500 may be performed via the first via contact electrode CP1 and the second via contact electrode CP2, or via the third via contact electrode CP3.

[0191] In this modified example, the same effects as in the third embodiment can be obtained.

[0192] Furthermore, as described above, in the peripheral region RP of the semiconductor memory device 1, the external pad PD and the third CMOS layer 500 are electrically connected by two types of connection methods (first via contact electrode CP1 and second via contact electrode CP2, or third via contact electrode CP3). Since the third via contact electrode CP3 has a smaller diameter in the XY plane compared to the second via contact electrode CP2, it can be formed in a smaller area than the second via contact electrode CP2.

[0193] The electrical connection between the external pad PD and the third CMOS layer 500 is performed using two methods: connection via the first via contact electrode CP1 and the second via contact electrode CP2, and connection via the third via contact electrode CP3. This results in lower resistivity during voltage supply compared to connecting entirely with the third via contact electrode CP3. Furthermore, it saves space compared to connecting entirely with the first via contact electrode CP1 and the second via contact electrode CP2, allowing for the formation of more via contact electrodes.

[0194] (Fourth Embodiment) The semiconductor memory device in the fourth embodiment comprises memory cells and CMOS circuits for accessing the memory cells. The semiconductor memory device has a structure in which the CMOS circuits are arranged on stacked substrates. Details of the fourth embodiment will be described below.

[0195] Figure 37 is a perspective view showing an example of the appearance of the semiconductor memory device 1 in the fourth embodiment. The fourth embodiment differs from the first embodiment in that it has two memory layers 200 and 600 and two CMOS layers 300 and 400. The semiconductor memory device 1 has a structure in which, for example, the memory layer 200, the second memory layer 600, the first CMOS layer 300, and the second CMOS layer 400 are stacked in order from top to bottom in the Z direction.

[0196] In the Z direction, the first CMOS layer 300 and the second CMOS layer 400 may each have a first substrate 30 and a second substrate 40, respectively, as shown in Figure 38, which will be described later, beneath their respective CMOS layers. Also, in the Z direction, the memory layer 200 may have a wiring layer above it. Note that the wiring layer in the memory layer 200 includes layers formed after the bonding process of the memory layer 200, the second memory layer 600, the first CMOS layer 300, and the second CMOS layer 400, which will be described later. The wiring layer and external pad PD in the memory layer may be the same as in the first embodiment.

[0197] The memory layer 200, the first CMOS layer 300, and the second CMOS layer 400 may be the same as in the first embodiment. The second memory layer 600 includes a memory cell array 3.

[0198] In the semiconductor memory device 1, the memory layer 200, the second memory layer 600, the first CMOS layer 300, and the second CMOS layer 400 are bonded together. At this time, the contact (boundary) portion between the memory layer 200 and the second memory layer 600, the contact (boundary) portion between the second memory layer 600 and the first CMOS layer 300, and the contact (boundary) portion between the second CMOS layer 400 and the first substrate are each bonded surfaces.

[0199] Figure 38 is a cross-sectional view showing an example configuration of the semiconductor memory device 1 in the fourth embodiment. Specifically, Figure 38 shows the configuration of the peripheral region RP in the semiconductor memory device 1.

[0200] The memory layer 200 and the second memory layer 600 are bonded together by contact between a bonding pad 25 (described later) and a bonding pad 65B (described later). Furthermore, an oxide film (not shown) may be provided on the bonding surface between the memory layer 200 and the second memory layer 600, along with the bonding pad, and the layers may be bonded by the oxide film and the bonding pad.

[0201] The second memory layer 600 and the first CMOS layer 300 are bonded together by the bonding pad 65A and the bonding pad 35, which will be described later, coming into contact with each other. In addition, an oxide film (not shown) may be provided on the bonding surface between the second memory layer 600 and the first CMOS layer 300 along with the bonding pad, and the layers may be bonded by the oxide film and the bonding pad.

[0202] The first CMOS layer 300 and the second CMOS layer 400 each have oxide films 39 and 49 on their bonding surfaces. The first CMOS layer 300 and the second CMOS layer 400 may be bonded together by contact between the oxide films 39 and 49. In the peripheral region RP, the first CMOS layer 300 and the second CMOS layer 400 may also be bonded together by contact between the second via contact electrode CP2 (described later) and the bonding pad in the second CMOS layer 400.

[0203] The configuration of the peripheral region RP of the semiconductor memory device 1 will be described below.

[0204] In the fourth embodiment, the peripheral region RP of the semiconductor memory device 1 includes an insulating film 20, a wiring layer 21, a bonding pad 25, a conductive layer 26, a diffusion suppression layer 27, an interlayer insulating film 28, a first substrate 30, a wiring layer 33, an interlayer insulating film 38, an oxide film 39, a second substrate 40, a wiring layer 43, an interlayer insulating film 48, an oxide film 49, a bonding pad 65A, a bonding pad 65B, a diffusion suppression layer 67, an interlayer insulating film 68, a first via contact electrode CP1, a second via contact electrode CP2, a third via contact electrode CP3, and external pads PD5-6.

[0205] Furthermore, the peripheral region RP may also include wiring layers 22-23, 31-32, and 41-42 as in the first embodiment. In addition, the peripheral region RP of the second memory layer 600 may also include multiple wiring layers.

[0206] In the fourth embodiment, the bonding process of the memory layer 200 and the second memory layer 600 is described in which the bonding pad 25 and the bonding pad 65B face each other. However, the bonding process of the memory layer 200 and the second memory layer 600 is not limited to this, and the bonding pad 25 and the bonding pad 65A may also face each other.

[0207] The memory layer 200 includes external pads PD5-6, insulating film 20, wiring layer 21, bonding pad 25, conductive layer 26, diffusion suppression layer 27, interlayer insulating film 28, first via contact electrode CP1, second via contact electrode CP2, and third via contact electrode CP3.

[0208] External pads PD5-PD6 are located in the peripheral area RP of the memory layer 200. Hereafter, external pads PD5-PD6 may be collectively referred to as external pad PD.

[0209] The external pad PD is electrically connected to the first via contact electrode CP1 and the second via contact electrode CP2, or the third via contact electrode CP3 and the fourth via contact electrode CP4, as described later. This supplies voltage to the CMOS circuits formed on the first CMOS layer 300 and the second CMOS layer 400.

[0210] The insulating film 20 may be the same as in the first embodiment.

[0211] The first via contact electrode CP1 is formed in the peripheral region RP of the memory layer 200. The first via contact electrode CP1 may be the same as in the first embodiment. Voltage is supplied from the external pad PD5 to the second CMOS layer 400 via the first via contact electrode CP1 and the second via contact electrode CP2, which will be described later.

[0212] The second via contact electrode CP2 is formed in the peripheral region RP of the memory layer 200. The second via contact electrode CP2 is electrically connected to the first via contact electrode CP1, and is electrically connected to the external pad PD5 via the first via contact electrode CP1.

[0213] Similar to the first embodiment, in the second via contact electrode CP2, the diameter of the surface facing the first via contact electrode CP1 is larger than the diameter of the surface facing the second via contact electrode CP2 in the first via contact electrode CP1.

[0214] The second via contact electrode CP2 contacts the bonding pad of the second CMOS layer 400, which will be described later, on the surface opposite to the surface that contacts the conductive layer 26. In other words, the second via contact electrode CP2 has a structure that penetrates the entirety of the first CMOS layer 300 and the second memory layer 600, which will be described later, and a part of the memory layer 200 in the Z direction.

[0215] The second via contact electrode CP2 has a height of at least half the height of the second laminate 29B in the Z direction. More specifically, the second via contact electrode CP2 has a height in the Z direction that is almost the same as the height from the second laminate 29B to the bonding surface between the first CMOS layer 300 and the second CMOS layer 400. In other words, in the Z direction, the height of the second via contact electrode CP2 is greater than the sum of the height of the second laminate 29B, the height of the second memory layer 600, and the height of the first CMOS layer 300, which will be described later.

[0216] The material included in the second via contact electrode CP2 may be the same as in the first embodiment, and may include, for example, a different material from that of the first via contact electrode CP1.

[0217] Multiple third via contact electrodes CP3 are arranged in the memory layer 200. The third via contact electrodes CP3 may be the same as in the first embodiment. The third via contact electrodes CP3 arranged in the peripheral region RP are electrically connected to the external pad PD6. The third via contact electrodes CP3 arranged in the peripheral region RP may also be connected to wiring layers 23 and 24 (not shown). Furthermore, they are electrically connected to the fourth via contact electrode CP4 in the second memory layer 600 (described later) via the bonding pad 25 and the bonding pad 65B (described later). In other words, voltage is supplied from the external pad PD6 to the first CMOS layer 300 via the third via contact electrode CP3 and the fourth via contact electrode CP4. To put it another way, the third via contact electrode CP3 in the peripheral region RP can supply voltage to the CMOS layer that is in direct contact with the layer containing the memory cell array.

[0218] The height of the third via contact electrode CP3, located in the peripheral region RP, in the Z direction is greater than that of the first via contact electrode CP1 in the Z direction.

[0219] The wiring layer 21, conductive layer 26, diffusion suppression layer 27, and interlayer insulating film 28 may be the same as in the first embodiment, so their description is omitted.

[0220] The configuration of the second memory layer 600 may be almost the same as that of the memory layer 200. Including a storage area RM (not shown), the second memory layer 600 includes a wiring layer, bonding pads 65A, 65B, a diffusion suppression layer 67, an interlayer insulating film 68, a memory pillar, a second via contact electrode CP2, and a fourth via contact electrode CP4. The second memory layer 600, like the memory layer 200, has a memory cell array 3. In other words, the semiconductor memory device 1 of the fourth embodiment has a structure in which multiple memory layers, each containing a memory cell array 3, are stacked.

[0221] In the peripheral region RP, the second memory layer 600 includes a bonding pad 65A, a bonding pad 65B, a diffusion suppression layer 67, an interlayer insulating film 68, a second via contact electrode CP2, and a fourth via contact electrode CP4.

[0222] The second via contact electrode CP2 is formed in the peripheral region RP of the second memory layer 600 and has a structure that penetrates the second memory layer 600 in the Z direction.

[0223] Multiple fourth via contact electrodes CP4 are arranged in the second memory layer 600. The fourth via contact electrodes CP4 may have the same structure as the third via contact electrodes CP3 in the memory layer 200. In this case, multiple fourth via contact electrodes CP4 may be electrically connected to a single external pad PD6. Furthermore, fourth via contact electrodes CP4 located in the peripheral region RP may be connected to the bonding pad 65A or bonding pad 65B via a wiring layer (not shown).

[0224] The fourth via contact electrode CP4 is electrically connected to the bonding pads 65A and 65B, and is electrically connected to the external pad PD6 and the first CMOS layer 300. In other words, in the peripheral region RP, voltage is supplied from the external pad PD6 to the first CMOS layer 300 via the third via contact electrode CP3 and the fourth via contact electrode CP4. To put it another way, the fourth via contact electrode CP4 in the peripheral region RP can supply voltage to the CMOS layer that is in direct contact with the layer containing the memory cell array.

[0225] The height of the fourth via contact electrode CP4, located in the peripheral region RP, in the Z direction is greater than that of the first via contact electrode CP1 in the Z direction.

[0226] The fourth via contact electrode CP4 contains, for example, tungsten.

[0227] Multiple wirings included in the bonding pad 65A are electrically connected to at least one of the configurations in the first CMOS layer 300 and the second memory layer 600, for example, as described later. Similarly, multiple wirings included in the bonding pad 65B are electrically connected to at least one of the configurations in the memory layer 200 and the second memory layer 600, for example. Specifically, the bonding pad 65A in the peripheral region RP is electrically connected to the bonding pad 35 in the first CMOS layer 300. The bonding pad 65B in the peripheral region RP is electrically connected to the bonding pad 25 in the memory layer 200.

[0228] The bonded pads 65A and 65B include multiple bonded pads. These multiple bonded pads 65A and 65B may include, for example, a laminated film of a barrier conductive film such as titanium nitride and a metal film such as copper. In the following description, one bonded pad included in the second memory layer 600 may be described as bonded pad 65A, or multiple bonded pads included in the second memory layer 600 may be described as bonded pad 65A. The same applies to bonded pad 65B as to bonded pad 65A.

[0229] The interlayer insulating film 68 fills the second memory layer 600 and insulates the other elements from each other. The interlayer insulating film 68 is, for example, a silicon oxide film or a silicon nitride film.

[0230] Furthermore, the second memory layer 600 includes a fourth stack 69A and a fifth stack 69B in a storage area RM (not shown). The storage area RM in the second memory layer 600 is included, for example, in a third area.

[0231] The fourth and fifth laminates 69A and 69B, like the first and second laminates 29A and 29B, have a structure in which multiple insulating layers and multiple wiring layers are alternately stacked in a storage area RM (not shown). The multiple wiring layers are formed in a stepped manner in the Z direction, and the fifth laminate 69B is formed below the fourth laminate 69A. The fourth and fifth laminates 69A and 69B may have the same height or different heights in the Z direction.

[0232] The diffusion suppression layer 67 is provided around the second via contact electrode CP2. The diffusion suppression layer 67 may have a structure similar to that of the diffusion suppression layer 27. That is, it may have approximately the same height in the Z direction as the height of the multiple stacked structures in the memory cell array 3 of the second memory layer 600 (not shown).

[0233] The diffusion suppression layer 67 contains, for example, tungsten.

[0234] In this embodiment, in the memory area RM (not shown), slits are formed after the formation of the fourth stack 69A and the fifth stack 69B. The height of the diffusion suppression layer 67 in the Z direction is approximately the same as, for example, the height of the slit (not shown) in the second memory layer 600 in the Z direction. In other words, the height of the diffusion suppression layer 67 in the Z direction is approximately the same as, for example, the sum of the height of the fourth stack 69A in the Z direction and the height of the fifth stack 69B in the Z direction.

[0235] The second memory layer 600 is bonded to the first CMOS layer 300 on the side opposite to the side that is bonded to the memory layer 200.

[0236] The first CMOS layer 300 and the second CMOS layer 400 may be the same as in the first embodiment, so their description is omitted.

[0237] Figures 39 to 42 are cross-sectional views showing an example of the bonding process between the second memory layer 600 and the first CMOS layer 300 in the fourth embodiment. Specifically, Figures 39 to 42 show the configuration of the peripheral region RP in the semiconductor memory device 1.

[0238] As shown in Figure 39, the second memory layer 600 and the first CMOS layer 300 are arranged to face each other. In other words, the second memory layer 600 and the first CMOS layer 300 are arranged so that the adhesive pad 65A formed on the second memory layer 600 and the adhesive pad 35 formed on the first CMOS layer 300 face each other.

[0239] In this case, the method for forming the fourth via contact electrode CP4 in the second memory layer 600 may be the same as that for the third via contact electrode CP3 in the first embodiment. That is, as shown in Figures 13 to 14, the fourth via contact electrode CP4 is formed after the fourth stack 69A and the fifth stack 69B are formed. Also, the method for forming the diffusion suppression layer 67 in the second memory layer 600 may be the same as that for the diffusion suppression layer 27 in the first embodiment. That is, as shown in Figures 11 to 12, the diffusion suppression layer 67 is formed at the same time that a slit (not shown) is formed in the memory area RM.

[0240] Furthermore, the method for forming the first CMOS layer 300 may be the same as that for the first CMOS layer 300 in the first embodiment. That is, the first CMOS layer 300 is formed as shown in Figures 16 to 18.

[0241] As shown in Figure 40, a bonding process is performed to bond the second memory layer 600 and the first CMOS layer 300. The bonding pad 65A and the bonding pad 35 correspond to each other, and the bonding pad 65A and the bonding pad 35 are electrically connected. This makes it possible to electrically connect the second memory layer 600 and the first CMOS layer 300. Alternatively, the second memory layer 600 and the first CMOS layer 300 may be bonded by contact between oxide films (not shown) contained in the layers on which the bonding pad 65A and the bonding pad 35 are formed.

[0242] Furthermore, after the bonding process of the second memory layer 600 and the first CMOS layer 300, an oxide film 39 may be formed on the surface of the first CMOS layer 300 opposite to the surface bonded to the second memory layer 600.

[0243] As shown in Figure 41, the fourth substrate 60 is removed in the second memory layer 600. The fourth substrate 60 is removed using a chemical solution containing, for example, potassium hydroxide (KOH). The fourth substrate 60 is, for example, a silicon wafer.

[0244] As shown in Fig. 42, bonding pads 65B are formed on the surface exposed after the removal of the fourth substrate 60. The bonding pads 65B may include an insulating film such as a silicon nitride film. For example, an insulating film is formed on the surface exposed after the removal of the fourth substrate 60, and the insulating film in a part of the region is removed. The bonding pads 65B are formed by embedding a metal or the like in the portion where the insulating film has been removed.

[0245] Figs. 43 to 46 are cross-sectional views showing an example of the bonding process of the second memory layer 600 and the memory layer 200 in the fourth embodiment. Specifically, Figs. 43 to 46 show the configuration of the peripheral region RP in the semiconductor memory device 1.

[0246] As shown in Fig. 43, the second memory layer 600 and the memory layer 200 are arranged to face each other. That is, the second memory layer 600 and the memory layer 200 are arranged such that the bonding pads 65B formed on the second memory layer 600 and the bonding pads 25 formed on the memory layer 200 face each other.

[0247] The configuration of the memory layer 200 when being bonded may be the same as that in the first embodiment. That is, the memory layer 200 at this time is manufactured as shown in Figs. 5 to 15.

[0248] As shown in Fig. 44, a bonding process is performed to bond the second memory layer 600 and the memory layer 200. Also, an oxide film 39 is formed on the surface of the first CMOS layer 300 opposite to the surface bonded to the second memory layer 600.

[0249] The bonding pads 65B and the bonding pads 25 correspond to each other, and the bonding pads 65B and the bonding pads 25 are electrically connected. Thereby, the second memory layer 600 and the memory layer 200 can be electrically connected. Also, by electrically connecting the third via contact electrode CP3, the fourth via contact electrode CP4, and the bonding pads 25, 35, 65A, 65B, the memory layer 200, the second memory layer 600, and the first CMOS layer 300 can be electrically connected.

[0250] The memory layer 200 and the first CMOS layer 300 may be bonded by contact between the bonding pads 65B and the oxide films (not shown) included in the layer where the bonding pads 25 are formed.

[0251] As shown in FIG. 45, in the peripheral region RP of the memory layer 200, the second memory layer 600, and the first CMOS layer 300 after the bonding process, a second via contact hole CP2' is formed. The second via contact hole CP2' is formed from the oxide film 39 side of the first CMOS layer 300, penetrates the first CMOS layer 300 and the second memory layer 600, and is formed up to the conductive layer 26 of the memory layer 200. In other words, the second via contact hole CP2' is formed by anisotropic etching so as to penetrate the oxide film 39, the first substrate 30, the interlayer insulating film 38, the interlayer insulating film 68, and the interlayer insulating film 28 and reach the conductive layer 26. When viewed from the negative Z direction, the second via contact hole CP2' is formed so as to overlap the conductive layer 26 and the first via contact electrode CP1.

[0252] As shown in FIG. 46, a material containing copper is embedded in the second via contact hole CP2' to form the second via contact electrode CP2. The second via contact electrode CP2 is formed from the oxide film 39 side of the first CMOS layer 300, penetrates the first CMOS layer 300 and the second memory layer 600, and is formed up to the conductive layer 26 of the memory layer 2�0.

[0253] When a material containing copper is embedded in the second via contact hole CP2', diffusion suppression layers 27, 37, and 67 are provided so as to surround the second via contact hole CP2'. Therefore, it is possible to suppress the diffusion of copper to other regions in the memory layer 200, the second memory layer 600, and the first CMOS layer 300.

[0254] Thereafter, a bonding process between the first CMOS layer 300 and the second CMOS layer 400 is performed. Since it may be the same as FIGS. 23 to 25 of the first embodiment, the description is omitted.

[0255] Subsequently, as shown in Figure 38, an insulating film 20 and an external pad PD are formed on the wiring layer 21 of the memory layer 200 by etching the wiring layer 21 or the like.

[0256] The external pad PD5 is electrically connected to the first via contact electrode CP1 and the second via contact electrode CP2, allowing voltage to be supplied from the external pad PD5 to the second CMOS layer 400. Furthermore, the external pad PD6 is electrically connected to the third via contact electrode CP3 and the fourth via contact electrode CP4, allowing voltage to be supplied from the external pad PD6 to the first CMOS layer 300.

[0257] Figure 47 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 in the fourth embodiment. Figure 47 also shows the configuration of the memory area RM. Note that in the memory area RM of the second memory layer 600, the configuration other than the wiring layer 62 is omitted.

[0258] As shown in Figure 47, the memory layer 200 and the second memory layer 600 are bonded together such that the second stack 29B and the fourth stack 69A (described later) face each other. However, the bonding process of the memory layer 200 and the second memory layer 600 is not limited to this, and the second stack 29B and the fifth stack 69B (described later) may be bonded together such that they face each other.

[0259] The second memory layer 600 has multiple wiring layers 62 in the storage area RM.

[0260] The wiring layer 62 is formed in a position that overlaps with the second via contact electrode CP2 and the fourth via contact electrode CP4 when viewed from the Y direction. The multiple wiring layers 62 are spaced apart from each other, and an interlayer insulating film 68 is formed between adjacent wiring layers 62. In the Z direction, a structure in which multiple insulating layers and multiple wiring layers 62 are alternately stacked is defined as the fourth laminate 69A, formed on a source line (not shown) and in contact with the uppermost wiring layer 62, starting from the interlayer insulating film 68. In the Z direction, a structure in which multiple insulating layers and wiring layers 22 are alternately stacked is defined as the fifth laminate 69B, formed below the fourth laminate 69A in the Z direction.

[0261] The wiring layer 62 comprises multiple word lines and multiple select gate lines as multiple electrode layers in the memory cell array 3. The wiring layer 62 has a stepped structure. In addition, multiple memory pillars (not shown) are formed to penetrate the wiring layer 62. The wiring layer 62 is included in, for example, a third conductive layer and a fourth conductive layer, and the interlayer insulating film 68 formed between the multiple wiring layers 62 in the memory area RM is included in a third insulating layer and a fourth insulating layer.

[0262] In the fourth embodiment, the same effects as in the first embodiment can be obtained.

[0263] Furthermore, in the fourth embodiment, a second memory layer 600 is included, and the second via contact electrode CP2 has a structure that penetrates the first CMOS layer 300, the second memory layer 600, and a portion of the memory layer 200 in the Z direction. Since the second via contact electrode CP2 can be formed with a larger diameter in the XY plane than the first via contact electrode CP1, it is less affected by the aspect ratio even when multiple memory layers are stacked.

[0264] As the number of stacked memory layers increases, the proportion of the second via contact electrode CP2 that electrically connects the external pad PD and the second CMOS layer 400 increases. Therefore, in this embodiment, the second via contact electrode CP2 penetrates the second memory layer 600 in the Z direction, and the proportion of the second via contact electrode CP2 becomes relatively larger, so the resistance when supplying voltage from the external pad PD to the second CMOS layer 400 becomes relatively lower.

[0265] (Fifth embodiment) The semiconductor memory device in the fifth embodiment comprises memory cells and CMOS circuits for accessing the memory cells. The semiconductor memory device has a structure in which the CMOS circuits are arranged on stacked substrates. Details of the fifth embodiment will be described below.

[0266] Figure 48 is a perspective view showing an example of the appearance of the semiconductor memory device 1 in the fifth embodiment.

[0267] In the fifth embodiment, it has two memory layers 200, 600, and one CMOS layer 500.

[0268] The semiconductor memory device 1 has a structure in which, for example, in the Z direction, the memory layer 200, the second memory layer 600, and the third CMOS layer 500 are stacked in this order from above.

[0269] Note that the configurations of the memory layer 200 and the second memory layer 600 may be the same as those in the fourth embodiment, so they will be briefly described. Also, since the third CMOS layer 500 may be the same as that in the third embodiment, the description thereof will be omitted.

[0270] In the Z direction, the memory layer 200 may have a wiring layer on the memory layer. The wiring layer includes, for example, a plurality of external pads PD7 used for connecting the semiconductor memory device 1 and the controller 2. The external pads PD7 are connected to the input / output circuit 4 and are exposed on the surface of the semiconductor memory device 1.

[0271] The third CMOS layer 500 may be the same as that in the third embodiment. That is, in the third CMOS layer 500 in the fifth embodiment, the CMOS circuits that were divided into two in the first embodiment are included in one CMOS layer.

[0272] In the semiconductor memory device 1, the memory layer 200, the second memory layer 600, and the third CMOS layer 500 are bonded together. At this time, the contact (boundary) portion between the memory layer 200 and the second memory layer 600 and the contact (boundary) portion between the second memory layer 600 and the third CMOS layer 500 each serve as a bonding surface.

[0273] FIG. 49 is a cross-sectional view showing a configuration example of the semiconductor memory device 1 in the fifth embodiment. Specifically, FIG. 49 shows the configuration of the peripheral region RP in the semiconductor memory device 1. Hereinafter, the peripheral region RP of the semiconductor memory device 1 will be described.

[0274] The memory layer 200 and the second memory layer 600 are bonded together by the contact between an adhesive pad (not shown) in the memory layer 200 and an adhesive pad (not shown) in the second memory layer 600.

[0275] The second memory layer 600 and the third CMOS layer 500 are bonded together in the peripheral region RP by contact between the second via contact electrode CP2 (described later) and the bonding pad 55. Furthermore, an oxide film (not shown) may be provided on the bonding surface between the memory layer 200 and the third CMOS layer 500, along with the bonding pad, and the memory layer 200 and the third CMOS layer 500 may be bonded together by the oxide film and the bonding pad.

[0276] In the fifth embodiment, the peripheral region RP of the semiconductor memory device 1 includes an insulating film 20, a wiring layer 21, a conductive layer 26, a diffusion suppression layer 27, an interlayer insulating film 28, a third substrate 50, a wiring layer 53, an interlayer insulating film 58, a diffusion suppression layer 67, an interlayer insulating film 68, a first via contact electrode CP1, a second via contact electrode CP2, and an external pad PD7.

[0277] In the fifth embodiment, the bonding process of the memory layer 200 and the second memory layer 600 is described in the same manner as in the fourth embodiment. However, the bonding process of the memory layer 200 and the second memory layer 600 is not limited to this.

[0278] The memory layer 200 includes an external pad PD7, an insulating film 20, a wiring layer 21, a conductive layer 26, a diffusion suppression layer 27, an interlayer insulating film 28, a first via contact electrode CP1, and a second via contact electrode CP2.

[0279] Multiple external pads PD7 are provided in the peripheral area RP of the memory layer 200.

[0280] The external pad PD7 is electrically connected to the first via contact electrode CP1 and the second via contact electrode CP2, which will be described later, and supplies voltage to the CMOS circuit formed on the third CMOS layer 500.

[0281] The insulating film 20 may be the same as in the first embodiment.

[0282] The first via contact electrode CP1 may be the same as in the first embodiment, and has a height of at least half the height in the Z direction of the first laminate 29A. Voltage is supplied from the external pad PD7 to the third CMOS layer 500 via the first via contact electrode CP1 and the second via contact electrode CP2, which will be described later.

[0283] The second via contact electrode CP2 is formed in the peripheral region RP of the memory layer 200. The second via contact electrode CP2 is electrically connected to the first via contact electrode CP1, and is electrically connected to the external pad PD7 via the first via contact electrode CP1.

[0284] Similar to the first embodiment, in the second via contact electrode CP2, the diameter of the surface facing the first via contact electrode CP1 is larger than the diameter of the surface facing the second via contact electrode CP2 in the first via contact electrode CP1.

[0285] The second via contact electrode CP2 may also be in contact with the bonding pad 55 of the third CMOS layer 500 on the surface opposite to the surface in contact with the conductive layer 26. In this case, the second via contact electrode CP2 has a structure that penetrates the entirety of the second memory layer 600 (described later) and a portion of the memory layer 200 in the Z direction. The second via contact electrode CP2 has a height of at least half the height of the second laminate 29B (described later) in the Z direction. More specifically, the second via contact electrode CP2 has a height in the Z direction that is almost the same as the height from the second laminate 29B to the bonding surface between the second memory layer 600 and the third CMOS layer 500. In other words, in the Z direction, the height of the second via contact electrode CP2 is greater than the sum of the height of the second laminate 29B and the height of the second memory layer 600 (described later).

[0286] The material included in the second via contact electrode CP2 may be the same as in the first embodiment.

[0287] The conductive layer 26, the diffusion suppression layer 27, and the interlayer insulating film 28 may be the same as in the first embodiment, so their description is omitted.

[0288] The configuration of the second memory layer 600 can be the same as in the fourth embodiment, so it will be described briefly.

[0289] In the peripheral region RP, the second memory layer 600 includes a diffusion suppression layer 67, an interlayer insulating film 68, and a second via contact electrode CP2. Alternatively, it may include a bonding pad (not shown).

[0290] The diffusion suppression layer 67 and the interlayer insulating film 68 may be the same as in the fourth embodiment, so their description is omitted.

[0291] The second memory layer 600 includes a fourth stack 69A and a fifth stack 69B in a storage area RM (not shown). The fourth stack 69A and the fifth stack 69B may be the same as in the fourth embodiment.

[0292] The second memory layer 600 is bonded to the third CMOS layer 500 on the side opposite to the side that is bonded to the memory layer 200.

[0293] The third CMOS layer 500 can be the same as in the third embodiment, so its description is omitted.

[0294] Figures 50 to 53 are cross-sectional views showing an example of the bonding process between the memory layer 200 and the second memory layer 600 in the fifth embodiment. Specifically, Figures 50 to 53 show the configuration of the peripheral region RP in the semiconductor memory device 1.

[0295] The configuration of the memory layer 200 when it is bonded may be the same as in the first embodiment. That is, the memory layer 200 at this time is manufactured as shown in Figures 5 to 15. The configuration of the second memory layer 600 when it is bonded may be the same as in the fourth embodiment. Also, the method for forming the diffusion suppression layer 67 in the second memory layer 600 may be the same as the diffusion suppression layer 27 in the first embodiment. That is, as shown in Figures 11 to 12, the diffusion suppression layer 67 is formed at the same time that a slit (not shown) is formed in the storage area RM.

[0296] As shown in Figure 50, the memory layer 200 and the second memory layer 600 are arranged facing each other. In other words, the memory layer 200 and the second memory layer 600 are arranged so that the second stacked body 29B formed on the memory layer 200 and the fourth stacked body 69A formed on the second memory layer 600 face each other.

[0297] After bonding the memory layer 200 and the second memory layer 600, as shown in Figure 51, a second via contact hole CP2' is formed in the peripheral region RP of the memory layer 200 and the second memory layer 600 after bonding. The second via contact hole CP2' is formed by anisotropic etching so as to penetrate the interlayer insulating film 68 and a portion of the interlayer insulating film 28 in the Z direction and reach the conductive layer 26. When viewed from the negative Z direction, the second via contact hole CP2' is formed to overlap with the conductive layer 26 and the first via contact electrode CP1.

[0298] As shown in Figure 52, a copper-containing material is embedded in the second via contact hole CP2' to form the second via contact electrode CP2. The second via contact electrode CP2 is formed on the side of the second memory layer 600 opposite to the side that bonds with the memory layer 200, penetrates the second memory layer 600, and extends to the conductive layer 26 of the memory layer 200.

[0299] When a copper-containing material is embedded in the second via contact hole CP2', diffusion suppression layers 27 and 67 are provided so as to surround the second via contact hole CP2', thereby suppressing the diffusion of copper to other areas in the memory layer 200 and the second memory layer 600.

[0300] Figures 53 to 55 are cross-sectional views showing an example of the bonding process of the second memory layer 600 and the third CMOS layer 500 in the fifth embodiment. Specifically, Figures 54 to 56 show the configuration of the peripheral region RP in the semiconductor memory device 1.

[0301] As shown in Figure 53, the second memory layer 600 and the third CMOS layer 500 are arranged facing each other. In other words, the second memory layer 600 and the third CMOS layer 500 are arranged such that the side of the second memory layer 600 opposite to the side bonded to the memory layer 200 faces the bonding pad 55 formed on the third CMOS layer 500.

[0302] As shown in Figure 54, a bonding process is performed to bond the second memory layer 600 and the third CMOS layer 500 together. At this time, the second via contact electrode CP2 and the bonding pad 55 are electrically connected.

[0303] As shown in Figure 55, the fifth substrate 201 is removed from the memory layer 200. The fifth substrate 201 is removed using a chemical solution containing, for example, potassium hydroxide (KOH). The fifth substrate 201 is, for example, a silicon wafer.

[0304] Subsequently, as shown in Figure 49, an insulating film 20 and an external pad PD7 are formed on the wiring layer 21 of the memory layer 200 by etching the wiring layer 21 or the like.

[0305] The external pad PD7 is located in the peripheral region RP and is electrically connected to the first via contact electrode CP1. The second via contact electrode CP2 is also connected to the external pad PD5 via the first via contact electrode CP1. The electrical connection of the external pad PD7, the first via contact electrode CP1, the second via contact electrode CP2, and the bonded pad 55 allows voltage to be supplied from the external pad PD7 to the third CMOS layer 500.

[0306] In the fifth embodiment, the same effects as in the first embodiment can be obtained.

[0307] Furthermore, in the fifth embodiment, a second memory layer 600 is included, and the second via contact electrode CP2 has a structure that penetrates the second memory layer 600 and a portion of the memory layer 200 in the Z direction. Since the second via contact electrode CP2 can be formed with a larger diameter in the XY plane than the first via contact electrode CP1, it is less affected by the aspect ratio even when multiple memory layers are stacked.

[0308] As the number of stacked memory layers increases, the proportion of the second via contact electrode CP2 that electrically connects the external pad PD and the third CMOS layer 500 increases. Therefore, in this embodiment, the second via contact electrode CP2 penetrates the second memory layer 600 in the Z direction, and the proportion of the second via contact electrode CP2 becomes relatively larger, so the resistance when supplying voltage from the external pad PD to the third CMOS layer 500 becomes relatively lower.

[0309] (modified version) Figure 56 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 in a modified example of the fifth embodiment. Specifically, Figure 56 shows the configuration of the peripheral region RP in the semiconductor memory device 1.

[0310] The semiconductor memory device 1 in the modified version of the fifth embodiment differs from the semiconductor memory device 1 in the fifth embodiment in that a third via contact electrode CP3 and a fourth via contact electrode CP4 are provided in the peripheral region RP. Other configuration examples are the same as those in the semiconductor memory device 1 of the fifth embodiment, so their explanation is omitted.

[0311] As shown in Figure 56, multiple external pads PD8 are provided in the peripheral region RP of the memory layer 200 and supply voltage to the CMOS circuit formed on the third CMOS layer 500, similar to external pads PD7. Hereafter, external pads PD7 and PD8 may be collectively referred to as external pads PD.

[0312] The configuration of the third via contact electrode CP3 and the fourth via contact electrode CP4 may be the same as in the fourth embodiment, so their explanation will be omitted.

[0313] In the peripheral region RP of the semiconductor memory device 1 of this modified example, a plurality of external pads PD7 to PD8 are formed. External pad PD7 is electrically connected to the third CMOS layer 500 via a first via contact electrode CP1 and a second via contact electrode CP2. External pad PD8 is also electrically connected to the third CMOS layer 500 via a third via contact electrode CP3 and a fourth via contact electrode CP4. In other words, voltage supply to the third CMOS layer 500 may be performed via the first via contact electrode CP1 and the second via contact electrode CP2, or via the third via contact electrode CP3 and the fourth via contact electrode CP4.

[0314] In this modified example, the same effects as in the fifth embodiment can be obtained.

[0315] The electrical connection between the external pad PD and the third CMOS layer 500 is made by two methods: connection using the first via contact electrode CP1 and the second via contact electrode CP2, and connection using the third via contact electrode CP3 and the fourth via contact electrode CP4. Therefore, the same effects as the modification of the third embodiment can be obtained in this modified example as well.

[0316] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0317] 1: Semiconductor memory 2: Controller 3: Memory cell array 4: Input / Output Circuits 5: Logic control circuit 6: Register 7: Sequencer 8: Voltage generation circuit 9: Raw Decoder 10: SenseAmp 20: Insulating film 21: Wiring layer 22: Wiring layer 26: Conductive layer 27: Diffusion suppression layer 28: Interlayer insulating film 37: Diffusion suppression layer 62: Wiring layer 67: Diffusion suppression layer 68: Interlayer insulating film 29A: First layer 29B: Second layer 29C: Third layer 69A: Fourth layer 69B: Fifth layer 200: Memory layer 300: 1st CMOS layer 400: 2nd CMOS layer 500: 3rd CMOS layer 600: Second memory layer CP1: First via contact electrode CP2: Second via contact electrode CP3: Third via contact electrode CP4: Fourth via contact electrode CP1': First Beer Contact Hall CP2': Second Beer Contact Hall CP3': Third Beer Contact Hall CP4': 4th Beer Contact Hall MP: Memory Pillar MH: Memory Hole PD: External pad

Claims

1. A first laminate in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked in a first region, A second laminate is disposed on the first laminate in the stacking direction of the first laminate, and is formed by alternately stacking a plurality of second conductive layers and a plurality of second insulating layers, A first via contact electrode is arranged in a second region adjacent to the first region and has a height of at least half the height of the first laminate in the stacking direction, The second region includes a second via contact electrode, which is positioned on the first via contact electrode in the stacking direction, electrically connected to the first via contact electrode, and having a height of at least half the height of the second laminate in the stacking direction, A semiconductor memory device wherein the diameter of the surface of the second via contact electrode facing the first via contact electrode is greater than the diameter of the surface of the first via contact electrode facing the second via contact electrode.

2. When viewed from a direction perpendicular to the stacking direction, the first stack and the first via contact electrode overlap. The semiconductor memory device according to claim 1.

3. When viewed from the aforementioned stacking direction, the first via contact electrode and the second via contact electrode overlap. The semiconductor memory device according to claim 2.

4. The present invention further includes a third via contact electrode, which is arranged in the second region and has a height in the stacking direction that is greater than or equal to the sum of the height of the first laminate and the height of the second laminate. The third via contact electrode is provided spaced apart from the first via contact electrode and the second via contact electrode. The semiconductor memory device according to claim 1.

5. A first chip comprising the first laminate and the second laminate, A second chip to be bonded to the first chip, The present invention comprises a second via contact electrode provided through the bonding surface between the first chip and the second chip, The semiconductor memory device according to claim 1.

6. The first laminate and the second laminate each have a cell array, The second chip has a first CMOS circuit. The semiconductor memory device according to claim 5.

7. The second via contact electrode has a height greater than the sum of the height of the second laminate and the height of the second tip in the stacking direction. The semiconductor memory device according to claim 6.

8. The second chip further includes a diffusion suppression layer provided so as to surround the second via contact electrode. The semiconductor memory device according to claim 6.

9. The third chip further includes a second CMOS circuit, The third chip is bonded to the side of the second chip opposite to the first chip. The aforementioned second via contact electrode is electrically connected to the aforementioned third chip. The semiconductor memory device according to claim 5.

10. The second via contact electrode has a height greater than the sum of the height of the second laminate and the height of the second tip in the stacking direction. The semiconductor memory device according to claim 9.

11. The present invention further includes a third via contact electrode, which is arranged in the second region and has a height in the stacking direction that is greater than or equal to the sum of the height of the first laminate and the height of the second laminate. The third via contact electrode is provided spaced apart from the first via contact electrode and the second via contact electrode. The aforementioned third via contact electrode is electrically connected to the aforementioned second tip. The semiconductor memory device according to claim 10.

12. The second chip further includes a third laminate in which a plurality of third conductive layers and a plurality of third insulating layers are alternately stacked in a third region, and a fourth laminate disposed on the third laminate in the stacking direction of the third laminate, in which a plurality of fourth conductive layers and a plurality of fourth insulating layers are alternately stacked. The first laminate, the second laminate, the third laminate, and the fourth laminate each have a cell array. The semiconductor memory device according to claim 5.

13. The second via contact electrode has a height in the stacking direction that is greater than the sum of the height of the second stack, the height of the third stack, and the height of the fourth stack. The semiconductor memory device according to claim 12.

14. The present invention further includes a conductive layer provided between the first via contact electrode and the second via contact electrode, When viewed from the aforementioned stacking direction, the conductive layer is circular or quadrilateral in shape. The diameter of the surface of the conductive layer when viewed from the stacking direction, or the distance between opposing sides, is greater than or equal to the diameter of the surface of the second via contact electrode facing the first via contact electrode. The semiconductor memory device according to claim 1.

15. The following further includes a diffusion-suppressing layer that extends in the lamination direction and is provided so as to surround the second via contact electrode. The semiconductor memory device according to claim 1.

16. The second via contact electrode comprises a material with lower resistivity than the first via contact electrode. The semiconductor memory device according to claim 1.

17. The second via contact electrode contains copper, The semiconductor memory device according to claim 15.

18. The second via contact electrode has a height greater than the height of the second laminate in the stacking direction. The semiconductor memory device according to claim 1.

19. In the first region, a first laminate is formed in which a plurality of first sacrificial layers and a plurality of first insulating layers are alternately stacked. A first insulator is formed in a second region adjacent to the first region, having a height substantially the same as the height of the first laminate in the stacking direction of the first laminate. In the first region, a first memory hole is formed in the first laminate. The first memory hole is formed in the first region, and the first via contact hole is formed in the first insulator in the second region. A conductor is embedded in the first via contact hole to form the first via contact electrode. In the first region, a second laminate is formed on the first laminate in which a plurality of second sacrificial layers and a plurality of second insulating layers are alternately laminated. In the second region, a second insulator is formed on the first insulator having a height substantially the same as the height of the second laminate in the lamination direction. In the first region, a second memory hole is formed in the second laminate that connects to the first memory hole. In the second region, a second via contact hole is formed in the second insulator. A conductor containing a material different from that of the first via contact electrode is embedded in the second via contact hole to form a second via contact electrode that can be electrically connected to the first via contact electrode. A method for manufacturing semiconductor memory devices.

20. After forming the first via contact electrode and before forming the second laminate, a conductive layer that can be electrically connected to the first via contact electrode is formed in the second region. A method for manufacturing a semiconductor memory device according to claim 19.

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