Printed circuit board

Abstract

One of the several objectives of the present invention is to provide a printed circuit board that allows for easy warping control even in asymmetric structures. [Solution] The present invention relates to a printed circuit board comprising: a glass layer having a first surface and a second surface facing each other in a first direction; a through via penetrating at least a portion between the first surface and the second surface of the glass layer; a first pad disposed on the first surface side of the glass layer and connected to one end of the through via in the first direction; and a second pad disposed on the second surface side of the glass layer and connected to the other end of the through via in the first direction, wherein the structure and / or arrangement of the first and second pads are different.

Description

Technical Field

[0001] The present invention relates to a printed circuit board.

Background Art

[0002] An interposer is a type of intermediate substrate used in semiconductor packaging technology. Usually, a redistribution layer is included in a portion connected to a chip for electrical connection between a chip and a substrate with a large pitch difference. Therefore, the interposer can have an asymmetric structure in the upper and lower parts, and in this case, there may be a limit in controlling the occurrence of warpage.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of several objects of the present invention is to provide a printed circuit board in which warpage control is easy even in an asymmetric structure.

Means for Solving the Problems

[0004] One of several solutions proposed in the present invention is to utilize a glass layer in which through vias are formed, and to form the arrangement, structure, etc. of pads on both sides of the through vias to be different.

[0005] For example, a printed circuit board according to an example may include a glass layer having a first surface and a second surface facing each other in a first direction, through vias penetrating at least a part between the first surface and the second surface of the glass layer, a first pad embedded on the first surface side of the glass layer and connected to one end portion of the through via in the first direction, and a second pad protruding on the second surface of the glass layer and connected to the other end portion of the through via in the first direction.

[0006] For example, a printed circuit board according to one example includes a glass layer having a first surface and a second surface facing each other in a first direction, a through via penetrating at least a portion between the first surface and the second surface of the glass layer, a first pad positioned on the first surface side of the glass layer and connected to one end of the through via in the first direction, and a second pad positioned on the second surface side of the glass layer and connected to the other end of the through via in the first direction, wherein the first pad and the second pad may have an asymmetrical structure with respect to the center line between the first surface and the second surface of the glass layer. [Effects of the Invention]

[0007] One of the various effects of the present invention is the ability to provide a printed circuit board that allows for easy warping control even in asymmetric structures. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram illustrating an example of an electronic equipment system. [Figure 2] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 3] Figure 2 is a schematic cross-sectional view showing an example of the manufacturing process of through-vias and the first and second pads included in the printed circuit board. [Figure 4] This is a schematic cross-sectional view of the process, illustrating an example of stage B in Figure 3. [Figure 5] This is a schematic cross-sectional view of another example of stage B in Figure 3. [Figure 6] This is a schematic cross-sectional view showing another example of a printed circuit board. [Modes for carrying out the invention]

[0009] The present invention will be described below with reference to the attached drawings. The shapes and sizes of the elements in the drawings may be exaggerated or reduced for clearer explanation.

[0010] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0011] Referring to the drawing, the electronic device 1000 houses the main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These are also coupled with other electronic components, which will be described later, to form various signal lines 1090.

[0012] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). It goes without saying that other different forms of chip-related electronic components may also be included. Furthermore, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may also be in the form of a package that includes the chips and electronic components mentioned above.

[0013] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth®, 3G, 4G, 5G, and later. It also includes any other diverse wireless or wired standards and protocols. Furthermore, it goes without saying that network-related component 1030 may be combined with chip-related component 1020.

[0014] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCCs (multi-layer ceramic condensers), etc. However, they are not limited to these, and may also include other passive elements in chip component form used for various other applications. It goes without saying that other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0015] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the main board 1010 or not. Examples of other electronic components include, but are not limited to, audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. Needless to say, other electronic components used for various purposes may also be included depending on the type of electronic device 1000.

[0016] The electronic device 1000 may be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smartwatch, automobile, server, etc. However, it is not limited to these, and it goes without saying that it may be any other electronic device that processes data.

[0017] Figure 2 is a schematic cross-sectional view showing an example of a printed circuit board.

[0018] Referring to the drawings, an example of a printed circuit board 100A may include a glass layer 111 having a first surface and a second surface facing each other in a first direction, a through via 131 penetrating at least a portion between the first and second surfaces of the glass layer 111, a first pad 131a positioned on the first surface side of the glass layer 111 and connected to one end of the through via 131 in the first direction, and a second pad 131b positioned on the second surface side of the glass layer and connected to the other end of the through via 131 in the first direction. The structure and / or arrangement of the first and second pads 131a, 131b may differ. For example, the first and second pads 131a, 131b may have an asymmetrical structure with respect to the center line C between the first and second surfaces of the glass layer 111.

[0019] As described above, the printed circuit board 100A in one example includes a glass layer 111 on which through vias 131 are formed, and in this case, the structure and / or arrangement of the first and second pads 131a and 131b formed on both sides of the through vias 131 may differ. Therefore, even when the build-up layer is formed asymmetrically with respect to the glass layer 111, the neutral axis caused by the mismatch in thermal expansion coefficients in the asymmetric structure can be shifted to the side with fewer layers, thereby realizing a structure advantageous for improving warpage. In this case, design freedom such as the number of wiring and via layers formed in the build-up layer can be ensured. Therefore, it can be easily applied, for example, to a substrate with an asymmetrical upper and lower surface, such as an interposer substrate.

[0020] On the other hand, the first pad 131a can be embedded on the first surface side of the glass layer 111, and the second pad 131b can protrude onto the second surface of the glass layer 111. Therefore, with respect to the first direction, the distance between the first pad 131a and the center line C may be shorter than the distance between the second pad 131b and the center line C. In this case, in an asymmetric structure where a larger number of build-up layers are formed on the first surface of the glass layer 111, the neutral axis caused by the mismatch in thermal expansion coefficients can be shifted downward, which may be advantageous in improving warpage. In addition, the overall thickness of the substrate can be reduced via the embedded first pad 131a.

[0021] In addition, the first pad 131a can have a shape with substantially rounded sides and bottom surface. In contrast, the second pad 131b can have a shape with substantially flat sides and bottom surface. For example, the surface connected to one end of the through via 131 has a substantially rounded shape, while the second pad 131b can have a surface connected to the other end of the through via 131 with a substantially flat shape. Due to such structural features, generally, the problems of connectivity and reliability caused by dimples that may occur during the formation of Through Glass Via (TGV) can be easily solved. Furthermore, through such first and second pads 131a and 131b, a sufficient bonding area in the alignment process between the via and the pad can be ensured. Therefore, the reliability can be further improved.

[0022] If necessary, the printed circuit board 100A according to an example can further include a first insulator 112 disposed on the first surface of the glass layer 111, a second insulator 113 disposed on the second surface of the glass layer 111, a plurality of first wiring layers 121 respectively disposed on or within the first insulator 112, and a plurality of first via layers 132 respectively disposed within the first insulator 112 and each connected to one or more of the plurality of first wiring layers 121. In the first direction, the first insulator 112 may be thicker than the second insulator 113. For example, the printed circuit board 100A according to an example can have an interposer structure with an asymmetric structure in which the build-up layer and the wiring layer are deflected and formed on the first surface side of the glass layer 111.

[0023] If necessary, the printed circuit board 100A according to an example is disposed on the first insulator 112, covers at least a part of the first wiring layer 121 disposed outermost in the first direction among the plurality of first wiring layers 121, and exposes at least another part thereof, and may further include a first resist layer 141 disposed on the second insulator 113, covering at least a part of the second pad 131b and exposing at least another part thereof. On at least another part of the outermost first wiring layer 121 exposed through the first resist layer 141 and on at least another part of the second pad 131b exposed through the second resist layer 142, a surface treatment layer P can be disposed respectively. Such a surface treatment layer P can include one or more of HASL (Hot Air Solder Leveling), ENIG (Electroless Nickel Immersion Gold), OSP (Organic Solderability Preservative), ImAg (Immersion Silver), and ImSn (Immersion Tin).

[0024] If necessary, the printed circuit board 100A according to one example may have a cavity H in the glass layer 111 that penetrates at least a portion of the glass layer 111 from the first surface of the glass layer 111 in a first direction. At least a portion of the first electronic component 151 may be placed in the cavity H. The first electronic component 151 can be attached to the back surface of the cavity H via an adhesive film B. The adhesive film B may be a DAF (Die Attach Film), but is not limited to this. The first insulator 112 may cover at least a portion of the first electronic component 151, or fill at least a portion of the cavity H. The first electronic component 151 may be connected to one or more of the multiple first wiring layers 121 via one or more of the multiple first via layers 132. In this way, the printed circuit board 100A according to one example can embed the first electronic component 151, and the cavity H of the glass layer 111 can be used for this. Therefore, the overall thickness of products to which such printed circuit boards 100A are applied can be further reduced, making it easier to improve the performance of the products.

[0025] The components of a printed circuit board 100A, as an example, will be described in more detail below with reference to the drawings.

[0026] The glass layer 111 may include glass, which is an amorphous solid. The glass may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, it is not limited to these, and alternative glass materials, such as fluorine glass, phosphoric acid glass, chalcogen glass, etc., can also be used. Furthermore, other additives may be included to form glass with specific physical properties. Such additives may include not only calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates and / or oxides of these elements and other elements. On the other hand, the glass layer 111 can be distinguished from organic insulating materials containing glass fibers (glass fiber, glass cloth, glass fabric), such as CCL (copper clad laminate) and PPG (prepreg). The glass layer 111 may be in the form of, for example, a glass plate.

[0027] The first and second insulators 112 and 113 may each contain an organic insulating material. The organic insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may contain an inorganic filler, an organic filler, and / or glass fiber (glass cloth, glass fabric) together with the resin. For example, the organic insulating material may be PPG (Prepreg), ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), etc., but is not limited to these. The first and second insulators 112 and 113 may have asymmetric structures. For example, the number of insulating layers contained in the first insulator 112 may be greater than the number of insulating layers contained in the second insulator 113. On the other hand, the boundaries between the multiple insulating layers contained in the first insulator 112 may be indistinct, but is not limited to this, and may be separated from each other as needed. The first and second insulators 112 and 113 may contain substantially the same organic insulating material, but are not limited to this, and may contain different organic insulating materials.

[0028] The first wiring layer 121 may contain metals. These metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first wiring layer 121 may include chemical copper formed by electroless plating as a seed layer, and based on this, electroplated copper formed by electroplating may be included as a pattern plating layer. However, it is not limited to this, and may include titanium (Ti) layers and copper (Cu) layers formed by sputtering as multiple seed layers as needed. The first wiring layer 121 can perform various functions depending on the design. For example, it may include signal patterns, power patterns, ground patterns, etc. These patterns can each have various forms such as lines, traces, planes, and pads. A pad may be a concept that includes a land. The first wiring layer 121 can consist of multiple layers, and the above-described content may be applied to each layer.

[0029] The through via 131 may contain metals. These metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the through via 131 may contain multiple seed layers of titanium (Ti) and copper (Cu) formed by sputtering, and an electroplated layer of electrolytic copper formed by electroplating based on these seed layers. However, it is not limited to this, and may also contain chemical copper formed by electroless plating as a seed layer if necessary. The through via 131 can perform various functions depending on the design. For example, it may include signal vias, power vias, ground vias, etc. If necessary, the length of the through via 131 in the first direction may be relatively shorter than the length of the glass layer 111 in the first direction. For example, both ends of the through via 131 in the first direction may be partially recessed compared to the first and second surfaces of the glass layer 111. The through via 131 may have a tapered side shape, such as an hourglass shape, on the cross-section in the first and second directions, but is not limited to this, and may have a substantially vertical cylindrical side shape. The through via 131 may also be a TGV (Through Glass Via). There may be multiple through vias 131, and the multiple through vias 131 may be spaced apart from each other in the second direction.

[0030] The first and second pads 131a and 131b may contain metals. These metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first and second pads 131a and 131b may each contain multiple seed layers of titanium (Ti) and copper (Cu) formed by sputtering, and based on these, electroplated copper may be formed as a pattern plating layer. However, the pads are not limited to these, and may also contain chemically formed copper as a seed layer if necessary. The first and second pads 131a and 131b can each perform various functions depending on the design. For example, they may include signal pads, power pads, ground pads, etc.

[0031] The first via layer 132 may contain metals. These metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first via layer 132 may include chemical copper formed by electroless plating as a seed layer, and electrocopper formed by electroplating based on this as a via plating layer. However, it is not limited to this, and may include titanium (Ti) and copper (Cu) layers formed by sputtering as multiple seed layers as needed. The first via layer 132 can perform various functions depending on the design. For example, it may include signal vias, power vias, ground vias, etc. The first via layer 132 may include filled vias in which the via holes are filled with metal, or it may include conformal vias in which metal is arranged along the walls of the via holes. The first via layer 132 may have a tapered shape in cross-section in the first and second directions. The first via layer 132 may consist of multiple layers, and the above-described content may be applied to each layer.

[0032] The first and second resist layers 141 and 142 may each contain an organic insulating material. The organic insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may contain an inorganic filler and / or an organic filler together with the resin. For example, the organic insulating material may be, but is not limited to, ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), SR (Solder Resist), etc. The first and second resist layers 141 and 142 may each consist of multiple layers. The first resist layer 141 may have an opening that exposes the first wiring layer 121 located on the outermost side in the first direction. The second resist layer 142 may have an opening that exposes the second pad 131b. There may be multiple openings. The portion exposed through the opening may be of the SMD (Solder Mask Defined) and / or NSMD (Non Solder Mask Defined) type.

[0033] The first electronic component 151 may be various types of active and / or passive components. For example, the first electronic component 151 may include, but is not limited to, an ICD (Integrated Circuit Device) or an EPIC (Embedded Passive Integrated Component). The first electronic component 151 can be attached to the bottom surface of the cavity H using an adhesive film B and positioned in a face-up configuration. The first electronic component 151 may have a plurality of connection pads on the side opposite to the side connected to the bottom surface of the cavity H. The plurality of connection pads may include metals such as copper (Cu) or aluminum (Al). Each of the plurality of connection pads may be connected to a first wiring layer 121, which is positioned on the innermost side with respect to the first direction, via a first via layer 132, which is positioned on the innermost side with respect to the first direction.

[0034] Figure 3 is a schematic cross-sectional view showing an example of the manufacturing process of the through-vias and the first and second pads included in the printed circuit board shown in Figure 2.

[0035] Referring to the drawings, first, through holes h can be formed in the glass layer 111 using etching, blasting, laser, plasma, etc. Then, a seed layer containing a titanium (Ti) layer and a copper (Cu) layer can be formed on the inner walls of the glass layer 111 and the through holes h by sputtering, and a plating layer containing electroplated copper can be formed by electroplating. Through this series of processes, the entire glass layer 111 in which the through holes h have been formed can be covered and filled with a metal layer M.

[0036] Next, a polishing process such as CMP (chemical mechanical polishing) can be performed to remove the metal layer M on the first and second surfaces of the glass layer 111. At this time, dimples or recesses can be formed at one end and the other end of the through hole h, respectively. For example, the first and second surfaces of the glass layer 111 may have steps between them and the one end and the other end of the through via 131 in the first direction, respectively, formed after the polishing process.

[0037] Next, a first pad 131a in an embedded form can be formed, connected to one end of the through via 131 in the first direction. A second pad 131b in a protruding form can also be formed, connected to the other end of the through via 131 in the first direction. A more detailed explanation of this will be provided with reference to Figures 4 and 5 below. By forming the first and second pads 131a and 131b at both ends of the through via 131 in this way, as described above, the neutral axis of the asymmetric structure can be adjusted to improve warping, the overall thickness can be reduced, and the reliability with the connecting via can be further improved.

[0038] Figure 4 is a schematic cross-sectional view of the process, illustrating an example of stage B in Figure 3.

[0039] Referring to the drawing, first, the glass layer 111 on the other end of the through via 131 can be polished by a cross-sectional glass polishing process. For example, the thickness of the glass layer 111 in the first direction may be reduced. Also, the other end of the through via 131 can be substantially coplanar with the second surface of the glass layer 111. In contrast, one end of the through via 131 can maintain a step difference with the first surface of the glass layer 111.

[0040] Next, a first masking film 211, patterned to expose one end of the through via 131, can be placed on the first surface of the glass layer 111, and a similarly patterned cover film 212 can be placed on the first masking film 211. A second masking film 213 can also be placed on the second surface of the glass layer 111 to cover the other end of the through via 131. A release layer may be placed between the first masking film 211 and the cover film 212. The cover film 212 may have chemical resistance.

[0041] Next, the exposed first surface of the glass layer 111 and the exposed one end of the through via 131 can be etched. Etching can remove a portion of the glass layer 111 and a portion of the through via 131, and a groove g can be formed on one end of the through via 131. After that, the first and second masking films 211, 213 and the cover film 212 can be peeled off and removed by mechanical and / or chemical methods.

[0042] Next, a seed layer S can be formed to cover the first and second surfaces of the glass layer 111, the wall surface of the groove g, and one end and the other end of the through via 131. The seed layer S can be formed by sputtering. For example, a titanium (Ti) layer and a copper (Cu) layer can be formed sequentially by sputtering. However, it is not limited to this, and if necessary, a seed layer S containing chemical copper may be formed by electroless plating. Alternatively, a combination of both can be used.

[0043] Next, a plating layer containing electroplated copper can be formed on the seed layer S by electroplating to form the first and second pads 131a and 131b. The first pad 131a may be an embedded pad, and the second pad 131b may be a protruding pad. The first pad 131a may have substantially rounded sides and bottom surfaces, and the second pad 131b may have substantially flat sides and bottom surfaces. Seed layers S may be placed between the ends of the through via 131 and the bottom surfaces of the first and second pads 131a and 131b. In this way, since seed layers S can be placed between the through via 131 and the first and second pads 131a and 131b, the connection reliability between the through via 131 and the first and second pads 131a and 131b may be improved.

[0044] Figure 5 is a schematic cross-sectional view of another example of stage B in Figure 3.

[0045] Referring to the drawing, first, the first surface of the glass layer 111 and one end of the through via 131 can be laser-processed to form a groove g. For example, a groove g of a desired shape can be formed by laser processing to engrave it. Therefore, in another example, the groove g can have a wider variety of shapes than the structure shown in the figure, and as a result, the first pad 131a can also have a wider variety of shapes. On the other hand, a portion of the glass layer 111 and a portion of the through via 131 can be removed by laser processing.

[0046] Next, the glass layer 111 on the other end of the through via 131 can be polished in a cross-sectional glass polishing process. For example, the thickness of the glass layer 111 in the first direction may be reduced. Also, the other end of the through via 131 may be substantially coplanar with the second surface of the glass layer 111. In contrast, the one end of the through via 131 may maintain a step difference with the first surface of the glass layer 111.

[0047] Next, a seed layer S can be formed to cover the first and second surfaces of the glass layer 111, the wall surface of the groove g, and one end and the other end of the through via 131. The seed layer S can be formed by sputtering. For example, a titanium (Ti) layer and a copper (Cu) layer can be formed sequentially by sputtering. However, it is not limited to this, and if necessary, a seed layer S containing chemical copper may be formed by electroless plating. Alternatively, a combination of both can be used.

[0048] Next, a plating layer containing electroplated copper can be formed on the seed layer S by electroplating to form the first and second pads 131a and 131b. The first pad 131a may be in the form of an embedded pad, and the second pad 131b may be in the form of a protruding pad. The first pad 131a may have substantially rounded sides and bottom surfaces, but is not limited to this, and since it is laser processed, it can also be realized in a substantially angular shape. The second pad 131b may have substantially flat sides and bottom surfaces. Seed layers S can be placed between the ends of the through via 131 on one and the other side and between the bottom surfaces of the first and second pads 131a and 131b, respectively. In this way, since seed layers S can be placed between the through via 131 and the first and second pads 131a and 131b, the connection reliability between the through via 131 and the first and second pads 131a and 131b may be improved.

[0049] On the other hand, the formation process of the glass layer 111, through via 131, groove g, first and second pads 131a, 131b, and seed layer S, the final structure, and the resulting technical effects described in Figures 3 to 5 can be applied substantially similarly to the printed circuit board 100A in Figure 2.

[0050] Figure 6 is a schematic cross-sectional view showing another example of a printed circuit board.

[0051] Referring to the drawings, another example of a printed circuit board 100B may include a frame 105 having a through-hole T, a glass layer 111 having a first and second surface facing each other in a first direction, a filler 115 filling at least a portion of the space between the frame 105 and the glass layer 111, a through-via 131 penetrating at least a portion between the first and second surfaces of the glass layer 111, a first pad 131a located on the first surface side of the glass layer 111 and connected to one end of the through-via 131 in the first direction, and a second pad 131b located on the second surface side of the glass layer and connected to the other end of the through-via 131 in the first direction.

[0052] Furthermore, the material may further include a plurality of first insulating layers 112 disposed on the first surface of the glass layer 111, a second insulating layer 113 disposed on the second surface of the glass layer 111, a plurality of first wiring layers 121 disposed on or within the plurality of first insulating layers 112, a second wiring layer 122 disposed on or within the second insulating layer 113, a plurality of first via layers 132 disposed within the plurality of first insulating layers 112 and each connected to one or more of the plurality of first wiring layers 121, a second via layer 133 disposed within the second insulating layer 113 and connected to the second wiring layer 122, a first resist layer 141 disposed on the plurality of first insulating layers 112 that covers at least a portion of the outermost first wiring layer 121 in the first direction and exposes at least another portion, and a second resist layer 142 disposed on the second insulating layer 113 that covers at least a portion of the second wiring layer 122 and exposes at least another portion.

[0053] The present invention may further include a first electronic component 151 embedded in the glass layer 111 and connected to the first wiring layer 121 located on the innermost side in the first direction via a first via layer 132 located on the innermost side in the first direction, a plurality of second electronic components 152, 153 each disposed on the first resist layer 141 and connected to at least other exposed portions of the first wiring layer 121 located on the outermost side in the first direction via a plurality of first electrically connecting metals 161, and a plurality of second electrically connecting metals 162 each disposed on the second resist layer 142 and connected to at least other exposed portions of the second wiring layer 122.

[0054] The components of another example of a printed circuit board 100B will be described in more detail below with reference to the drawings.

[0055] The frame 105 can include, but is not limited to, a material with excellent rigidity, such as Copper Clad Laminate (CCL) or Unclad CCL. Since the frame 105 can be used as a jig during the manufacturing process, the process can be advanced at the panel level via the frame 105. Furthermore, leaving the frame 105 on the final unit after singulation can be advantageous in warping control. The frame 105 can continuously surround the glass layer 111 in second and third directions. For example, the penetration T may be formed to have a continuous wall surface.

[0056] The filler 115 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler and / or organic filler together with the resin. For example, the organic insulating material may include ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), BS (Bonding Sheet), etc. If necessary, the filler 115 may be integrated with the first insulating layer 112 which is located on the innermost side in the first direction. For example, the space between the frame 105 and the glass layer 111 may be filled with the first insulating layer 112 which is located on the innermost side, in which case the filler 115 may be part of the first insulating layer 112 which is located on the innermost side. However, it is not limited thereto, and the filler 115 may be formed from a different material.

[0057] Each of the multiple first insulating layers 112 and second insulating layers 113 may contain an organic insulating material. The organic insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may contain an inorganic filler, an organic filler, and / or glass fiber (glass cloth, glass fabric) together with the resin. For example, the organic insulating material may be PPG (Prepreg), ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), etc., but is not limited to these. The multiple first insulating layers 112 and second insulating layers 113 may contain substantially the same insulating material to each other. The number of layers of the multiple first insulating layers 112 may be greater than the number of layers of the second insulating layers 113. For example, it may have an asymmetric structure with respect to the glass layer 111, and may have more layers in the direction in which the multiple second electronic components 152, 153 are mounted.

[0058] Each of the multiple first wiring layers 121 and second wiring layers 122 may contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the multiple first wiring layers 121 and second wiring layers 122 may include chemical copper formed by electroless plating as a seed layer, and based on this, electrocopper formed by electroplating may be included as a pattern plating layer. However, it is not limited to this, and titanium (Ti) layers and copper (Cu) layers formed by sputtering may be included as multiple seed layers as needed. Each of the multiple first wiring layers 121 and second wiring layers 122 can perform various functions depending on the design. For example, they may include signal patterns, power patterns, ground patterns, etc. These patterns may each have various forms such as lines, traces, planes, and pads. A pad may be a concept that includes a land. The number of layers of the multiple first wiring layers 121 may be greater than the number of layers of the second wiring layers 122. For example, it may have an asymmetric structure with respect to the glass layer 111, and may have more layers in the direction in which multiple second electronic components 152, 153 are mounted.

[0059] Each of the multiple first via layers 132 and second via layers 133 can contain a metal. The metals can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, each of the multiple first via layers 132 and second via layers 133 can contain chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this can contain electroplated copper as a via plating layer. However, it is not limited to this, and titanium (Ti) layers and copper (Cu) layers formed by sputtering may be included as multiple seed layers as needed. Each of the multiple first via layers 132 and second via layers 133 can perform various functions depending on the design. For example, they can include signal vias, power vias, ground vias, etc. The multiple first via layers 132 and second via layers 133 may each include filled vias in which the via holes are filled with metal, or they may include conformal vias in which metal is arranged along the walls of the via holes. The multiple first via layers 132 and second via layers 133 may each have a tapered shape in the cross-section in the first and second directions, for example, they may have tapered shapes in opposite directions. The number of layers of the multiple first via layers 132 may be greater than the number of layers of the second via layers 133. For example, they may have an asymmetric structure with respect to the glass layer 111, and there may be more layers in the direction in which the multiple second electronic components 152 and 153 are mounted.

[0060] The first electronic component 151 may be various types of active and / or passive components. For example, the first electronic component 151 may include, but is not limited to, an ICD (Integrated Circuit Device) or an EPIC (Embedded Passive Integrated Component). The first electronic component 151 can be embedded in the glass layer 111, and the specific structure therefor may be the same as that of the printed circuit board 100A in the example described above. However, it is not limited to this, and embedding may be possible in various other forms.

[0061] Each of the multiple second electronic components 152, 153 may include active and / or passive components. Active components may include various types of semiconductor chips, and passive components may include various types of chip-type components such as chip capacitors and chip inductors. Each semiconductor chip may include an integrated circuit (IC) die in which hundreds to millions or more elements are integrated within a single chip. In this case, the integrated circuit may be, but is not limited to, logic chips such as a central processor (e.g., CPU), graphics processor (e.g., GPU), field-programmable gate array (FPGA), digital signal processor, cryptographic processor, microprocessor, microcontroller, application processor (e.g., AP), analog-to-digital converter, or ASIC (application-specific IC).

[0062] The multiple first and second electrical connecting metals 161, 162 can each be formed from a low-melting-point metal, such as a tin (Sn)-aluminum (Al)-copper (Cu) solder, but this is merely an example and the material is not particularly limited thereto. The multiple first and second electrical connecting metals 161, 162 can each be balls, pins, etc. The multiple first and second electrical connecting metals 161, 162 can each be formed in multilayer or single layer. When formed in multilayer, it may include copper columns and solder, and when formed in single layer, it may include tin-silver solder, but is not limited thereto. The multiple first electrical connecting metals 161 may be used to mount multiple second electronic components 152, 153, and the multiple second electrical connecting metals 162 may be used to mount a printed circuit board 100B according to another example onto another board such as a main board.

[0063] On the other hand, the details of the glass layer 111, through-vias 131, first and second pads 131a, 131b, and first and second resist layers 141, 142 of the printed circuit board 100A as described in one example based on Figure 2, and the resulting technical effects, can be applied substantially similarly to the printed circuit board 100B as another example. Furthermore, the formation process of the glass layer 111, through-vias 131, first and second pads 131a, 131b, groove g, and seed layer S, the final structure, and the resulting technical effects, as described in Figures 3 to 5, can also be applied substantially similarly to the printed circuit board 100B as another example.

[0064] In this invention, the expression "cover" can include not only cases of covering the entire surface but also cases of covering at least a part of it, and can include cases of covering not only directly but also indirectly. Furthermore, the expression "fill" can include not only cases of completely filling but also cases of filling at least a part of it, and cases of almost completely filling it. For example, it can include cases where there are some gaps or voids. Also, the expression "enclose" can include not only cases of completely enclosing but also cases of partially enclosing and generally enclosing. Furthermore, "expose" can include cases of completely exposing but also cases of partially exposing it, and "exposure" can mean that the structure is exposed from what is embedded in it. For example, when an opening exposes a pad, it means exposing the pad from the resist layer, and a surface treatment layer or the like can be placed on the exposed pad.

[0065] In this invention, "placed within a through-hole or penetrating portion" includes not only cases where the object is completely placed within the through-hole or penetrating portion, but also cases where a portion of it protrudes upward or downward on the cross-section. For example, if the object is placed within a through-hole or penetrating portion on a plane, it can be interpreted in a broader sense.

[0066] In this invention, "substantially" can be determined to include process errors, positional deviations, and measurement errors that occur during the manufacturing process. For example, "substantially the same direction" can include not only completely identical directions but also nearly identical directions. Similarly, "substantially flat" can include not only completely flat but also nearly flat. Furthermore, "substantially having a specific shape" can include not only having exactly that shape but also having approximately that shape.

[0067] In this invention, "substantially identical insulating material" can mean not only completely identical insulating materials, but also insulating materials of the same type. Therefore, although the composition of the insulating material is substantially the same, the specific composition ratios may differ slightly.

[0068] In this invention, "on a cross-section" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. "On a plane" can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0069] In this invention, terms such as "lower side," "lower part," and "bottom surface" are used for convenience to mean the downward direction relative to the cross-section in the drawing, while terms such as "upper side," "upper part," and "top surface" are used to mean the opposite direction. However, this is merely a definition of direction for explanatory purposes, and it goes without saying that the scope of rights in the patent claims is not particularly limited by such descriptions of direction, and the concepts of up / down can be changed at any time.

[0070] In this invention, "connected" is a concept that includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept that includes both cases where they are physically connected and cases where they are not connected. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, within the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0071] In this invention, "thickness, width, length, depth, line width, spacing, pitch, separation distance, surface roughness," etc., can be measured using a scanning microscope or optical microscope based on a cross-section obtained by polishing or cutting the printed circuit board. The cut cross-section can be a vertical or horizontal cross-section, and each value can be measured based on the required cut cross-section. For example, the width of the upper and / or lower ends of a via can be measured on a cross-section cut along the central axis of the via. In this case, if the values ​​are not constant, the values ​​can be determined by the average value of the values ​​measured at any five points.

[0072] The expression "example" as used in this invention does not mean that each embodiment is the same as another, but is provided to highlight and illustrate the unique and distinct features of each. However, the examples presented above do not preclude their realization in combination with features of other examples. For example, even if a matter described in a particular example is not described in another example, it can be understood as a description related to that other example, unless there is a description in the other example that contradicts or is contrary to that description.

[0073] The terms used in this invention are for illustrative purposes only and are not intended to limit the invention. In this context, singular expressions include plural expressions unless the context clearly indicates a different meaning. [Explanation of symbols]

[0074] 1000:Electronic equipment 1010: Mainboard 1020: Chip-related components 1030: Network-related components 1040: Other parts 1050: Camera 1060: Antenna 1070: Display 1080: Battery 1090: Signal line 100A, 100B: Printed circuit board 105: Frame 111: Glass layer 112, 113: Insulator (insulating layer) 115: Filling material 121, 122: Wiring layer 131: Through-beam 131a, 131b: Pad 132, 133: Beer layer 141, 142: Resistance layer 151, 152, 153: Electronic components 161, 162: Electrically connected metals 211, 213: Masking film 212: Cover film

Claims

1. A glass layer having a first surface and a second surface facing each other in a first direction, A through via that penetrates at least a portion of the space between the first and second surfaces of the glass layer, A first pad embedded on the first surface side of the glass layer and connected to one end of the through via in the first direction, A printed circuit board comprising: a second pad protruding from the second surface of the glass layer and connected to the other end of the through via in the first direction.

2. The printed circuit board according to claim 1, wherein the first pad has a substantially rounded shape on its sides and bottom.

3. The printed circuit board according to claim 2, wherein the second pad has a substantially flat shape on its sides and bottom.

4. The printed circuit board according to claim 1, wherein the one end of the through via has a step difference with the first surface of the glass layer.

5. The printed circuit board according to claim 4, wherein the other end of the through via substantially coplanes with the second surface of the glass layer.

6. Between the one end of the through via and the bottom surface of the first pad, the first seed layer contained in the first pad is placed. The printed circuit board according to claim 1, wherein a second seed layer included in the second pad is disposed between the other end of the through via and the bottom surface of the second pad.

7. A first insulator disposed on the first surface of the glass layer, The present invention further includes a second insulator disposed on the second surface of the glass layer, The printed circuit board according to claim 1, wherein the first insulator is thicker than the second insulator in the first direction.

8. A plurality of first wiring layers are disposed on or inside the first insulator, The present invention further includes a second wiring layer disposed on or within the second insulator, The printed circuit board according to claim 7, wherein the plurality of first wiring layers have more layers than the second wiring layers.

9. A plurality of first via layers, each disposed within the first insulator and connected to one or more of the plurality of first wiring layers, The invention includes a second via layer disposed within the second insulator and connected to the second wiring layer, The printed circuit board according to claim 8, wherein the plurality of first via layers have a greater number of layers than the second via layers.

10. The glass layer has a cavity that penetrates at least a portion of the glass layer from the first surface of the glass layer in the first direction. At least a portion of the first electronic component is placed in the cavity. The first insulator covers at least a portion of the first electronic component and fills at least a portion of the cavity. The printed circuit board according to claim 9, wherein the first electronic component is connected to one or more of the plurality of first wiring layers via one or more of the plurality of first via layers.

11. A first resist layer is disposed on the first insulator, covering at least a portion of the first wiring layer that is located on the outermost side of the plurality of first wiring layers with reference to the first direction, and exposing at least a portion of the other; A second resist layer is disposed on the second insulator, covering at least a portion of the second wiring layer and exposing at least another portion; A second electronic component is disposed on the first resist layer and connected via a first electrically connecting metal to at least another exposed portion of the outermost first wiring layer, The printed circuit board according to claim 9, further comprising a second electrically connecting metal disposed on the second resist layer and connected to at least other exposed portions of the second wiring layer.

12. The frame further includes a through portion, At least a portion of the glass layer is disposed within the penetration portion, The printed circuit board according to claim 1, wherein the space between the frame and the glass layer is filled with a filler material.

13. A glass layer having a first surface and a second surface facing each other in a first direction, A through via that penetrates at least a portion of the space between the first and second surfaces of the glass layer, A first pad is positioned on the first surface side of the glass layer and connected to one end of the through via in the first direction, The glass layer includes a second pad positioned on the second surface side and connected to the other end of the through via in the first direction, A printed circuit board in which the first pad and the second pad have an asymmetrical structure with respect to the center line between the first and second surfaces of the glass layer.

14. The printed circuit board according to claim 13, wherein, with reference to the first direction, the distance between the first pad and the center line is shorter than the distance between the second pad and the center line.

15. The printed circuit board according to claim 13, wherein the surface of the first pad connected to one end of the through via has a substantially rounded shape, and the surface of the second pad connected to the other end of the through via has a substantially flat shape.

16. A first seed layer is placed between the first pad and the through via. The printed circuit board according to claim 13, wherein a second seed layer is disposed between the second pad and the through-via.

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