Power converter

Abstract

To obtain a power conversion device that can reduce energy loss. [Solution] A power conversion device according to one embodiment of the present disclosure comprises a first power terminal, an inductor, a capacitor, a switching circuit having a first switching element and a second switching element, a transformer having a first winding and a second winding, a rectifier circuit having a third switching element and a fourth switching element, a smoothing circuit, a second power terminal, and a control circuit capable of controlling the operation of the switching circuit and the rectifier circuit by performing a first control that repeats a first operation, a second operation, a third operation, a fourth operation, a fifth operation, and a sixth operation in this order.

Description

Technical Field

[0004] ,

[0006] , , , , , ,

[0005] , , ,

[0003] , , , , , ,

[0001] The present invention relates to a power conversion device for converting power.

Background Art

[0002] There is a so-called active clamp forward type DCDC converter in a power conversion device (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a power conversion device, it is desired to reduce energy loss, and further reduction of energy loss is expected.

[0005] It is desirable to provide a power conversion device that reduces energy loss.

Means for Solving the Problems

[0006] A power conversion device according to one embodiment of the present invention comprises a first power terminal, an inductor, a capacitor, a switching circuit, a transformer, a rectifier circuit, a smoothing circuit, and a control circuit. The first power terminal has a first connection terminal and a second connection terminal. The inductor has one end connected to the first connection terminal and the other end connected to the first node. The capacitor has one end connected to the first or second connection terminal and the other end connected to the second node. The switching circuit has a first switching element having one end connected to the third node and the other end connected to the second connection terminal, and a second switching element having one end connected to the second node and the other end connected to the third node. The transformer has a first winding having one end connected to the first node and the other end connected to the third node, and a second winding having one end connected to the fourth node and the other end connected to the fifth node. The rectifier circuit includes a third switching element having one end connected to the fifth node and the other end connected to the sixth node, and a fourth switching element having one end connected to the fourth node and the other end connected to the sixth node. The smoothing circuit is connected to the fourth node and the sixth node. The second power terminal is connected to the smoothing circuit. The control circuit can control the operation of the switching circuit and the rectifier circuit by performing a first control that repeats the first operation, second operation, third operation, fourth operation, fifth operation, and sixth operation in this order. The first operation includes turning the first switching element, the second switching element, the third switching element, and the fourth switching element to the off state. The second operation includes turning the second switching element and the fourth switching element to the on state, and turning the first switching element and the third switching element to the off state. The third operation includes turning on the third and fourth switching elements, and turning off the first and second switching elements.The fourth operation includes turning on the third switching element and turning off the first, second, and fourth switching elements. The fifth operation includes turning on the first and third switching elements and turning off the second and fourth switching elements. The sixth operation includes turning on the third switching element and turning off the first, second, and fourth switching elements. [Effects of the Invention]

[0007] According to one embodiment of the present invention, energy loss can be reduced. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a circuit diagram showing an example configuration of a power conversion device according to the first embodiment of the present invention. [Figure 2] Figure 2 is an explanatory diagram illustrating an example of an operating mode in the power converter shown in Figure 1. [Figure 3] Figure 3 is a timing waveform diagram showing an example of operation of the power converter shown in Figure 1. [Figure 4A] Figure 4A is an explanatory diagram illustrating one operating state of the power converter shown in Figure 1. [Figure 4B] Figure 4B is an explanatory diagram showing another operating state of the power converter shown in Figure 1. [Figure 4C] Figure 4C is an explanatory diagram illustrating another operating state of the power converter shown in Figure 1. [Figure 4D] Figure 4D is an explanatory diagram illustrating another operating state of the power converter shown in Figure 1. [Figure 4E] Figure 4E is an explanatory diagram illustrating another operating state of the power converter shown in Figure 1. [Figure 4F] Figure 4F is an explanatory diagram illustrating another operating state of the power converter shown in Figure 1. [Figure 4G] FIG. 4G is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 1. [Figure 4H] FIG. 4H is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 1. [Figure 4I] FIG. 4I is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 1. [Figure 4J] FIG. 4J is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 1. [Figure 4K] FIG. 4K is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 1. [Figure 4L] FIG. 4L is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 1. [Figure 5] FIG. 5 is a timing waveform diagram showing another operation example of the power conversion device shown in FIG. 1. [Figure 6] FIG. 6 is a timing waveform diagram showing another operation example of the power conversion device shown in FIG. 1. [Figure 7] FIG. 7 is a timing waveform diagram showing an operation example of the power conversion device according to the reference example. [Figure 8] FIG. 8 is a timing waveform diagram showing an operation example of the power conversion device according to another reference example. [Figure 9] FIG. 9 is a characteristic diagram showing a characteristic example of the power conversion device shown in FIG. 1. [Figure 10] FIG. 10 is a circuit diagram showing a configuration example of the power conversion device according to the second embodiment. [Figure 11] FIG. 11 is a timing waveform diagram showing an operation example of the power conversion device shown in FIG. 10. [Figure 12A] FIG. 12A is an explanatory diagram showing an operating state of the power conversion device shown in FIG. 10. [Figure 12B] FIG. 12B is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10. [Figure 12C] FIG. 12C is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10. [Figure 12D]FIG. 12D is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10. [Figure 12E] FIG. 12E is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10. [Figure 12F] FIG. 12F is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10. [Figure 12G] FIG. 12G is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10. [Figure 12H] FIG. 12H is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10. [Figure 12I] FIG. 12I is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10. [Figure 12J] FIG. 12J is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10. [Figure 12K] FIG. 12K is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10. [Figure 12L] FIG. 12L is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10. [Figure 12M] FIG. 12M is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10. [Figure 13] FIG. 13 is a circuit diagram showing a configuration example of the power conversion device according to the third embodiment. [Figure 14] FIG. 14 is an explanatory diagram showing an example of an operation mode in the power conversion device shown in FIG. 13. [Figure 15] FIG. 15 is a timing waveform diagram showing an example of an operation of the power conversion device shown in FIG. 13. [Figure 16A] FIG. 16A is an explanatory diagram showing an operating state of the power conversion device shown in FIG. 13. [Figure 16B] FIG. 16B is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 13. [Figure 16C] FIG. 16C is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 13. [Figure 16D] Figure 16D is an explanatory diagram illustrating another operating state of the power converter shown in Figure 13. [Figure 16E] Figure 16E is an explanatory diagram illustrating another operating state of the power converter shown in Figure 13. [Figure 16F] Figure 16F is an explanatory diagram showing another operating state of the power converter shown in Figure 13. [Figure 16G] Figure 16G is an explanatory diagram showing another operating state of the power converter shown in Figure 13. [Figure 16H] Figure 16H is an explanatory diagram showing another operating state of the power converter shown in Figure 13. [Figure 16I] Figure 16I is an explanatory diagram illustrating another operating state of the power converter shown in Figure 13. [Figure 16J] Figure 16J is an explanatory diagram illustrating another operating state of the power converter shown in Figure 13. [Figure 16K] Figure 16K is an explanatory diagram illustrating another operating state of the power converter shown in Figure 13. [Figure 16L] Figure 16L is an explanatory diagram showing another operating state of the power converter shown in Figure 13. [Figure 16M] Figure 16M is an explanatory diagram showing another operating state of the power converter shown in Figure 13. [Figure 17] Figure 17 is a circuit diagram showing one example configuration of a power conversion device according to a modified example. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described in detail below with reference to the drawings. The description will be in the following order. 1. First Embodiment 2. Second Embodiment 3. Third Embodiment

[0010] <1. First Embodiment> [Example Configuration] Figure 1 shows an example configuration of a power converter (power converter 1) according to one embodiment of the present invention. In this example, the power converter 1 is connected to a high-voltage battery BH and a low-voltage battery BL. The power converter 1 is configured to convert power by stepping down the voltage supplied from the high-voltage battery BH and to supply the converted power to the low-voltage battery BL. The power converter 1 has terminals T11, T12, a capacitor 11, a capacitor 12, a current sensor 13, an inductor 14, a switching circuit 15, a transformer 16, a rectifier circuit 17, a smoothing circuit 18, a voltage sensor 21, a control circuit 30, and terminals T21, T22. Capacitors 11, 12, 13, 14, and 15 constitute the primary circuit of the power converter 1, while the rectifier circuit 17, smoothing circuit 18, and voltage sensor 21 constitute the secondary circuit of the power converter 1.

[0011] Terminals T11 and T12 are configured to receive voltage VH from the high-voltage battery BH. Within the power converter 1, terminal T11 is connected to voltage line L11A, and terminal T12 is connected to reference voltage line L12. Terminal T11 is connected to the positive terminal of the high-voltage battery BH, and terminal T12 is connected to the negative terminal of the high-voltage battery BH.

[0012] One end of the capacitor 11 is connected to the voltage line L11A, and the other end is connected to the reference voltage line L12.

[0013] One end of the capacitor 12 is connected to the voltage line L11A, and the other end is connected to node N11.

[0014] One end of the current sensor 13 is connected to the voltage line L11A, and the other end is connected to the voltage line L11B. The current sensor 13 is configured to detect the current ILr flowing from the voltage line L11A to the voltage line L11B.

[0015] One end of the inductor 14 is connected to the voltage line L11B, and the other end is connected to the winding 16A (described later) of the transformer 16.

[0016] The switching circuit 15 is configured to perform switching operations based on control signals Gmain and Gclamp. The switching circuit 15 has transistors Qmain and Qclamp. Transistors Qmain and Qclamp are switching elements that perform switching operations based on control signals Gmain and Gclamp, respectively. Transistors Qmain and Qclamp are constructed using, for example, N-type field-effect transistors (FETs). Each of transistors Qmain and Qclamp has a body diode and a parasitic capacitor. For example, the anode of the body diode of transistor Qmain is connected to the source of the body of transistor Qmain, and the cathode is connected to the drain of the body of transistor Qmain. One end of the parasitic capacitor of transistor Qmain is connected to the source of the body of transistor Qmain, and the other end is connected to the drain of the body of transistor Qmain. The same applies to transistor Qclamp. In this example, N-type field-effect transistors are used, but any switching element can be used. The drain of transistor Qmain is connected to node N12, the source is connected to the reference voltage line L12, and the control signal Gmain is supplied to the gate. The drain of transistor Qclamp is connected to node N11, its source is connected to node N12, and the gate is supplied with the control signal Gclamp.

[0017] The transformer 16 is configured to isolate the primary and secondary circuits, convert the AC voltage supplied from the primary circuit according to the transformation ratio of the transformer 16, and supply the converted AC voltage to the secondary circuit. The transformer 16 has windings 16A and 16B. Winding 16A is the primary winding of the transformer 16, with one end connected to the other end of the inductor 14 and the other end connected to node N12. Winding 16B is the secondary winding of the transformer 16, with one end connected to voltage line L21A (described later) and the other end connected to node N13.

[0018] The rectifier circuit 17 is configured to rectify the AC voltage output from the winding 16B of the transformer 16. The rectifier circuit 17 has transistors Qfwd and Qfly. Transistors Qfwd and Qfly are switching elements that perform switching operations based on control signals Gfwd and Gfly, respectively. Transistors Qfwd and Qfly are constructed using, for example, N-type field-effect transistors, similar to transistors Qmain and Qclamp. Transistors Qfwd and Qfly have a body diode and a parasitic capacitor, similar to transistors Qmain and Qclamp. The drain of transistor Qfwd is connected to node N13, its source is connected to the reference voltage line L22, and the control signal Gfwd is supplied to its gate. The drain of transistor Qfly is connected to the voltage line L21A, its source is connected to the reference voltage line L22, and the control signal Gfly is supplied to its gate.

[0019] The smoothing circuit 18 is configured to smooth the voltage rectified by the rectifier circuit 17. The smoothing circuit 18 includes an inductor 19 and a capacitor 20. One end of the inductor 19 is connected to voltage line L21A, and the other end is connected to voltage line L21B. One end of the capacitor 20 is connected to voltage line L21B, and the other end is connected to reference voltage line L22.

[0020] One end of the voltage sensor 21 is connected to the voltage line L21B, and the other end is connected to the reference voltage line L22. The voltage sensor 21 is configured to detect the voltage VL in the voltage line L21B, with the voltage in the reference voltage line L22 as the reference.

[0021] The control circuit 30 is configured to control the operation of the power converter 1 based on the current ILr detected by the current sensor 13 and the voltage VL detected by the voltage sensor 21. Specifically, the control circuit 30 controls the operation of transistors Qmain, Qclamp, Qfwd, and Qfly using control signals Gmain, Gclamp, Gfwd, and Gfly so that the voltage VL is maintained at a predetermined target voltage, based on the voltage VL detected by the voltage sensor 21. The control circuit 30 also sets the operating mode of the power converter 1 based on the current ILr detected by the current sensor 13. That is, since the current ILr is the current corresponding to the output current Iout output from terminals T21 and T22 of the power converter 1, the control circuit 30 sets the operating mode of the power converter 1 to the operating mode corresponding to the output current Iout based on the current ILr. The control circuit 30 is configured using, for example, a microcontroller.

[0022] Terminals T21 and T22 are configured to supply the voltage VL generated by the power converter 1 to the low-voltage battery BL. Within the power converter 1, terminal T21 is connected to voltage line L21B, and terminal T22 is connected to reference voltage line L22. In addition, terminal T21 is connected to the positive terminal of the low-voltage battery BL, and terminal T22 is connected to the negative terminal of the low-voltage battery BL.

[0023] Here, terminals T11 and T12 correspond to a specific example of the "first power terminal" in one embodiment of the present disclosure. Terminal T11 corresponds to a specific example of the "first connection terminal" in one embodiment of the present disclosure. Terminal T12 corresponds to a specific example of the "second connection terminal" in one embodiment of the present disclosure. Inductor 14 corresponds to a specific example of the "inductor" in one embodiment of the present disclosure. Capacitor 12 corresponds to a specific example of the "capacitor" in one embodiment of the present disclosure. Switching circuit 15 corresponds to a specific example of the "switching circuit" in one embodiment of the present disclosure. Transistor Qmain corresponds to a specific example of the "first switching element" in one embodiment of the present disclosure. Transistor Qclamp corresponds to a specific example of the "second switching element" in one embodiment of the present disclosure. Transformer 16 corresponds to a specific example of the "transformer" in one embodiment of the present disclosure. Winding 16A corresponds to a specific example of the "first winding" in one embodiment of the present disclosure. Winding 16B corresponds to a specific example of the "second winding" in one embodiment of the present disclosure. The rectifier circuit 17 corresponds to a specific example of the "rectifier circuit" in one embodiment of the present disclosure. The transistor Qfwd corresponds to a specific example of the "third switching element" in one embodiment of the present disclosure. The transistor Qfly corresponds to a specific example of the "fourth switching element" in one embodiment of the present disclosure. The smoothing circuit 18 corresponds to a specific example of the "smoothing circuit" in one embodiment of the present disclosure. The terminals T21 and T22 correspond to a specific example of the "second power terminal" in one embodiment of the present disclosure. The control circuit 30 corresponds to a specific example of the "control circuit" in one embodiment of the present disclosure.

[0024] [Action and function] Next, the operation and function of the power converter 1 of this embodiment will be described.

[0025] (Overview of overall operation) First, the overall operation of the power converter 1 will be explained with reference to Figure 1. The control circuit 30 generates control signals Gmain, Gclamp, Gfwd, and Gfly based on the voltage VL. The switching circuit 15 performs switching operations based on the control signals Gmain and Gclamp. The rectifier circuit 17 performs switching operations based on the control signals Gfwd and Gfly. As a result, the power converter 1 converts the power supplied from the high-voltage battery BH and supplies the converted power to the low-voltage battery BL. Based on the voltage VL detected by the voltage sensor 21, the control circuit 30 controls the operation of transistors Qmain, Qclamp, Qfwd, and Qfly using the control signals Gmain, Gclamp, Gfwd, and Gfly so that the voltage VL maintains a predetermined target voltage. The control circuit 30 also sets the operating mode of the power converter 1 based on the current ILr detected by the current sensor 13.

[0026] (Detailed operation) Figure 2 shows an example of the operating modes of the power converter 1. The power converter 1 has three operating modes M1 to M3, and the control circuit 30 sets the operating mode of the power converter 1 to the operating mode corresponding to the output current Iout based on the current ILr.

[0027] Specifically, the control circuit 30 sets the operating mode of the power converter 1 to operating mode M1 when the output current Iout is greater than the threshold Ith1. Furthermore, the control circuit 30 sets the operating mode of the power converter 1 to operating mode M2 ​​when the output current Iout is less than or equal to the threshold Ith1 and greater than the threshold Ith2. Finally, the control circuit 30 sets the operating mode of the power converter 1 to operating mode M3 when the output current Iout is less than or equal to the threshold Ith2. The operating modes M1 to M3 are described in detail below.

[0028] (Operating mode M1) Figure 3 shows an example of operation of the power converter 1 in operating mode M1, where (A) shows the waveform of the control signal Gmain, (B) shows the waveform of the control signal Gclamp, (C) shows the waveform of the control signal Gfwd, (D) shows the waveform of the control signal Gfly, (E) is the voltage VLr across the inductor 14, (F) shows the waveform of the current ILr, (G) shows the waveform of the current IQmain flowing through transistor Qmain, (H) shows the waveform of the current IQclamp flowing through transistor Qclamp, (I) shows the waveform of the current ILch flowing through inductor 19, (J) shows the waveform of the current IQfwd flowing through transistor Qfwd, (K) shows the waveform of the current IQfly flowing through transistor Qfly, and (L) shows the waveform of the drain-source voltage Vds_Qmain of transistor Qmain. The voltage VLr is the voltage of voltage line L11B, with the voltage at one end of winding 16A of transformer 16 as the reference. Current IQmain is the current that is positive when it flows from the drain to the source of transistor Qmain. Current IQclamp is the current that is positive when it flows from the source to the drain of transistor Qclamp. Current IQfwd is the current that is positive when it flows from the source to the drain of transistor Qfwd. Current IQfly is the current that is positive when it flows from the source to the drain of transistor Qfly. In Figures 3(A) to (D), "H" indicates a high signal level, and "L" indicates a low signal level.

[0029] Figures 4A to 4L show the operating states of power converter 1 at various time periods in Figure 3. For ease of explanation, the circuits in Figures 4A to 4L are simplified. Also, for ease of explanation, voltage lines L11A and L11B shown in Figure 1 are shown as voltage line L11 in Figures 4A to 4L. Furthermore, the on / off states of transistors Qmain, Qclamp, Qfwd, and Qfly are also indicated in Figures 4A to 4L. In Figures 4A to 4L, "on" is circled immediately after a change from off to on, and "off" is circled immediately after a change from on to off.

[0030] At timing t11, the control circuit 30 changes the control signal Gclamp from a high level to a low level and the control signal Gfwd from a low level to a high level (Figures 3(B), (C)). As a result, as shown in Figure 4A, transistor Qclamp changes from the ON state to the OFF state, and transistor Qfwd changes from the OFF state to the ON state. Transistor Qmain is in the OFF state, and transistor Qfly is in the ON state. At timing t11, the drain-source voltage Vds_Qmain of transistor Qmain is the voltage corresponding to the sum of the voltages VH at terminals T11 and T12 and the voltage Vclamp of capacitor 12 (VH+Vclamp) (Figures 3(L), ​​4A). Therefore, at timing t11, the voltage at node N12 is higher than the voltage at voltage line L11. During the period from timing t11 to t12, current flows in the primary side circuit of power converter 1 as shown in Figure 4A. Current flows from node N12 to inductor 14 in winding 16A of transformer 16. The absolute value of this current (current ILr) increases (Figure 3(F)). In transistor Qmain, current flows from source to drain through the parasitic capacitor. As a result, the parasitic capacitor of transistor Qmain is gradually discharged, and the drain-source voltage Vds_Qmain decreases (Figure 3(L)). In addition, current flows in the secondary circuit of power converter 1 as shown in Figure 4A.

[0031] Then, at timing t12, the polarity of the voltage VL changes from negative to positive, as shown in Figure 3(E). As a result, the voltage at one end of winding 16A of transformer 16 becomes lower than the voltage at voltage line L11B. During the period from timing t12 to t13, current flows through the same paths as in the previous period in the primary and secondary circuits of power converter 1, as shown in Figure 4B. The absolute values ​​of the current ILr, current IQmain, and current IQclamp in the primary circuit begin to decrease (Figures 3(F), (G), (H)), and the absolute values ​​of the current IQfwd and current IQfly in the secondary circuit begin to decrease (Figures 3(J), (K)). The drain-source voltage Vds_Qmain continues to decrease and at some point during the period from timing t11 to t13, it falls below the voltage VH (Figure 3(L)).

[0032] Then, at timing t13, the control circuit 30 changes the control signal Gfly from a high level to a low level (Figure 3(D)). As a result, transistor Qfly changes from the ON state to the OFF state, as shown in Figure 4C. During the period from timing t13 to t14, current flows in the secondary circuit of the power converter 1 as shown in Figure 4C. Also, in the primary circuit of the power converter 1, current flows through the same path as in the previous period, as shown in Figure 4C.

[0033] Then, at timing t14, the control circuit 30 changes the control signal Gmain from a low level to a high level (Figure 3(A)). As a result, transistor Qmain changes from the off state to the on state, as shown in Figure 4D. Since transistor Qmain is in the on state, the drain-source voltage Vds_Qmain becomes 0V (Figure 3(L)). During the period from timing t14 to t15, current flows in the primary circuit of power converter 1 as shown in Figure 4D. Also, in the secondary circuit of power converter 1, current flows along the same path as in the previous period, as shown in Figure 4D.

[0034] Then, at timing t15, as shown in Figures 3(F) and (G), the polarity of the currents ILr and IQmain changes from negative to positive. As a result, during the period from timing t15 to t16, current flows in the primary circuit of the power converter 1 as shown in Figure 4E. Current flows from inductor 14 to node N12 in winding 16A of transformer 16. Also, in the secondary circuit of the power converter 1, current flows along the same path as in the previous period, as shown in Figure 4E.

[0035] Then, at timing t16, as shown in Figure 3(K), the current IQfly in the secondary circuit becomes 0A. As a result, during the period from timing t16 to t17, current flows in the secondary circuit of power converter 1 as shown in Figure 4F. The current ILch in the secondary circuit begins to increase (Figure 3(I)). Also, in the primary circuit of power converter 1, current flows along the same path as in the previous period, as shown in Figure 4F.

[0036] Then, at timing t17, the control circuit 30 changes the control signal Gmain from a high level to a low level (Figure 3(A)). As a result, transistor Qmain changes from the ON state to the OFF state, as shown in Figure 4G. Consequently, during the period from timing t17 to t18, current flows in the primary circuit of power converter 1 as shown in Figure 4G. In transistor Qmain, current flows from the drain to the source via the parasitic capacitor. As a result, the parasitic capacitor of transistor Qmain is gradually charged, and the drain-source voltage Vds_Qmain increases (Figure 3(L)). Also, current flows in the secondary circuit of power converter 1 as shown in Figure 4G. In the secondary circuit, the absolute value of the current IQfwd begins to decrease, and the absolute value of the current IQfly begins to increase from 0A (Figure 3(J),(K)).

[0037] Then, at timing t18, charging of the parasitic capacitor of transistor Qmain is completed, and the voltage at node N12 becomes higher than the voltage at voltage line L11. During the period from timing t18 to t19, current flows in the primary circuit of power converter 1 as shown in Figure 4H. Since charging of the parasitic capacitor of transistor Qmain is completed, no current flows through transistor Qmain (Figure 3(G)). The absolute value of the current ILr in the primary circuit begins to decrease (Figure 3(F)). Also, in the secondary circuit of power converter 1, current flows along the same path as in the previous period, as shown in Figure 4H.

[0038] Then, at timing t19, the control circuit 30 changes the control signal Gfwd from a high level to a low level (Figure 3(C)). As a result, the transistor Qfwd changes from the ON state to the OFF state, as shown in Figure 4I. During the period from timing t19 to t20, current flows in the secondary circuit of the power converter 1 as shown in Figure 4I. Also, in the primary circuit of the power converter 1, current flows through the same path as in the previous period, as shown in Figure 4I.

[0039] Then, at timing t20, the control circuit 30 changes the control signals Gclamp and Gfly from a low level to a high level (Figures 3(B) and 3(D)). As a result, transistors Qclamp and Qfly change from the off state to the on state, as shown in Figure 4J. Consequently, during the period from timing t20 to t21, current flows in the primary and secondary circuits of the power converter 1, as shown in Figure 4J.

[0040] Then, at timing t21, as shown in Figure 3(J), the current IQfwd in the secondary circuit becomes 0A. During the period from timing t21 to t22, current flows in the secondary circuit of power converter 1 as shown in Figure 4K. In the secondary circuit, the absolute value of the current IQfly begins to decrease (Figure 3(K)). Also, in the primary circuit of power converter 1, current flows along the same path as in the previous period, as shown in Figure 4K.

[0041] Then, at timing t22, as shown in Figures 3(F) and (H), the polarity of the currents ILr and IQclamp in the primary circuit changes from positive to negative. As a result, during the period from timing t22 to t23, current flows in the primary circuit of the power converter 1 as shown in Figure 4L. In the winding 16A of the transformer 16, current flows from node N12 towards inductor 14. Also, in the secondary circuit of the power converter 1, current flows along the same path as in the previous period, as shown in Figure 4L.

[0042] Then, at timing t23, the control circuit 30 changes the control signal Gclamp from a high level to a low level and changes the control signal Gfwd from a low level to a high level (Figure 3(B), (C)). This operation is the same as the operation at timing t11.

[0043] In operating mode M1, the power converter 1 repeats the operation at timings t11 to t23.

[0044] Here, the control related to operating mode M1 corresponds to a specific example of the "first control" in one embodiment of this disclosure. The operation at timings t19 to t20 corresponds to a specific example of the "first operation" in one embodiment of this disclosure. The operation at timings t20 to t23 corresponds to a specific example of the "second operation" in one embodiment of this disclosure. The operation at timings t11 to t13 corresponds to a specific example of the "third operation" in one embodiment of this disclosure. The operation at timings t13 to t14 corresponds to a specific example of the "fourth operation" in one embodiment of this disclosure. The operation at timings t14 to t17 corresponds to a specific example of the "fifth operation" in one embodiment of this disclosure. The operation at timings t17 to t19 corresponds to a specific example of the "sixth operation" in one embodiment of this disclosure.

[0045] (Operating mode M2) Figure 5 shows an example of operation of the power converter 1 in operating mode M2, where (A) shows the waveform of the control signal Gmain, (B) shows the waveform of the control signal Gclamp, (C) shows the waveform of the control signal Gfwd, (D) shows the waveform of the control signal Gfly, (E) shows the waveform of the current ILr, (F) shows the waveform of the current IQmain flowing through transistor Qmain, (G) shows the waveform of the current IQclamp flowing through transistor Qclamp, (H) shows the waveform of the current ILch flowing through inductor 19, (I) shows the waveform of the current IQfwd flowing through transistor Qfwd, (J) shows the waveform of the current IQfly flowing through transistor Qfly, and (K) shows the waveform of the drain-source voltage Vds_Qmain of transistor Qmain.

[0046] In this operating mode M2, the control circuit 30 changes the control signal Gclamp from a high level to a low level at timing t31, changes the control signal Gmain from a low level to a high level at timing t32, changes the control signal Gmain from a high level to a low level at timing t33, and changes the control signal Gclamp from a low level to a high level at timing t34 (Figure 5(A), (B)).

[0047] In this operating mode M2, the control circuit 30 maintains the control signals Gfwd and Gfly at a low level (Figure 5(C), (D)). Therefore, transistors Qfwd and Qfly remain in the off state. In this case, current flows through transistors Qfwd and Qfly via the body diode and parasitic capacitor. That is, in this operating mode M2, the rectifier circuit 17 does not perform switching operations as in operating mode M1, but operates as a diode rectifier circuit.

[0048] (Operating mode M3) Figure 6 shows an example of operation of the power converter 1 in operating mode M3, where (A) shows the waveform of the control signal Gmain, (B) shows the waveform of the control signal Gclamp, (C) shows the waveform of the control signal Gfwd, (D) shows the waveform of the control signal Gfly, (E) shows the waveform of the voltage VL, and (F) shows the waveform of the current ILch flowing through the inductor 19.

[0049] In this operating mode M3, the control circuit 30 intermittently performs the operation in operating mode M2. That is, during period P1, the control circuit 30 controls the power converter 1 to operate in the same manner as in operating mode M2. As a result, the voltage VL rises (Figure 6(E)). Then, during period P2, the control circuit 30 maintains the control signals Gmain, Gclamp, Gfwd, and Gfly at low levels. As a result, the voltage VH falls (Figure 6(E)). The control circuit 30 alternately repeats the operation of period P1 and period P2.

[0050] In this way, the control circuit 30 sets the operating mode of the power converter 1 to one of the above-described operating modes M1 to M3. Specifically, as shown in Figure 2, the control circuit 30 sets the operating mode of the power converter 1 to operating mode M1 when the output current Iout is greater than the threshold Ith1. The control circuit 30 also sets the operating mode of the power converter 1 to operating mode M2 ​​when the output current Iout is less than or equal to the threshold Ith1 and greater than the threshold Ith2. The control circuit 30 also sets the operating mode of the power converter 1 to operating mode M3 when the output current Iout is less than or equal to the threshold Ith2.

[0051] The threshold Ith1 is set to an output current Iout such that, for example, in operating mode M1, the lowest current value Imin of the current ILch shown in Figure 3(I) becomes 0A.

[0052] Furthermore, the threshold Ith2 is set to an output current Iout such that, in operating mode M2, the duty cycle of the control signal Gmain becomes equal to the lower limit of the duty cycle of the control signal Gmain that the control circuit 30 can generate. In other words, in operating mode M2, the smaller the output current Iout, the smaller the duty cycle of the control signal Gmain can become. If the duty cycle of the control signal Gmain becomes too small, the pulse width of the control signal Gmain becomes too narrow, so a lower limit is defined for the duty cycle of the control signal Gmain, and the control circuit 30 cannot set the duty cycle to a value smaller than this lower limit. The threshold Ith2 is set to an output current Iout such that the duty cycle of the control signal Gmain becomes equal to this lower limit.

[0053] (Reference example) Next, the operation of this embodiment will be explained in comparison with several reference examples.

[0054] Figure 7 shows an example of operation in operating mode M1 of the power converter 1R according to the reference example. For the sake of explanation, in Figure 7, the waveform of the power converter 1 according to this embodiment (Figure 3) is shown as a dashed line.

[0055] In this example, the control circuit 30 changes the control signals Gclamp and Gfly from high to low levels at timing t41, and changes the control signals Gmain and Gfwd from low to high levels at timing t42 (Figures 7(A)~(D)). During this period from timing t41 to t42, the drain-source voltage Vds_Qmain of transistor Qmain decreases. At timing t42, when transistor Qmain changes from the off state to the on state based on the control signal Gmain, it is desirable for this drain-source voltage Vds_Qmain to be low, but in this power converter 1R, the drain-source voltage Vds_Qmain tends to be high. As a result, the turn-on loss in power converter 1R becomes large.

[0056] For example, in this power converter 1R, it is possible to increase the inductance of inductor 14 in order to lower the drain-source voltage Vds_Qmain at timing t42. However, in this case, the size of inductor 14 will increase, which may increase the cost of power converter 1R. Alternatively, for example, in this power converter 1R, it is also possible to increase the excitation current of transformer 16 in order to lower the drain-source voltage Vds_Qmain at timing t42. However, in this case, the efficiency may decrease.

[0057] Figure 8 shows an example of operation in operating mode M1 of a power converter 1S according to another reference example, where (A) shows the waveform of the control signal Gmain, (B) shows the waveform of the control signal Gclamp, (C) shows the waveform of the control signal Gfwd, (D) shows the waveform of the control signal Gfly, (E) shows the waveform of the current ILr, (F) shows the waveform of the drain current ID_Qclamp of transistor Qclamp, and (G) shows the waveform of the drain-source voltage Vds_Qmain of transistor Qmain. This power converter 1S utilizes the technology described in Patent Document 1.

[0058] In this example, the control circuit 30 changes the control signal Gfwd from a low level to a high level at timing t51, changes the control signals Gclamp and Gfly from high levels to low levels at timing t52, and changes the control signal Gmain from a low level to a high level at timing t53 (Figures 8(A)~(D)). In this example, at timings t51~t52, transistors Qclamp, Qfwd, and Qfly are all turned on. This increases the current flowing through the leakage inductance of transformer 16, and this current is used to charge and discharge the parasitic capacitors of transistors Qmain and Qclamp, thereby reducing the turn-on loss of transistor Qmain.

[0059] However, in this case, as shown in Figure 8(F), the current flowing through transistor Qclamp may increase sharply just before timing t52. In this case, noise countermeasures become necessary. Furthermore, because a large current flows through transistor Qclamp in this way, conduction losses become large, and since transistor Qclamp is turned off at timing t52 while a large current is flowing through it, turn-off losses become large.

[0060] On the other hand, in the power converter 1 according to this embodiment, as shown in Figure 3, the control circuit 30 changes the control signal Gclamp from a high level to a low level and the control signal Gfwd from a low level to a high level at timing t11, changes the control signal Gfly from a high level to a low level at timing t13, and changes the control signal Gmain from a low level to a high level at timing t14. In other words, the control circuit 30 sets both the control signals Gfwd and Gfly to a high level during the period from timing t11 to t13 after the control signal Gclamp has changed from a high level to a low level. As a result, during this period from timing t11 to t13, both ends of the winding 16B of the transformer 16 are short-circuited via the ON-state transistors Qfwd and Qfly. During this period, the primary circuit uses the energy stored in the parasitic capacitor of transistor Qmain to supply current ILr to the inductor 14 (Figure 3(F)). Therefore, it is not necessary to supply a large current to transistor Qclamp. As the drain-source voltage Vds_Qmain decreases, the absolute value of the current ILr decreases during the timing period t12-t13. In this way, the power converter 1 can reduce the drain-source voltage Vds_Qmain to a certain extent at timing t14 when transistor Qmain changes from the off state to the on state, thereby reducing the turn-on loss of transistor Qmain. In addition, since a large current does not flow through transistor Qclamp in the power converter 1, conduction losses can be reduced, as can the turn-off losses of transistor Qclamp. Therefore, the power converter 1 can reduce energy loss.

[0061] Figure 9 shows an example of efficiency characteristics. The solid line shows the efficiency characteristics of the power converter 1 according to this embodiment, and the dashed line shows the efficiency characteristics of the power converter 1R according to the reference example. In Figure 9, the horizontal axis represents the output current Iout, and the vertical axis represents efficiency. The power converter 1 according to this embodiment can achieve higher efficiency than the power converter 1R according to the modified example when the output current Iout is 30A or more.

[0062] As described above, the power converter 1 has a first power terminal (terminals T11, T12) having a first connection terminal (terminal T11) and a second connection terminal (terminal T12), an inductor (inductor 14) having one end connected to the first connection terminal and the other end connected to the first node, a capacitor 12 having one end connected to the first connection terminal (terminal T11) and the other end connected to the second node (node ​​N11), and one end connected to the third node (node ​​N12) and the second connection terminal (terminal A switching circuit 15 having a first switching element (transistor Qmain) having one end connected to a second node (node ​​N11) and the other end connected to a third node (node ​​N12), a first winding (winding 16A) having one end connected to a first node and the other end connected to a third node (node ​​N12), and one end connected to a fourth node (voltage line L21A) and the other A transformer 16 having a second winding (winding 16B) with the other end connected to node 5 (node ​​N13), a third switching element (transistor Qfwd) having one end connected to node 5 (node ​​N13) and the other end connected to node 6 (reference voltage line L22), and a rectifier circuit 17 having a fourth switching element (transistor Qfly) having one end connected to node 4 (voltage line L21A) and the other end connected to node 6 (reference voltage line L22) The circuit also includes a smoothing circuit 18 connected to the fourth node (voltage line L21A) and the sixth node (reference voltage line L22), second power terminals (terminals T21, T22) connected to the smoothing circuit 18, and a control circuit 30 capable of controlling the operation of the switching circuit 15 and the rectifier circuit 17 by performing a first control (control of operation mode M1) that repeats the first operation (operation at timings t18 to t19), the second operation, the third operation, the fourth operation, the fifth operation, and the sixth operation in this order.The first operation (operation at timings t19 to t20) includes turning off the first switching element (transistor Qmain), the second switching element (transistor Qclamp), the third switching element (transistor Qfwd), and the fourth switching element (transistor Qfly). The second operation (operation at timings t20 to t23) includes turning on the second switching element (transistor Qclamp) and the fourth switching element (transistor Qfly), while turning off the first switching element (transistor Qmain) and the third switching element (transistor Qfwd). The third operation (operation at timings t11 to t13) includes turning on the third switching element (transistor Qfwd) and the fourth switching element (transistor Qfly), while turning off the first switching element (transistor Qmain) and the second switching element (transistor Qclamp). The fourth operation (operation at timings t13 to t14) includes turning on the third switching element (transistor Qfwd) and turning off the first switching element (transistor Qmain), the second switching element (transistor Qclamp), and the fourth switching element (transistor Qfly). The fifth operation (operation at timings t14 to t17) includes turning on the first switching element (transistor Qmain) and the third switching element (transistor Qfwd) and turning off the second switching element (transistor Qclamp) and the fourth switching element (transistor Qfly). The sixth operation (operation at timings t17 to t19) includes turning on the third switching element (transistor Qfwd) and turning off the first switching element (transistor Qmain), the second switching element (transistor Qclamp), and the fourth switching element (transistor Qfly).As a result, in the power converter 1, as described above, the drain-source voltage Vds_Qmain can be made somewhat lower at timing t14 when transistor Qmain changes from the off state to the on state, thereby reducing the turn-on loss of transistor Qmain. In addition, in the power converter 1, since a large current does not flow through transistor Qclamp, conduction losses can be reduced, as can the turn-off losses of transistor Qclamp. As a result, energy loss can be reduced in the power converter 1.

[0063] Furthermore, in the power converter 1, during the period when the control circuit 30 is performing the third operation (timing t11 to t13), the first voltage across the first switching element (transistor Qmain) (drain-source voltage Vds_Qmain) can change from a voltage higher than the second voltage (voltage VH) between the first connection terminal (terminal T11) and the second connection terminal (terminal T12) to a voltage lower than the second voltage (voltage VH). As a result, in the power converter 1, as described above, the drain-source voltage Vds_Qmain can be lowered to some extent at timing t14 when transistor Qmain changes from the off state to the on state. Consequently, the power converter 1 can reduce energy loss.

[0064] [effect] As described above, in this embodiment, a switching circuit is provided, comprising: a first power terminal having a first connection terminal and a second connection terminal; an inductor having one end connected to the first connection terminal and the other end connected to the first node; a capacitor having one end connected to the first connection terminal and the other end connected to the second node; a first switching element having one end connected to the third node and the other end connected to the second connection terminal; a second switching element having one end connected to the second node and the other end connected to the third node; a first winding having one end connected to the first node and the other end connected to the third node; and a fourth node connected to The device comprises a transformer having a second winding with one end exposed and the other end connected to a fifth node; a rectifier circuit having a third switching element with one end connected to a fifth node and the other end connected to a sixth node; a fourth switching element with one end connected to a fourth node and the other end connected to a sixth node; a smoothing circuit connected to the fourth node and the sixth node; a second power terminal connected to the smoothing circuit; and a control circuit capable of controlling the operation of the switching circuit and the rectifier circuit by performing a first control that repeats a first operation, a second operation, a third operation, a fourth operation, a fifth operation, and a sixth operation in this order. The first operation includes turning the first switching element, the second switching element, the third switching element, and the fourth switching element to an off state. The second operation includes turning the second switching element and the fourth switching element to an on state, and turning the first switching element and the third switching element to an off state. The third operation includes turning on the third and fourth switching elements and turning off the first and second switching elements. The fourth operation includes turning on the third switching element and turning off the first, second, and fourth switching elements. The fifth operation includes turning on the first and third switching elements and turning off the second and fourth switching elements.The sixth operation includes turning on the third switching element and turning off the first, second, and fourth switching elements. This reduces energy loss.

[0065] In this embodiment, during the period when the control circuit is performing the third operation, the first voltage across the first switching element can change from a voltage higher than the second voltage between the first and second connection terminals to a voltage lower than the second voltage. This reduces energy loss.

[0066] <2. Second Embodiment> Next, a power converter 2 according to the second embodiment will be described. Components that are substantially the same as those in the power converter 1 according to the first embodiment will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0067] Figure 10 shows an example configuration of the power converter 2. The power converter 2 includes a control circuit 130. Similar to the control circuit 30 in the above embodiment, the control circuit 130 is configured to control the operation of the power converter 2 based on the current ILr detected by the current sensor 13 and the voltage VL detected by the voltage sensor 21.

[0068] The power converter 2 has one operating mode M1. That is, unlike the control circuit 30 in the first embodiment described above, the control circuit 130 does not switch the operating mode of the power converter 2. When the output current Iout is large, it operates in the same way as in the first embodiment described above. On the other hand, when the output current Iout becomes small and the lowest current value Imin of the current ILch shown in Figure 3(H) becomes lower than 0A, the power converter 2 operates as follows.

[0069] Figure 11 shows an example of the operation of the power converter 2 when the output current Iout is small. Figures 12A to 12M show the operating states of the power converter 2 at various time periods in Figure 11. In this operation, the power converter 2 transmits power from the primary circuit to the secondary circuit during the timing period t65 to t73 of one cycle, and transmits power from the secondary circuit to the primary circuit during the rest of the cycle.

[0070] At timing t61, the control circuit 130 changes the control signal Gclamp from a high level to a low level and the control signal Gfwd from a low level to a high level (Figures 11(B), (C)). As a result, as shown in Figure 12A, transistor Qclamp changes from the ON state to the OFF state, and transistor Qfwd changes from the OFF state to the ON state. Transistor Qmain is in the OFF state, and transistor Qfly is in the ON state. At timing t61, the drain-source voltage Vds_Qmain of transistor Qmain is the voltage corresponding to the sum of the voltages VH at terminals T11 and T12 and the voltage Vclamp of capacitor 12 (VH+Vclamp) (Figures 11(L), 12A). Therefore, at timing t61, the voltage at node N12 is higher than the voltage at voltage line L11. During the period from timing t61 to t62, current flows in the primary circuit of power converter 2 as shown in Figure 12A. Current flows from node N12 to inductor 14 through winding 16A of transformer 16. The absolute value of this current (current ILr) increases (Figure 11(F)). In transistor Qmain, current flows from source to drain through the parasitic capacitor. As a result, the parasitic capacitor of transistor Qmain is gradually discharged, and the drain-source voltage Vds_Qmain decreases (Figure 11(L)). At a certain timing during the period t61~t62, the drain-source voltage Vds_Qmain falls below voltage VH. Also, current flows in the secondary circuit of power converter 2 as shown in Figure 12A. Current ILch flows through inductor 19 from voltage line L21B to voltage line L21A.

[0071] Then, at timing t62, the control circuit 130 changes the control signal Gfly from a high level to a low level (Figure 11(D)). As a result, transistor Qfly changes from the ON state to the OFF state, as shown in Figure 12B. During the period from timing t62 to t63, current flows in the secondary circuit of the power converter 2 as shown in Figure 12B. Also, in the primary circuit of the power converter 2, current flows through the same path as in the previous period, as shown in Figure 12B. The drain-source voltage Vds_Qmain continues to decrease (Figure 11(L)).

[0072] Then, at timing t63, the drain-source voltage Vds_Qmain of transistor Qmain becomes 0V (Figure 11(L)). During the period from timing t63 to t64, current flows in the primary and secondary circuits of power converter 2 as shown in Figure 12C. The absolute values ​​of the current ILr and the current IQmain in the primary circuit begin to decrease (Figure 11(F),(G)). Also, in the secondary circuit, the absolute value of the current IQfwd begins to decrease, and the current IQfly becomes 0A (Figure 11(J),(K)). During the period of timing t63, the absolute value of the current ILch in the secondary circuit changes from increasing to decreasing (Figure 11(I)).

[0073] Then, at timing t64, the control circuit 130 changes the control signal Gmain from a low level to a high level (Figure 11(A)). As a result, transistor Qmain changes from the off state to the on state, as shown in Figure 12D. During the period from timing t64 to t65, current flows in the primary circuit of the power converter 2 as shown in Figure 12D. Also, in the secondary circuit of the power converter 2, current flows along the same path as in the previous period, as shown in Figure 12D.

[0074] Then, at timing t65, as shown in Figures 11(I) and (J), the polarity of the currents ILch and IQfwd changes from negative to positive. As a result, during the period from timing t65 to t66, current flows in the secondary circuit of the power converter 2 as shown in Figure 12E. Current ILch flows through inductor 19 from voltage line L21A to voltage line L21B. Also, in the primary circuit of the power converter 2, current flows along the same path as in the previous period, as shown in Figure 12E.

[0075] Then, at timing t66, as shown in Figures 11(F) and (G), the polarity of the currents ILr and IQmain changes from negative to positive. As a result, during the period from timing t66 to t67, current flows in the primary circuit of the power converter 2 as shown in Figure 12F. In the winding 16A of the transformer 16, current flows from the inductor 14 towards node N12. Also, in the secondary circuit of the power converter 2, current flows along the same path as in the previous period, as shown in Figure 12F.

[0076] Then, at timing t67, the control circuit 130 changes the control signal Gmain from a high level to a low level (Figure 11(A)). As a result, transistor Qmain changes from the ON state to the OFF state, as shown in Figure 12G. Consequently, during the period from timing t67 to t68, current flows in the primary circuit of power converter 2 as shown in Figure 12G. In transistor Qmain, current flows from the drain to the source via the parasitic capacitor. As a result, the parasitic capacitor of transistor Qmain is gradually charged, and the drain-source voltage Vds_Qmain increases (Figure 11(L)). Also, current flows in the secondary circuit of power converter 2 as shown in Figure 12G. At timing t67, the absolute value of the current ILch in the secondary circuit changes from increasing to decreasing (Figure 11(I)).

[0077] Then, at timing t68, charging of the parasitic capacitor of transistor Qmain is completed, and the voltage at node N12 becomes higher than the voltage at voltage line L11. During the period from timing t68 to t69, current flows in the primary circuit of power converter 2 as shown in Figure 12H. Since charging of the parasitic capacitor of transistor Qmain is completed, no current flows through transistor Qmain (Figure 11(G)). The absolute value of the current ILr in the primary circuit begins to decrease (Figure 11(F)). Also, in the secondary circuit of power converter 2, current flows along the same path as in the previous period, as shown in Figure 12H.

[0078] Then, at timing t69, the control circuit 130 changes the control signal Gfwd from a high level to a low level (Figure 11(C)). As a result, transistor Qfwd changes from the ON state to the OFF state, as shown in Figure 12I. During the period from timing t69 to t70, current flows in the secondary circuit of the power converter 2 as shown in Figure 12I. Also, in the primary circuit of the power converter 2, current flows through the same path as in the previous period, as shown in Figure 12I.

[0079] Then, at timing t70, the control circuit 130 changes the control signals Gclamp and Gfly from a low level to a high level (Figures 11(B) and (D)). As a result, transistors Qclamp and Qfly change from the off state to the on state, as shown in Figure 12J. Consequently, during the period from timing t70 to t71, current flows in the primary and secondary circuits of the power converter 2, as shown in Figure 12J.

[0080] Then, at timing t71, as shown in Figure 11(J), the current IQfwd in the secondary circuit becomes 0A. As a result, during the period from timing t71 to t72, current flows in the secondary circuit of the power converter 2 as shown in Figure 12K. In the secondary circuit, the absolute value of the current IQfly begins to decrease (Figure 11(K)). Also, in the secondary circuit of the power converter 2, current flows along the same path as in the previous period, as shown in Figure 12K.

[0081] Then, at timing t72, as shown in Figures 11(F) and (H), the polarity of the currents ILr and IQclamp changes from positive to negative. As a result, during the period from timing t72 to t73, current flows in the primary circuit of the power converter 2 as shown in Figure 12L. In the winding 16A of the transformer 16, current flows from node N12 towards inductor 14. Also, in the secondary circuit of the power converter 2, current flows along the same path as in the previous period, as shown in Figure 12L.

[0082] Then, at timing t73, as shown in Figures 11(I) and (K), the polarity of currents ILch and IQfly changes from positive to negative. As a result, during the period from timing t73 to t74, current flows in the secondary circuit of power converter 2 as shown in Figure 12M. Current ILch flows through inductor 19 from voltage line L21B to voltage line L21A. Also, in the primary circuit of power converter 2, current flows along the same path as in the previous period, as shown in Figure 12M.

[0083] Then, at timing t74, the control circuit 130 changes the control signal Gclamp from a high level to a low level and changes the control signal Gfwd from a low level to a high level (Figure 11(B), (C)). This operation is the same as the operation at timing t61.

[0084] When the output current Iout is small, the power converter 2 repeats the operation at timings t61 to t74.

[0085] Here, the operation at timings t69 to t70 corresponds to a specific example of the "first operation" in one embodiment of the present disclosure. The operation at timings t70 to t74 corresponds to a specific example of the "second operation" in one embodiment of the present disclosure. The operation at timings t61 to t62 corresponds to a specific example of the "third operation" in one embodiment of the present disclosure. The operation at timings t62 to t64 corresponds to a specific example of the "fourth operation" in one embodiment of the present disclosure. The operation at timings t64 to t67 corresponds to a specific example of the "fifth operation" in one embodiment of the present disclosure. The operation at timings t67 to t69 corresponds to a specific example of the "sixth operation" in one embodiment of the present disclosure.

[0086] Thus, in the power converter 2, during the second operation (operation at timings t70 to t74), the current can flow in this order through the first circulation path including the smoothing circuit 18, the sixth node (reference voltage line L22), the fourth switching element (transistor Qfly), and the fourth node (voltage line L21A), and then flow in the reverse order through this first circulation path. During the fifth period (operation at timings t64 to t66), the current can flow in this order through the second circulation path including the smoothing circuit 18, the fourth node (voltage line L21A), the second winding (winding 16B), the fifth node (node ​​N13), the third switching element (transistor Qfwd), and the sixth node (reference voltage line L22), and then flow in the reverse order through this second circulation path. As a result, the power converter 2 transmits power from the primary circuit to the secondary circuit during the timing period t65 to t73 of one cycle, and transmits power from the secondary circuit to the primary circuit during the rest of the cycle. Therefore, the current ILch of the power converter 2 fluctuates between positive and negative values, as shown in Figure 11(I). The power converter 2 alternately repeats this operation of transmitting power from the primary circuit to the secondary circuit and transmitting power from the secondary circuit to the primary circuit. This enables the power converter 2 to achieve stable operation even when the output current Iout is small.

[0087] <3. Third Embodiment> Next, a power converter 3 according to the third embodiment will be described. Components that are substantially the same as those in the power converter 1 according to the first embodiment will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate.

[0088] Figure 13 shows an example configuration of the power converter 3. The power converter 3 includes a control circuit 230. Similar to the control circuit 30 in the above embodiment, the control circuit 230 is configured to control the operation of the power converter 3 based on the current ILr detected by the current sensor 13 and the voltage VL detected by the voltage sensor 21.

[0089] Figure 14 shows an example of the operating modes of the power converter 3. The power converter 3 has four operating modes M1 to M3 and M11, and the control circuit 230 sets the operating mode of the power converter 3 to the operating mode corresponding to the output current Iout based on the current ILr.

[0090] Specifically, the control circuit 230 sets the operating mode of the power converter 3 to operating mode M1 when the output current Iout is greater than the threshold Ith11. Furthermore, the control circuit 230 sets the operating mode of the power converter 3 to operating mode M11 when the output current Iout is less than or equal to the threshold Ith11 and greater than the threshold Ith12. Also, the control circuit 230 sets the operating mode of the power converter 3 to operating mode M2 ​​when the output current Iout is less than or equal to the threshold Ith12 and greater than the threshold Ith13. Finally, the control circuit 230 sets the operating mode of the power converter 3 to operating mode M3 when the output current Iout is less than or equal to the threshold Ith13. Operating modes M1 to M3 are the same as in the first embodiment described above. Operating mode M11 will be described in detail below.

[0091] Figure 15 shows an example of the operation of the power converter 3 in operating mode M11. Figures 16A to 16M show the operating states of the power converter 3 over various periods in Figure 15.

[0092] At timing t81, the control circuit 230 changes the control signal Gclamp from a high level to a low level and the control signal Gfwd from a low level to a high level (Figures 15(B), (C)). As a result, as shown in Figure 16A, transistor Qclamp changes from the ON state to the OFF state, and transistor Qfwd changes from the OFF state to the ON state. Both transistor Qmain and transistor Qfly are in the OFF state. At timing t81, the drain-source voltage Vds_Qmain of transistor Qmain is the voltage corresponding to the sum of the voltages VH at terminals T11 and T12 and the voltage Vclamp of capacitor 12 (VH+Vclamp) (Figures 15(L), 16A). Therefore, at timing t81, the voltage at node N12 is higher than the voltage at voltage line L11. During the period from timing t81 to t82, current flows in the primary circuit of power converter 3 as shown in Figure 16A. In the winding 16A of transformer 16, current flows from node N12 towards inductor 14. The absolute value of this current (current ILr) increases (Figure 15(F)). In transistor Qmain, current flows from source to drain through the parasitic capacitor. As a result, the parasitic capacitor of transistor Qmain is gradually discharged, and the drain-source voltage Vds_Qmain decreases (Figure 15(L)). Also, in the secondary circuit of power converter 3, current flows as shown in Figure 16A. No current ILch flows through inductor 19 (Figure 15(I)).

[0093] Then, at timing t82, the polarity of voltage VL changes from negative to positive, as shown in Figure 15(E). As a result, the voltage at one end of winding 16A of transformer 16 becomes lower than the voltage at voltage line L11B. During the period from timing t82 to t83, current flows through the same paths as in the previous period in the primary and secondary circuits of power converter 3, as shown in Figure 16B. The absolute values ​​of current ILr, current IQmain, and current IQclamp in the primary circuit begin to decrease (Figures 15(F), (G), (H)), and the absolute values ​​of current IQfwd and current IQfly in the secondary circuit begin to decrease (Figures 15(J), (K)). The drain-source voltage Vds_Qmain continues to decrease and falls below voltage VH at some point during the period from timing t81 to t83 (Figure 15(L)).

[0094] Then, at timing t83, the currents IQfwd and IQfly become 0A, as shown in Figures 15(J) and (K). During the period from timing t83 to t84, current flows in the secondary circuit of the power converter 3 as shown in Figure 16C. In the secondary circuit, current ILch begins to flow through inductor 19 from voltage line L21A to voltage line L21B (Figure 15(I)). Also, the absolute value of current IQfwd begins to increase (Figure 15(J)). Furthermore, in the primary circuit of the power converter 3, current flows along the same path as in the previous period, as shown in Figure 16C.

[0095] Then, at timing t84, the control circuit 230 changes the control signal Gmain from a low level to a high level (Figure 15(A)). As a result, transistor Qmain changes from the off state to the on state, as shown in Figure 16D. Since transistor Qmain is in the on state, the drain-source voltage Vds_Qmain becomes 0V (Figure 15(L)). During the period from timing t84 to t85, current flows in the primary circuit of power converter 3 as shown in Figure 16D. Also, in the secondary circuit of power converter 3, current flows along the same path as in the previous period, as shown in Figure 16D.

[0096] Then, at timing t85, as shown in Figures 15(F) and (G), the polarity of the currents ILr and IQmain changes from negative to positive. As a result, during the period from timing t85 to t86, current flows in the primary circuit of the power converter 3 as shown in Figure 16E. In the winding 16A of the transformer 16, current flows from the inductor 14 towards node N12. Also, in the secondary circuit of the power converter 3, current flows along the same path as in the previous period, as shown in Figure 16E.

[0097] Then, at timing t86, the control circuit 230 changes the control signal Gmain from a high level to a low level (Figure 15(A)). As a result, transistor Qmain changes from the ON state to the OFF state, as shown in Figure 16F. Consequently, during the period from timing t86 to t87, current flows in the primary circuit of power converter 3 as shown in Figure 16F. In transistor Qmain, current flows from the drain to the source via the parasitic capacitor. As a result, the parasitic capacitor of transistor Qmain is gradually charged, and the drain-source voltage Vds_Qmain increases (Figure 15(L)). Also, current flows in the secondary circuit of power converter 3 as shown in Figure 16F. In the secondary circuit, the absolute value of current IQfwd begins to decrease, and the absolute value of current IQfly begins to increase from 0A (Figures 15(J), (K)). At timing t86, the absolute value of current ILch changes from increasing to decreasing (Figure 15(I)).

[0098] Then, at timing t87, charging of the parasitic capacitor of transistor Qmain is completed, and the voltage at node N12 becomes higher than the voltage at voltage line L11. During the period from timing t87 to t88, current flows in the primary circuit of power converter 3 as shown in Figure 16G. Since charging of the parasitic capacitor of transistor Qmain is completed, no current flows through transistor Qmain (Figure 15(G)). The absolute value of the current ILr in the primary circuit begins to decrease (Figure 15(F)). Also, in the secondary circuit of power converter 3, current flows along the same path as in the previous period, as shown in Figure 16G.

[0099] Then, at timing t88, the control circuit 230 changes the control signal Gfwd from a high level to a low level (Figure 15(C)). As a result, the transistor Qfwd changes from the ON state to the OFF state, as shown in Figure 16H. During the period from timing t88 to t89, current flows in the secondary circuit of the power converter 3 as shown in Figure 16H. Also, in the primary circuit of the power converter 3, current flows through the same path as in the previous period, as shown in Figure 16H.

[0100] Then, at timing t89, the control circuit 230 changes the control signals Gclamp and Gfly from a low level to a high level (Figures 15(B) and (D)). As a result, transistors Qclamp and Qfly change from the off state to the on state, as shown in Figure 16I. Consequently, during the period from timing t89 to t90, current flows in the primary and secondary circuits of the power converter 3, as shown in Figure 16I.

[0101] Then, at timing t90, as shown in Figure 15(J), the current IQfwd in the secondary circuit becomes 0A. During the period from timing t90 to t91, current flows in the secondary circuit of the power converter 3 as shown in Figure 16J. In the secondary circuit, the absolute value of the current IQfly begins to decrease (Figure 15(K)). Also, in the primary circuit of the power converter 3, current flows along the same path as in the previous period, as shown in Figure 16J.

[0102] Then, at timing t91, the control circuit 230 changes the control signal Gfly from a high level to a low level (Figure 15(D)). As a result, transistor Qfly changes from the ON state to the OFF state, as shown in Figure 16K. During the period from timing t91 to t92, current flows in the secondary circuit of the power converter 3 as shown in Figure 16K. Also, in the primary circuit of the power converter 3, current flows through the same path as in the previous period, as shown in Figure 16K.

[0103] Then, at timing t92, as shown in Figures 15(I) and (K), the absolute values ​​of both current ILch and current IQfly become 0A. As a result, during the period from timing t92 to t93, no current flows in the secondary circuit of power converter 3, as shown in Figure 16L. Also, in the primary circuit of power converter 3, current flows through the same path as in the previous period, as shown in Figure 16L.

[0104] Then, at timing t93, as shown in Figures 15(F) and (H), the polarity of the currents ILr and IQclamp in the primary circuit changes from positive to negative. As a result, during the period from timing t93 to t94, current flows in the primary circuit of the power converter 3 as shown in Figure 16M. In the winding 16A of the transformer 16, current flows from node N12 towards inductor 14. Also, in the secondary circuit of the power converter 3, as shown in Figure 16M, no current flows, similar to the previous period.

[0105] Then, at timing t94, the control circuit 230 changes the control signal Gclamp from a high level to a low level and changes the control signal Gfwd from a low level to a high level (Figure 15(B), (C)). This operation is the same as the operation at timing t81.

[0106] In operating mode M11, the power converter 3 repeats the operation at timings t81 to t94.

[0107] In this way, the control circuit 230 sets the operating mode of the power converter 3 to one of the above-described operating modes M1, M11, M2, or M3. Specifically, as shown in Figure 14, the control circuit 230 sets the operating mode of the power converter 3 to operating mode M1 when the output current Iout is greater than the threshold Ith11. The control circuit 230 also sets the operating mode of the power converter 3 to operating mode M11 when the output current Iout is less than or equal to the threshold Ith11 and greater than the threshold Ith12. The control circuit 230 also sets the operating mode of the power converter 3 to operating mode M2 ​​when the output current Iout is less than or equal to the threshold Ith12 and greater than the threshold Ith13. The control circuit 230 also sets the operating mode of the power converter 3 to operating mode M3 when the output current Iout is less than or equal to the threshold Ith13.

[0108] The threshold Ith11 is the same as the threshold Ith1 in the first embodiment, and for example, in operating mode M1, it is set to an output current Iout such that the lowest current value Imin of the current ILch shown in Figure 3(I) becomes 0A.

[0109] The threshold Ith12 is set, for example, by comparing the efficiency in operating mode M11 with the efficiency in operating mode M2. Specifically, the threshold Ith12 is set such that, for example, if the output current Iout is greater than the threshold Ith12, the efficiency in operating mode M11 is higher than the efficiency in operating mode M2, and if the output current Iout is less than or equal to the threshold Ith12, the efficiency in operating mode M2 ​​is higher than the efficiency in operating mode M11.

[0110] Furthermore, the threshold value Ith13 is the same as the threshold value Ith2 in the first embodiment, and in operating mode M2, the output current Iout is set such that the duty cycle of the control signal Gmain is equal to the lower limit of the duty cycle of the control signal Gmain that the control circuit 230 can generate.

[0111] Here, the control related to operating mode M11 corresponds to a specific example of the "second control" in one embodiment of this disclosure. The control related to operating mode M2 ​​corresponds to a specific example of the "third control" in one embodiment of this disclosure. The control related to operating mode M3 corresponds to a specific example of the "fourth control" in one embodiment of this disclosure. Threshold Ith11 corresponds to a specific example of the "first threshold" in one embodiment of this disclosure. Threshold Ith12 corresponds to a specific example of the "second threshold" in one embodiment of this disclosure. Threshold Ith13 corresponds to a specific example of the "third threshold" in one embodiment of this disclosure. The operation at timings t88~t89 corresponds to a specific example of the "seventh operation" in one embodiment of this disclosure. The operation at timings t89~t91 corresponds to a specific example of the "eighth operation" in one embodiment of this disclosure. The operation at timings t91~t94 corresponds to a specific example of the "ninth operation" in one embodiment of this disclosure. The operation at timings t81~t84 corresponds to a specific example of the "tenth operation" in one embodiment of this disclosure. The operation at timings t84 to t86 corresponds to a specific example of the "eleventh operation" in one embodiment of this disclosure. The operation at timings t86 to t88 corresponds to a specific example of the "twelfth operation" in one embodiment of this disclosure.

[0112] The control circuit 230 can perform a first control (operation mode M1) when the current value of the current flowing through the second power terminals (terminals T21, T22) is greater than the first threshold (threshold Ith11), and when the current value of the current flowing through the second power terminals (terminals T21, T22) is less than or equal to the first threshold (threshold Ith11), it can perform a second control (operation mode M11) which repeats the seventh operation (timing t88~t89 operation), the eighth operation (timing t89~t91 operation), the ninth operation (timing t91~t94 operation), the tenth operation (timing t81~t84 operation), the eleventh operation (timing t84~t86 operation), and the twelfth operation (timing t86~t88 operation) in this order, thereby enabling control of the operation of the switching circuit 15 and the rectifier circuit 17. The seventh operation (operation at timings t88 to t89) includes turning off the first switching element (transistor Qmain), the second switching element (transistor Qclamp), the third switching element (transistor Qfwd), and the fourth switching element (transistor Qfly). The eighth operation (operation at timings t89 to t91) includes turning on the second switching element (transistor Qclamp) and the fourth switching element (transistor Qfly), while turning off the first switching element (transistor Qmain) and the third switching element (transistor Qfwd). The ninth operation (operation at timings t91 to t94) includes turning on the second switching element (transistor Qclamp), while turning off the first switching element (transistor Qmain), the third switching element (transistor Qfwd), and the fourth switching element (transistor Qfly). The tenth operation (operation at timings t81 to t84) includes turning on the third switching element (transistor Qfwd) and turning off the first switching element (transistor Qmain), the second switching element (transistor Qclamp), and the fourth switching element (transistor Qfly).The eleventh operation (operation at timings t84 to t86) includes turning on the first switching element (transistor Qmain) and the third switching element (transistor Qfwd), while turning off the second switching element (transistor Qclamp) and the fourth switching element (transistor Qfly). The twelfth operation (operation at timings t86 to t88) includes turning on the third switching element (transistor Qfwd), while turning off the first switching element (transistor Qmain), the second switching element (transistor Qclamp), and the fourth switching element (transistor Qfly). As a result, the power converter 3 can increase its efficiency compared to the power converter 1 according to the first embodiment when the output current Iout is smaller than the threshold value Ith1.

[0113] Although the present invention has been described above with reference to embodiments and modifications, the present invention is not limited to these embodiments and various modifications are possible.

[0114] For example, in the above embodiment, power converters 1 to 3 are configured to perform a step-down operation during power conversion, but the invention is not limited to this, and they may also be configured to perform a step-up operation.

[0115] For example, in the first embodiment described above, the power converter 1 has the circuit configuration shown in Figure 1, but it is not limited to this. Alternatively, for example, the connection of the capacitor 12 may be different, as in the power converter 1A shown in Figure 17. In this power converter 1A, one end of the capacitor 12 is connected to the reference voltage line L12, and the other end is connected to node N11. The above explanation has been given using the power converter 1 according to the first embodiment as an example, but this modification may also be applied to the power converter 2 according to the second embodiment (Figure 10), or to the power converter 3 according to the third embodiment (Figure 13).

[0116] The effects described herein are illustrative only, and the effects of this disclosure are not limited to those described herein. Therefore, other effects may be obtained with respect to this disclosure.

[0117] Furthermore, this disclosure may take the following forms:

[0118] (1) A first power terminal having a first connection terminal and a second connection terminal, An inductor having one end connected to the first connection terminal and the other end connected to the first node, A capacitor having one end connected to the first connection terminal or the second connection terminal and the other end connected to the second node, A switching circuit comprising: a first switching element having one end connected to a third node and the other end connected to the second connection terminal; and a second switching element having one end connected to the second node and the other end connected to the third node; A transformer having a first winding with one end connected to the first node and the other end connected to the third node, and a second winding with one end connected to the fourth node and the other end connected to the fifth node, A rectifier circuit comprising a third switching element having one end connected to the fifth node and the other end connected to the sixth node, and a fourth switching element having one end connected to the fourth node and the other end connected to the sixth node, A smoothing circuit connected to the fourth node and the sixth node, A second power terminal connected to the smoothing circuit, A control circuit capable of controlling the operation of the switching circuit and the rectifier circuit by performing a first control that repeats the first operation, second operation, third operation, fourth operation, fifth operation, and sixth operation in this order. Equipped with, The first operation includes turning off the first switching element, the second switching element, the third switching element, and the fourth switching element. The second operation includes turning on the second switching element and the fourth switching element, and turning off the first switching element and the third switching element. The third operation includes turning on the third switching element and the fourth switching element, and turning off the first switching element and the second switching element. The fourth operation includes turning on the third switching element and turning off the first switching element, the second switching element, and the fourth switching element. The fifth operation includes turning on the first switching element and the third switching element, and turning off the second switching element and the fourth switching element. The sixth operation includes turning on the third switching element and turning off the first switching element, the second switching element, and the fourth switching element. Power converter. (2) During the period in which the control circuit is performing the third operation, the first voltage across the first switching element can change from a voltage higher than the second voltage between the first and second connection terminals to a voltage lower than the second voltage. The power conversion device described in (1) above. (3) In the second operation described above, the current can flow in this order through the first circulation path including the smoothing circuit, the sixth node, the fourth switching element, and the fourth node, and then flow in the reverse order through the same first circulation path. In the fifth operation described above, the current can flow in this order through a second circulation path including the smoothing circuit, the fourth node, the second winding, the fifth node, the third switching element, and the sixth node, and then flow in the reverse order through this second circulation path. The power conversion device described in (1) or (2) above. (4) The aforementioned control circuit is The first control can be performed when the current value of the current flowing through the second power terminal is greater than the first threshold value. When the current value flowing through the second power terminal is less than or equal to the first threshold, the operation of the switching circuit and the rectifier circuit can be controlled by performing a second control that repeats the seventh operation, the eighth operation, the ninth operation, the tenth operation, the eleventh operation, and the twelfth operation in this order. The seventh operation includes turning off the first switching element, the second switching element, the third switching element, and the fourth switching element. The eighth operation includes turning on the second switching element and the fourth switching element, and turning off the first switching element and the third switching element. The ninth operation includes turning on the second switching element and turning off the first switching element, the third switching element, and the fourth switching element. The tenth operation includes turning on the third switching element and turning off the first switching element, the second switching element, and the fourth switching element. The 11th operation includes turning on the first switching element and the third switching element, and turning off the second switching element and the fourth switching element. The 12th operation includes turning on the third switching element and turning off the first switching element, the second switching element, and the fourth switching element. The power conversion device described in (1) or (2) above. (5) The control circuit can control the operation of the switching circuit and the rectifier circuit by performing a third control, which alternately turns on the first switching element and the second switching element and keeps the third switching element and the fourth switching element in the off state when the current value of the current flowing through the second power terminal falls below a second threshold that is less than the first threshold. The power conversion device described in (4) above. (6) The control circuit can control the operation of the switching circuit and the rectifier circuit by performing a fourth control, which intermittently performs the third control, when the current value flowing through the second power terminal falls below a third threshold, which is smaller than the second threshold. The power conversion device described in (5) above. [Explanation of symbols]

[0119] 1,1A,2,3...Power converter, 11,12...Capacitor, 13...Current sensor, 14...Inductor, 15...Switching circuit, 16...Transformer, 16A,16B...Winding, 17...Rectifier circuit, 18...Smoothing circuit, 19...Inductor, 20...Capacitor, 21...Voltage sensor, 30,130,230...Control circuit, BH...High voltage battery, BL...Low voltage battery, Gclamp,Gfly,Gfwd,Gmain...Control signal, Ith1,Ith2,Ith11~Ith13...Threshold, L11,L11A,L11B...Voltage line, L12...Reference voltage line, L21A,L21B...Voltage line, L22...Reference voltage line, M1~M3,M11...Operating mode, Qclamp...Transistor, Qfly...Transistor, Qfwd...Transistor, Qmain...Transistor, T11,T12,T21,T22...Terminal.

Claims

1. A first power terminal having a first connection terminal and a second connection terminal, An inductor having one end connected to the first connection terminal and the other end connected to the first node, A capacitor having one end connected to the first connection terminal or the second connection terminal and the other end connected to the second node, A switching circuit comprising: a first switching element having one end connected to a third node and the other end connected to the second connection terminal; and a second switching element having one end connected to the second node and the other end connected to the third node; A transformer having a first winding with one end connected to the first node and the other end connected to the third node, and a second winding with one end connected to the fourth node and the other end connected to the fifth node, A rectifier circuit comprising a third switching element having one end connected to the fifth node and the other end connected to the sixth node, and a fourth switching element having one end connected to the fourth node and the other end connected to the sixth node, A smoothing circuit connected to the fourth node and the sixth node, A second power terminal connected to the smoothing circuit, A control circuit capable of controlling the operation of the switching circuit and the rectifier circuit by performing a first control that repeats the first operation, second operation, third operation, fourth operation, fifth operation, and sixth operation in this order. Equipped with, The first operation includes turning off the first switching element, the second switching element, the third switching element, and the fourth switching element. The second operation includes turning on the second switching element and the fourth switching element, and turning off the first switching element and the third switching element. The third operation includes turning on the third switching element and the fourth switching element, and turning off the first switching element and the second switching element. The fourth operation includes turning on the third switching element and turning off the first switching element, the second switching element, and the fourth switching element. The fifth operation includes turning on the first switching element and the third switching element, and turning off the second switching element and the fourth switching element. The sixth operation includes turning on the third switching element and turning off the first switching element, the second switching element, and the fourth switching element. Power converter.

2. During the period in which the control circuit is performing the third operation, the first voltage across the first switching element can change from a voltage higher than the second voltage between the first and second connection terminals to a voltage lower than the second voltage. The power conversion device according to claim 1.

3. In the second operation described above, the current can flow in this order through the first circulation path including the smoothing circuit, the sixth node, the fourth switching element, and the fourth node, and then flow in the reverse order through the same first circulation path. In the fifth operation described above, the current can flow in this order through a second circulation path including the smoothing circuit, the fourth node, the second winding, the fifth node, the third switching element, and the sixth node, and then flow in the reverse order through this second circulation path. The power conversion device according to claim 1.

4. The aforementioned control circuit is The first control can be performed when the current value of the current flowing through the second power terminal is greater than the first threshold value. When the current value flowing through the second power terminal is less than or equal to the first threshold, the operation of the switching circuit and the rectifier circuit can be controlled by performing a second control that repeats the seventh operation, the eighth operation, the ninth operation, the tenth operation, the eleventh operation, and the twelfth operation in this order. The seventh operation includes turning off the first switching element, the second switching element, the third switching element, and the fourth switching element. The eighth operation includes turning on the second switching element and the fourth switching element, and turning off the first switching element and the third switching element. The ninth operation includes turning on the second switching element and turning off the first switching element, the third switching element, and the fourth switching element. The tenth operation includes turning on the third switching element and turning off the first switching element, the second switching element, and the fourth switching element. The 11th operation includes turning on the first switching element and the third switching element, and turning off the second switching element and the fourth switching element. The 12th operation includes turning on the third switching element and turning off the first switching element, the second switching element, and the fourth switching element. The power conversion device according to claim 1.

5. The control circuit can control the operation of the switching circuit and the rectifier circuit by performing a third control, which alternately turns on the first switching element and the second switching element and keeps the third switching element and the fourth switching element in the off state when the current value of the current flowing through the second power terminal falls below a second threshold that is less than the first threshold. The power conversion device according to claim 4.

6. The control circuit can control the operation of the switching circuit and the rectifier circuit by performing a fourth control, which intermittently performs the third control, when the current value flowing through the second power terminal falls below a third threshold, which is smaller than the second threshold. The power conversion device according to claim 5.

Images