Universal serial bus power supply device and method for detecting invalid hard reset

Abstract

This invention provides a universal serial bus power supply device and a method for detecting invalid hard reset events. [Solution] The Universal Serial Bus (USB) Power Delivery (PD) device includes a bit detector that receives an input data signal and enables a preamble acknowledgment signal, a packet start cycle counter that enables a packet start enable signal when the preamble acknowledgment signal is deactivated, a reset detector that receives an input data signal and outputs an invalid hard reset signal and a K code acknowledgment signal, and a flag generator that receives the packet start enable signal, the invalid hard reset signal, the K code acknowledgment signal and the reset enable signal and outputs an invalid hard reset flag to an event recorder, wherein when the invalid hard reset signal is deactivated, the invalid flag indicates that there is no hard reset event and disables the packet start enable signal.

Description

Technical Field

[0001] The present invention relates to a universal serial bus power supply device, and particularly to a universal serial bus power supply device and a method for detecting an invalid hard reset event.

Background Art

[0002] In a universal serial bus (USB) power delivery (PD) test or the actual use of a USB PD device, the transmitted packet sequence usually includes a valid hard reset event. Further, it may be affected by interference (e.g., noise) during the transmission process, and the transmitted packet sequence may have bits inverted due to interference, resulting in an invalid hard reset event. Therefore, there is a need for a solution in which the USB PD device performs a hard reset when a valid hard reset event occurs and at the same time ignores the existence of an invalid hard reset event.

Summary of the Invention

Problems to be Solved by the Invention

[0003] A universal serial bus power supply device and a method for detecting an invalid hard reset event are provided.

Means for Solving the Problems

[0004] The present disclosure provides a universal serial bus power supply device comprising a bit detector, a packet start (SOP) cycle counter, a reset detector, and a flag generator, according to several embodiments of this disclosure. The bit detector receives and detects an input data signal and outputs a preamble acknowledgment signal having a first level in response to the preamble set in the input data signal. The packet start cycle counter is configured to start counting when the preamble acknowledgment signal having a second bit level becomes inactive and to output a packet start enable signal having a first bit level. The reset detector receives an input data signal and determines whether there is a code associated with a hard reset and outputs an invalid hard reset signal and a K code acknowledgment signal. The flag generator receives the packet start enable signal, the invalid hard reset signal, the K code acknowledgment signal, and the reset enable signal and outputs an invalid hard reset flag to an event recorder.

[0005] When an invalid hard reset signal with a second level becomes inactive, the flag generator deactivates the invalid hard reset flag with a second level, and the deactivated invalid hard reset flag with a second level indicates that no hard reset event occurred. In response to a preamble acknowledgment signal with a first level, or in response to the packet initiation cycle counter counting to a value greater than a predetermined value, the packet initiation cycle counter deactivates a packet initiation enable signal with a second level, where the first level is greater than the second level.

[0006] A method for detecting an invalid hard reset is further provided according to some embodiments of the present disclosure, the method comprising: deactivating a preamble acknowledgment signal having a first level in response to an input data signal without a preamble set; generating a packet start enable signal having a second level by having a packet start cycle counter start counting when the preamble acknowledgment signal having the first level becomes inactive; generating a K code acknowledgment signal and an invalid hard reset signal in response to the preamble acknowledgment signal and the packet start enable signal; and outputting an invalid hard reset flag to an event recorder in response to the packet start enable signal, the K code acknowledgment signal, the invalid hard reset signal and the reset enable signal.

[0007] The second level is greater than the first level. The packet initiation enable signal with the first level is deactivated in response to the packet initiation cycle counter counting to a value greater than a predetermined value, or in response to a preamble acknowledgment signal with the second level. An invalid hard reset flag with the second level is generated in response to an invalid hard reset signal and a packet initiation enable signal with the second level. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a schematic diagram of a packet specification according to one embodiment of the present invention. [Figure 2] Figure 2 is a block flow diagram of a universal serial bus (USB) power supply (PD) device detecting a hard reset event, according to one embodiment of the present invention. [Figure 3] Figure 3 is a flowchart of a flag generator that generates an invalid hard reset flag according to one embodiment of the present invention. [Figure 4] Figure 4 is a timing diagram of a USB PD device that detects an invalid hard reset event according to one embodiment of the present invention. [Modes for carrying out the invention]

[0009] To facilitate a more detailed understanding of the above and other purposes, features, and advantages of this disclosure, preferred embodiments are described below in detail in conjunction with the accompanying drawings.

[0010] Hereinafter, several embodiments are summarized to allow those skilled in the art to more easily understand embodiments of the present invention in the technical field to which the present invention pertains. However, these embodiments are merely examples and do not limit embodiments of the present invention. Those skilled in the art will understand that, if necessary, the embodiments described below can be modified, for example, by changing the order of processes and / or by including more or fewer steps than those described herein, and that such modifications will not exceed the scope of embodiments of the present invention.

[0011] Figure 1 is a schematic diagram of a packet specification 100 according to one embodiment of the present invention. Generally, the packet specification 100 can be used for transmission on a Universal Serial Bus (USB) Power Delivery (PD) device. As shown in Figure 1, the packet specification 100 includes a preamble 102, a packet start code 104, header data 106, a packet end code 108, and a bus idle code 110. The preamble 102 indicates that a packet is about to begin and consists of adjacent "0s" and "1s". For example, the preamble 102 may be a 32-bit or 64-bit code arranged as "0101..." or "1010...". The packet start code 104 represents the start of a packet and includes information contained in a hard reset event. Header data 106 contains information about a single packet and other reset events (e.g., soft reset, data reset, cable reset, etc.), packet termination code 108 indicates the end of a single packet, and bus idle code 110 forces the bus to be empty in preparation for receiving the next packet.

[0012] As described above, the packet initiation code 104 contains information about a hard reset event, and the header data 106 contains information contained in a single packet and other reset events. However, interference (e.g., noise) during the process of sending a single packet can cause errors (e.g., bits are flipped) in the information contained in the packet. For example, the encoding of a hard reset event appears only in the packet initiation code 104, but if a bit in the header data 106 is flipped due to interference, the originally contained information may be read as a hard reset event. This hard reset event is not originally present in the packet and is therefore called an "invalid hard reset event," and because a hard reset event resets the power supply and protocol, subsequent transmission or authentication operations may fail. Therefore, a method is needed to prevent a system or device from performing a hard reset due to an invalid hard reset event.

[0013] Figure 2 is a block flow diagram of a Universal Serial Bus (USB) power supply (PD) device 200 detecting a hard reset event according to one embodiment of the present invention. The USB PD device 200 includes a bit generator 210, a shift register 220, a bit detector 230, a packet start (SOP) cycle counter 240, a reset detector 250, a flag generator 260, and an event recorder 270. The bit generator 210 receives an input signal OAS and generates a corresponding digital signal DBS. The shift register 220 receives the digital signal DBS and generates an input data signal Din. The shift register 220 is a 20-bit shift register and, after each read cycle, converts the read digital signal DBS into a 20-bit input data signal Din.

[0014] When the shift register 220 reads the digital signal DBS and outputs the input data signal Din, the input data signal Din is output to an SOP mode determination unit (not shown) which can determine the SOP mode (e.g., SOP, SOP', SOP'', etc.) of the packet start code 104 of the current packet. When the SOP mode matches the current component setting (e.g., the setting of the USB PD device 200), the SOP mode determination unit generates a reset enable signal CSE with a second level (e.g., logic 1). Conversely, when the SOP mode does not match the current component setting, the SOP mode determination unit generates a reset enable signal CSE with a first level (e.g., logic 0).

[0015] The bit detector 230 further includes a bus idle detector 232 and a bit comparator 234. The bus idle detector 232 receives an input data signal Din and outputs a bus idle signal BI according to the contents of the input data signal Din (for example, the contents of the packet specification 100 shown in Figure 1). Specifically, when the input data signal Din read by the bus idle detector 232 does not contain a bus idle byte (for example, a bus idle code 110), the bus idle detector 232 outputs a bus idle signal BI having a first level (for example, logical 0). When the input data signal Din read by the bus idle detector 232 contains a bus idle byte, the bus idle detector 232 outputs a bus idle signal BI having a second level (for example, logical 1).

[0016] The bit comparator 234 receives the input data signal Din and outputs a preamble acknowledgment signal PB_OK depending on the contents of the input data signal Din. Specifically, when the input data signal Din read by the bit comparator 234 does not contain the preamble byte (for example, the 20-bit combination of "0101..." or "1010..." in the preamble 102), the bit comparator 234 outputs a preamble acknowledgment signal PB_OK with a first level (for example, logical 0) (i.e., the preamble acknowledgment signal PB_OK is inactive). When the input data signal Din read by the bit comparator 234 contains the preamble byte, the bit comparator 234 outputs a preamble acknowledgment signal PB_OK with a second level (for example, logical 1) (i.e., the preamble acknowledgment signal PB_OK is active).

[0017] The SOP cycle counter 240 receives a preamble acknowledgment signal PB_OK and a bus idle signal BI. When both the preamble acknowledgment signal PB_OK and the bus idle signal BI are at a first level (e.g., logical 0), the SOP cycle counter 240 starts counting from zero and simultaneously outputs a packet start (SOP) enable signal SOP_ON with a second level (e.g., logical 1). Next, when the SOP cycle counter 240 has counted to a value greater than a predetermined value (e.g., a predetermined time length or a predetermined value), the SOP cycle counter 240 outputs an SOP enable signal SOP_ON with a first level (e.g., logical 0). The predetermined value may also represent a predetermined SOP cycle length.

[0018] The reset detector 250 is configured to determine whether the input data signal Din contains a code associated with a hard reset event. For example, when the USB PD device 200 transmits data, the received data can be encoded and decoded using 4B / 5B encoding technology. The K codes associated with a hard reset event are RST-1 (5-bit encoded as 00111) and RST-2 (5-bit encoded as 11001). Furthermore, four K codes, each having 20 bits and arranged in a fixed code sequence, are required to constitute a single hard reset event. That is, the reset detector 250 determines that a hard reset event has occurred when it reads a fixed code sequence arranged as RST-1, RST-1, RST-1, and RST-2.

[0019] The reset detector 250 further includes an invalid hard reset detector 252 and a K-code comparator 254. The invalid hard reset detector 252 receives a preamble acknowledgment signal PB_OK and an input data signal Din, and when the preamble acknowledgment signal PB_OK has a first level (e.g., logic 0), it compares the input data signal Din with a valid hard reset code (e.g., a fixed code sequence arranged as RST-1, RST-1, RST-1, RST-2). If the comparison results are the same (e.g., at least three of the 20 bits of the input data signal Din are the same as the valid hard reset code), the invalid hard reset detector 252 outputs an invalid hard reset signal IHR having a second level (e.g., logic 1) to indicate that a hard reset event has occurred. Conversely, when the comparison results differ (for example, at least two K codes among the 20 bits of the input data signal Din differ from the valid hard reset code), the invalid hard reset detector 252 outputs an invalid hard reset signal IHR having a first level (e.g., logic 1) to indicate that no hard reset event has occurred.

[0020] The K-code comparator 254 receives the preamble acknowledgment signal PB_OK, the SOP enable signal SOP_ON, and the input data signal Din. When the preamble acknowledgment signal PB_OK has a first level (e.g., logic 0) and the SOP enable signal SOP_ON has a second level (e.g., logic 1), it compares the input data signal Din with the valid hard reset code. If the comparison results are the same (e.g., at least three of the 20 bits of the input data signal Din are the same as the valid hard reset code), the K-code comparator 254 outputs a K-code acknowledgment signal ASC having a second level (e.g., logic 1). Conversely, if the comparison results are different (e.g., at least two of the 20 bits of the input data signal Din are the same as the valid hard reset code), the K-code comparator 254 outputs a K-code acknowledgment signal ASC having a first level (e.g., logic 0).

[0021] The K-code comparator 254 compares the input data signal Din with the valid hard reset code when the preamble acknowledgment signal PB_OK has a first level (e.g., logical 0) and the SOP enable signal SOP_ON has a second level (e.g., logical 1). Therefore, the K-code comparator 254 can be considered to be performing the comparison during the period when the packet start code 104 is read. The invalid hard reset detector 252 compares the input data signal Din with the valid hard reset code when the preamble acknowledgment signal PB_OK has a first level (e.g., logical 0). Therefore, the invalid hard reset detector 252 can be considered to be performing the comparison during the entire packet read period after the preamble 102. With such a design, it is possible to determine whether a packet has a hard reset event in all its contents except the preamble 102, and also whether a packet has a hard reset event in the contents of the packet start code 104. The following describes in detail how such a design is useful in determining whether an invalid hard reset event has occurred.

[0022] The flag generator 260 receives a bus idle signal BI, a SOP enable signal SOP_ON, an invalid hard reset signal IHR, a K-code confirmation signal ASC, and a reset enable signal CSE. When the bus idle signal BI has a second level (e.g., logic 1), the flag generator 260 does not perform any operation. When the bus idle signal BI has a first level (e.g., logic 0), the flag generator 260 outputs an invalid hard reset flag IRD according to the SOP enable signal SOP_ON, the invalid hard reset signal IHR, the K-code confirmation signal ASC, and the reset enable signal CSE. The specific operation will be described below with reference to FIG. 3.

[0023] FIG. 3 is a flowchart 300 of a flag generator 260 that generates an invalid hard reset flag IRD according to an embodiment of the present invention. As described above, when the bus idle signal BI has a second level (e.g., logic 1), the flag generator 260 does not perform any operation. Therefore, the operations shown in the flowchart 300 are the operations performed by the flag generator 260 when the bus idle signal BI has a first level (e.g., logic 0). In step 302, the flag generator 260 determines whether the invalid hard reset signal IHR has a second level (e.g., logic 1). When the invalid hard reset signal IHR does not have a second level, the process proceeds to step 310b, and the flag generator 260 generates an invalid hard reset flag IRD having a first level (e.g., logic 0). When the invalid hard reset signal IHR has a second level, the process proceeds to step 304, and the flag generator 260 determines whether the SOP enable signal SOP_ON has a second level (e.g., logic 1).

[0024] When the SOP enable signal SOP_ON has a second level (e.g., logic 1), proceed to step 306a, and the flag generator 260 generates an invalid hard reset flag IRD having the second level (e.g., logic 1). When the SOP enable signal SOP_ON does not have the second level, proceed to step 306b, and the flag generator 260 determines whether the K-code confirmation signal ASC and the reset enable signal CSE each have the second level (e.g., logic 1) and the first level (e.g., logic 0), respectively. When the K-code confirmation signal ASC and the reset enable signal CSE each have the second level and the first level, proceed to step 308a, and the flag generator 260 generates an invalid hard reset flag IRD having the first level (e.g., logic 0).

[0025] When the K-code confirmation signal ASC and the reset enable signal CSE do not each have the second level and the first level, respectively (i.e., the K-code confirmation signal ASC does not have the second level or the reset enable signal CSE does not have the first level), proceed to step 308b, and the flag generator 260 determines whether the reset enable signal CSE has the second level (e.g., logic 1). When the reset enable signal CSE has the second level, proceed to step 310a, and the flag generator 260 generates an invalid hard reset flag IRD having the second level (e.g., logic 1). When the reset enable signal CSE does not have the second level, proceed to step 310b, and the flag generator 260 generates an invalid hard reset flag IRD having the first level (e.g., logic 0).

[0026] Figure 4 is a timing diagram 400 of a USB PD device 200 that detects an invalid hard reset event according to one embodiment of the present invention. Hard reset events 402, 404, and 406 correspond to the first, second, and third embodiments, respectively. As shown in Figures 2 and 3, at time t0, the shift register 220 begins reading the preamble 102 of one packet and outputs the input data signal Din to the bus idle detector 232 and the bit comparator 234. At time t1, the bit comparator 234 detects a 20-bit code sequence of "0101..." or "1010..." representing the preamble 102 and outputs a preamble acknowledgment signal PB_OK with a second level (e.g., logic 1). At this time, since the preamble acknowledgment signal PB_OK has a second level (e.g., logic 1), the SOP cycle counter 240 is reset to zero or does not start counting and outputs an SOP enable signal SOP_ON with a first level (e.g., logic 0).

[0027] At time t2, since the preamble 102 of the packet has been transmitted, the input data signal Din detected by the bit comparator 234 is no longer a 20-bit code sequence arranged as "0101..." or "1010...". At this time, the bit comparator 234 outputs a preamble acknowledgment signal PB_OK with a first level (e.g., logic 0), the SOP cycle counter 240 starts counting, and outputs an SOP enable signal SOP_ON with a second level (e.g., logic 1). Simultaneously, the invalid hard reset detector 252 and K code comparator 254, which receive the preamble acknowledgment signal PB_OK with a first level (e.g., logic 0), also start comparing the input data signal Din with the valid hard reset code.

[0028] At time t3, the SOP cycle counter 240 counts up to a value greater than a predetermined value (e.g., a predetermined transmission time for packet initiation code 104), thereby outputting an SOP enable signal SOP_ON having a first level (e.g., logical 0). As shown in the first embodiment, the hard reset event 402 occurs between times t2 and t3. Since the hard reset event 402 occurs at a predetermined transmission time for packet initiation code 104, the hard reset event 402 can be considered a single valid hard reset event (because the code associated with the hard reset event should only exist within packet initiation code 104). Then, after time t3, the SOP enable signal SOP_ON switches from a second level (e.g., logical 1) to a first level (e.g., logical 0), so the K code comparator 254 stops comparing the input data signal Din with the valid hard reset code. Simultaneously, the preamble acknowledgment signal PB_OK is maintained at a first level (e.g., logic 0), so the invalid hard reset detector 252 continues to compare the input data signal Din with the valid hard reset code.

[0029] At time t4, the bit detector 230 detects packet termination code 108, indicating packet termination (EOP), in the input data signal Din. As shown in the second and third embodiments, hard reset events 404 and 406 occur between times t3 and t4. Since the SOP enable signal SOP_ON at this time is at a first level (e.g., logical 0), hard reset events 404 and 406 do not occur within the SOP cycle (i.e., the transmission period of packet start code 104). Therefore, hard reset events 404 and 406 are considered invalid hard reset events. That is, in the second and third embodiments, the invalid hard reset detector 252 detects hard reset events 404 and 406 and outputs an invalid hard reset signal IHR with a second level (e.g., logical 1). However, as shown in the first embodiment, the invalid hard reset detector 252 does not detect the occurrence of any hard reset events outside of the SOP cycle. Accordingly, in the first embodiment, the invalid hard reset detector 252 outputs an invalid hard reset signal IHR having a first level (e.g., logic 0).

[0030] At time t5, the bus idle detector 232 detects the bus idle code 110 in the input data signal Din and outputs a bus idle signal BI with a second level (e.g., logic 1), thereby forcing the bus into an idle state and preparing it for the transmission of the next packet.

[0031] Table 1 below lists the multiple signals received by the flag generator 260 and the logic levels of the invalid hard reset flag IRD output after the first, second, and third embodiments, respectively, detect hard reset events 402, 404, and 406. The SOP modes of the first and second embodiments have a second level (e.g., logic 1) because they match the current component (e.g., USB PD device 200). The SOP mode of the third embodiment does not match the current component setting, so the reset enable signal CSE has a first level (e.g., logic 0). [Table 1]

[0032] As shown in Table 1 and Figure 3, in the first embodiment, the flag generator 260 determines that the invalid hard reset signal IHR has a second level (e.g., logic 1), and then proceeds to step 304, where it determines that the SOP enable signal SOP_ON has a second level (e.g., logic 1). At this point, the flag generator 260 generates an invalid hard reset flag IRD having a second level (e.g., logic 1) and outputs it to the event recorder 270, thereby causing the USB PD device 200 to detect the presence of the invalid hard reset flag IRD (i.e., that a hard reset is needed). Since the time point at which the hard reset event 402 occurred is within the SOP cycle, the USB PD device 200 determines that the hard reset event 402 is a valid hard reset event and performs a hard reset.

[0033] Similarly, as shown in Table 1 and Figure 3, in the second embodiment, the flag generator 260 determines that the invalid hard reset signal IHR has a second level (e.g., logic 1), and therefore proceeds to step 304, where it determines that the SOP enable signal SOP_ON does not have a second level (e.g., logic 1). Next, the flag generator 260 proceeds to step 306b, where it determines whether the K code acknowledgment signal ASC and the reset enable signal CSE have a second level (e.g., logic 1) and a first level (e.g., logic 0), respectively. Thus, the flag generator 260 proceeds to step 308b, where it determines whether the reset enable signal CSE has a second level (e.g., logic 1). At this point, the flag generator 260 generates an invalid reset flag IRD having a second level (e.g., logic 1) and outputs it to the event recorder 270, thereby causing the USB PD device 200 to detect the presence of the invalid hard reset flag IRD (i.e., that a hard reset is needed). Since the hard reset event 404 occurred outside of the SOP cycle, the USB PD device 200 determines that hard reset event 404 is a valid hard reset event and does not perform a hard reset.

[0034] Again, as shown in Table 1 and Figure 3, in the third embodiment, the flag generator 260 determines that the invalid hard reset signal IHR has a second level (e.g., logic 1), and therefore proceeds to step 304, where it determines that the SOP enable signal SOP_ON does not have a second level (e.g., logic 1). The flag generator 260 then proceeds to step 306b, where it determines that the K code acknowledgment signal ASC and the reset enable signal CSE do not have a second level (e.g., logic 1) and a first level (e.g., logic 0), respectively. Therefore, the flag generator 260 proceeds to step 308b, where it determines that the reset enable signal CSE does not have a second level (e.g., logic 1). Next, the flag generator 260 generates an invalid reset flag IRD having a first level (e.g., logical 0) and outputs it to the event recorder 270, thereby the USB PD device 200 detects that there is no invalid hard reset flag IRD (i.e., there is no need to perform a hard reset). That is, although the time point at which the hard reset event 406 occurred is outside the SOP cycle, the SOP mode and the settings of the USB PD device 200 at this time are not the same, so the USB PD device 200 determines that no hard reset event has occurred in the third embodiment and does not perform a hard reset.

[0035] The present invention provides a USB PD device that determines, via a bit detector, whether the content of an input data signal Din is a preamble indicating packet transmission or a bus idle code indicating to force the bus into an idle state. When the content of the input data signal is determined to be a preamble and the transmission of the preamble is complete, the SOP cycle counter starts counting and outputs an SOP enable signal SOP_ON having a second level (e.g., logical 1) indicating that it is in an SOP cycle. The SOP cycle counter continues counting until it exceeds a predetermined value (i.e., indicating the end of the SOP cycle) and the preamble has not yet been fully transmitted, or when the bit detector reads a bus idle code, the SOP cycle counter is reset to zero and outputs an SOP enable signal SOP_ON having a first level (i.e., logical 0) indicating that it is outside of an SOP cycle. The USB PD device also further includes an SOP mode detector that can determine the SOP mode of a packet transmitted via a packet start code and output a reset enable signal CSE having a second level (e.g., logical 1) when the SOP mode matches the current device setting.

[0036] When the preamble transmission is complete, detection is performed on the transmitted packet using the invalid hard reset detector and K-code comparator. The K-code comparator outputs a K-code acknowledgment signal ASC with a second level (e.g., logical 1) when it detects a hard reset event that matches the current component setting during the SOP cycle. When the SOP cycle ends, the K-code comparator terminates its operation. The invalid hard reset detector continues to detect whether there is a hard reset event in the packet that matches the current component setting until the bit detector detects a bus idle code and forces the bus to enter an idle state. When the invalid hard reset detector detects a hard reset event, it outputs an invalid hard reset signal IHR with a second level (e.g., logical 1).

[0037] The flag generator receives the SOP enable signal SOP_ON, the K code acknowledgment signal ASC, the invalid hard reset signal IHR, and the reset enable signal CSE, and based on these, determines whether to output an invalid hard reset flag IRD having a first level (e.g., logical 0) or a second level (e.g., logical 1). If the invalid hard reset signal IHR has a first level, indicating that no hard reset event was detected in the packet, the invalid hard reset flag IRD has a first level (e.g., logical 0), and the USB PD device does not perform a hard reset. If the invalid hard reset signal IHR has a second level, indicating that a hard reset event was detected in the packet. In this case, if the SOP enable signal SOP_ON has a second level, it indicates that a hard reset event was detected during the SOP cycle. In this case, the invalid hard reset flag IRD has a second level (e.g., logical 1), the USB PD device determines it to be a valid hard reset event, and performs a hard reset.

[0038] If both the invalid hard reset signal IHR and the SOP enable signal SOP_ON have a second level, it indicates that a hard reset event occurred outside of the SOP cycle. In this case, if the K code acknowledgment signal ASC and the reset enable signal CSE have a second level (e.g., logic 1) and a first level (e.g., logic 0), respectively, the invalid hard reset flag IRD has a first level, and the USB PD device does not perform a hard reset. If the K code acknowledgment signal ASC and the reset enable signal CSE do not have a second level (e.g., logic 1) and a first level (e.g., logic 0), respectively, it is determined whether the reset enable signal CSE has a second level (e.g., logic 1). If the reset enable signal CSE has a second level (e.g., logic 1), the invalid hard reset flag IRD has a second level, the USB PD device determines it to be an invalid hard reset event, and does not perform a hard reset. If the reset enable signal CSE has a first level (e.g., logic 0), the invalid hard reset flag IRD has a first level. In other words, even if an invalid hard reset event occurs, the USB PD device will not perform a hard reset because it determines that the SOP mode of the packet is different from the current component setting.

[0039] The USB PD device and the method for detecting invalid hard resets described above enable detection of hard reset events for the entire packet. Furthermore, by determining whether the hard reset event was detected during or outside the SOP cycle, the USB PD device can determine whether the hard reset event is invalid. The USB PD device can also determine, via the packet initiation code sent during the SOP cycle, whether the transmitted packet has an SOP mode, and further compare the SOP mode with the current component configuration. If the comparison does not match, the USB PD device will not perform a hard reset even if a hard reset event is detected. Such a design makes the USB PD device more reliable in determining invalid hard reset events, effectively filtering out unnecessary invalid hard reset events and preventing the system from performing unnecessary hard resets due to interference during packet transmission, which could affect subsequent transmissions or authentication. [Explanation of Symbols]

[0040] 100 packet specification 102 Preamble 104 Packet Start Code 106 Header data 108 Packet Termination Code 110 Bus Idle Code 200 Universal Serial Bus (USB) Power Delivery (PD) Devices 210-bit generator 220 Shift Registers 230-bit detector 232 Bus Idle Detectors 234-bit comparator 240 Packet Start (SOP) Cycle Counter 250 Reset Detectors 252 Invalid hard reset detector 254K code comparator 260 Flag Generator 270 Event Recorder OAS Input Signal DBS Digital Signal Din Input Data Signal BI Bus Idle Signal PB_OK Preamble confirmation signal SOP_ON Packet Start (SOP) Enable Signal IHR invalid hard reset signal ASC K Code Verification Signal CSE Reset Enable Signal IRD Invalid Hard Reset Flag 300 flowcharts Steps 302, 304, 306a, 306b, 308a, 308b, 310a, and 310b. 400 Timing Diagram 402, 404, 406 Hard Reset Event t0~t5 time

Claims

1. A bit detector that receives and detects an input data signal and, in response to the preamble set in the input signal, enables a preamble confirmation signal. A packet start cycle counter configured to enable a packet start enable signal when the preamble acknowledgment signal deactivates the start of the count, A reset detector receives the aforementioned input data signal, determines whether there is a code related to a hard reset, and outputs an invalid hard reset signal and a K code confirmation signal. The system includes a flag generator that receives the packet start enable signal, the invalid hard reset signal, the K code confirmation signal, and the reset enable signal, and outputs an invalid hard reset flag to the event recorder. In response to the invalid hard reset signal being deactivated, the flag generator deactivates the invalid hard reset flag, and the deactivated invalid hard reset flag indicates that no hard reset event occurred, and A universal serial bus power supply device that, in response to an enabled preamble acknowledgment signal, or in response to the packet initiation cycle counter counting to a value greater than a predetermined value, deactivates the packet initiation enable signal using the packet initiation cycle counter.

2. The bit detector is A bus idle detector configured to enable the bus idle signal in response to the bus idle byte in the input data signal, and The universal serial bus power supply device according to claim 1, comprising a bit comparator configured to enable the preamble acknowledgment signal in response to the preamble byte in the input data signal.

3. The reset detector is When the preamble acknowledgment signal is deactivated and the packet start enable signal is enabled, the K code comparator is configured to compare the input data signal with a valid hard reset code, and in response to the comparison results being the same, the K code comparator enables the K code acknowledgment signal, and The universal serial bus power supply device according to claim 1, comprising an invalid hard reset detector configured to compare the input data signal with the valid hard reset code in response to the preamble confirmation signal being deactivated, the invalid hard reset detector enabling the invalid hard reset signal in response to the comparison result being the same.

4. The aforementioned flag generator is, In response to the deactivation of the preamble confirmation signal, it is determined whether the invalid hard reset signal has been enabled. In response to the activation of the invalid hard reset signal, it is determined whether the packet start enable signal has been enabled, and The universal serial bus power supply device according to claim 1, which, in response to the packet start enable signal being enabled, enables the invalid hard reset flag and outputs it to the event recorder.

5. The flag generator determines whether the invalid hard reset signal is activated during the operation. The universal serial bus power supply device according to claim 4, further comprising the flag generator deactivating the invalid hard reset flag and outputting it to the event recorder in response to the invalid hard reset signal not being enabled.

6. The flag generator determines whether the packet start enable signal is enabled for the operation, In response to the packet start enable signal not being enabled, the flag generator determines whether the K code acknowledgment signal and the reset enable signal have been enabled or deactivated, and The universal serial bus power supply device according to claim 4, further comprising the flag generator deactivating the invalid hard reset flag and outputting it to the event recorder in response to the activation and deactivation of the K code confirmation signal and the reset enable signal, respectively.

7. The flag generator determines whether the K code confirmation signal and the reset enable signal are activated and deactivated, respectively. In response to the fact that the K code confirmation signal and the reset enable signal are not enabled and deactivated, respectively, the flag generator determines whether the reset enable signal has been enabled, and The universal serial bus power supply device according to claim 6, wherein, in response to the activation of the reset enable signal, the flag generator activates the invalid hard reset flag and outputs it to the event recorder.

8. The flag generator determines whether the reset enable signal is activated during the operation. The universal serial bus power supply device according to claim 7, wherein, in response to the failure to activate the reset enable signal, the flag generator deactivates the invalid hard reset flag and outputs it to the event recorder.

9. A step of deactivating the preamble acknowledgment signal in response to an input data signal that does not have a preamble set. In response to the deactivation of the preamble acknowledgment signal, the packet initiation cycle counter begins counting, thereby enabling the packet initiation enable signal. The steps of generating a K-code acknowledgment signal and an invalid hard reset signal in response to the preamble acknowledgment signal and the packet start enable signal, and The step includes outputting an invalid hard reset flag to the event recorder in response to the packet start enable signal, the K code confirmation signal, the invalid hard reset signal, and the reset enable signal, In response to the packet initiation cycle counter reaching a value greater than a predetermined value, or in response to the preamble acknowledgment signal being activated, the packet initiation enable signal is deactivated, and A method for detecting an invalid hard reset, which enables the invalid hard reset flag in response to the invalid hard reset signal and the packet start enable signal being enabled.

10. In response to the invalid hard reset signal being deactivated, the steps include: deactivating the invalid hard reset flag; In response to the invalid hard reset signal, the packet start enable signal and the K code acknowledgment signal are enabled, the reset enable signal is deactivated, and the invalid hard reset flag is deactivated. A method for detecting an invalid hard reset according to claim 9, further comprising the steps of enabling the invalid hard reset signal, the packet start enable signal, and the reset enable signal, and enabling the invalid hard reset flag.

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