Indication device

Abstract

A display device having a transparent structure that allows electronic devices to receive light normally without exposing them on the front of the display device. [Solution] A display device can be provided, comprising: a display area including a light-transmitting optical region, an optical bezel region on the outer edge of the optical region, and a general region on the outer edge of the optical bezel region; a substrate overlapping the optical bezel region and the general region; an electronic device overlapping the optical region and overlapping a part of the optical bezel region; a first transistor and a second transistor arranged in the optical bezel region; a first light-emitting element arranged in the optical bezel region and connected to the first transistor; and a second light-emitting element arranged in the optical region and connected to the second transistor, wherein the first transistor, the second transistor, and the first light-emitting element are arranged on the substrate, and the second light-emitting element is arranged on the electronic device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device.

Background Art

[0002] With the development of technology, in addition to an image display function, a display device can provide a photographing function and various sensing functions. For this purpose, the display device must include optoelectronic devices (also referred to as light receiving devices or sensors) such as a camera and a sensing sensor.

[0003] Since the optoelectronic device needs to receive light from the front of the display device, it must be installed in a place where light reception is advantageous. Therefore, conventionally, there was no choice but to install a camera (camera lens) and a sensing sensor so as to be exposed on the front surface of the display device. As a result, the bezels of the display panel are widened, or a notch or a physical hole is formed in the display area of the display panel, and a camera or a sensing sensor is provided therein.

[0004] When the display device includes an optoelectronic device, due to the structure for including the optoelectronic device, an unexpected decrease in image quality occurs, and it is necessary to improve the resolution, secure a transmission area, and secure a transmittance.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Embodiments of the present disclosure can provide a display device having a transmissive structure in which an electronic device can normally receive light without being exposed on the front surface of the display device.

[0006] Embodiments of the present disclosure can provide a display device having a structure capable of improving the transmittance of an optical region by arranging light emitting elements in a transmissive optical region and arranging pixel circuits for driving the light emitting elements in the optical bezel region.

[0007] Embodiments of this disclosure provide a display device having a structure that can improve the transmittance of an optical region by connecting a light-emitting element arranged in a transmissive optical region and a pixel circuit arranged in an optical bezel region with transparent wiring containing a transparent conductive material. [Means for solving the problem]

[0008] Embodiments of the present disclosure can provide a display device comprising: a display area including a light-transmitting optical region, an optical bezel region on the outer edge of the optical region, and a general region on the outer edge of the optical bezel region; a substrate overlapping the optical bezel region and the general region; an electronic device overlapping the optical region and overlapping a portion of the optical bezel region; a first transistor and a second transistor disposed in the optical bezel region; a first light-emitting element disposed in the optical bezel region and connected to the first transistor; and a second light-emitting element disposed in the optical region and connected to the second transistor, wherein the first transistor, the second transistor, and the first light-emitting element are disposed on the substrate, and the second light-emitting element is disposed on the electronic device.

[0009] Embodiments of the present disclosure can provide a display device comprising: an upper substrate including a first region and a second region surrounding the first region; a lower substrate including a third region and a fourth region surrounding the third region and located below the first region; a first via hole and a second via hole formed in the first region of the upper substrate; a first transistor disposed on the upper substrate; a second transistor disposed on the upper substrate; a common electrode disposed on the upper substrate to which a cathode voltage is applied; a first light-emitting element disposed on the upper substrate; a second light-emitting element disposed on the lower substrate; a first transparent wiring electrically connected to the anode electrode of the second light-emitting element; a first conductive pattern disposed in the first via hole and electrically connecting one electrode of the second transistor to the first transparent wiring; a second transparent wiring electrically connected to the cathode electrode of the second light-emitting element; and a second conductive pattern disposed in the second via hole and electrically connecting the common electrode to the second transparent wiring, wherein the first and second transparent wirings include a transparent conductive material.

[0010] According to embodiments of this disclosure, it is possible to provide a display device having a transparent structure that allows electronic devices to receive light normally without exposing the electronic devices on the front surface of the display device.

[0011] According to embodiments of this disclosure, a display device can be provided that has a structure that can improve the transmittance of an optical region by arranging light-emitting elements in a transparent optical region and arranging a pixel circuit for driving the light-emitting elements in the optical region in an optical bezel region.

[0012] According to embodiments of this disclosure, by connecting a light-emitting element arranged in a transmissive optical region and a pixel circuit arranged in an optical bezel region with transparent wiring containing a transparent conductive material, it is possible to improve the transmittance of the optical region and provide a display device that can improve the resolution of the optical region and ensure transmittance even when driven at low power. [Brief explanation of the drawing]

[0013] [Figure 1] This disclosure shows a display device according to an embodiment of this disclosure. [Figure 2] This is a system configuration diagram of a display device according to an embodiment of the present disclosure. [Figure 3] This is a schematic diagram of a display panel according to an embodiment of the present disclosure. [Figure 4] In the display panel according to the embodiment of this disclosure, the optical region and the surrounding general region are schematically shown. [Figure 5a] An embodiment of the present disclosure shows a display panel comprising a general area, an optical bezel area, and light-emitting elements arranged in the optical area, as well as a pixel circuit for driving the light-emitting elements. [Figure 5b] An embodiment of the present disclosure shows a display panel comprising a general area, an optical bezel area, and light-emitting elements arranged in the optical area, as well as a pixel circuit for driving the light-emitting elements. [Figure 6] This is a circuit diagram of the subpixel configuration of a display panel according to an embodiment of the present disclosure. [Figure 7]It is an equivalent circuit of a subpixel of a display panel according to an embodiment of the present disclosure. [Figure 8] It is a cross-sectional view taken along X-Y of FIG. 5b according to an embodiment of the present disclosure. [Figure 9] It is a cross-sectional view taken along X-Y of FIG. 5b according to an embodiment of the present disclosure. [Figure 10a] It is a cross-sectional view showing the structure of a light-emitting element according to an embodiment of the present disclosure. [Figure 10b] It is a cross-sectional view showing the structure of a light-emitting element according to an embodiment of the present disclosure. [Figure 11] It is a plan view of an upper substrate and a lower substrate for showing the formation positions of components according to an embodiment of the present disclosure. [Figure 12] It is a figure in which FIG. 11 according to an embodiment of the present disclosure is made to correspond to FIG. 8. [Figure 13] It is a plan view of an upper substrate and a lower substrate for showing the formation positions of components according to an embodiment of the present disclosure. [Figure 14] It is a figure in which FIG. 13 according to an embodiment of the present disclosure is made to correspond to FIG. 8.

Embodiments for Carrying Out the Invention

[0014] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to exemplary drawings. When adding reference numerals to the components of each drawing, for the same components, even if they are shown on other drawings, the same numerals may be used as much as possible. In describing the present disclosure, if it is determined that a specific description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description thereof will be omitted. When terms such as "including", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it can include the case of including a plurality unless there is a particularly explicit description.

[0015] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. can be used. These terms are only for distinguishing the components from other components, and the essence, order, sequence, number, etc. of the components are not limited by these terms.

[0016] In the description of the positional relationship of components, when it is described that two or more components are "connected", "coupled", or "connected", it should be understood that the two or more components can be directly "connected", "coupled", or "connected", but it is also possible that two or more components and other components are further "interposed" and "connected", "coupled", or "connected". Here, the other components may be included in at least one of the two or more components that are "connected", "coupled", or "connected" to each other.

[0017] In the description of the relationship of the time flow regarding components, operation methods, manufacturing methods, etc., for example, when the time sequence relationship or the sequential relationship of the flow is described by "after ~", "subsequent to ~", "next to ~", "before ~", etc., it may include cases where it is not continuous unless "immediately" or "directly" is used.

[0018] On the other hand, when a numerical value regarding a component or its corresponding information (for example, level, etc.) is mentioned, the numerical value or its corresponding information can be interpreted to include the range of errors that can occur due to various factors (for example, process factors, internal or external impacts, noise, etc.) even without separate explicit description.

[0019] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0020] FIG. 1 shows a display device 100 according to an embodiment of the present disclosure.

[0021] Referring to FIG. 1, a display device 100 according to an embodiment of the present disclosure can include a display panel 110 that displays an image and an electronic device 11.

[0022] The display panel 110 may include a display area DA on which video (images) may be displayed, and a non-display area NDA on which video is not displayed.

[0023] The display area DA may contain multiple subpixels, and various signal lines for driving these subpixels may be arranged within it.

[0024] The non-display area (NDA) may be the outer region of the display area (DA). Various signal lines may be placed in the non-display area (NDA), and various drive circuits may be connected to it. The non-display area (NDA) may be bent to conceal it from view from the front, or covered by a case (not shown). The non-display area (NDA) is also called a bezel or bezel region.

[0025] Referring to Figure 1, in the display device 100 according to the embodiment of this disclosure, the electronic device 11 is an electronic component that is provided and installed separately from the display panel 110 and is located below the display panel 110 (on the opposite side of the viewing surface).

[0026] Light can enter the front (viewing surface) of the display panel 110, pass through the display panel 110, and be transmitted to the electronic device 11 located at the bottom of the display panel 110 (opposite the viewing surface). For example, the light that passes through the display panel 110 may include visible light, infrared rays, or ultraviolet rays.

[0027] The electronic device 11 may be a device that receives light transmitted through the display panel 110 and performs a predetermined function according to the received light. For example, the electronic device 11 may include at least one of the following: an imaging device such as a camera (image sensor), a proximity sensor, and a sensing sensor such as an illuminance sensor. Here, for example, the sensing sensor may be an infrared sensor, but is not limited to this.

[0028] In the display panel 110 according to the embodiments of this disclosure, the display area DA may include a general area NA, an optical bezel area OBA (not shown), and an optical area OA. The optical area OA may be an area that overlaps with the electronic device 11.

[0029] As illustrated in Figure 1, the display area DA may include a general area NA, an optical bezel area OBA (not shown), and an optical area OA. Here, at least a portion of the optical area OA can be superimposed on the electronic device 11.

[0030] The optical region OA must have both an image display structure and a light transmission structure. That is, since the optical region OA is a part of the display region DA, the optical region OA must have light-emitting areas for subpixels for displaying images. Furthermore, the optical region OA must have a light transmission structure for transmitting light to the electronic device 11.

[0031] The electronic device 11 is a device that requires light reception, but it is located on the back (bottom, opposite the viewing surface) of the display panel 110 and receives light that has passed through the display panel 110. The electronic device 11 is not exposed on the front (viewing surface) of the display panel 110. Therefore, when the user looks at the front of the display panel 110, the electronic device 11 is not visible to the user.

[0032] For example, the electronic device 11 could be a camera, a proximity sensor, an illuminance sensor, or other sensing sensor. For example, the sensing sensor could be an infrared sensor that detects infrared light. For the sake of explanation, the following example will assume that the electronic device 11 is a camera. Here, the camera could be a camera lens or an image sensor.

[0033] If the electronic device 11 is a camera, this camera is located on the back (bottom) of the display panel 110, but it may also be a front camera that photographs the front of the display panel 110. Therefore, the user may take pictures through a camera that is not visible on the viewing surface of the display panel 110 while looking at the viewing surface.

[0034] The general area NA, optical bezel area OBA (not shown), and optical area OA included in the display area DA are areas where images can be displayed. However, the general area NA and optical bezel area OBA (not shown) are areas where a light-transmitting structure does not need to be formed, while the optical area OA is an area where a light-transmitting structure should be formed.

[0035] Therefore, the optical region OA should have a transmittance above a certain level, while the general region NA may have no light transmittance or a low transmittance below a certain level.

[0036] For example, the optical region OA, the optical bezel region OBA (not shown), and the general region NA may differ from each other in terms of resolution, subpixel arrangement structure, number of subpixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure.

[0037] For example, the number of subpixels per unit area in the optical region (OA) may be less than the number of subpixels per unit area in the general region (NA). That is, the resolution of the optical region (OA) may be lower than the resolution of the general region (NA). Here, the number of subpixels per unit area can be synonymous with resolution, pixel density, or pixel integration. For example, the unit of the number of subpixels per unit area can also be expressed as PPI (Pixels Per Inch), which means the number of pixels in one inch.

[0038] On the other hand, as one method to improve the transmittance of the optical region OA, the pixel density difference design method can be applied, as described above. According to the pixel density difference design method, the display panel 110 can be designed such that the number of subpixels per unit area of ​​the optical region OA is greater than the number of subpixels per unit area of ​​the optical bezel region OBA (not shown) and the general region NA.

[0039] However, in some cases, a different approach can be taken to increase the transmittance of the optical region OA, and a pixel size difference design method can be applied. According to the pixel size difference design method, the number of subpixels per unit area of ​​the optical region OA is the same as or similar to the number of subpixels per unit area of ​​the optical bezel region OBA (not shown) and the general region NA, but the display panel 110 can be designed such that the size of each subpixel SP located in the optical region OA (i.e., the size of the light-emitting region) is smaller than the size of each subpixel SP located in the optical bezel region OBA (not shown) and the general region NA (i.e., the size of the light-emitting region).

[0040] In the following explanation, for the sake of clarity, we will assume that the pixel density difference design method is applied, one of two methods for increasing the transmittance of the optical domain OA (the pixel density difference design method and the pixel size difference design method). Therefore, in the following, a small number of subpixels per unit area may correspond to a small subpixel size, and a large number of subpixels per unit area may correspond to a large subpixel size.

[0041] The optical region (OA) can have various shapes, such as circular, elliptical, square, hexagonal, or octagonal.

[0042] In the display device 100 according to the embodiment of this disclosure, if the electronic device 11 hidden at the bottom of the display panel 110 without being exposed to the outside is a camera, then the display device 100 according to the embodiment of this disclosure can be said to be a display to which UDC (Under Display Camera) technology is applied.

[0043] According to this, in the case of the display device 100 according to the embodiment of the present disclosure, a notch or camera hole for camera exposure does not need to be formed in the display panel 110, so there is no reduction in the area of ​​the display area DA. As a result, a notch or camera hole for camera exposure does not need to be formed in the display panel 110, so the size of the bezel area can be reduced, eliminating design constraints and potentially increasing the degree of freedom in design.

[0044] In the display device 100 according to the embodiment of the present disclosure, even though the electronic device 11 is hidden behind the display panel 110, the electronic device 11 must be able to receive light normally and perform predetermined functions normally.

[0045] Furthermore, in the display device 100 according to the embodiment of this disclosure, even though the electronic device 11 is hidden behind the display panel 110 and overlaps with the display area DA, it must be possible to display a normal image in the optical area OA that overlaps with the electronic device 11 within the display area DA.

[0046] As the aforementioned optical region OA is designed as a transparent region, the image display characteristics in the optical region OA may differ from those in the optical bezel region OBA (not shown) and the general region NA.

[0047] Furthermore, when designing optical OA equipment to improve image display characteristics, there is a possibility that the transmittance of the optical OA equipment may decrease.

[0048] Therefore, embodiments of this disclosure present an optical region OA structure that can prevent variations in image quality between the optical region OA, the optical bezel region OBA (not shown), and the general region NA, and improve transmittance in the optical region OA.

[0049] Figure 2 is a system configuration diagram of the display device 100 according to an embodiment of the present disclosure.

[0050] Referring to Figure 2, the display device 100 is a component for displaying images and may include a display panel 110 and a display driving circuit.

[0051] The display driving circuit is a circuit for driving the display panel 110 and may include a data driving circuit 220, a gate driving circuit 230, and a display controller 240, etc.

[0052] The display panel 110 may include a display area DA on which an image is displayed and a non-display area NDA on which no image is displayed. The non-display area NDA may be the outer area of ​​the display area DA, or it may also be called the bezel area. All or part of the non-display area NDA may be an area visible from the front of the display device 100, or an area that is bent and not visible from the front of the display device 100.

[0053] The display panel 110 may include a substrate SUB and a plurality of subpixels SP arranged on the substrate SUB. Furthermore, the display panel 110 may further include various types of signal lines to drive the plurality of subpixels SP.

[0054] The display device 100 according to the embodiments of this disclosure may be a liquid crystal display device or the like, or it may be a self-emissive display device in which the display panel 110 emits light itself. When the display device 100 according to the embodiments of this disclosure is a self-emissive display device, each of the plurality of subpixels SP may include an element-emitting element. For example, the display device 100 according to the embodiments of this disclosure may be an organic light-emitting display device in which the element-emitting element is realized by an organic light-emitting diode (OLED). As another example, the display device 100 according to the embodiments of this disclosure may be an inorganic light-emitting display device in which the element-emitting element is realized by an inorganic-based light-emitting diode. As yet another example, the display device 100 according to the embodiments of this disclosure may be a quantum dot display device in which the element-emitting element is realized by a quantum dot, which is a semiconductor crystal that emits light itself.

[0055] The structure of each of the multiple subpixels SP may vary depending on the type of display device 100. For example, if the display device 100 is a self-emissive display device that emits light from the subpixels SP itself, each subpixel SP may include a light-emitting element that emits light itself, at least one transistor, and at least one capacitor.

[0056] For example, some types of signal lines may include multiple data lines DL that transmit data signals (also known as data voltages or video signals), and multiple gate lines GL that transmit gate signals (also known as scan signals).

[0057] Multiple data lines DL and multiple gate lines GL can intersect each other. Each of the multiple data lines DL can be arranged extending in a first direction. Each of the multiple gate lines GL can be arranged extending in a second direction, where the first direction is the column direction and the second direction is the row direction. Alternatively, the first direction is the row direction and the second direction is the column direction.

[0058] The data drive circuit 220 is a circuit for driving multiple data lines DL and can output data signals to multiple data lines DL. The gate drive circuit 230 is a circuit for driving multiple gate lines GL and can output gate signals to multiple gate lines GL.

[0059] The display controller 240 is a device for controlling the data drive circuit 220 and the gate drive circuit 230, and can control the drive timing for multiple data lines DL and the drive timing for multiple gate lines GL.

[0060] The display controller 240 can supply a data drive control signal DCS to the data drive circuit 220 to control the data drive circuit 220, and can supply a gate drive control signal GCS to the gate drive circuit 230 to control the gate drive circuit 230.

[0061] The display controller 240 can receive input video data from the host system 250 and supply video data Data to the data drive circuit 220 based on the input video data.

[0062] The data drive circuit 220 receives digital video data from the display controller 240, converts the received video data into an analog data signal, and outputs it to multiple data lines DL.

[0063] The gate drive circuit 230 is supplied with various gate drive control signals GCS, a first gate voltage corresponding to the turn-on level voltage, and a second gate voltage corresponding to the turn-off level voltage, generates a gate signal, and can supply the generated gate signal to multiple gate lines GL.

[0064] On the other hand, at least one of the data drive circuit 220 and gate drive circuit 230 may be placed in the display area DA of the display panel 110. For example, at least one of the data drive circuit 220 and gate drive circuit 230 may be placed so as not to overlap with the subpixel SP, or it may be placed so as to partially or entirely overlap with the subpixel SP.

[0065] The data drive circuit 220 and the gate drive circuit 230 may be connected to one side of the display panel 110 (for example, the top or bottom). Depending on the drive method, panel design method, etc., the data drive circuit 220 may be connected to both sides of the display panel 110 (for example, the top and bottom), or to two or more of the four sides of the display panel 110.

[0066] The display controller 240 can be implemented as a separate component from the data drive circuit 220, or it can be implemented as an integrated circuit by integrating it together with the data drive circuit 220.

[0067] The display controller 240 may be a timing controller used in conventional display technology, a control device that can perform other control functions in addition to the timing controller, a control device different from the timing controller, or a circuit within the control device. The display controller 240 can be implemented as various circuits or electronic components such as an IC (Integrated Circuit), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or processor.

[0068] The display controller 240 can be mounted on a printed circuit board, a flexible printed circuit board, etc., and can be electrically connected to the data drive circuit 220 and the gate drive circuit 230 via the printed circuit board, flexible printed circuit board, etc.

[0069] The display controller 240 can send and receive signals with the data drive circuit 220 according to at least one predetermined interface. For example, the interface may include an LVDS (Low Voltage Differential Signaling) interface, an EPI (Embedded Clock Point-Point Interface), or an SPI (Serial Peripheral Interface).

[0070] The display device 100 according to the embodiments of this disclosure may include, in addition to a video display function, a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or pen, or to detect the touch position, in order to further provide a touch sensing function.

[0071] The touch sensing circuit may include a touch drive circuit 260 that drives and senses a touch sensor and generates and outputs touch sensing data, and a touch controller 270 that can use the touch sensing data to detect a touch or determine the touch position.

[0072] The touch sensor may include multiple touch electrodes. The touch sensor may further include multiple touch lines for electrically connecting the multiple touch electrodes to the touch drive circuit 260.

[0073] The touch drive circuit 260 can supply a touch drive signal to at least one of the multiple touch electrodes, sense at least one of the multiple touch electrodes, and generate touch sensing data.

[0074] The display device 100 may further include a power supply circuit that supplies various power sources to the display driving circuit and / or touch sensing circuit.

[0075] The display device 100 according to the embodiments of this disclosure may be a mobile terminal such as a smartphone or tablet, or it may be a monitor or television (TV) of various sizes, but is not limited thereto, and may be a display of various types and sizes capable of displaying information or images.

[0076] As described above, in the display panel 110, the display area DA may include a general area NA, an optical bezel area OBA (not shown), and an optical area OA. The general area NA, the optical bezel area OBA (not shown), and the optical area OA are areas on which images can be displayed. However, the general area NA and the optical bezel area OBA (not shown) are areas on which a light-transmitting structure does not need to be formed, while the optical area OA is an area on which a light-transmitting structure should be formed.

[0077] As mentioned above, in the display panel 110, the display area DA is assumed to include the optical area OA along with the general area NA and the optical bezel area OBA (not shown).

[0078] Figure 3 is a schematic diagram of the display panel 110 according to an embodiment of the present disclosure.

[0079] Referring to Figure 3, multiple subpixels SP may be arranged in the display area DA of the display panel 110. Multiple subpixels SP may be arranged in the general area NA, the optical bezel area OBA, and the optical area OA, which are included in the display area DA.

[0080] Each of the multiple subpixels SP may include a light-emitting element ED and a pixel circuit SPC configured to drive the light-emitting element ED.

[0081] The pixel circuit SPC may include a drive transistor DT for driving the light-emitting element ED, a scan transistor ST for transmitting a data voltage VDATA to the first node N1 of the drive transistor DT, and a storage capacitor Cst for maintaining a constant voltage for one frame.

[0082] The drive transistor DT may include a first node N1 to which a data voltage may be applied, a second node N2 electrically connected to a light-emitting element ED, and a third node N3 to which a drive voltage VDD is applied from a drive voltage line VDDL. In the drive transistor DT, the first node N1 is the gate node, the second node N2 is either the source node or the drain node, and the third node N3 is either the drain node or the source node. For the sake of explanation, the following example will be given in which the drive transistor DT has a first node N1 as the gate node, a second node N2 as the source node, and a third node N3 as the drain node.

[0083] The light-emitting element ED may include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE. The anode electrode AE ​​is a pixel electrode placed in each subpixel SP and may be electrically connected to the second node N2 of the driving transistor DT of each subpixel SP. The cathode electrode CE is a common electrode placed in common by multiple subpixels SP and may have a base voltage VSS applied to it.

[0084] For example, the anode electrode AE ​​may be a pixel electrode and the cathode electrode CE may be a common electrode. Conversely, the anode electrode AE ​​may be a common electrode and the cathode electrode CE may be a pixel electrode, but this is not the case. For the sake of explanation, we will assume below that the anode electrode AE ​​is a pixel electrode and the cathode electrode CE is a common electrode.

[0085] The light-emitting element ED may have a predetermined light-emitting region EA, and the light-emitting region EA of the light-emitting element ED can be defined as the region where the anode electrode AE, the light-emitting layer EL, and the cathode electrode CE overlap.

[0086] For example, the light-emitting element ED may be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot light-emitting element. If the light-emitting element ED is an organic light-emitting diode, the light-emitting layer EL in the light-emitting element ED may, but is not limited to, an organic light-emitting layer EL containing organic material.

[0087] The scan transistor ST is controlled on and off by the scan signal SCAN of the gate signal applied via the gate line GL, and can be electrically connected between the first node N1 of the drive transistor DT and the data line DL.

[0088] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the drive transistor DT.

[0089] The pixel circuit SPC may have a 2T (Transistor) 1C (Capacitor) structure including two transistors DT and ST and one capacitor Cst, as shown in Figure 3, and may optionally include one or more transistors or one or more capacitors.

[0090] The storage capacitor Cst may be an intentionally designed external capacitor located outside the drive transistor DT, rather than a parasitic capacitor (e.g., Cgs, Cgd) which is an internal capacitor that may exist between the first node N1 and the second node N2 of the drive transistor DT. The drive transistor DT and the scan transistor ST may each be either an n-type or p-type transistor.

[0091] Since the circuit elements within each subpixel SP (particularly the light-emitting elements ED, which are realized with organic light-emitting diodes (OLEDs) containing organic materials) are vulnerable to external moisture and oxygen, a sealing layer ENCAP may be placed on the display panel 110 to prevent external moisture and oxygen from penetrating the circuit elements (particularly the light-emitting elements ED). The sealing layer ENCAP can be placed in a manner that covers the light-emitting elements ED.

[0092] Figure 4 schematically shows the optical region OA and the surrounding general region NA in a display panel 110 according to an embodiment of the present disclosure.

[0093] The display panel 110 according to the embodiments of this disclosure may include a display area DA on which video is displayed and a non-display area NDA on which video is not displayed.

[0094] The display area DA may include a transmissive optical area OA and a general area NA surrounding it.

[0095] An optical bezel region OBA may be arranged around the outer casing of the optical region OA. In embodiments of this disclosure, the optical bezel region OBA can be considered as part of the general region NA.

[0096] In other words, the display area DA may include an optical area OA, a general area NA located on the outer edge of the optical area OA, and an optical bezel area OBA which is the area between the optical area OA and the general area NA.

[0097] Referring to Figure 4, the optical region OA is the region that overlaps with the electronic device 11 and can be a passable region through which light necessary for the operation of the electronic device 11 can pass.

[0098] Here, the light transmitted through the optical region OA may include light in a single wavelength band or light in various wavelength bands. For example, the light transmitted through the optical region OA may include one or more types of light such as visible light, infrared light, or ultraviolet light.

[0099] The electronic device 11 can receive light transmitted through the optical region OA and perform predetermined operations using the received light. Here, the light that the electronic device 11 receives through the optical region OA may include at least one of visible light, infrared light, or ultraviolet light.

[0100] For example, if the electronic device 11 is a camera, the light transmitted through the optical region OA and used by the electronic device 11 may include visible light. As another example, if the electronic device 11 is an infrared-based sensor, the light transmitted through the optical region OA and used by the electronic device 11 may include infrared light (also called infrared light).

[0101] Referring to Figure 4, the optical bezel region OBA may be the region located on the outer edge of the optical region OA. The general region NA may be the region located on the outer edge of the optical bezel region OBA. The optical bezel region OBA may be located between the optical region OA and the general region NA.

[0102] For example, the optical bezel area OBA may be located only on the outer edge of a portion of the boundary of the optical area OA, or it may be located on the outer edge of the entire boundary of the optical area OA, but is not limited to this.

[0103] When the optical bezel area OBA is positioned around the entire boundary of the optical area OA, the optical bezel area OBA may have a ring shape that surrounds the optical area OA.

[0104] For example, the optical region OA can have various shapes, such as circular, elliptical, polygonal, or irregular shapes. The optical bezel region OBA can have various ring shapes (e.g., circular ring shape, elliptical ring shape, polygonal ring shape, or irregular ring shape) surrounding the optical region OA, which has various shapes.

[0105] Referring to Figure 4, the display area DA can include multiple light-emitting areas EA. Since the optical area OA, optical bezel area OBA, and general area NA are areas included in the display area DA, each of the optical area OA, optical bezel area OBA, and general area NA can include multiple light-emitting areas EA.

[0106] For example, multiple light-emitting regions EA may include, but are not limited to, a first-color light-emitting region that emits a first color of light, a second-color light-emitting region that emits a second color of light, and a third-color light-emitting region that emits a third color of light.

[0107] At least one of the first color emission region, the second color emission region, and the third color emission region may have a different area from the rest.

[0108] The first, second, and third colors can be a variety of different colors. For example, the first, second, and third colors may include red, green, and blue.

[0109] For the sake of explanation, the following example will use the case where the first color is red, the second color is green, and the third color is blue. However, it is not limited to this example.

[0110] If the first color is red, the second color is green, and the third color is blue, then the area of ​​the blue emission region EA_B may be the largest among the areas of the red emission region EA_R, the green emission region EA_G, and the blue emission region EA_B.

[0111] A light-emitting element ED located in the red light-emitting region EA_R may include a light-emitting layer EL that emits red light. A light-emitting element ED located in the green light-emitting region EA_G may include a light-emitting layer EL that emits green light. A light-emitting element ED located in the blue light-emitting region EA_B may include a light-emitting layer EL that emits blue light.

[0112] Of the three light-emitting layers (EL) – the red light-emitting layer, the green light-emitting layer, and the blue light-emitting layer – the organic material contained in the blue light-emitting layer is likely to be the most susceptible to material degradation.

[0113] By designing the area of ​​the blue light-emitting region EA_B to be the largest, the current density supplied to the light-emitting element ED located in the blue light-emitting region EA_B may be the lowest. Therefore, the degradation of the light-emitting element ED located in the blue light-emitting region EA_B may be similar to the degradation of the light-emitting element ED located in the red light-emitting region EA_R and the light-emitting element ED located in the green light-emitting region EA_G.

[0114] Therefore, variations in degradation between the light-emitting elements ED located in the red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B are eliminated or reduced, thereby improving image quality. Furthermore, eliminating or reducing variations in degradation between the light-emitting elements ED located in the red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B may reduce variations in lifespan among these elements.

[0115] Referring to Figure 4, the optical region OA should have high transmittance by including a transmissible region. For this reason, the cathode electrode CE can consist of a transparent electrode containing a transparent conductive material.

[0116] The cathode electrode CE may contain different materials in the general region NA and the optical bezel region OBA than in the optical region OA. For example, the cathode electrode CE in the general region NA and the optical region OBA may contain a metal or a metal alloy. In this case, by forming the cathode electrode CE with a thin thickness, it can have a translucent property.

[0117] The optical region OA may include an emission region EA and a transmission region TA.

[0118] Figures 5a and 5b show the light-emitting elements ED1, ED2, ED3, and ED4 arranged in the general area NA, the optical bezel area OBA, and the optical area OA, as well as the pixel circuits SPC1, SPC2, SPC3, and SPC4 for driving the light-emitting elements ED1, ED2, ED3, and ED4 in the display panel 110 according to an embodiment of the present disclosure.

[0119] However, each of the pixel circuits SPC1, SPC2, SPC3, and SPC4 may include transistors DT and ST and storage capacitors Cst, as shown in Figure 3. However, for the sake of explanation, the pixel circuits SPC1, SPC2, SPC3, and SPC4 are abbreviated as drive transistors DT1, DT2, DT3, and DT4, respectively.

[0120] Referring to Figure 5a, the general region NA, the optical region OA, and the optical bezel region OBA may have structural differences as well as positional differences.

[0121] In terms of structural differences, pixel circuits SPC1, SPC2, SPC3, and SPC4 may be placed in the optical bezel region OBA and the general region NA, but no pixel circuits are placed in the optical region OA. That is, transistors DT1, DT2, DT3, and DT4 may be placed in the optical bezel region OBA and the general region NA, but no transistors are placed in the optical region OA.

[0122] The transistors and storage capacitors included in the pixel circuits SPC1, SPC2, SPC3, and SPC4 are configured to reduce transmittance. As a result, the transmittance of the optical region OA can be further increased because the pixel circuits SPC1, SPC2, SPC3, and SPC are not placed in the optical region OA.

[0123] Pixel circuits SPC1, SPC2, SPC3, and SPC4 are placed only in the general region NA and the optical bezel region OBA, while light-emitting elements ED1, ED2, ED3, and ED4 can be placed in all of the general region NA, the optical bezel region OBA, and the optical region OA.

[0124] The optical region OA contains a first light-emitting element ED1, but the optical region OA1 does not contain a first pixel circuit SPC1 for driving the first light-emitting element ED1.

[0125] The first pixel circuit SPC1 for driving the first light-emitting element ED1 located in the optical region OA may not be located in the optical region OA1, but rather in the optical bezel region OBA.

[0126] The general area NA, optical area OA, and optical bezel area OBA will be explained in more detail below.

[0127] The multiple light-emitting regions EA included in the display panel 110 according to the embodiments of this disclosure may include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3. Here, the first light-emitting region EA1 may be included in the optical region OA, the second light-emitting region EA2 may be included in the optical bezel region OBA, and the third light-emitting region EA3 may be included in the general region NA. Hereafter, it will be assumed that the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 are light-emitting regions of the same color.

[0128] The display panel 110 according to the embodiments of this disclosure may include a first light-emitting element ED1 arranged in the optical region OA and having a first light-emitting region EA1, a second light-emitting element ED2 arranged in the optical bezel region OBA and having a second light-emitting region EA2, and a third light-emitting element ED3 arranged in the general region NA and having a third light-emitting region EA3.

[0129] The display panel 110 according to the embodiments of the present disclosure may further include a first pixel circuit SPC1 configured to drive a first light-emitting element ED1, a second pixel circuit SPC2 configured to drive a second light-emitting element ED2, and a third pixel circuit SPC3 configured to drive a third light-emitting element ED3.

[0130] For example, the first pixel circuit SPC1 may include a first drive transistor DT1. The second pixel circuit SPC2 may include a second drive transistor DT2. The third pixel circuit SPC3 may include a third drive transistor DT3, but is not limited to these.

[0131] In the display panel 110 according to the embodiment of the present disclosure, the second pixel circuit SPC2 may be located in the optical bezel region OBA on which the corresponding second light-emitting element ED2 is located, and the third pixel circuit SPC3 may be located in the general region NA on which the corresponding third light-emitting element ED3 is located.

[0132] In the display panel 110 according to the embodiment of this disclosure, the first pixel circuit SPC1 is not located in the optical region OA where the corresponding first light-emitting element ED1 is arranged, but can be located in the optical bezel region OBA which is located on the outer edge of the optical region OA. This makes it possible to increase the transmittance of the optical region OA.

[0133] The display panel 110 according to the embodiments of the present disclosure may further include an anode extension line AEL that electrically connects a first pixel circuit SPC1 located in the optical bezel area OBA and a first light-emitting element ED1 located in the optical area OA.

[0134] The anode extension line AEL can electrically extend the anode electrode AE ​​of the first light-emitting element ED1 to the second node N2 of the first drive transistor DT1 in the first pixel circuit SPC1.

[0135] As described above, in the display panel 110 according to the embodiment of this disclosure, the first pixel circuit SPC1 for driving the first light-emitting element ED1 located in the optical region OA may not be located in the optical region OA, but rather in the optical bezel region OBA. Such a structure is also called an anode extension structure.

[0136] If the display panel 110 according to the embodiment of the present disclosure has an anode extension structure, all or part of the anode extension line AEL can be placed in the optical region OA, and the anode extension line AEL may include transparent wiring. This prevents a decrease in the transmittance of the optical region OA even if the anode extension line AEL connecting the first pixel circuit SPC1 and the first light-emitting element ED1 is placed in the optical region OA.

[0137] Multiple light-emitting regions EA may further include a fourth light-emitting region EA4 that emits light of the same color as the first light-emitting region EA1 and is included in the optical region OA.

[0138] For example, the fourth light-emitting region EA4 may be positioned adjacent to the first light-emitting region EA1 in the row or column direction.

[0139] The display panel 110 according to embodiments of the present disclosure may further include a fourth light-emitting element ED4 having a fourth light-emitting region EA4 and a fourth pixel circuit SPC4 configured to drive the fourth light-emitting element ED4, which is located in an optical region OA.

[0140] The fourth pixel circuit SPC4 may include a fourth drive transistor DT4. For convenience of explanation, the scan transistor ST and storage capacitor Cst included in the fourth pixel circuit SPC4 are omitted from Figure 5a.

[0141] The fourth pixel circuit SPC4 is a circuit for driving the fourth light-emitting element ED4 located in the optical region OA, but it may also be located in the optical bezel region OBA.

[0142] The display panel 110 according to the embodiments of this disclosure may further include an anode extension line AEL that electrically connects a fourth pixel circuit SPC4 and a fourth light-emitting element ED4.

[0143] All or part of such anode extension lines (AELs) can be placed in the optical region (OA), and the anode extension lines (AELs) may include transparent wiring.

[0144] As described above, the first pixel circuit SPC1 located in the optical bezel region OBA can drive one light-emitting element ED1 located in the optical region OA. This type of circuit connection method is called a one-to-one (1:1) circuit connection method.

[0145] This allows for a significant increase in the number of pixel circuits (SPCs) placed in the optical bezel area (OBA). The structure of the optical bezel area (OBA) becomes more complex, and the aperture ratio (or light-emitting area) of the optical bezel area (OBA) can be reduced.

[0146] Despite having an anode extension structure, the display device 100 according to the embodiment of this disclosure may have a 1:N (where N is 2 or more) circuit section connection method in order to increase the aperture ratio (or light-emitting area) of the optical bezel region OBA.

[0147] According to the 1:N circuit connection method, a first pixel circuit SPC1 located in the optical bezel area OBA can simultaneously drive two or more light-emitting elements ED located in the optical area OA.

[0148] In Figure 5b, for the sake of explanation, an example is given in which a 1:2 circuit connection method is applied, that is, when the first pixel circuit SPC1 located in the optical bezel area OBA simultaneously drives two or more light-emitting elements ED1 and ED4 located in the optical area OA.

[0149] Figure 5b shows the light-emitting elements ED1, ED2, ED3, and ED4 arranged in the general area NA, the optical bezel area OBA, and the optical area OA, as well as the pixel circuits SPC1, SPC2, and SPC3 for driving the light-emitting elements ED1, ED2, ED3, and ED4, in a display panel 110 according to an embodiment of the present disclosure.

[0150] Referring to Figure 5b, the fourth light-emitting element ED4 located in the optical region OA may be driven by the first pixel circuit SPC1, which drives the first light-emitting element ED1 located in the optical region OA. That is, the first pixel circuit SPC1 located in the optical bezel region OBA may be configured to drive both the first light-emitting element ED1 and the fourth light-emitting element ED4 located in the optical region OA.

[0151] As a result, even though the display panel 110 has an anode extension structure, the number of pixel circuits SPCs arranged in the optical bezel area OBA is reduced, thereby increasing the aperture and light-emitting area of ​​the optical bezel area OBA.

[0152] For example, the first light-emitting element ED1 and the fourth light-emitting element ED4, which are driven together by the first pixel circuit SPC1 located in the optical bezel region OBA, are light-emitting elements that emit light of the same color and may be adjacent to each other in the row or column direction, but are not limited to these.

[0153] For example, the anode extension line AEL can connect a first pixel circuit SPC1 located in the optical bezel region OBA to a first light-emitting element ED1 and a fourth light-emitting element ED4 located in the optical region OA, but is not limited to this.

[0154] Figure 6 is a subpixel configuration circuit diagram of a display panel according to an embodiment of the present disclosure.

[0155] Referring to Figure 6, in the display panel 110, a plurality of subpixels SP may be arranged in the display area DA. Each subpixel SP may include a light-emitting element ED and a pixel circuit SPC configured to drive the light-emitting element ED.

[0156] For example, the first, second, and third colors can be a variety of different colors. For example, the first, second, and third colors may include red, green, and blue, but embodiments of the present disclosure are not limited thereto.

[0157] Referring to Figure 6, for example, a plurality of subpixels SP may include a pixel circuit SPC_R configured to drive a light-emitting element ED_R for emitting light of a first color R. Another example is a pixel circuit SPC_G configured to drive a light-emitting element ED_G for emitting light of a second color G. Yet another example is a pixel circuit SPC_B configured to drive a light-emitting element ED_B for emitting light of a third color B, but embodiments of the present disclosure are not limited thereto.

[0158] Referring to Figure 6, for example, multiple light-emitting elements ED_B for emitting third color B light can be formed. Multiple light-emitting elements ED_B may include light-emitting elements ED_B1 and ED_B2 being connected in a parallel structure, but the embodiments of this disclosure are not limited thereto. As another example, multiple light-emitting elements ED_B may have a redundancy structure by arranging light-emitting elements ED_B1 and ED_B2 in a parallel structure, but are not limited thereto.

[0159] Referring to Figure 6, for example, the light-emitting element ED_R for emitting light of the first color R, the light-emitting element ED_G for emitting light of the second color G, and the light-emitting element ED_B for emitting light of the third color B may each include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE. The cathode electrode CE may be a common electrode arranged in common by multiple subpixels SP, and a base voltage VSS may be applied, but is not limited to this.

[0160] Figure 7 shows the equivalent circuit of a subpixel of a display panel according to an embodiment of the present disclosure.

[0161] Referring to Figure 7, each of the subpixels SP of the display panel according to the embodiments of the present disclosure may include a light-emitting element ED and a subpixel circuit SPC.

[0162] Referring to Figure 7, the light-emitting element ED includes a pixel electrode AE ​​and a common electrode CE, the common electrode CE may be connected to a base voltage line VSSL to which the base voltage VSS is applied. For example, the pixel electrode AE ​​may be the anode and the common electrode CE may be the cathode, but is not limited to this.

[0163] Referring to Figure 7, the subpixel circuit SPC may include first to fourth nodes N1 to N4. Of the first to fourth nodes N1 to N4, the fourth node N4 may be electrically connected to the pixel electrode of the light-emitting element ED.

[0164] The subpixel circuit SPC may be supplied with the first to fourth scan signals SC1, SC2, SC3, SC4 from the first to fourth scan signal lines SCL1, SCL2, SCL3, SCL4, and the data voltage VDATA from the corresponding data line DL.

[0165] The subpixel circuit SPC may be supplied with a drive voltage VDD from the drive voltage line VDDL, an initialization voltage VINI from the initialization voltage line VINIL, and a bias voltage VOBS from the bias voltage line VOBSL.

[0166] The subpixel circuit SPC may be supplied with a reset voltage VAR from the reset voltage line VARL. When the pixel electrode AE ​​is the anode, the reset voltage VAR is sometimes called the anode reset voltage.

[0167] For example, the reset voltage VAR may be one of several common signals CS1, CS2, and CS3. The reset voltage line VARL may, but is not limited to, one of several common signal lines CSL1, CSL2, and CSL3.

[0168] Referring to Figure 7, the subpixel circuit SPC can include eight transistors T1-T7, DT and one capacitor Cst. This is merely an example for illustrative purposes and is not limited to this configuration; it can be modified in various ways.

[0169] Referring to Figure 7, the subpixel circuit SPC may include a first transistor T1 connected between the first node N1 and the third node N3, a second transistor T2 whose on-off state is controlled by a second scan signal SC2 supplied from the second scan signal line SCL2 and controls the electrical connection between the corresponding data line DL and the second node N2, and a third transistor T3 connected between the second node N2 and a drive voltage line VDDL to which a drive voltage VDD is applied, whose on-off state is controlled by a light emission control signal EM supplied from the light emission control signal line EML.

[0170] Referring to Figure 7, the subpixel circuit SPC may further include a fourth transistor T4 whose on-off switch is controlled by a light emission control signal EM supplied from a light emission control signal line EML, and which controls the electrical connection between the third node N3 and the fourth node N4; and a fifth transistor T5 whose on-off switch is controlled by a fourth scan signal line SCL4 supplied from a fourth scan signal line SCL, and which controls the electrical connection between the initialization voltage line VINIL, to which the initialization voltage VINI is applied, and the first node N1.

[0171] Referring to Figure 7, the subpixel circuit SPC may further include a sixth transistor T6 that controls the electrical connection between the fourth node N4 and a reset voltage line VARL, to which a reset voltage VAR is applied, and which is controlled to be switched on and off by a third scan signal SC3 supplied from a third scan signal line SCL3; and a seventh transistor T7 that controls the electrical connection between the second node N2 and a bias voltage line VOBSL, to which a bias voltage VOBS is applied, and which is controlled to be switched on and off by a third scan signal SC3 supplied from a third scan signal line SCL3.

[0172] Referring to Figure 7, the drive transistor DT is a transistor for supplying a drive current to the light-emitting element ED, and may be, but is not limited to, the fourth transistor T4 or the sixth transistor T6. The drive transistor DT can drive the light-emitting element ED by supplying a drive current to it at a predetermined timing. The light-emitting element ED can emit light when driven by the drive current.

[0173] Referring to Figure 7, the fourth node N4 may be, but is not limited to, the pixel electrode PE of the light-emitting element ED or a node electrically connected to the pixel electrode PE.

[0174] Referring to Figure 7, the gate nodes of the third transistor T3 and the fourth transistor T4 can be electrically connected together to the light emission control line EML. Therefore, the third transistor T3 and the fourth transistor T4 can be turned on together or turned off together.

[0175] Referring to Figure 7, the gate nodes of the sixth transistor T6 and the seventh transistor T7 can be electrically connected together to the third scan signal line SCL3. Therefore, the sixth transistor T6 and the seventh transistor T7 can be turned on together or turned off together.

[0176] Referring to Figure 7, the subpixel circuit SPC may further include a storage capacitor Cst formed between the first node N1 and the drive voltage line VDDL.

[0177] Referring to Figure 7, for example, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the drive transistor DT may all be p-type transistors, but are not limited to this.

[0178] As an example, transistors T1 to T8 (1st to 8th) could all be p-type transistors. As another example, transistors T1 to T8 (1st to 8th) could all be n-type transistors. As yet another example, at least one type (n-type or p-type) of transistors T1 to T8 (1st to 8th) could be different from the remaining types (p-type or n-type), but is not limited to these.

[0179] Referring to Figure 7, among the signals supplied to the subpixel circuit SPC, the remaining signals, excluding the data voltage VDATA and the first to fourth scan signals SC1 to SC4, may be common drive signals supplied to multiple subpixel circuits SPC. For example, the common drive signals may include, but are not limited to, at least one of the drive voltage VDD, bias voltage VOBS, initialization voltage VINI, and reset voltage VAR.

[0180] The common drive signal includes multiple common signals CS1, CS2, and CS3, each of which may be one of the following: drive voltage VDD, bias voltage VOBS, initialization voltage VINI, and reset voltage VAR.

[0181] For example, the multiple common signals CS1, CS2, CS3 may be a reset voltage VAR applied to the fourth node N4, and the multiple common signal lines CSL1, CSL2, CSL3 may be a reset voltage line VARL connected to the fourth node N4, but are not limited to these. In this case, one of the multiple common signals CS1, CS2, CS3 is a reset voltage VAR, which can be applied to the fourth node N4, which is electrically connected to the pixel electrode PE, via the sixth transistor T6 at the drive timing when the sixth transistor T6 is turned on.

[0182] Figures 8 and 9 are cross-sectional views taken along the line X-Y of Figure 5b according to an embodiment of the present disclosure.

[0183] Referring to Figures 8 and 9, the display panel according to the embodiment of the present disclosure may include an optical area OA and a display area DA which includes an optical bezel area OBA surrounding the optical area OA and a general area NA surrounding the optical bezel area OBA.

[0184] Referring to Figures 8 and 9, the display panel 110 according to an embodiment of the present disclosure may include a substrate SUB that overlaps the optical bezel area OBA and the general area NA. The substrate SUB includes a first substrate SUB1 and a second substrate SUB2, and may include an interlayer film INTL between the first substrate SUB1 and the second substrate SUB2. Here, for example, the interlayer film INTL is an inorganic film that can block moisture penetration.

[0185] As an example, the substrate SUB may include, but is not limited to, a first region A1 and a second region A2 surrounding the first region A1.

[0186] Referring to Figure 8, the insulating layers BUF, GI, and ILD on the substrate SUB of the optical bezel region OBA of the display panel 110 according to the embodiment of the present disclosure may include transistor sections. The transistor section may include a first transistor TFT1 and a second transistor TFT2.

[0187] Referring to Figure 8, the first transistor TFT1 may include a first shield pattern BSM1, a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1.

[0188] Referring to Figure 8, the first shield pattern BSM1 can be superimposed on the first active layer ACT1. The first shield pattern BSM1 can be placed beneath the first active layer ACT1 of the first thin-film transistor TFT1. The first shield pattern BSM1 can be placed between the substrate SUB and the buffer layer BUF, but is not limited to this.

[0189] As an example, the first shield pattern BSM1 can be electrically connected to the first gate electrode G1. As another example, the first shield pattern BSM1 can function as a light shield that blocks light incident from below. In this case, the first shield pattern BSM1 may, but is not limited to, be electrically connected to the first source electrode S1.

[0190] Referring to Figure 8, the second transistor TFT2 may include a second shield pattern BSM2, a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2.

[0191] Referring to Figure 8, the second shield pattern BSM2 can be superimposed on the second active layer ACT2. The second shield pattern BSM2 can be placed beneath the second active layer ACT2 of the second thin-film transistor TFT2. The second shield pattern BSM2 can be placed between the substrate SUB and the buffer layer BUF, but is not limited to this.

[0192] As an example, the second shield pattern BSM2 can be electrically connected to the second gate electrode G2. As another example, the second shield pattern BSM2 can function as a light shield that blocks light incident from below. In this case, the second shield pattern BSM2 may, but is not limited to, be electrically connected to the second source electrode S2.

[0193] Referring to Figure 8, the substrate SUB of the optical bezel area OBA of the display panel 110 according to the embodiment of the present disclosure may further include a first light-emitting element ED1 and a common electrode 850.

[0194] Referring to Figure 8, the first light-emitting element ED1 of the optical bezel region OBA of the display panel 110 according to the embodiment of the present disclosure can be placed in the sealing layer PLN.

[0195] Referring to Figure 8, the common electrode 850 may be connected to the base voltage line VSSL to which the base voltage VSS is applied. A cathode voltage can be applied to the common electrode 850.

[0196] Referring to Figures 8 and 9, the display panel according to the embodiment of the present disclosure may include an electronic device 11 that overlaps with the optical region OA and overlaps with a portion of the optical bezel region OBA. The electronic device 11 may include a third region A3 and a fourth region A4 that surrounds the third region A3 and is located below the first region A1. The first region A1 and the fourth region A4 can overlap.

[0197] For example, the electronic device 11 may be a device that receives light transmitted through the display panel 110 and performs a predetermined function according to the received light. For example, the electronic device 11 may include one or more of the following: a camera (image sensor) or other imaging device, a proximity sensor, an illuminance sensor or other sensing sensor. Here, for example, the sensing sensor may be an infrared sensor, but is not limited to that. In the following explanation, for convenience, we will give an example where the electronic device 11 is a camera. Here, the camera may be a camera lens or an image sensor, but is not limited to that.

[0198] Referring to Figure 8, a second light-emitting element ED2 may be further included on the electronic device 11 that overlaps the optical region OA of the display panel 110 according to an embodiment of the present disclosure. That is, the second light-emitting element ED2 may be superimposed on the electronic device 11 in the optical region OA. As shown in Figure 8, the second light-emitting element ED2 may be located at a lower height than the first light-emitting element ED1, but the optical region OA may not have multiple layers formed in the optical bezel region OBA in order to increase light transmittance.

[0199] Referring to Figure 8, the optical region OA has a second light-emitting element ED2, but the optical region OA does not have a pixel circuit SPC for driving the second light-emitting element ED2. The pixel circuit SPC for driving the second light-emitting element ED2 located in the optical region OA may not be located in the optical region OA, but rather in the optical bezel region OBA.

[0200] Referring to Figure 8, the optical bezel area OBA of the display panel 110 according to the embodiment of the present disclosure may include a first connection electrode 810 and a second connection electrode 820.

[0201] Referring to Figure 8, the first connecting electrode 810 can electrically connect the anode electrode of the first light-emitting element ED1 to one electrode of the first transistor TFT1. The second connecting electrode 820 can electrically connect the cathode electrode of the first light-emitting element ED1 to the common electrode 850.

[0202] For example, the first connecting electrode 810 and the second connecting electrode 820 may include, but are not limited to, a transparent conductive material.

[0203] Referring to Figure 8, a bank BK can be placed on a portion of the upper surface of the first and second connection electrodes 810 and 820 of the optical bezel area OBA of the display panel 110 according to an embodiment of the present disclosure, but is not limited thereto.

[0204] Referring to Figure 8, the general region NA, the optical bezel region OBA, and the optical region OA are arranged on the first light-emitting element ED1 and the second light-emitting element ED2, and the planarization layer OC containing a transparent insulating material may be further included.

[0205] For example, the upper surface of bank BK may include a planarization layer OC, but is not limited to this.

[0206] Referring to Figure 8, the electronic devices 11 located in the optical area OA and optical bezel area OBA of the display panel 110 according to the embodiments of this disclosure may include a first transparent wiring 830 and a second transparent wiring 840.

[0207] Referring to Figure 8, the first transparent wiring 830 is located on the electronic device 11 and is arranged in the optical region OA and the optical bezel region OBA, and can electrically connect the anode electrode of the second light-emitting element ED2 to one electrode of the second transistor TFT2.

[0208] Referring to Figure 8, the second transparent wiring 840 is located on the electronic device 11 and is arranged in the optical region OA and the optical bezel region OBA, and can electrically connect the cathode electrode of the second light-emitting element ED2 to the common electrode 850.

[0209] Referring to Figure 8, a plan view 11a of the electronic devices arranged in the optical area OA and optical bezel area OBA of the display panel 110 according to an embodiment of the present disclosure shows that the first transparent wiring 830 and the second transparent wiring 840 can be arranged on the same plane, but are not limited to this.

[0210] Referring to Figure 8, a plan view 11a of the electronic devices arranged in the optical region OA and optical bezel region OBA of the display panel 110 according to an embodiment of the present disclosure shows that the first transparent wiring 830 can be connected to the anode electrode 821 of the second light-emitting element ED2, and the second transparent wiring 840 can be connected to the cathode electrode 822 of the second light-emitting element ED2, but is not limited thereto.

[0211] Referring to Figure 8, a third light-emitting element may be further included on the electronic device 11 that overlaps the optical region OA of the display panel 110 according to the embodiment of the present disclosure.

[0212] For example, the anode electrode of the third light-emitting element can be electrically connected to one electrode of the second transistor TFT2 via the first transparent wiring 830, and the cathode electrode of the third light-emitting element can be electrically connected to the common electrode 850 via the second transparent wiring 840, but is not limited to this.

[0213] Referring to Figure 8, the optical region OA should have high transmittance by including a transmissible region, so the first transparent wiring 830 and the second transparent wiring 840 may, but are not limited to, contain a transparent conductive material. This prevents a decrease in the transmittance of the optical region OA even when the first transparent wiring 830 and the second transparent wiring 840 are placed in the optical region OA.

[0214] Referring to Figures 8 and 9, the substrate SUB positioned in the optical bezel region OBA of the display panel 110 according to the embodiments of the present disclosure may include a first via hole VIA1 and a second via hole VIA2. The first via hole VIA1 and the second via hole VIA2 may be located in the first region A1.

[0215] For example, the first via hole VIA1 and the second via hole VIA2 can be formed by through-silicon vias (TSVs), but are not limited to this. As another example, through-silicon TSVs can be realized by filling the inside of microholes (vias) that penetrate a silicon wafer with conductive materials, and can mean electrical connection lines that penetrate the inside of the substrate, but are not limited to this.

[0216] Referring to Figure 8, the first via hole VIA1 may include a first conductive pattern 861 which is a conductive material that fills the interior of the first via hole VIA1, a first connecting pad 863 may be formed on the upper surface (e.g., first surface) of the first via hole VIA1, and a first adhesive pad 865 may be formed on the lower surface (e.g., second surface) of the first via hole VIA1 which is the opposite surface of the upper surface.

[0217] Referring to Figure 8, the second via hole VIA2 may include a second conductive pattern 862 which is a conductive material that fills the interior of the second via hole VIA2, a second connecting pad 864 may be formed on the upper surface (e.g., the first surface) of the second via hole VIA2, and a second adhesive pad 866 may be formed on the lower surface (e.g., the second surface) of the second via hole VIA2.

[0218] Referring to Figure 8, the first conductive pattern 861 may include a metallic material to electrically connect one electrode of the second transistor TFT2 to the first transparent wiring 830. For example, the metallic material may include, but is not limited to, any metal or alloy thereof such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti).

[0219] Referring to Figure 8, the second conductive pattern 862 may include a metallic material to electrically connect the common electrode 850 and the second transparent wiring 840. As an example, the metallic material may include, but is not limited to, any metal or alloy thereof such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti).

[0220] Referring to Figure 8, the first connection pad 863 is formed on the upper surface (e.g., the first surface) of the first via hole VIA1 and can electrically connect the first connection electrode 810, which is connected to one electrode of the second transistor TFT2, to the first conductive pattern 861. The first adhesive pad 865 is formed on the lower surface (e.g., the second surface) of the first via hole VIA1 and can electrically connect the first conductive pattern 861 to the first transparent wiring 830. The first connection pad 863 and the first adhesive pad 865 may include a metallic material. As an example, the metallic material may include, but is not limited to, any metal or alloy thereof such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti).

[0221] As an example, a drive voltage applied to one electrode of the second transistor TFT2 is transmitted to the first connecting electrode 810, electrically transmitted to the first conductive pattern 861 charged inside the first via hole VIA1 via the first connecting pad 863 formed on the upper surface (e.g., first surface) of the first via hole VIA1 which is in contact with the first connecting electrode 810, electrically transmitted to the first adhesive pad 865 formed on the lower surface (e.g., second surface) of the first via hole VIA1, and electrically transmitted to the first transparent wiring 830 which is in contact with the first adhesive pad 865, thereby electrically connecting one electrode of the second transistor TFT2 and the first transparent wiring 830, but is not limited to this.

[0222] Referring to Figure 8, the second connection pad 864 is formed on the upper surface (e.g., the first surface) of the second via hole VIA2 and can electrically connect the second connection electrode 820, which is connected to the common electrode 850, to the second conductive pattern 862. The second adhesive pad 866 is formed on the lower surface (e.g., the second surface) of the second via hole VIA2 and can electrically connect the second conductive pattern 862 to the second transparent wiring 840. The second connection pad 864 and the second adhesive pad 866 may include a metallic material. As an example, the metallic material may include, but is not limited to, any metal or alloy thereof such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti).

[0223] As an example, the cathode voltage applied to the common electrode 850 is transmitted to the second connecting electrode 820, electrically transmitted to the second conductive pattern 862 charged inside the second via hole VIA2 via the second connecting pad 864 formed on the upper surface (e.g., the first surface) of the second via hole VIA2 which is in contact with the second connecting electrode 820, electrically transmitted to the second adhesive pad 866 formed on the lower surface (e.g., the second surface) of the second via hole VIA2, and electrically transmitted to the second transparent wiring 840 which is in contact with the second adhesive pad 866, thereby electrically connecting the common electrode 850 and the second transparent wiring 840, but is not limited to this.

[0224] Referring to Figures 8 and 9, the display panel 110 according to the embodiment of the present disclosure may include an upper substrate SUB and a lower substrate 11.

[0225] Referring to Figures 8 and 9, the upper substrate SUB may include a first region A1 and a second region A2 surrounding the first region A1.

[0226] Referring to Figures 8 and 9, the lower substrate 11 may include a third region A3 and a fourth region A4 that surrounds the third region A3 and is located below the first region A1. The first region A1 and the fourth region A4 can be superimposed.

[0227] For example, the lower substrate 11 may be a device that receives light transmitted through the display panel 110 and performs a predetermined function according to the received light. For example, the lower substrate 11 may include one or more of the following: an imaging device such as a camera (image sensor), a proximity sensor, and an illuminance sensor. Here, for example, the sensing sensor may be an infrared sensor, but is not limited to that. In the following explanation, for convenience, we will give an example where the lower substrate 11 is a camera. Here, the camera may be a camera lens or an image sensor, but is not limited to that.

[0228] Referring to Figures 8 and 9, the upper substrate SUB can include a first transistor TFT1 and a second transistor TFT2.

[0229] Referring to Figures 8 and 9, the upper substrate SUB may further include a common electrode 850 to which a cathode voltage is applied. The common electrode 850 may be connected to a base voltage line VSSL to which a base voltage VSS is applied. A cathode voltage can be applied to the common electrode 850.

[0230] Referring to Figures 8 and 9, the first light-emitting element ED1 can be placed on the upper substrate SUB, and the second light-emitting element ED2 can be placed on the lower substrate 11.

[0231] Referring to Figures 8 and 9, the device may include a first connecting electrode 810 that connects the anode electrode of the first light-emitting element ED1 to the first transistor TFT1, and a second connecting electrode 820 that connects the cathode electrode of the first light-emitting element ED1 to the common electrode 850.

[0232] For example, the first connecting electrode 810 and the second connecting electrode 820 may include, but are not limited to, a transparent conductive material.

[0233] Referring to Figures 8 and 9, a second light-emitting element ED2 is placed on the lower substrate 11, but a pixel circuit SPC for driving the second light-emitting element ED2 is not placed on the lower substrate 11. The pixel circuit SPC for driving the second light-emitting element ED2 placed on the lower substrate 11 may not be placed on the lower substrate 11, but on the upper substrate SUB.

[0234] Referring to Figures 8 and 9, a third light-emitting element may be further included on the lower substrate 11 of the display panel 110 according to the embodiment of the present disclosure.

[0235] For example, the anode electrode of the third light-emitting element can be electrically connected to one electrode of the second transistor TFT2 via the first transparent wiring 830, and the cathode electrode of the third light-emitting element can be electrically connected to the common electrode 850 via the second transparent wiring 840, but is not limited to this.

[0236] Referring to Figures 8 and 9, the configuration may include a first transparent wiring 830 electrically connected to the anode electrode 821 of the second light-emitting element ED2, and a second transparent wiring 840 electrically connected to the cathode electrode 822 of the second light-emitting element ED2.

[0237] For example, the first transparent wiring 830 and the second transparent wiring 840 may, but are not limited to, include a transparent conductive material.

[0238] Referring to Figures 8 and 9, the lower substrate 11 must have high transmittance by including a transmissive region. Therefore, the first transparent wiring 830 and the second transparent wiring 840 may, but are not limited to, a transparent conductive material. This prevents a decrease in the transmittance of the lower substrate 11 even when the first transparent wiring 830 and the second transparent wiring 840 are placed on the lower substrate 11.

[0239] Referring to Figures 8 and 9, the upper substrate SUB may include a first via hole VIA1 and a second via hole VIA2 formed in the first region A1.

[0240] Referring to Figures 8 and 9, the first via hole VIA1 may include a first conductive pattern 861 that is placed inside the first via hole VIA1 and electrically connects one electrode of the second transistor TFT2 to the first transparent wiring 830, a first connection pad 863 may be formed on the upper surface of the first via hole VIA1, and a first adhesive pad 865 may be formed on the lower surface of the first via hole VIA1.

[0241] Referring to Figures 8 and 9, the first conductive pattern 861 may include a metallic material to electrically connect one electrode of the second transistor TFT2 to the first transparent wiring 830. For example, the metallic material may include, but is not limited to, any metal or alloy thereof such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti).

[0242] Referring to Figures 8 and 9, the first connection pad 863 is formed on the upper surface of the first via hole VIA1 and can electrically connect the first connection electrode 810, which is connected to one electrode of the second transistor TFT2, to the first conductive pattern 861. The first adhesive pad 865 is formed on the lower surface of the first via hole VIA1 and can electrically connect the first conductive pattern 861 to the first transparent wiring 830. The first connection pad 863 and the first adhesive pad 865 may include a metallic material. For example, the metallic material may include, but is not limited to, any metal or alloy thereof such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti).

[0243] Referring to Figures 8 and 9, the second via hole VIA2 may include a second conductive pattern 862 that is positioned within the second via hole VIA2 and electrically connects the common electrode 850 and the second transparent wiring 840, a second connection pad 864 may be formed on the upper surface of the second via hole VIA2, and a second adhesive pad 866 may be formed on the lower surface of the second via hole VIA2.

[0244] Referring to Figures 8 and 9, the second conductive pattern 862 may include a metallic material to electrically connect the common electrode 850 and the second transparent wiring 840. As an example, the metallic material may include, but is not limited to, any metal or alloy thereof such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti).

[0245] Referring to Figures 8 and 9, the second connection pad 864 is formed on the upper surface of the second via hole VIA2 and can electrically connect the second connection electrode 820, which is connected to the common electrode 850, to the second conductive pattern 862. The second adhesive pad 866 is formed on the lower surface of the second via hole VIA2 and can electrically connect the second conductive pattern 862 to the second transparent wiring 840. The second connection pad 864 and the second adhesive pad 866 may include a metallic material. For example, the metallic material may include, but is not limited to, any metal or alloy thereof such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti).

[0246] Referring to Figures 8 and 9, a bank BK can be placed on a portion of the upper surface of the first and second connection electrodes 810 and 820 of the optical bezel area OBA of the display panel 110 according to an embodiment of the present disclosure, but is not limited thereto.

[0247] Referring to Figures 8 and 9, the general region NA, the optical bezel region OBA, and the optical region OA are arranged on the first light-emitting element ED1 and the second light-emitting element ED2, and the planarization layer OC containing a transparent insulating material may be further included.

[0248] For example, the upper surface of bank BK may include a planarization layer OC, but is not limited to this.

[0249] Referring to Figures 8 and 9, the first light-emitting element ED1 and the second light-emitting element ED2 can include different types of LED (Light-emitting diode) chips.

[0250] As an example, the first light-emitting element ED1 may include an LED chip with a lateral chip structure, and the second light-emitting element ED2 may include an LED chip with a flip chip structure, but is not limited to these. As another example, the first light-emitting element ED1 may include an LED chip with a flip chip structure, and the second light-emitting element ED2 may include an LED chip with a lateral chip structure different from a flip chip structure, but is not limited to these.

[0251] For example, the first light-emitting element ED1 and the second light-emitting element ED2 may include, but are not limited to, microLEDs. In another example, the microLED can be formed in a size of approximately 10 to 100 μm, but are not limited to that. In yet another example, the microLED can be fabricated by forming a buffer layer on a substrate and growing a GaN thin film thereon. In this case, the substrate used for growing the GaN thin film may include, but are not limited to, sapphire, silicon (Si), GaN, silicon carbide (SiC), gallium arsenide (GaAs), zinc oxide (ZnO), etc.

[0252] Figures 10a and 10b are cross-sectional views showing the structure of a light-emitting element according to an embodiment of the present disclosure.

[0253] Referring to Figures 10a and 10b, the first light-emitting element ED1 of the display panel 110 according to the embodiment of the present disclosure may include an LED chip with a lateral chip structure, and the second light-emitting element ED2 may include an LED chip with a flip chip structure.

[0254] Referring to Figures 10a and 10b, the first light-emitting element ED1 and the second light-emitting element ED2 may include anode electrodes 811, 821, cathode electrodes 812, 822, GaN layers 813, 823, active layers 814, 824, anode GaN layers 815, 825, first contact layers 816, 826, and second contact layers 817, 827.

[0255] Referring to Figures 10a and 10b, the GaN layers 813 and 823 can include undoped semiconductor layers. For example, a cathode GaN layer (not shown) can be placed on the GaN layers 813 and 823. The cathode GaN layer (not shown) is a layer for supplying electrons to the active layers 814 and 824, and can be formed by doping the cathode GaN layer (not shown) with impurities such as Si, but is not limited to this.

[0256] Referring to Figures 10a and 10b, the active layers 814 and 824 are layers in which injected electrons and holes combine to emit light. Although not shown in the drawings, as an example, the multiple quantum well structure of the active layers 814 and 824 may consist of alternating arrangements of barrier layers and well layers, with the well layers being composed of InGaN layers and the barrier layers being composed of GaN, but is not limited to this.

[0257] Referring to Figures 10a and 10b, the anode GaN layers 815 and 825 are layers for injecting holes into the active layers 814 and 824, and may be formed by doping GaN layers 813 and 823 with impurities such as Mg, Zn, and Be, but are not limited to this.

[0258] Referring to Figures 10a and 10b, the first contact layers 816 and 826 are layers for bringing the anode GaN layers 815 and 825 into contact with the anode electrodes 811 and 821. As an example, transparent metal oxides such as ITO (Indium Tin Oxide), IGZO (Indium Gallium Zinc Oxide), and IZO (Indium Zinc Oxide) can be used, but are not limited to these.

[0259] Referring to Figures 10a and 10b, the second contact layers 817 and 827 are layers for bringing the cathode GaN layer (not shown) into contact with the cathode electrodes 812 and 822. As an example, transparent metal oxides such as ITO (Indium Tin Oxide), IGZO (Indium Gallium Zinc Oxide), and IZO (Indium Zinc Oxide) can be used, but are not limited to these.

[0260] Referring to Figures 10a and 10b, the anode electrodes 811, 821 and cathode electrodes 812, 822 may consist of a single layer or multiple layers made of at least one metal or an alloy thereof from Ni, Au, Pt, Ti, Al, and Cr, but are not limited to these.

[0261] Referring to Figures 10a and 10b, in such an LED chip structure, as voltage is applied to the anode electrodes 811, 821 and cathode electrodes 812, 822, electrons and holes are injected from the anode GaN layers 815, 825 and cathode GaN layer (not shown) into the active layers 814, 824, respectively. Excitons are generated within the active layers 814, 824, and as these excitons decay, light corresponding to the energy difference between the LUMO (Lowest Unoccupied Molecular Orbital) and HOMO (Highest Occupied Molecular Orbital) of the light-emitting layer is generated and emitted to the outside.

[0262] Figure 11 is a plan view of the upper and lower substrates to show the formation positions of the components according to the embodiment of the present disclosure, and Figure 12 is a diagram showing Figure 11 corresponding to Figure 8 according to the embodiment of the present disclosure.

[0263] Referring to Figures 11 and 12, an optical bezel area OBA can be arranged to surround the optical area OA.

[0264] Referring to Figures 11 and 12, the first transistor TFT1, the second transistor TFT2, and the first light-emitting element ED1 can be arranged in the optical bezel region OBA.

[0265] Referring to Figures 11 and 12, a first via hole VIA1 may be placed at the first connecting electrode 810 of the optical bezel region OBA, and a second via hole VIA2 may be placed at the second connecting electrode 820.

[0266] Referring to Figures 11 and 12, the edge 1100 of the electronic device can be formed so as to surround the first connecting electrode 810 of the optical bezel region OBA. In one example, the edge 1100 of the electronic device may correspond to the outer periphery of the lower substrate 11, but is not limited thereto. In another example, the edge 1100 of the electronic device may correspond to the periphery of the camera lens, but is not limited thereto.

[0267] Figure 13 is a plan view of the upper and lower substrates to show the formation positions of the components according to the embodiment of the present disclosure, and Figure 14 is a diagram showing Figure 13 according to the embodiment of the present disclosure, with correspondence to Figure 8.

[0268] Referring to Figures 13 and 14, the optical bezel region OBA surrounding the optical region OA can be arranged.

[0269] Referring to Figures 13 and 14, the second light-emitting element ED2 can be placed in the optical region OA.

[0270] Referring to Figures 13 and 14, the design may include a first transparent wiring 830 and a second transparent wiring 840 extending from the optical bezel area OBA to the optical area OA.

[0271] Referring to Figures 13 and 14, the first transparent wiring 830 can connect the first connecting electrode 810 located in the optical bezel region OBA to the anode electrode of the second light-emitting element located in the optical region OA.

[0272] Referring to Figures 13 and 14, the second transparent wiring 840 can connect the second connecting electrode 820 located in the optical bezel region OBA to the cathode electrode of the second light-emitting element located in the optical region OA.

[0273] Referring to Figures 13 and 14, the second connecting electrode 820, located in the optical bezel region OBA, can be connected to the second via hole VIA2.

[0274] The embodiments of this disclosure described above can be briefly described as follows.

[0275] A display device according to an embodiment of the present disclosure includes a display area comprising a light-transmitting optical region and an optical bezel region and a general region on the outer edge of the optical bezel region; a substrate overlapping the optical bezel region and the general region; an electronic device overlapping the optical region and overlapping a portion of the optical bezel region; a first transistor and a second transistor arranged in the optical bezel region; a first light-emitting element arranged in the optical bezel region and connected to the first transistor; and a second light-emitting element arranged in the optical region and connected to the second transistor, wherein the first transistor, the second transistor, and the first light-emitting element are arranged on the substrate, and the second light-emitting element is arranged on the electronic device.

[0276] The embodiments of the present disclosure may further include a first connecting electrode that electrically connects the anode electrode of a first light-emitting element of a display device to one electrode of a first transistor; a common electrode disposed on a substrate to which a cathode voltage is applied; and a second connecting electrode that electrically connects the cathode electrode of the first light-emitting element to the common electrode.

[0277] The first and second connecting electrodes of the display device according to the embodiments of this disclosure may include a transparent conductive material.

[0278] The present invention further includes a common electrode disposed on a substrate of a display device and to which a cathode voltage is applied; a first transparent wiring located on the electronic device and positioned in an optical region and an optical bezel region; and a second transparent wiring located on the electronic device and positioned in an optical region and an optical bezel region, wherein the anode electrode of the second light-emitting element is electrically connected to one electrode of the second transistor via the first transparent wiring, and the cathode electrode of the second light-emitting element is electrically connected to the common electrode via the second transparent wiring.

[0279] The first and second transparent wirings of the display device according to the embodiments of this disclosure may include a transparent conductive material.

[0280] The invention may further include a first via hole formed on the substrate of the display device according to the embodiments of this disclosure; a first conductive pattern located within the first via hole that electrically connects one electrode of a second transistor to the first transparent wiring; a second via hole formed on the substrate; and a second conductive pattern located within the second via hole that electrically connects a common electrode to the second transparent wiring.

[0281] The substrate of the display device according to the embodiments of the present disclosure includes a first region and a second region surrounding the first region, and the electronic device includes a third region and a fourth region surrounding the third region and located below the first region, the first region and the fourth region overlap, and a first beer hole and a second beer hole may be located in the first region.

[0282] A first connection pad and a second connection pad formed on upper surfaces of a first via hole and a second via hole of a display device according to an embodiment of the present disclosure; a first adhesion pad and a second adhesion pad formed on lower surfaces of the first via hole and the second via hole; a first conductive pattern which is a conductive substance filled inside the first via hole; and a second conductive pattern which is a conductive substance filled inside the second via hole can be included.

[0283] A planarization layer including a transparent insulating substance and disposed in a general area, an optical bezel area, and an optical area of a display device according to an embodiment of the present disclosure, and located on a first light-emitting element and a second light-emitting element can be further included.

[0284] An electronic device of a display device according to an embodiment of the present disclosure can be a camera or a sensing sensor that receives light and performs a predetermined operation.

[0285] A first light-emitting element and a second light-emitting element of a display device according to an embodiment of the present disclosure can include different types of LED (Light emitting diode) chips.

[0286] A first light-emitting element of a display device according to an embodiment of the present disclosure is an LED chip having a lateral chip structure, and a second light-emitting element can include an LED chip having a flip chip structure.

[0287] A display device according to an embodiment of the present disclosure further includes a third light-emitting element disposed in an optical area, an anode electrode of the third light-emitting element is electrically connected to one electrode of a second transistor via a first transparent wiring, and a cathode electrode of the third light-emitting element can be electrically connected to a common electrode via a second transparent wiring.

[0288] An embodiment of the display device according to the present disclosure includes: an upper substrate including a first region and a second region surrounding the first region; a lower substrate including a third region and a fourth region surrounding the third region and located below the first region; a first via hole and a second via hole formed in the first region of the upper substrate; a first transistor disposed on the upper substrate; a second transistor disposed on the upper substrate; a common electrode disposed on the upper substrate to which a cathode voltage is applied; a first light-emitting element disposed on the upper substrate; a second light-emitting element disposed on the lower substrate; a first transparent wiring electrically connected to the anode electrode of the second light-emitting element; a first conductive pattern disposed in the first via hole and electrically connecting one electrode of the second transistor to the first transparent wiring; a second transparent wiring electrically connected to the cathode electrode of the second light-emitting element; and a second conductive pattern disposed in the two via holes and electrically connecting the common electrode to the second transparent wiring, wherein the first and second transparent wirings may include a transparent conductive material.

[0289] The present embodiment of the display device includes a first connecting electrode that connects the anode electrode of the first light-emitting element to a first transistor, and a second connecting electrode that connects the cathode electrode of the first light-emitting element to a common electrode, wherein the first and second connecting electrodes may be made of a transparent conductive material.

[0290] The lower substrate of the display device according to the embodiments of this disclosure may include an electronic device that receives light and performs a predetermined operation.

[0291] The first light-emitting element of the display device according to the embodiments of this disclosure is an LED chip with a lateral chip structure, and the second light-emitting element may include an LED chip with a flip chip structure.

[0292] The display device according to the embodiments of this disclosure may further include a planarization layer located on the first and second light-emitting elements and containing a transparent insulating material.

[0293] The embodiment of the present disclosure further includes a third light-emitting element disposed on a lower substrate of the display device, wherein the anode electrode of the third light-emitting element is electrically connected to one electrode of a second transistor via a first transparent wiring, and the cathode electrode of the third light-emitting element can be electrically connected to a common electrode via a second transparent wiring.

[0294] The embodiments of the present disclosure may include first and second connection pads formed on the upper surfaces of the first and second via holes of the display device; and first and second adhesive pads formed on the lower surfaces of the first and second via holes.

[0295] A display device according to an embodiment of the present disclosure may include a display area comprising a light-transmitting optical region and an optical bezel region surrounding the optical region in a plan view and having a lower light transmittance than the optical region; an electronic device superimposed on the optical region and overlapping with a portion of the optical bezel region; a first transistor located in the optical bezel region; a common electrode located in the optical bezel region to which a cathode voltage is applied; a first light-emitting element located in the optical bezel region and connected to the first transistor; a first connecting electrode located in the optical bezel region surrounding the optical region in a plan view and electrically connecting the anode electrode of the first light-emitting element and one electrode of the first transistor; and a second connecting electrode located in the optical bezel region surrounding the optical region in a plan view, positioned between the optical region and the first connecting electrode, and electrically connecting the cathode electrode of the first light-emitting element and the common electrode.

[0296] A display device according to an embodiment of the present disclosure further includes a second transistor located in an optical bezel region, and a second light-emitting element located in the optical region, disposed on an electronic device and connected to the second transistor, wherein the height of the first light-emitting element is greater than the height of the second light-emitting element, and may further include a planarizing layer disposed on the second light-emitting element located in the optical region and the first light-emitting element located in the optical bezel region.

[0297] A display device according to an embodiment of the present disclosure further includes a first transparent wiring located on an electronic device and arranged in an optical region and an optical bezel region, and a second transparent wiring located on an electronic device and arranged in an optical region and an optical bezel region, wherein the anode electrode of a second light-emitting element is electrically connected to one electrode of a second transistor via the first transparent wiring, and the cathode electrode of a second light-emitting element may be electrically connected to a common electrode via the second transparent wiring.

[0298] According to the embodiments of the present disclosure described above, it is possible to provide a display device having a transparent structure that allows electronic devices to receive light normally without exposing the electronic devices to the entire surface of the display device.

[0299] According to embodiments of this disclosure, a display device can be provided that has a structure that can improve the transmittance of an optical region by arranging light-emitting elements in a transparent optical region and arranging a pixel circuit for driving the light-emitting elements in the optical region in an optical bezel region.

[0300] According to embodiments of this disclosure, by connecting a light-emitting element arranged in a transmissive optical region and a pixel circuit arranged in an optical bezel region with transparent wiring containing a transparent conductive material, it is possible to provide a display device that can improve the transmittance of the optical region, improve the resolution of the optical region, and ensure transmittance even when driven at low power.

[0301] The above description is merely illustrative of the technical concept of this disclosure, and any person with ordinary skill in the art to which this disclosure belongs could make various modifications and variations without departing from the essential characteristics of this disclosure. Furthermore, the embodiments disclosed herein are for illustrative purposes only and not to limit the technical concept of this disclosure, and such embodiments do not limit the scope of the technical concept of this disclosure. [Explanation of symbols]

[0302] 100:Display device 110: Display Panel 11:Electronic equipment DA:Display area OA: Optical area OBA: Optical bezel area VIA1: The First Beer Hall VIA2: The Second Beer Hall 830: First transparent wiring 840: Second transparent wiring

Claims

1. A display device, A display area comprising a light-transmitting optical region, an optical bezel region that at least partially surrounds the optical region when the display device is viewed in a plan view, and a general region that at least partially surrounds the optical bezel region in the plan view. A substrate that overlaps with the optical bezel region and the general region, but does not overlap with the optical region. An electronic device that overlaps with the aforementioned optical region and overlaps with a part of the aforementioned optical bezel region, A first transistor and a second transistor arranged in the optical bezel region, A first light-emitting element is arranged in the optical bezel region and connected to the first transistor, and A second light-emitting element is arranged in the optical region and connected to the second transistor located in the optical bezel region. Includes, The first transistor, the second transistor, and the first light-emitting element are arranged on the substrate in the optical bezel region. The second light-emitting element is a display device arranged on the electronic device in the optical region.

2. A first connecting electrode is arranged in the optical bezel region and electrically connects the anode electrode of the first light-emitting element and one electrode of the first transistor. A common electrode is placed on the substrate in the optical bezel region to which a cathode voltage is applied. A second connecting electrode is positioned in the optical bezel region and electrically connects the cathode electrode of the first light-emitting element and the common electrode. It further includes, The display device according to claim 1, wherein the first connecting electrode and the second connecting electrode include a transparent conductive material.

3. A common electrode is placed on the substrate in the optical bezel region to which a cathode voltage is applied. A first transparent wiring located on the electronic device and arranged in the optical region and the optical bezel region, and A second transparent wiring located on the electronic device and positioned in the optical region and the optical bezel region. It further includes, The anode electrode of the second light-emitting element is electrically connected to one electrode of the second transistor via the first transparent wiring. The cathode electrode of the second light-emitting element is electrically connected to the common electrode via the second transparent wiring. The display device according to claim 1, wherein the first transparent wiring and the second transparent wiring include a transparent conductive material.

4. A first via hole formed in the substrate, One electrode of the second transistor and the first transparent wiring are electrically connected, and the first conductive pattern located in the first via hole, A second via hole formed in the substrate, and The common electrode and the second transparent wiring are electrically connected, and the second conductive pattern is located within the second via hole. The display device according to claim 3, further comprising:

5. The substrate includes a first region and a second region surrounding the first region. The electronic device includes a third region and a fourth region that surrounds the third region and is located below the first region. The first region and the fourth region are superimposed, The display device according to claim 4, wherein the first beer hall and the second beer hall are located in the first region.

6. A first connecting pad is positioned on the first surface of the first beer hole, A second connecting pad is positioned on the first surface of the second via hole. A first adhesive pad is positioned on the second surface of the first beer hole, opposite to the first surface of the first beer hole. A second adhesive pad is positioned on the second surface of the second via hole, opposite to the first surface of the second via hole. A first conductive pattern, which is a first conductive material filled inside the first via hole, and A second conductive pattern, which is a second conductive material, is filled inside the second via hole. The display device according to claim 4, further comprising:

7. The display device according to claim 1, further comprising a planarization layer disposed in the general region, the optical bezel region, and the optical region, located on the first light-emitting element and the second light-emitting element, and containing a transparent insulating material.

8. The display device according to claim 1, wherein the electronic device is a camera or sensing sensor that receives light and performs a predetermined operation.

9. The first light-emitting element and the second light-emitting element are different types of LED (Light-emitting diode) chips. The first light-emitting element is a first LED chip with a lateral chip structure, The display device according to claim 1, wherein the second light-emitting element is a second LED chip having a flip-chip structure different from that of a lateral chip.

10. The optical region further includes a third light-emitting element, The anode electrode of the third light-emitting element is electrically connected to one electrode of the second transistor via the first transparent wiring. The display device according to claim 3, wherein the cathode electrode of the third light-emitting element is electrically connected to the common electrode via the second transparent wiring.

11. A display device, An upper substrate including a first region and a second region that surrounds the first region when the display device is viewed in a plan view, A lower substrate including a third region and a fourth region that surrounds the third region in a plan view and is located below the first region, A first via hole and a second via hole formed in the first region of the upper substrate, A first transistor, which is arranged on the upper substrate, A second transistor, which is positioned on the upper substrate, A common electrode, which is placed on the upper substrate and to which a cathode voltage is applied, A first light-emitting element disposed on the upper substrate, A second light-emitting element disposed on the lower substrate, A first transparent wiring electrically connected to the anode electrode of the second light-emitting element, A first conductive pattern is placed within the first via hole and electrically connects one electrode of the second transistor and the first transparent wiring. A second transparent wiring electrically connected to the cathode electrode of the second light-emitting element, and A second conductive pattern is placed within the second via hole and electrically connects the common electrode and the second transparent wiring. Includes, A display device comprising the first transparent wiring and the second transparent wiring, each containing a first transparent conductive material.

12. A first connecting electrode connecting the anode electrode of the first light-emitting element and the first transistor, and A second connecting electrode that connects the cathode electrode of the first light-emitting element and the common electrode. It further includes, The display device according to claim 11, wherein the first connecting electrode and the second connecting electrode each contain a second transparent conductive material.

13. The display device according to claim 11, wherein the lower substrate is an electronic device that receives light and performs a predetermined operation.

14. The first light-emitting element is a first LED chip with a lateral chip structure, The display device according to claim 11, wherein the second light-emitting element is a second LED chip having a flip-chip structure different from that of a lateral chip.

15. The display device according to claim 11, further comprising a planarization layer located on the first light-emitting element and the second light-emitting element, and containing a transparent insulating material.

16. The present invention further includes a third light-emitting element disposed on the lower substrate, The anode electrode of the third light-emitting element is electrically connected to one electrode of the second transistor via the first transparent wiring. The display device according to claim 11, wherein the cathode electrode of the third light-emitting element is electrically connected to the common electrode via the second transparent wiring.

17. A first connecting pad is positioned on the first surface of the first beer hole, A second connecting pad is positioned on the first surface of the second via hole. A first adhesive pad is positioned on the second surface of the first via hole, opposite to the first surface of the first via hole, and A second adhesive pad is positioned on the second surface of the second via hole, opposite to the first surface of the second via hole. The display device according to claim 11, further comprising:

18. A display device, A display area including an optical region and an optical bezel region that surrounds the optical region when the display device is viewed in a plan view and has a lower light transmittance than the optical region. An electronic device superimposed on the optical region and partially overlapping the optical bezel region, The first transistor located in the optical bezel region, A common electrode located in the optical bezel region to which a cathode voltage is applied, A first light-emitting element located in the optical bezel region and connected to the first transistor, A first connecting electrode located in the optical bezel region, surrounding the optical region in a plan view, and electrically connecting the anode electrode of the first light-emitting element and the first transistor, and A second connecting electrode located in the optical bezel region, surrounding the optical region in a plan view, positioned between the optical region and the first connecting electrode, electrically connecting the cathode electrode of the first light-emitting element and the common electrode. A display device, including a display device.

19. A second transistor located in the optical bezel region, and A second light-emitting element is disposed on the electronic device in the optical region and connected to the second transistor. It further includes, The height of the first light-emitting element is greater than the height of the second light-emitting element. The display device according to claim 18, further comprising the second light-emitting element located in the optical region and a planarizing layer disposed above the first light-emitting element located in the optical bezel region.

20. A first transparent wiring, disposed on the electronic device and located in the optical region and the optical bezel region, A second transparent wiring is placed on the electronic device and is located in the optical region and the optical bezel region. It further includes, The display device according to claim 19, wherein the anode electrode of the second light-emitting element is electrically connected to one electrode of the second transistor via the first transparent wiring, and the cathode electrode of the second light-emitting element is electrically connected to the common electrode via the second transparent wiring.

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