Method for manufacturing a display device

Abstract

The present invention provides a method for manufacturing a display device that can suppress a decline in display quality. [Solution] A method for manufacturing a display device according to one embodiment involves forming a lower electrode in a display area for displaying an image, forming a rib layer covering the lower electrode from an inorganic material, forming a partition wall including a conductive lower portion disposed on the rib layer and an upper portion disposed on the lower portion and protruding from the side surface of the lower portion, forming a pixel aperture in the rib layer that overlaps with the lower electrode, forming an organic layer that covers the lower electrode through the pixel aperture, and passing an electric current between the partition wall and the lower electrode to electrically insulate the lower portion and the organic layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for suppressing deterioration of display quality are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a method for manufacturing a display device capable of suppressing deterioration of display quality.

Means for Solving the Problems

[0005] A method for manufacturing a display device according to one embodiment involves forming a lower electrode in a display area for displaying an image, forming a rib layer covering the lower electrode from an inorganic material, forming a partition wall including a conductive lower portion disposed on the rib layer and an upper portion disposed on the lower portion and protruding from the side surface of the lower portion, forming a pixel aperture in the rib layer that overlaps with the lower electrode, forming an organic layer that covers the lower electrode through the pixel aperture, and passing an electric current between the partition wall and the lower electrode to electrically insulate the lower portion and the organic layer. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 shows an example of the configuration of a display device according to one embodiment. [Figure 2] Figure 2 is a circuit diagram showing an example of a configuration applicable to the pixel circuit provided by each sub-pixel. [Figure 3] Figure 3 is a schematic plan view showing an example of a sub-pixel layout. [Figure 4] Figure 4 is a schematic cross-sectional view of the display device along line IV-IV in Figure 3. [Figure 5] Figure 5 shows an example of a layer structure that can be applied to a display element. [Figure 6] Figure 6 is a schematic cross-sectional view showing an example of a partition wall and its surroundings. [Figure 7] Figure 7 is a schematic plan view of a motherboard according to one embodiment. [Figure 8] Figure 8 is a schematic plan view of a portion of the motherboard. [Figure 9A] Figure 9A is a schematic cross-sectional view showing the process for manufacturing the display device according to this embodiment. [Figure 9B] Figure 9B is a schematic cross-sectional view showing the process following Figure 9A. [Figure 9C] Figure 9C is a schematic cross-sectional view showing the process following Figure 9B. [Figure 9D] Figure 9D is a schematic cross-sectional view showing the process following Figure 9C. [Figure 9E] Figure 9E is a schematic cross-sectional view showing the process following Figure 9D. [Figure 9F] Figure 9F is a schematic cross-sectional view showing the process following Figure 9E. [Figure 9G] Figure 9G is a schematic cross-sectional view showing the process following Figure 9F. [Figure 9H] Figure 9H is a schematic cross-sectional view showing the process following Figure 9G. [Figure 9I] Figure 9I is a schematic cross-sectional view showing the process following Figure 9H. [Figure 10A] Figure 10A is a schematic cross-sectional view showing an example of the process of electrically insulating an organic layer and a partition wall. [Figure 10B] Figure 10B is a schematic cross-sectional view showing the process following Figure 10A. [Figure 10C] Figure 10C is a schematic cross-sectional view showing the process following Figure 10B. [Figure 11] Figure 11 is a circuit diagram in the process shown in Figure 10A. [Figure 12A] Figure 12A is a schematic cross-sectional view showing another example of the process of electrically insulating an organic layer and a partition wall. [Figure 12B] Figure 12B is a schematic cross-sectional view showing the process following Figure 12A. [Figure 13A] Figure 13A is a schematic cross-sectional view showing still another example of the process of electrically insulating an organic layer and a partition wall. [Figure 13B] Figure 13B is a schematic cross-sectional view showing the process following Figure 13A. [Figure 13C] Figure 13C is a schematic cross-sectional view showing the process following Figure 13B. [Figure 14] Figure 14 is a schematic cross-sectional view showing another example of the process shown in Figure 13A. [Figure 15] Figure 15 is a schematic cross-sectional view showing still another example of the process shown in Figure 13A.

Embodiments for Carrying Out the Invention

[0007] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0008] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X-axis is referred to as the X-direction, the direction along the Y-axis as the Y-direction, and the direction along the Z-axis as the Z-direction. Viewing various elements parallel to the Z-direction is called a plan view.

[0009] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0010] Figure 1 shows an example configuration of a display device DSP according to one embodiment. The display device DSP includes a display panel PNL including an insulating substrate 10. The display panel PNL has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0011] In this embodiment, the shape of the substrate 10 in plan view is a rectangle that is elongated in the Y direction. However, the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, circle, or ellipse.

[0012] The display area DA comprises multiple pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes multiple sub-pixels SP that display different colors. In this embodiment, we assume that each pixel PX includes three sub-pixels SP1, SP2, and SP3. For example, sub-pixel SP1 displays green, sub-pixel SP2 displays blue, and sub-pixel SP3 displays red. However, the colors displayed by sub-pixels SP1, SP2, and SP3 are not limited to this example. Furthermore, each pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0013] The display device DSP further includes a terminal section T located in the peripheral region SA. A flexible circuit board, for example, that supplies voltage and signals for driving the display device DSP, is connected to the terminal section T.

[0014] Figure 2 is a circuit diagram showing an example of a configuration applicable to the pixel circuit PC provided in each of the sub-pixels SP (SP1, SP2, SP3). The pixel circuit PC shown in this figure includes seven transistors TR1 to TR7 and one retaining capacitor Cst.

[0015] In the following explanation, one of the source and drain electrodes of each transistor TR1 to TR7 will be referred to as the first electrode, and the other as the second electrode. Similarly, one electrode of the retaining capacitance Cst will be referred to as the first electrode, and the other electrode as the second electrode.

[0016] The first electrode of transistor TR1 is connected to node n3. The second electrode of transistor TR1 is connected to signal line SL, which supplies the video signal Sdata. The video signal Sdata is the signal written to the pixels for image display.

[0017] Transistor TR2 corresponds to a drive transistor that supplies current to the display element DE included in the sub-pixel SP. The first electrode of transistor TR2 is connected to node n1. The second electrode of transistor TR2 is connected to node n3.

[0018] The first electrode of transistor TR3 is connected to node n1. The second electrode of transistor TR3 is connected to node n2.

[0019] The first electrode of transistor TR4 is connected to node n1. The second electrode of transistor TR4 is connected to power line PL1, which supplies the power supply voltage VDDEL.

[0020] The first electrode of transistor TR5 is connected to node n3. The second electrode of transistor TR5 is connected to node n4.

[0021] The first electrode of transistor TR6 is connected to node n4. The second electrode of transistor TR6 is connected to the initialization line IL, which supplies the initialization voltage Vini.

[0022] The first electrode of transistor TR7 is connected to node n1. The second electrode of transistor TR7 is connected to power line PL2, which supplies the power supply voltage VSH.

[0023] The first electrode of the retention capacitance Cst is connected to node n2. The second electrode of the retention capacitance Cst is connected to node n4.

[0024] The gate electrode of transistor TR1 is connected to scan line GL1, which supplies the scan signal Sg1. The gate electrode of transistor TR3 is connected to scan line GL2, which supplies the scan signal Sg2. The gate electrodes of transistors TR4, TR5, and TR6 are connected to scan line GL3, which supplies the scan signal Sg3. The gate electrode of transistor TR7 is connected to scan line GL4, which supplies the scan signal Sg4.

[0025] The anode of the display element DE is connected to node n4. The cathode of the display element DE is connected to power line PL3, which supplies the power supply voltage VSSEL. The power supply voltage VDDEL mentioned above corresponds to the anode voltage supplied to the display element DE, and the power supply voltage VSSEL corresponds to the cathode voltage supplied to the display element DE.

[0026] Note that the configuration of the pixel circuit PC is not limited to the example shown in Figure 2. For example, the pixel circuit PC may have six or fewer transistors, or eight or more transistors. Also, the pixel circuit PC may have multiple retention capacitors Cst.

[0027] In the circuit configuration shown in Figure 2, when a low (L) level signal is supplied to the gate electrodes of transistors TR1-TR3, TR6, and TR7, each transistor TR1-TR3, TR6, and TR7 will be in the OFF state (non-conductive state). On the other hand, when a high (H) level signal is supplied to the gate electrodes of transistors TR1-TR3, TR6, and TR7, each transistor TR1-TR3, TR6, and TR7 will be in the ON state (conductive state).

[0028] Furthermore, when a low-level signal is supplied to the gate electrodes of transistors TR4 and TR5, each transistor TR4 and TR5 will be in the ON state (conducting state). Conversely, when a high-level signal is supplied to the gate electrodes of transistors TR4 and TR5, each transistor TR4 and TR5 will be in the OFF state (non-conducting state).

[0029] Figure 3 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 3, sub-pixels SP2 and SP3 are aligned with sub-pixel SP1 in the X direction. Furthermore, sub-pixels SP2 and SP3 are aligned in the Y direction.

[0030] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the Y direction, and columns in which multiple sub-pixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 3.

[0031] A rib layer 5 is arranged in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 3, pixel aperture AP1 is larger than pixel aperture AP2, and pixel aperture AP2 is larger than pixel aperture AP3. That is, among sub-pixels SP1, SP2, and SP3, sub-pixel SP1 has the largest aperture ratio, and sub-pixel SP3 has the smallest aperture ratio. Note that the size and shape of pixel apertures AP1, AP2, and AP3 are not limited to the example shown.

[0032] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3.

[0033] The portion of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlaps with the pixel aperture AP1 constitutes the display element DE1 of the sub-pixel SP1. The portion of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlaps with the pixel aperture AP2 constitutes the display element DE2 of the sub-pixel SP2. The portion of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlaps with the pixel aperture AP3 constitutes the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0034] A conductive partition wall 6 is positioned in the display area DA. The partition wall 6 is located above the rib layer 5 and overlaps with the rib layer 5 overall. In the example in Figure 3, the partition wall 6 has a planar shape similar to that of the rib layer 5. That is, the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3, respectively. From another perspective, the rib layer 5 and the partition wall 6 are grid-like in plan view and surround the display elements DE1, DE2, and DE3, respectively. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0035] Figure 4 is a schematic cross-sectional view of the display device DSP along the IV-IV line in Figure 3. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring, such as the pixel circuit PC, scan lines GL1-GL4, signal line SL, power lines PL1-PL3, and initialization line IL shown in Figure 2. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.

[0036] The lower electrodes LE1, LE2, and LE3 are positioned on the organic insulating layer 12 and spaced apart from each other. The rib layer 5 is positioned on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross-section of Figure 4, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit PC of the circuit layer 11 through contact holes provided in the organic insulating layer 12.

[0037] The partition wall 6 includes a conductive lower section 61 positioned on the rib layer 5 and an upper section 62 positioned on top of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of partition wall 6 is called an overhang.

[0038] In the example shown in Figure 4, the lower section 61 has a bottom layer 63 positioned on top of the rib layer 5 and an axial layer 64 positioned on top of the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the axial layer 64. In the example shown in Figure 4, both ends of the bottom layer 63 protrude from the sides of the axial layer 64. Also, the ends of the bottom layer 63 are located between the ends of the upper section 62 and the sides of the axial layer 64 in a plan view. The upper section 62 is positioned on top of the axial layer 64.

[0039] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surface of the lower part 61 of the partition wall 6.

[0040] Display element DE1 includes a cap layer CP1 covering the upper electrode UE1. Display element DE2 includes a cap layer CP2 covering the upper electrode UE2. Display element DE3 includes a cap layer CP3 covering the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0041] In the following explanation, a multilayer containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.

[0042] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE11, SE12, and SE13, which cover the stacked films FL1, FL2, and FL3, respectively. Sealing layer SE11 continuously covers the display element DE1 and the surrounding partition wall 6. Sealing layer SE12 continuously covers the display element DE2 and the surrounding partition wall 6. Sealing layer SE13 continuously covers the display element DE3 and the surrounding partition wall 6.

[0043] In the example shown in Figure 4, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition wall 6. Also, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact above the partition wall 6.

[0044] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. The laminated films FL1, FL2, FL3 may be placed in at least a portion of these gaps.

[0045] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion extending into the peripheral area SA. In Figure 4, elements above the resin layer RS2 are omitted.

[0046] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0047] The lower electrodes LE1, LE2, and LE3 each have a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed from a metallic material with excellent light reflectivity, such as silver. Each conductive oxide layer can be formed from a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0048] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0049] The cap layers CP1, CP2, and CP3 have a laminated structure in which multiple transparent layers are stacked, for example. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0050] The bottom layer 63 and axial layer 64 of the partition wall 6 are formed of, for example, a metallic material. Examples of metallic materials for the bottom layer 63 include molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb). Examples of metallic materials for the axial layer 64 include aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the axial layer 64 may have a laminated structure of multiple layers. Furthermore, the axial layer 64 may include a layer formed of an insulating material.

[0051] For example, the upper part 62 of the partition wall 6 has a laminated structure consisting of a lower layer made of a metallic material and an upper layer made of a conductive oxide. As the metallic material forming the lower layer, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide forming the upper layer, for example, ITO or IZO can be used. The upper part 62 may also have a single-layer structure of metallic material. Furthermore, the upper part 62 may include a layer made of an insulating material.

[0052] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the sides of the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the video signal on the signal line SL through the pixel circuits PC of the sub-pixels SP1, SP2, and SP3, respectively.

[0053] In one example, the organic layers OR1, OR2, and OR3 are configured to emit light of different colors. In another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by each light-emitting layer contained in each of the organic layers OR1, OR2, and OR3 (light-emitting layers EM1, EM2, and EM3 shown in Figure 5) into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0054] Figure 5 shows an example of a layer structure applicable to the display elements DE1, DE2, and DE3. Here, the lower electrodes LE1, LE2, and LE3 correspond to the anodes, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes. Furthermore, the organic layers OR1, OR2, and OR3 are configured to emit light in different colors.

[0055] The organic layer OR1 includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, an emission layer EM1, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. The hole injection layer HIL is located above the lower electrode LE1, the hole transport layer HTL is located above the hole injection layer HIL, the electron blocking layer EBL is located above the hole transport layer HTL, the emission layer EM1 is located above the electron blocking layer EBL, the hole blocking layer HBL is located above the emission layer EM1, the electron transport layer ETL is located above the hole blocking layer HBL, the electron injection layer EIL is located above the electron transport layer ETL, and the upper electrode UE1 is located above the electron injection layer EIL. The emission layer EM1 is made of a material that emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the emission layer EM1 emits light in the green wavelength range.

[0056] In addition to the functional layers described above, the organic layer OR1 may include other functional layers such as a carrier generation layer as needed, or at least one of the functional layers described above may be omitted.

[0057] Display element DE2 is configured similarly to display element DE1, except that the organic layer OR2 between the lower electrode LE2 and the upper electrode UE2 includes a light-emitting layer EM2 instead of a light-emitting layer EM1. Display element DE3 is configured similarly to display element DE1, except that the organic layer OR3 between the lower electrode LE3 and the upper electrode UE3 includes a light-emitting layer EM3 instead of a light-emitting layer EM1. The light-emitting layer EM2 is made of a material that emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EM2 emits light in the blue wavelength range. The light-emitting layer EM3 is made of a material that emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EM3 emits light in the red wavelength range.

[0058] In the following description, the laminate of each layer of organic layer OR1 excluding the hole injection layer HIL will be called laminated film F1, the laminate of each layer of organic layer OR2 excluding the hole injection layer HIL will be called laminated film F2, and the laminate of each layer of organic layer OR3 excluding the hole injection layer HIL will be called laminated film F3. That is, laminated film F1 includes a hole transport layer HTL, an electron blocking layer EBL, an emissive layer EM1, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Laminated film F2 includes a hole transport layer HTL, an electron blocking layer EBL, an emissive layer EM2, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Laminated film F3 includes a hole transport layer HTL, an electron blocking layer EBL, an emissive layer EM3, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL.

[0059] Figure 6 is a schematic cross-sectional view showing an example of the partition wall 6 and its surroundings. The configuration in the region between sub-pixels SP1 and SP2 will be described below, but the same can be applied to the configurations in the region between sub-pixels SP1 and SP3 and the region between sub-pixels SP2 and SP3. In Figure 6, elements below the organic insulating layer 12 and elements above the sealing layers SE11 and SE12 are omitted.

[0060] Organic layer OR1 has an end E11 that is in contact with rib layer 5. Organic layer OR2 has an end E12 that is in contact with rib layer 5. Bottom layer 63 has both ends E2 that are in contact with rib layer 5. In the example in Figure 6, ends E11 and E2 are separated from each other via a gap V1, and ends E12 and E2 are separated from each other via a gap V2.

[0061] The void V1 is surrounded by the rib layer 5, the bottom layer 63, the organic layer OR1, and the upper electrode UE1. In the example in Figure 6, the void V1 faces the hole injection layer HIL of the organic layer OR1. The void V1 may also face the laminated film F1.

[0062] The void V2 is surrounded by the rib layer 5, the bottom layer 63, the organic layer OR2, and the upper electrode UE2. In the example in Figure 6, the void V2 faces the hole injection layer HIL of the organic layer OR2. The void V2 may also face the laminated film F2.

[0063] Organic layer OR1 is separated from the lower part 61 (bottom layer 63) via a gap V1. Organic layer OR2 is separated from the lower part 61 (bottom layer 63) via a gap V2. That is, organic layer OR1 and the lower part 61 are electrically insulated via the gap V1. Similarly, organic layer OR2 and the lower part 61 are electrically insulated via the gap V2. Note that gaps V1 and V2 do not necessarily have to be formed. That is, the ends E11, E2 and E12, E2 may be in contact. However, even in this case, organic layers OR1, OR2 and the lower part 61 are electrically insulated.

[0064] During the manufacturing of a display device (DSP), a large motherboard is created in which multiple areas (panel sections) corresponding to the display panel PNL are formed. The following describes the configurations that can be applied to this motherboard.

[0065] Figure 7 is a schematic plan view of a motherboard MB (display device motherboard) according to one embodiment. The motherboard MB is rectangular, as shown in the figure, but it may have other shapes such as a circle.

[0066] The motherboard MB has multiple panel sections PP arranged in a matrix, and a marginal area BA surrounding these panel sections PP. In the example in Figure 7, the panel sections PP are arranged in the X and Y directions with the marginal area BA in between. However, at least two of the multiple panel sections PP of the motherboard MB may be adjacent to each other without being separated by the marginal area BA.

[0067] Figure 8 is a schematic plan view of a portion of the motherboard MB. This figure focuses on one panel section PP. The outline of the panel section PP corresponds to the cut line CL1 used to cut the panel section PP from the motherboard MB.

[0068] Each panel section PP has the aforementioned display area DA and peripheral area SA. Furthermore, the peripheral area SA includes an inspection area TA. The inspection area TA contains inspection pads PD and other components for inspecting the operation of the display panel PNL.

[0069] Each panel section PP has a cut line CL2 formed on it. This cut line CL2 divides the panel section PP into a portion including the display area DA and a portion including the inspection area TA.

[0070] During the manufacturing of the DSP display device, the panel portion PP is first cut out from the motherboard MB along the cut line CL1. Furthermore, the cut-out panel portion PP is inspected using an inspection pad PD. After this inspection, the inspection area TA is separated from the panel portion PP along the cut line CL2.

[0071] Next, an example of a method for manufacturing a display device DSP will be described. Figures 9A to 9I are schematic cross-sectional views showing the process for manufacturing a display device DSP. In Figures 9A to 9I, the focus is mainly on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0072] In the manufacturing of the display device DSP, a circuit layer 11 and an organic insulating layer 12 are first formed on the substrate 10. Next, as shown in Figure 9A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12.

[0073] Next, as shown in Figure 9B, a rib layer 5 is formed covering the lower electrodes LE1, LE2, and LE3. Inorganic materials can be used for the rib layer 5. At this point, the pixel apertures AP1, AP2, and AP3 are not provided in the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0074] After the formation of the rib layer 5, a process for forming the partition wall 6 is carried out. In this process, a layer for processing the bottom layer 63, a layer for processing the axial layer 64, and a layer for processing the upper part 62 are formed in order. Then, a resist patterned to the shape of the partition wall 6 is placed, and the above layers are patterned using this resist as a mask. As a result, the partition wall 6 is formed as shown in Figure 9C.

[0075] Next, a process is carried out to create pixel apertures AP1, AP2, and AP3. In this process, a resist is formed to cover the partition wall 6, and the rib layer 5 is patterned using this resist as a mask. As a result, as shown in Figure 9D, pixel apertures AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed in the rib layer 5. Note that the process of forming the partition wall 6 may be carried out after the process of forming the pixel apertures AP1, AP2, and AP3 in the rib layer 5.

[0076] Subsequently, a process for forming the display element DE1 is carried out. In forming the display element DE1, first, as shown in Figure 9E, a laminated film FL1 and a sealing layer SE11 are formed. As shown in Figure 4, the laminated film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel aperture AP1, an upper electrode UE1 that covers the organic layer OR1, and a cap layer CP1 that covers the upper electrode UE1. The laminated film FL1 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6.

[0077] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed, for example, by vapor deposition. The sealing layer SE11 can also be formed, for example, by CVD.

[0078] Next, the multilayer film FL1 and the sealing layer SE11 are patterned. In this patterning process, as shown in Figure 9E, a resist R1 is placed on top of the sealing layer SE11. The resist R1 covers the subpixel SP1 and a portion of the surrounding partition wall 6.

[0079] Subsequently, an etching process is performed using resist R1 as a mask. As a result, as shown in Figure 9F, the portions of the multilayer film FL1 and the encapsulation layer SE11 that are exposed from resist R1 are removed. In other words, the portions of the multilayer film FL1 and the encapsulation layer SE11 that overlap with the lower electrode LE1 are left, and the other portions are removed. This forms the display element DE1 on the sub-pixel SP1. This etching process may include wet etching or dry etching performed sequentially on the encapsulation layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, resist R1 is removed (peeled off).

[0080] Furthermore, during wet etching of the multilayer film FL1, the portion of the multilayer film FL1 located above the partition wall 6 and below the sealing layer SE11 is also removed. This creates a gap between the sealing layer SE11 above the partition wall 6 and the partition wall 6. Since the multilayer film FL1 constituting the display element DE1 is completely surrounded by the sealing layer SE11 and the partition wall 6, it is not eroded by the wet etching described above.

[0081] Subsequently, a process for forming the display element DE2 is carried out. The display element DE2 can be formed using the same procedure as the display element DE1. That is, in forming the display element DE2, a multilayer film FL2 and a sealing layer SE12 are formed. As shown in Figure 4, the multilayer film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel aperture AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0082] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed, for example, by vapor deposition. The sealing layer SE12 can also be formed, for example, by CVD. The multilayer film FL2 is divided into multiple parts by overhanging partitions 6. The sealing layer SE12 continuously covers each divided part of the multilayer film FL2 and the partitions 6. By patterning the multilayer film FL2 and the sealing layer SE2 in this way, a display element DE2 is formed on the sub-pixel SP2, as shown in Figure 9G.

[0083] Subsequently, a process for forming the display element DE3 is carried out. The display element DE3 can be formed using the same procedure as for the display elements DE1 and DE2. That is, in forming the display element DE3, a multilayer film FL3 and a sealing layer SE13 are formed. As shown in Figure 4, the multilayer film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel aperture AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.

[0084] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed, for example, by vapor deposition. The sealing layer SE13 can be formed, for example, by CVD. The multilayer film FL3 is divided into multiple parts by overhanging partitions 6. The sealing layer SE13 continuously covers each divided part of the multilayer film FL3 and the partitions 6. By patterning the multilayer film FL3 and the sealing layer SE13, a display element DE3 is formed on the sub-pixel SP3, as shown in Figure 9H.

[0085] Note that, while this example assumes that the display elements DE1, DE2, and DE3 are formed in this order, they may be formed in any other order.

[0086] After the display elements DE1, DE2, and DE3 are formed, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 are formed in sequence, as shown in Figure 9I. Furthermore, each panel portion PP is cut out from the motherboard MB along the cut line CL1.

[0087] Subsequently, inspections are performed on each panel section PP. These inspections include lighting tests of each display element DE1, DE2, and DE3 using inspection pads PD placed in the inspection area TA. After the inspections, the inspection area TA is cut along the cut line CL2. This completes the display panel PNL.

[0088] Figures 10A to 10C are schematic cross-sectional views showing an example of a process for electrically insulating the organic layer OR1 and the partition wall 6. This process is carried out, for example, between the process shown in Figure 9D and the process shown in Figure 9E.

[0089] After the formation of pixel apertures AP1, AP2, and AP3, an organic layer OR1 covering the lower electrode LE1 and an upper electrode UE1 covering the organic layer OR1 are formed through the pixel aperture AP1, as shown in Figure 10A. The organic layer OR1 includes a hole injection layer HIL and a multilayer film F1. The hole injection layer HIL is in contact with the lower electrode LE1. In the example in Figure 10A, the hole injection layer HIL is formed on the lower electrode LE1 and the rib layer 5, the multilayer film F1 is formed on the hole injection layer HIL, and the upper electrode UE1 is formed on the multilayer film F1. The hole injection layer HIL, the multilayer film F1, and the upper electrode UE1 are stacked on top of the upper 62.

[0090] At this time, due to unintended variations in the manufacturing process, the organic layer OR1 and the lower layer 61 may partially come into contact within the motherboard MB. That is, a state may occur where the very thin organic layer OR1 is in contact with the edge E2 of the bottom layer 63. Figure 10A shows the case where the edge E11 of the hole injection layer HIL is in contact with the edge E2 of the bottom layer 63. In other words, Figure 10A shows a state where the very thin hole injection layer HIL is in contact with the edge E2 of the bottom layer 63. Here, the state where the edges E11 and E2 are in contact means that there is electrical conductivity between the edges E11 and E2. In this case, the contact area of ​​the edges E11 and E2 constitutes a leak area LK. For example, the electrical resistance of the leak area LK per pixel due to the contact of the edges E11 and E2 is between several tens of G ohms and several hundred G ohms.

[0091] After the formation of the upper electrode UE1, the partition wall 6 and the lower electrode LE1 are connected to the power supply C1, as shown in Figure 10A. In the example shown in Figure 10A, the power supply C1 is a direct current (DC) power supply. The partition wall 6 is connected to the high potential side, and the lower electrode LE1 is connected to the low potential side.

[0092] Next, a voltage is applied between the partition wall 6 and the lower electrode LE1, causing a current I to flow from the high-potential partition wall 6 to the low-potential lower electrode LE1. In the example shown in Figure 10A, since the end E11 of the hole injection layer HIL and the end E2 of the bottom layer 63 are in contact at the leakage section LK, the current I flows in the order of bottom layer 63, hole injection layer HIL, and lower electrode LE1. When the lower electrode LE1 corresponds to the anode and the upper electrode UE1 corresponds to the cathode, by flowing a current I from the partition wall 6 towards the lower electrode LE1 (applying a reverse bias voltage), almost no current flows between the lower electrode LE1 and the upper electrode UE1. Therefore, the current I flows concentratedly at the leakage section LK.

[0093] When current I flows through the leak LK, the portion of the organic layer OR1 near the leak LK disappears, and end E11 recedes as shown in the example in Figure 10B. As a result, ends E11 and E2 are separated from each other, and a gap V1 is formed between the lower part 61 and the organic layer OR1. In other words, the lower part 61 and the organic layer OR1 are electrically insulated. In the example shown in Figure 10B, a gap V1 is formed between the bottom layer 63 and the hole injection layer HIL, and the bottom layer 63 and the hole injection layer HIL are electrically insulated. Note that the gap V1 does not necessarily have to be formed. In other words, ends E11 and E2 may be in contact. However, even in this case, when current I flows through the leak LK, the partition wall 6 and the organic layer OR1 are electrically insulated.

[0094] The magnitude of the voltage applied in the above process (potential difference between the partition wall 6 and the lower electrode LE1) is, for example, 20V or less. In one example, the magnitude of the voltage is 10-20V. Also, the time during which the voltage is applied (time during which the current I flows) is, in one example, 2 seconds or less. Note that the magnitude of the voltage and the time are not limited to this example.

[0095] Next, as shown in Figure 10C, a cap layer CP1 covering the upper electrode UE1 and a sealing layer SE11 covering the cap layer CP1 are formed. After that, an etching process is performed to form the display element DE1, as shown in Figures 9E and 9F.

[0096] Figure 11 is a circuit diagram of the process shown in Figure 10A. The leak section LK is connected in parallel with the display element DE1.

[0097] In this process, low-level scanning signals Sg1, Sg2, and Sg4 and a high-level scanning signal Sg3 are supplied to each transistor. As a result, as shown in Figure 11, transistor TR6 is turned ON, and transistors TR1, TR3 to TR5 and TR7 are turned OFF.

[0098] The partition wall 6 shown in Figure 10A is connected to the power line PL3 and supplied with the power supply voltage VSSEL. The lower electrode LE1 is connected to the initialization line IL and supplied with the initialization voltage Vini. The power supply voltage VSSEL and the initialization voltage Vini are supplied from, for example, the test pad PD shown in Figure 8. In this embodiment, the power supply voltage VSSEL is higher than the initialization voltage Vini (VSSEL > Vini). Therefore, a current I flows from the partition wall 6 to the lower electrode LE1. As shown in Figure 11, the current I flows almost entirely through the display element DE1 and then through the leakage section LK. After flowing through the leakage section LK, the current I flows through the transistor TR6.

[0099] If the DSP display device is manufactured with the organic layer OR1 and the partition wall 6 in contact and electrically conductive, there is a risk of current leakage between the organic layer OR1 and the partition wall 6 through the leakage section LK. As a result, insufficient current may flow to the organic layer OR1 due to the leakage, and the display element DE1 may not be able to emit light in the intended color. This situation can be particularly problematic when it is necessary to represent colors in the low-gradation range, such as when it is desired that the display element DE1 emit light in a dark gray close to black.

[0100] Therefore, it is necessary to form the organic layer OR1 so that it does not come into contact with the lower part 61. However, during the manufacturing process, it is possible that the organic layer OR1 may unintentionally come into contact with the lower part 61.

[0101] In this embodiment, a voltage is applied between the partition wall 6 and the lower electrode LE1, and a current I is passed through the leakage section LK, thereby electrically insulating the lower part 61 from the organic layer OR1. This suppresses current leakage between the lower part 61 and the organic layer OR1, preventing unintended color emission. Consequently, it is possible to suppress a decrease in the brightness characteristics (display quality) of the display device DSP.

[0102] The above problem is particularly likely to occur when the hole injection layer HIL of the organic layer OR1 is in contact with the lower part 61. When the hole injection layer HIL is in contact with the lower part 61, holes flow from the hole injection layer HIL to the lower part, reducing the supply of holes to the light-emitting layer EM1, making it impossible to make the light-emitting layer EM1 emit light in the intended color. Therefore, as shown in this embodiment, by electrically insulating the lower part 61 and the hole injection layer HIL, it is possible to prevent the emission of unintended colors and suppress the deterioration of the brightness characteristics of the display device DSP.

[0103] Furthermore, the process of applying the current described above can be carried out even when the lower part 61 and the organic layer OR1 are separated. When the lower part 61 and the organic layer OR1 are separated, no current flows between the partition wall 6 and the lower electrode LE1, so no problems occur even after going through the above process. Therefore, it is possible to carry out the process of applying the current described above without checking whether the lower part 61 and the organic layer OR1 are separated or not. As a result, the manufacturing man-hours for the display device DSP can be reduced.

[0104] Furthermore, in this embodiment, the potential of the partition wall 6 is higher than the potential of the lower electrode LE1. Therefore, current I flows from the partition wall 6 towards the lower electrode LE1. When the lower electrode LE1 corresponds to the anode and the upper electrode UE1 corresponds to the cathode, and current I flows from the partition wall 6 towards the lower electrode LE1 (a reverse bias voltage is applied), almost no current flows between the lower electrode LE1 and the upper electrode UE1. Therefore, damage to the organic layer OR1 due to the current flowing between the lower electrode LE1 and the upper electrode UE1 can be prevented. Consequently, it is possible to suppress a decrease in the display quality of the display device DSP.

[0105] Figures 12A and 12B are schematic cross-sectional views illustrating another example of the process for electrically insulating the organic layer OR1 and the partition wall 6. In the example shown in Figure 12A, the process of applying current I is carried out after the formation of the cap layer CP1 and the sealing layer SE11. In the process of applying current I, current I is passed from the partition wall 6 connected to the high potential side to the lower electrode LE1 connected to the low potential side via the leakage section LK. This creates a gap V1 as shown in Figure 12B, electrically insulating the lower part 61 from the organic layer OR1.

[0106] The process shown in Figures 12A and 12B is performed, for example, between the process shown in Figure 9H and the process shown in Figure 9I. That is, the process of applying current I is performed after the cap layers CP1, CP2, CP3 and the sealing layers SE11, SE12, SE13 have been formed. In this case, the current I is applied only once. Therefore, it is possible to reduce the number of steps compared to the case where current I is applied each time each display element DE1, DE2, DE3 is formed.

[0107] Furthermore, the steps shown in Figures 12A and 12B may be performed each time a display element DE1, DE2, or DE3 is formed. In other words, the steps shown in Figures 12A and 12B may be performed between Figure 9F and Figure 9G, between Figure 9G and Figure 9H, and between Figure 9H and Figure 9I. In such cases, it is possible to obtain the same effects as described above.

[0108] Figures 13A to 13C are schematic cross-sectional views showing yet another example of the process of electrically insulating the organic layer OR1 and the partition wall 6. This process is carried out, for example, between the process shown in Figure 9D and the process shown in Figure 9E.

[0109] After the formation of pixel apertures AP1, AP2, and AP3, an organic layer OR1 is formed to cover the lower electrode LE1 through the pixel aperture AP1, as shown in Figure 13A. Subsequently, the partition wall 6 and the lower electrode LE1 are connected to the power supply C1. In the example shown in Figure 13A, the partition wall 6 is connected to the high potential side and the lower electrode LE1 is connected to the low potential side. Then, as described above, a current I is passed from the partition wall 6 to the lower electrode LE1. This forms an air gap V1, as shown in Figure 13B, and insulates the lower part 61 from the organic layer OR1.

[0110] After the process of applying current I, an upper electrode UE1 covering the organic layer, a cap layer CP1 covering the upper electrode UE1, and a sealing layer SE11 covering the cap layer CP1 are formed. The upper electrode UE1 is in contact with the rib layer 5 between ends E11 and E2.

[0111] Thus, even after the formation of the organic layer OR1 but before the formation of the upper electrode UE1, it is possible to perform the process of passing a current I through the leakage portion LK as described above. In this case, since the upper electrode UE1 has not yet been formed, the situation in which current flows between the lower electrode LE1 and the upper electrode UE1 and damages the organic layer OR1 does not occur. Therefore, it is possible to suppress a decrease in the display quality of the display device DSP.

[0112] Furthermore, if a current I is applied before the upper electrode UE1 is formed, the direction in which the current I flows is not limited to the direction from the partition wall 6 to the lower electrode LE1. Therefore, the current I may flow from the lower electrode LE1 to the partition wall 6 by connecting the lower electrode LE1 to the high potential side and the partition wall 6 to the low potential side. Alternatively, an AC voltage may be applied.

[0113] Figure 14 is a schematic cross-sectional view showing another example of the process shown in Figure 13A. In the example shown in Figure 14, the partition wall 6 is connected to the low potential side, and the lower electrode LE1 is connected to the high potential side. Therefore, the current I flows from the lower electrode LE1 towards the partition wall 6.

[0114] Thus, before forming the upper electrode UE1, a current I may be passed from the lower electrode LE1 toward the partition wall 6. By performing this process, the same effects as described above can be obtained.

[0115] Figure 15 is a schematic cross-sectional view showing yet another example of the process shown in Figure 13A. In the example shown in Figure 15, the partition wall 6 and the lower electrode LE1 are connected to the AC power supply C2. Therefore, an AC bias voltage is applied between the partition wall 6 and the lower electrode LE1, and an AC current I flows between the partition wall 6 and the lower electrode LE1.

[0116] Thus, before forming the upper electrode UE1, an AC bias voltage may be applied between the partition wall 6 and the lower electrode LE1 to allow a current I to flow. By performing this process, the same effects as described above can be obtained.

[0117] All methods for manufacturing a display device that can be implemented by those skilled in the art by appropriately modifying the design based on the methods for manufacturing a display device described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0118] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications to the above-described embodiments in which a person skilled in the art has appropriately added, deleted, or modified components, or added, omitted, or modified processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0119] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0120] DSP...Display device, DE1, DE2, DE3...Display elements, LE1, LE2, LE3...Lower electrodes, OR1, OR2, OR3...Organic layers, UE1, UE2, UE3...Upper electrodes, SE11, SE12, SE13, SE2...Sealing layers, 5...Rib layer, 6...Partition wall, 61...Lower part, 62...Upper part, 63...Bottom layer, 64...Axial layer, LK...Leakage part, V1, V2...Voids.

Claims

1. A lower electrode is formed in the display area where the image is displayed. The rib layer covering the lower electrode is formed of an inorganic material, A partition wall is formed, comprising a conductive lower portion disposed on the rib layer and an upper portion disposed on the lower portion and protruding from the side surface of the lower portion. A pixel aperture overlapping the lower electrode is formed in the rib layer, An organic layer is formed to cover the lower electrode through the pixel aperture, A current is passed between the partition wall and the lower electrode to electrically insulate the lower part from the organic layer. A method for manufacturing a display device.

2. The organic layer includes a hole injection layer in contact with the lower electrode. In the process of applying the current, the lower part and the hole injection layer are electrically insulated. A method for manufacturing the display device according to claim 1.

3. Between the step of forming the organic layer and the step of applying the current, an upper electrode is formed that covers the organic layer and is in contact with the lower part. After the step of applying the current, a cap layer covering the upper electrode and a sealing layer covering the cap layer are formed. A method for manufacturing the display device according to claim 1.

4. Between the step of forming the organic layer and the step of applying the current, an upper electrode covering the organic layer and in contact with the lower part, a cap layer covering the upper electrode, and a sealing layer covering the cap layer are formed. A method for manufacturing a display device according to claim 1.

5. After the step of applying the current, an upper electrode covering the organic layer and in contact with the lower part, a cap layer covering the upper electrode, and a sealing layer covering the cap layer are formed. A method for manufacturing a display device according to claim 1.

6. The lower electrode corresponds to the anode, The aforementioned upper electrode corresponds to the cathode, In the process of applying the current, the current is applied from the partition wall toward the lower electrode. A method for manufacturing a display device according to any one of claims 3 to 5.

7. The lower electrode corresponds to the anode, The aforementioned upper electrode corresponds to the cathode, In the process of applying the current, the current is applied from the lower electrode toward the partition wall. A method for manufacturing a display device according to claim 5.

8. In the process of supplying the current, an AC bias voltage is applied. A method for manufacturing a display device according to claim 5.

9. The potential difference between the partition wall and the lower electrode during the process of applying the current is 20V or less. A method for manufacturing a display device according to claim 1.

10. The time for which the current is applied is 2 seconds or less. A method for manufacturing a display device according to claim 1.

11. The lower part includes a bottom layer placed on the rib layer and an axial layer placed on the bottom layer, In the process of applying the current, the bottom layer and the organic layer are electrically insulated. A method for manufacturing a display device according to claim 1.

12. The organic layer includes a hole injection layer in contact with the bottom layer, In the process of applying the current, the bottom layer and the hole injection layer are electrically insulated. A method for manufacturing a display device according to claim 11.

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